Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device may include: an access line; a variable resistance layer; an electrode located between the access line and the variable resistance layer; and a blocking structure located between the access line and the electrode and including an amorphous blocking member. The blocking structure may also include a diffusion barrier, and the resistivity of the amorphous barrier is higher than the resistivity of the diffusion barrier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0131682, filed on October 4, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, with the miniaturization, low power consumption, improved performance, diversification, etc. of electronic devices, semiconductor devices capable of storing information are required in various electronic devices such as computers and portable communication devices. Therefore, semiconductor devices capable of storing data using the characteristic of switching between different resistance states according to applied voltage or current have been studied. Examples of such semiconductor devices include resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuses, etc. Summary of the invention

[0005] In an embodiment, a semiconductor device may include: an access line; a variable resistance layer; an electrode located between the access line and the variable resistance layer; and a blocking structure located between the access line and the electrode and including an amorphous blocking member.

[0006] In an embodiment, a semiconductor device may include: a first access line; a second access line crossing the first access line; a memory cell connected between the first access line and the second access line and including a variable resistance layer; a crystal barrier located between the memory cell and the first access line; and an amorphous barrier located between the crystal barrier and the memory cell.

[0007] In an embodiment, a method for manufacturing a semiconductor device may include: forming a first conductive layer; forming a blocking structure on the first conductive layer, the blocking structure including an amorphous blocking member; forming a first electrode layer on the blocking structure; and forming a variable resistance layer on the first electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing the structure of a semiconductor device according to an embodiment.

[0009] Figure 2 is a diagram showing the structure of a semiconductor device according to an embodiment.

[0010] Figure 3 is a diagram showing the structure of a semiconductor device according to an embodiment.

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a diagram for describing the structure of a semiconductor device according to an embodiment.

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D is a diagram for describing the structure of a semiconductor device according to an embodiment.

[0013] Fig. 6A , Figure 6B , Figure 6C and Fig.6D 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment.

[0014] Fig. 7A , Figure 7B , Figure 7C and Fig.7D 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0015] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0016] By stacking memory cells in three dimensions, the integration of a semiconductor device can be improved. A semiconductor device having a stable structure and improved reliability can also be provided.

[0017] As used herein, "at least one of ... and ..." indicates a disjunctive list of each item and possible combinations. For example, "at least one of A and B" means "only A, or only B, or both A and B", and "at least one of A, B, and C" means "only A, or only B, only C, or both A and B, or both A and C, or both B and C, or all of A, B, and C", and so on. Below, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 is a diagram showing the structure of a semiconductor device according to an embodiment.

[0019] Reference Figure 1 , a semiconductor device according to an embodiment may include at least one first access line L1, at least one second access line L2, and at least one memory cell MC.

[0020] The first access line L1 and the second access line L2 may cross each other. The first access line L1 may extend in a first direction I. The second access line L2 may extend in a second direction II that crosses the first direction I. The first access line L1 and the second access line L2 may be stacked in a third direction III. The third direction III may be a direction substantially perpendicular to a plane defined by the first direction I and the second direction II. The first access line L1 and the second access line L2 may both be word lines or bit lines. As an example, the first access line L1 may be a word line and the second access line L2 may be a bit line. Alternatively, the first access line L1 may be a bit line and the second access line L2 may be a word line.

[0021] The memory cells MC may be located in a region where the first access line L1 and the second access line L2 cross each other. The memory cells MC may be arranged in the first direction I and the second direction II. The memory cells MC may be connected between the first access line L1 and the second access line L2.

[0022] The memory cell MC may include a first electrode 11, a second electrode 12, and a variable resistance layer 15. For reference, the memory cell MC may further include a switch layer instead of the variable resistance layer 15, or include a switch layer in addition to the variable resistance layer 15. The variable resistance layer 15 may be located between the first electrode 11 and the second electrode 12. As an example, the first electrode 11, the variable resistance layer 15, and the second electrode 12 may be stacked in the third direction III. The first electrode 11 may be electrically connected to the first access line L1. The second electrode 12 may be electrically connected to the second access line L2.

[0023] The blocking structure 17 may be located at one or both of a first position between the memory cell MC and the first access line L1 and a second position between the memory cell MC and the second access line L2. The blocking structure 17 may include at least one of an amorphous barrier, a diffusion barrier, and a resistance barrier (e.g., a high resistance barrier). The diffusion barrier may be located between the amorphous barrier and the high resistance barrier. The amorphous barrier may be located between the diffusion barrier and the first electrode 11. The high resistance barrier may be located between the diffusion barrier and the first access line L1. The diffusion barrier may be a crystalline barrier. The diffusion barrier may include at least one of a metal nitride and graphene. The amorphous barrier may include at least one of a metal oxynitride, graphene oxide, and reduced graphene oxide. The high resistance barrier may include a tungsten silicon nitride layer.

[0024] In addition, although Figure 1Although not shown in the figure, the semiconductor device may further include a circuit for controlling the first access line L1 and the second access line L2. As an example, the semiconductor device may include a first circuit such as a word line decoder and a word line driver. The first circuit may select the first access line L1 on which a programming operation is to be performed according to a row address. The semiconductor device may include a second circuit such as a bit line decoder and a bit line driver. The second circuit may select the second access line L2 on which a programming operation is to be performed according to a column address. During the programming operation, a memory cell MC connected between the selected first access line L1 and the selected second access line L2 may be selected.

[0025] According to the above structure, the memory cell MC can be protected by the barrier structure 17. The damage to the memory cell MC caused by the spike current can be reduced by the high resistance barrier or the amorphous barrier or both. In addition, the diffusion of one or more elements of the high resistance barrier into the memory cell MC can be significantly reduced by the diffusion barrier or the amorphous barrier or both.

[0026] Figure 2 is a diagram illustrating a structure of a semiconductor device according to an embodiment. Hereinafter, for the sake of brevity, contents overlapping with previously described contents may be omitted.

[0027] Reference Figure 2 The semiconductor device may include at least one first access line L1 , at least one second access line L2 , and at least one memory cell MC. The semiconductor device may also include at least one insulating layer 23 .

[0028] The first access line L1 may be alternately stacked with the insulating layer 23. The second access line L2 may pass through the first access line L1. Alternatively, the vertical electrode may extend through the first access line L1 and the insulating layer 23 in the vertical direction, and the second access line L2 may be electrically connected to the vertical electrode. The first access line L1 and the second access line L2 may both be word lines or bit lines. As an example, the first access line L1 may be a word line, and the second access line L2 may be a bit line. Alternatively, the first access line L1 may be a bit line, and the second access line L2 may be a word line.

[0029] The memory cell MC may be located in a region where the first access line L1 and the second access line L2 cross each other. As an example, the memory cell MC may be stacked in a vertical direction along the second access line L2. The memory cell MC may be connected between the first access line L1 and the second access line L2.

[0030] The memory cell MC may include a first electrode 21, a second electrode 22, and a variable resistance layer 25. For reference, the memory cell MC may further include a switch layer instead of the variable resistance layer 25, or include a switch layer in addition to the variable resistance layer 25. The variable resistance layer 25 may be located between the first electrode 21 and the second electrode 22. As an example, the second electrode 22 may surround a sidewall of the second access line L2. The variable resistance layer 25 may surround the second electrode 22. The first electrode 21 may surround the variable resistance layer 25. The first electrode 21 may be electrically connected to the first access line L1. The second electrode 22 may be electrically connected to the second access line L2.

[0031] The blocking structure 27 may be located at one or both of a first position between the memory cell MC and the first access line L1 and a second position between the memory cell MC and the second access line L2. The blocking structure 27 may include at least one of an amorphous barrier, a diffusion barrier, and a resistance barrier (e.g., a high resistance barrier). The diffusion barrier may be located between the amorphous barrier and the high resistance barrier. The amorphous barrier may be located between the diffusion barrier and the first electrode 21. The high resistance barrier may be located between the diffusion barrier and the first access line L1. The diffusion barrier may be a crystalline barrier. The crystalline barrier may include at least one of a metal nitride and graphene. The amorphous barrier may include at least one of a metal oxynitride, graphene oxide, and reduced graphene oxide. The high resistance barrier may include a tungsten silicon nitride layer.

[0032] According to the above structure, the integration of the memory can be improved by stacking the memory cells MC. In addition, the memory cells MC can be protected by the barrier structure 27. The damage to the memory cells MC caused by the spike current can be reduced by the high resistance barrier and the amorphous barrier. In an embodiment, each of the high resistance barrier and the amorphous barrier can have a relatively high resistivity to significantly reduce the amplitude of the spike current. In addition, the diffusion of the elements of the high resistance barrier into the memory cells MC can be reduced by the diffusion barrier and the amorphous barrier.

[0033] Figure 3 is a diagram illustrating a structure of a semiconductor device according to an embodiment. Hereinafter, for the sake of brevity, contents overlapping with previously described contents may be omitted.

[0034] Reference Figure 3 The semiconductor device may include at least one first access line L1 , at least one second access line L2 , and at least one memory cell MC. The semiconductor device may further include at least one insulating layer 33 .

[0035] The first access line L1 may be alternately stacked with the insulating layer 33. The second access line L2 may pass through the first access line L1. The first access line L1 and the second access line L2 may each be a word line or a bit line.

[0036] The memory cell MC may be located in a region where the first access line L1 and the second access line L2 cross each other. The memory cell MC may include a first electrode 31, a second electrode 32, and a variable resistance layer 35. For reference, the memory cell MC may also include a switch layer instead of the variable resistance layer 35, or include a switch layer in addition to the variable resistance layer 35. The variable resistance layer 35 may be located between the first electrode 31 and the second electrode 32. The second electrode 32, the variable resistance layer 35, and the first electrode 31 may be located between the stacked insulating layers 33. The variable resistance layers 35 of the stacked memory cells MC may be separated from each other. The first electrode 31 may be electrically connected to the first access line L1. The second electrode 32 may be electrically connected to the second access line L2.

[0037] The blocking structure 37 may be located at one or both of a first position between the memory cell MC and the first access line L1 and a second position between the memory cell MC and the second access line L2. The blocking structure 37 may include at least one of an amorphous barrier, a diffusion barrier, and a high resistance barrier. The diffusion barrier may be located between the amorphous barrier and the high resistance barrier. The amorphous barrier may be located between the diffusion barrier and the first electrode 31. The high resistance barrier may be located between the diffusion barrier and the first access line L1. The diffusion barrier may be a crystalline barrier. The crystalline barrier may include at least one of a metal nitride and graphene. The amorphous barrier may include at least one of a metal oxynitride, graphene oxide, and reduced graphene oxide. The high resistance barrier may include a tungsten silicon nitride layer.

[0038] According to the above structure, the integration of the memory can be improved by stacking the memory cells MC. By separating the variable resistance layers 35 of the memory cells MC from each other, the data retention characteristics can be improved. In addition, the memory cells MC can be protected by the barrier structure 37. The damage to the memory cells MC caused by the spike current can be reduced by the high resistance barrier and the amorphous barrier. In addition, the diffusion barrier and the amorphous barrier can reduce the diffusion of the elements of the high resistance barrier into the memory cells MC.

[0039] FIG. 4A to FIG. 4D 1 is a diagram for describing a structure of a semiconductor device according to an embodiment. Hereinafter, for the sake of brevity, contents overlapping with previously described contents may be omitted.

[0040] Reference FIG. 4A to FIG. 4D , the semiconductor device may include a first access line L1, a second access line L2, and a memory cell MC. The memory cell MC may be connected between the first access line L1 and the second access line L2.

[0041] The memory cell MC may include a selection element S and a memory element M. The selection element S may adjust the flow of current according to the amplitude of the applied voltage or current. The memory cell MC may be selected according to the on or off of the selection element S. The selection element S may include a first electrode 41, a switch layer 44, and a second electrode 42. The switch layer 44 may be located between the first electrode 41 and the second electrode 42. The switch layer 44 may maintain a specific phase such as an amorphous phase during the operation of the memory cell MC. As an example, the switch layer 44 may include a chalcogenide material. The first electrode 41 may be located between the switch layer 44 and the first access line L1, and may be electrically connected to the first access line L1.

[0042] The memory element M may include a second electrode 42, a variable resistance layer 45, and a third electrode 43. The variable resistance layer 45 may be located between the second electrode 42 and the third electrode 43. The selection element S and the memory element M may share the second electrode 42 with each other. The third electrode 43 of the memory element M may be electrically connected to the second access line L2.

[0043] The variable resistance layer 45 may have a characteristic of reversibly switching between different resistance states according to a voltage or current applied to the memory element M. As an example, when the variable resistance layer 45 has a low resistance state, data "1" may be stored, and when the variable resistance layer 45 has a high resistance state, data "0" may be stored.

[0044] As an example, the variable resistance layer 45 may include a resistance material. An electrical path is generated or disappears in the variable resistance layer 45 so that data can be stored. As an example, the variable resistance layer 45 may include a transition metal oxide or include a metal oxide such as a perovskite-based material.

[0045] As an example, the variable resistance layer 45 may have a magnetic tunnel junction (MTJ) structure including a magnetized pinned layer, a tunnel barrier layer, and a magnetized free layer. Data may be stored according to a change in the magnetization direction of the magnetized free layer relative to the magnetization direction of the magnetized pinned layer. As an example, the magnetized pinned layer and the magnetized free layer may each include a magnetic material, and the tunnel barrier layer may include a metal oxide.

[0046] As an example, the variable resistance layer 45 may include a phase change material or include a chalcogenide-based material. The variable resistance layer 45 may change its phase according to a programming operation. As an example, the variable resistance layer 45 may have a low resistance crystalline state by a set operation. As an example, the variable resistance layer 45 may have a high resistance amorphous state by a reset operation. Therefore, data may be stored in a memory cell using a difference in resistance according to the phase of the variable resistance layer 45.

[0047] As an example, the variable resistance layer 45 may include a variable resistance material whose resistance changes without phase change or include a chalcogenide-based material. The variable resistance layer 45 may maintain its phase after the programming operation. As an example, the variable resistance layer 45 may have an amorphous state, and may maintain the amorphous state without changing to a crystalline state after the programming operation. The threshold voltage of the memory cell may be changed according to the programming voltage applied to the memory cell, and the memory cell may be programmed to at least two states. As an example, a memory cell may be programmed to a set state or a reset state using programming voltages with different polarities. Therefore, data may be stored in the memory cell using the difference in the threshold voltage of the memory cell.

[0048] The first electrode 41, the second electrode 42, and the third electrode 43 may each include a conductive material such as polysilicon or a metal. As an example, the first electrode 41, the second electrode 42, and the third electrode 43 may each include polysilicon, tungsten (W), tungsten nitride (WN x ), tungsten silicide (WSi x ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo) and ruthenium (Ru). The first electrode 41, the second electrode 42 and the third electrode 43 may include the same material or different materials. As an example, at least one of the first electrode 41, the second electrode 42 and the third electrode 43 may include a carbon layer.

[0049] The semiconductor device may further include a blocking structure 47 located at one or both of a first position between the first access line L1 and the memory cell MC and a second position between the second access line L2 and the memory cell MC. The blocking structure may include at least one of a diffusion barrier 47A, an amorphous barrier 47B, and a high resistance barrier 47C.

[0050] Reference Figure 4A , the barrier structure 47 may include a diffusion barrier 47A and an amorphous barrier 47B. As an example, the amorphous barrier 47B may be located on the diffusion barrier 47A. Here, the positions of the diffusion barrier 47A and the amorphous barrier 47B may be changed. As an example, the diffusion barrier 47A may be located on the amorphous barrier 47B.

[0051] The diffusion barrier 47A may be located between the first electrode 41 and the first access line L1. Diffusion of metal included in the first access line L1 and the like into the memory cell MC may be reduced by the diffusion barrier 47A. The diffusion barrier 47A may have a thickness of several nanometers. As an example, the diffusion barrier 47A may have a thickness of to Thickness or to The diffusion barrier 47A may be a crystalline barrier. As an example, the diffusion barrier 47A may have a polycrystalline structure.

[0052] The bonding distance between the elements included in the diffusion barrier 47A may be smaller than the diameter of the element whose diffusion will be reduced. As an example, the diffusion barrier 47A may include at least one of a metal nitride and graphene. The metal nitride may include at least one of titanium, tungsten, nickel, and molybdenum. The bonding distance between the elements of the metal nitride may be smaller than the diameter of tungsten and / or silicon. Graphene may have a two-dimensional plate-like structure, and the carbon-carbon lattice distance may be smaller than the diameter of tungsten and / or silicon.

[0053] The amorphous barrier 47B may be located between the first electrode 41 and the first access line L1, and may be located between the diffusion barrier 47A and the first electrode 41. The amorphous barrier 47B may have a different crystal structure from the diffusion barrier 47A. The amorphous barrier 47B may have a higher resistivity than the diffusion barrier 47A.

[0054] As an example, the diffusion barrier 47A may have a crystalline structure, while the amorphous barrier 47B may have an amorphous structure. Because the amorphous barrier 47B does not have a grain structure unlike the diffusion barrier 47A, even if an element (e.g., metal) diffuses through the grain boundary of the diffusion barrier 47A, the diffusion of the metal through the amorphous barrier 47B may be reduced compared to the diffusion of the metal through the diffusion barrier 47A. The change in the composition of the variable resistance layer 45 caused by the diffusion of the metal into the memory cell MC can be reduced, and the memory cell MC can be protected.

[0055] The diffusion barrier 47A may include a metal nitride, while the amorphous barrier 47B may include a metal oxynitride. The metal oxynitride layer may be formed by oxidizing the surface of the metal nitride layer. The diffusion barrier 47A may include graphene, while the amorphous barrier 47B may include graphene oxide. The diffusion barrier 47A may include graphene, while the amorphous barrier 47B may include reduced graphene oxide. The amorphous barrier 47B may have a thickness smaller than that of the diffusion barrier 47A. For example, the thickness of the amorphous barrier 47B may be less than 30% of the thickness of the diffusion barrier 47A.

[0056] Graphene oxide and reduced graphene oxide have a carbon ring structure and can therefore be used as a diffusion barrier. In addition, graphene oxide and reduced graphene oxide include a functional group bonded to a carbon ring and can therefore be used as a seed of the first electrode 41 or increase the bonding strength of the first electrode 41. Reduced graphene oxide may have a smaller interlayer distance than graphene oxide and a smaller band gap energy than graphene oxide. Therefore, reduced graphene oxide may have higher electrical conductivity and / or thermal conductivity than graphene oxide.

[0057] Reference Figure 4B , the barrier structure 47 may include a plurality of diffusion barriers 47A and a plurality of amorphous barriers 47B. The barrier structure 47 may include a plurality of diffusion barriers 47A and a plurality of amorphous barriers 47B stacked alternately. As an example, the barrier structure 47 may include metal nitride layers and metal oxynitride layers stacked alternately. The barrier structure 47 may include graphene layers and graphene oxide layers stacked alternately. The barrier structure 47 may include graphene layers and reduced graphene oxide layers stacked alternately.

[0058] For reference, two of the diffusion barrier 47A, the amorphous barrier 47B, and the high resistance barrier 47C may also be alternately stacked. As an example, the blocking structure 47 may include an amorphous barrier 47B and a high resistance barrier 47C alternately stacked. The blocking structure 47 may include a diffusion barrier 47A and a high resistance barrier 47C alternately stacked. The blocking structure 47 may include an amorphous barrier 47B and a high resistance barrier 47C alternately stacked and a diffusion barrier 47A and a high resistance barrier 47C alternately stacked.

[0059] Reference Figure 4C , the blocking structure 47 may include a diffusion barrier 47A, an amorphous barrier 47B, and a high resistance barrier 47C. The high resistance barrier 47C may be located between the amorphous barrier 47B and the first access line L1. The high resistance barrier 47C may be located between the diffusion barrier 47A and the first access line L1. In some embodiments, a plurality of diffusion barriers 47A and a plurality of amorphous barriers 47B may also be alternately stacked on the high resistance barrier 47C.

[0060] The high resistance barrier 47C may have a higher resistivity than the amorphous barrier 47B. The high resistance barrier 47C may reduce the transmission of a spike current generated during operation to the memory cell MC. The high resistance barrier 47C may include a metal. As an example, the high resistance barrier 47C may include a tungsten silicon nitride layer.

[0061] When the programming operation is repeatedly performed, the high resistance barrier 47C may be degraded, and the element included in the high resistance barrier 47C may diffuse into the memory cell MC. In this case, at least one of the diffusion barrier 47A and the amorphous barrier 47B may reduce the diffusion of the element included in the high resistance barrier 47C into the memory cell MC. As an example, at least one of the diffusion barrier 47A and the amorphous barrier 47B may reduce the diffusion of at least one of tungsten and silicon included in the high resistance barrier 47C into the memory cell MC.

[0062] Reference Figure 4D , the semiconductor device may include a first barrier structure 47_1 and a second barrier structure 47_2. The first barrier structure 47_1 may include at least one of a diffusion barrier 47A, an amorphous barrier 47B, and a high resistance barrier 47C. The second barrier structure 47_2 may include at least one of a diffusion barrier 47A, an amorphous barrier 47B, and a high resistance barrier 47C. As an example, each of the first barrier structure 47_1 and the second barrier structure 47_2 may have the above reference FIG. 4A to FIG. 4C The described structures or combinations thereof.

[0063] The first barrier structure 47_1 and the second barrier structure 47_2 may have a symmetrical shape or an asymmetrical shape with respect to the memory cell MC. As an example, in the first barrier structure 47_1, the diffusion barrier 47A may be located on the high resistance barrier 47C, and the amorphous barrier 47B may be located on the diffusion barrier 47A. In the second barrier structure 47_2, the diffusion barrier 47A may be located on the amorphous barrier 47B, and the high resistance barrier 47C may be located on the diffusion barrier 47A. For example, in Figure 4D In the embodiment of FIG. 4 , the layers in the first barrier structure 47_1 are stacked in the order of the high resistance barrier 47C, the diffusion barrier 47A, and the amorphous barrier 47B, while the layers in the second barrier structure 47_2 are stacked in the order of the amorphous barrier 47B, the diffusion barrier 47A, and the high resistance barrier 47C. Figure 4D In the embodiment of FIG. 4 , the first barrier structure 47_1 and the second barrier structure 47_2 have a substantially symmetrical structure with respect to the memory cell MC.

[0064] According to the above structure, the barrier structure 47 may include at least one of a diffusion barrier 47A, an amorphous barrier 47B, and a high resistance barrier 47C. The diffusion barrier 47A may reduce the diffusion of elements included in the first access line L1 and / or the high resistance barrier 47C into the memory cell MC. The high resistance barrier 47C may reduce the transmission of a spike current to the memory cell MC.

[0065] The amorphous barrier 47B may function as both a diffusion barrier and a high resistance barrier. The diffusion barrier 47A and the amorphous barrier 47B may reduce diffusion of elements included in the high resistance barrier 47C into the memory cell MC. The high resistance barrier 47C and the amorphous barrier 47B may reduce spike current transmission to the memory cell MC.

[0066] Therefore, the memory cell MC may be protected by positioning the blocking structure 47 at one or both of a first position between the memory cell MC and the first access line L1 and a second position between the memory cell MC and the second access line L2 .

[0067] FIG. 5A to FIG. 5D 1 is a diagram for describing a structure of a semiconductor device according to an embodiment. Hereinafter, for the sake of brevity, contents overlapping with previously described contents may be omitted.

[0068] Reference FIG. 5A to FIG. 5D , the semiconductor device may include a first access line L1, a second access line L2, and a memory cell MC. The memory cell MC may be connected between the first access line L1 and the second access line L2.

[0069] The memory cell MC may be a storage element and a selection element at the same time. As an example, the memory cell MC may include a first electrode 51, a second electrode 52, and a variable resistance layer 55 located between the first electrode 51 and the second electrode 52. The variable resistance layer 55 may be a switch layer of the selection element and a storage layer of the memory element at the same time. The variable resistance layer 55 may have an amorphous state and may remain in the amorphous state without changing to a crystalline state after a programming operation. According to a programming voltage applied to the memory cell, the composition of the variable resistance layer 55 may change and the threshold voltage of the memory cell may change. Therefore, the difference in the threshold voltage of the memory cell may be used to store data in the memory cell.

[0070] Reference Figure 5A , the barrier structure 57 may include a diffusion barrier 57A and an amorphous barrier 57B. The diffusion barrier 57A may be a crystalline barrier. The amorphous barrier 57B may be formed by oxidizing the diffusion barrier 57A. The diffusion barrier 57A may include a metal nitride, and the amorphous barrier 57B may include a metal nitride oxide. The diffusion barrier 57A may include graphene, and the amorphous barrier 57B may include graphene oxide. The diffusion barrier 57A may include graphene, and the amorphous barrier 57B may include reduced graphene oxide.

[0071] Reference Figure 5B, the barrier structure 57 may include diffusion barriers 57A and amorphous barriers 57B stacked alternately. As an example, the barrier structure 57 may include metal nitride layers and metal oxynitride layers stacked alternately. The barrier structure 57 may include graphene layers and graphene oxide layers stacked alternately. The barrier structure 57 may include graphene layers and reduced graphene oxide layers stacked alternately.

[0072] Reference Figure 5C , the blocking structure 57 may include a diffusion barrier 57A, an amorphous barrier 57B, and a high resistance barrier 57C. The diffusion barrier 57A may be a crystalline barrier. The high resistance barrier 57C may be located between the memory cell MC and the first access line L1. The diffusion barrier 57A (e.g., a crystalline barrier) may be located between the high resistance barrier 57C and the memory cell MC. The amorphous barrier 57B may be located between the crystalline barrier 57A and the memory cell MC.

[0073] The amorphous barrier 57B may have a higher resistivity than the crystalline barrier 57A. The high resistance barrier 57C may have a higher resistivity than the amorphous barrier 57B and the crystalline barrier 57A. The crystalline barrier 57A may include at least one of a metal nitride and graphene. The amorphous barrier 57B may include at least one of a metal nitride oxide, graphene oxide, and reduced graphene oxide. The high resistance barrier 57C may include a tungsten silicon nitride layer.

[0074] Reference Figure 5D , the semiconductor device may include a first barrier structure 57_1 and a second barrier structure 57_2. The first barrier structure 57_1 may include at least one of a diffusion barrier 57A, an amorphous barrier 57B, and a high resistance barrier 57C. The second barrier structure 57_2 may include at least one of a diffusion barrier 57A, an amorphous barrier 57B, and a high resistance barrier 57C.

[0075] According to the above structure, the variable resistance layer 55 of the memory cell MC can be used as both a memory element and a selection element. The blocking structure 57 may include at least one of a diffusion barrier 57A, an amorphous barrier 57B, and a high resistance barrier 57C. The diffusion of elements in the peripheral layer (e.g., the first line L1, the second line L2, and / or the high resistance barrier 57C) into the memory cell MC can be reduced by the blocking structure 57. In addition, the peak current transmission to the memory cell MC can be reduced by the blocking structure 57.

[0076] FIG. 6A to FIG. 6D 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment. Hereinafter, for the sake of brevity, contents overlapping with previously described contents may be omitted.

[0077] Reference Fig. 6A, a first conductive layer 60 may be formed. The first conductive layer 60 may be used to form an access line or an electrode. The access line may be a word line or a bit line.

[0078] Subsequently, a barrier structure including an amorphous barrier may be formed on the first conductive layer 60. First, a first barrier layer 61 may be formed on the first conductive layer 60. The first barrier layer 61 may be a high resistance barrier. The first barrier layer 61 may be a metal-containing layer. As an example, the first barrier layer 61 may include a tungsten silicon nitride layer.

[0079] Reference Figure 6B , the second barrier layer 62 may be formed on the first barrier layer 61. For reference, the first barrier layer 61 may also be omitted and the second barrier layer 62 may be formed on the first conductive layer 60. Here, the second barrier layer 62 may be a diffusion barrier. As an example, the second barrier layer 62 may include a metal nitride layer. The second barrier layer 62 may include at least one of titanium, tungsten, nickel, and molybdenum. As an example, the second barrier layer 62 may include graphene. Graphene may be formed by a deposition method such as chemical vapor deposition (CVD). The second barrier layer 62 may include a single layer of graphene or a multilayer of graphene. The thickness of the single layer of graphene may be 1000 Å. to And can be about

[0080] Reference Figure 6C , a third barrier layer 63 may be formed on the second barrier layer 62. For reference, at least one of the first barrier layer 61 and the second barrier layer 62 may be omitted and the third barrier layer 63 may be formed. Here, the third barrier layer 63 may be an amorphous barrier. The third barrier layer 63 may have a higher resistivity than the second barrier layer 62, and the first barrier layer 61 may have a higher resistivity than the third barrier layer 63.

[0081] As an example, the third barrier layer 63 may be formed by oxidizing the surface of the second barrier layer 62. The second barrier layer 62 may be a metal nitride layer, and the third barrier layer 63 may be a metal oxynitride layer formed by oxidizing the metal nitride layer. The thickness of the third barrier layer 63 may be less than that of the second barrier layer 62.

[0082] As an example, the third barrier layer 63 may include graphene oxide. The graphene oxide may be formed by a method such as spin coating. The graphene oxide may have semiconductor properties or insulating properties. The graphene oxide may have a greater thickness than graphene. The thickness of the graphene oxide may be about 0.8 nm to about 1.2 nm.

[0083] As an example, the third barrier layer 63 may include reduced graphene oxide. The reduced graphene oxide may be formed by heating graphene oxide to remove at least some functional groups by a thermal reduction method using a furnace. The reduced graphene oxide may have a smaller band gap than graphene oxide. The electrical conductivity and thermal conductivity of the reduced graphene oxide may be higher than those of graphene oxide. The reduced graphene oxide may have a greater thickness than graphene, and may have a smaller thickness than graphene oxide. The thickness of the reduced graphene oxide may be about 0.8 nm to about 1.2 nm.

[0084] Thus, a barrier structure B including at least one of the first barrier layer 61, the second barrier layer 62, and the third barrier layer 63 may be formed. For reference, the stacking order of the first barrier layer 61, the second barrier layer 62, and the third barrier layer 63 may be changed according to the embodiment. The third barrier layer 63 may be formed on the first conductive layer 60, the second barrier layer 62 may be formed on the third barrier layer 63, and the first conductive layer 61 may be formed on the second barrier layer 62.

[0085] The barrier structure B may also be formed by alternately stacking at least two of the first barrier layer 61, the second barrier layer 62, and the third barrier layer 63. As an example, the barrier structure B may be formed by alternately stacking a plurality of second barrier layers 62 and a plurality of third barrier layers 63. In some embodiments, the barrier structure B may be formed by alternately stacking a plurality of second barrier layers 62 and a plurality of third barrier layers 63 over a single first barrier layer 61. As a result, when the first barrier layer 61 is used as a high resistance layer to protect the memory cell from damage associated with a spike current, the plurality of second barrier layers 62 and the plurality of third barrier layers 63 may be used to substantially prevent elements from diffusing from the first barrier layer 61 into the memory cell. The barrier structure B may also be formed by alternately stacking a barrier layer having a relatively high resistivity and a barrier layer having a relatively low resistivity.

[0086] Reference Fig.6D , the first electrode layer 64 may be formed on the blocking structure B (or the first blocking structure). The variable resistance layer 65 may be formed on the first electrode layer 64. The second electrode layer 66 may be formed on the variable resistance layer 65. The first electrode layer 64, the variable resistance layer 65, and the second electrode layer 66 may be used to form a memory cell. In some embodiments, a second blocking structure may be additionally formed on the second electrode layer 66. For example, the second blocking structure and the first blocking structure B may be formed to have a substantially symmetrical structure with respect to the memory cell.

[0087] Subsequently, a second conductive layer 67 may be formed on the second electrode layer 66. The second conductive layer 67 may be used to form an access line. As an example, the first conductive layer 60 may be used to form a word line, and the second conductive layer 67 may be used to form a bit line. Alternatively, the first conductive layer 60 may be used to form a bit line, and the second conductive layer 67 may be used to form a word line.

[0088] For reference, the barrier structure B may also be formed after forming the second electrode layer 66. In this case, the second conductive layer 67 may be formed on the barrier structure B.

[0089] According to the above-mentioned manufacturing method, the barrier structure B can be formed between the access line and the electrode layer. The first barrier layer 61 can be a high resistance barrier and can reduce the damage to the memory cell due to the spike current. The second barrier layer 62 can be a diffusion barrier and can reduce the diffusion of the metal included in the first barrier layer 61 into the variable resistance layer 65. The third barrier layer 63 can be an amorphous barrier. The third barrier layer 63 can be used as a high resistance barrier together with the first barrier layer 61, or used as a diffusion barrier together with the second barrier layer 62.

[0090] 7A to 7D 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment. Fig. 7A It is a floor plan. Figure 7B and Figure 7C is along Fig. 7A A cross-sectional view taken along line AA' of Fig.7D is along Fig. 7A Hereinafter, for the sake of brevity, contents overlapping with the previously described contents will be omitted.

[0091] Reference Fig. 7A and Figure 7B , a first conductive layer 70 may be formed. The first conductive layer 70 may be used to form a first access line.

[0092] Subsequently, a blocking structure (or initial blocking structure) 71 may be formed on the first conductive layer 70. The blocking structure 71 may include at least one of a high resistance blocking member, a diffusion blocking member, and an amorphous blocking member. Subsequently, a stacked ST may be formed on the blocking structure 71. The stacked ST may include a first electrode layer (or initial first electrode layer) 72, a switch layer (or initial switch layer) 73, a second electrode layer (or initial second electrode layer) 74, a variable resistance layer (or initial variable resistance layer) 75, and a third electrode layer (or initial third electrode layer) 76, or a combination thereof. The stacking order of the layers included in the stacked ST may be changed according to the embodiment. For reference, a blocking structure may also be additionally formed on the stacked ST.

[0093] Reference Fig. 7A and Figure 7C , a first access line 70A and a cell pattern CP may be formed. As an example, the cell pattern CP may be formed by etching the stack ST using the mask pattern as an etching barrier. The cell pattern CP may include an intermediate first electrode layer 72, an intermediate switch layer 73, an intermediate second electrode layer 74, an intermediate variable resistance layer 75, and an intermediate third electrode layer 76. Figure 7C The blocking structure (or intermediate blocking structure) 71 in the middle can be etched Figure 7B The first access line 70A may be formed by etching the first conductive layer 70. The first access line 70A, the barrier structure 71, and the cell pattern CP may extend in the first direction I. Subsequently, an insulating layer 77 may be formed between the cell patterns CP, between the barrier structures 71, and between the first access lines 70A.

[0094] Subsequently, a second conductive layer 78 may be formed on the cell pattern CP and the insulating layer 77. The second conductive layer 78 may be used to form a second access line. For reference, a barrier structure may be additionally formed before forming the second conductive layer 78.

[0095] Reference Fig. 7A and Fig.7D , a second access line 78A extending in a second direction II crossing the first direction I may be formed by etching the second conductive layer 78. Subsequently, memory cells MC may be formed by etching the cell pattern CP and the insulating layer 77. Each memory cell MC may include a first electrode 72A, a switching layer 73A, a second electrode 74A, a variable resistance layer 75A, and a third electrode 76A. The memory cells MC may be located in regions where the first access line 70A and the second access line 78A cross each other, respectively.

[0096] Subsequently, a barrier structure 71A located respectively between the memory cells MC and the first access line 70A may be formed by etching the barrier structure 71. The barrier structure 71A may be arranged in the first direction I and the second direction II. For reference, the line shape of the barrier structure 71 may also be maintained without etching the barrier structure 71. Subsequently, an insulating layer 79 may be formed between the memory cells MC, between the barrier structures 71A, and between the second access lines 78A.

[0097] According to the above manufacturing method, the blocking structure 71A can be formed at one or both of the position between the memory cell MC and the first access line 70A and the position between the memory cell MC and the second access line 78A. Therefore, the memory cell MC can be protected from metal diffusion, spike current, etc.

[0098] Although the embodiments according to the technical ideas of the present disclosure have been described above with reference to the accompanying drawings, the embodiments of the present disclosure are not limited to the above embodiments. Without departing from the technical ideas of the present disclosure defined in the attached claims, technicians in the field to which the present disclosure belongs can make various types of replacements, modifications and changes to the embodiments, and it should be interpreted that these replacements, modifications and changes all belong to the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Access lines; A variable resistance layer; an electrode, located between the access line and the variable resistance layer; as well as The blocking structure is located between the access line and the electrode and includes an amorphous blocking member.

2. The semiconductor device according to claim 1, wherein The barrier structure further includes a diffusion barrier, and a resistivity of the amorphous barrier is higher than a resistivity of the diffusion barrier.

3. The semiconductor device according to claim 2, wherein: The diffusion barrier is located between the amorphous barrier and the access line.

4. The semiconductor device according to claim 2, wherein: The barrier structure further includes a resistance barrier between the diffusion barrier and the access line, and a resistivity of the resistance barrier is higher than a resistivity of the amorphous barrier.

5. The semiconductor device according to claim 2, wherein: The amorphous barrier is located between the diffusion barrier and the electrode.

6. The semiconductor device according to claim 2, wherein: The diffusion barrier includes a metal nitride, and the amorphous barrier includes a metal oxynitride.

7. The semiconductor device according to claim 2, wherein: The diffusion barrier includes graphene, and the amorphous barrier includes graphene oxide.

8. The semiconductor device according to claim 2, wherein: The diffusion barrier includes graphene, and the amorphous barrier includes reduced graphene oxide.

9. The semiconductor device according to claim 1, wherein: The amorphous barrier includes at least one of metal oxynitride, graphene oxide, and reduced graphene oxide.

10. The semiconductor device according to claim 1, wherein The barrier structure includes a plurality of diffusion barriers and a plurality of amorphous barriers that are alternately stacked.

11. The semiconductor device according to claim 1, wherein The blocking structure further includes a resistance blocking member located between the amorphous blocking member and the access line, and a resistivity of the resistance blocking member is higher than a resistivity of the amorphous blocking member.

12. The semiconductor device according to claim 11, wherein The resistance barrier includes a tungsten silicon nitride layer.

13. The semiconductor device according to claim 11, wherein The barrier structure further includes a diffusion barrier between the amorphous barrier and the resistance barrier.

14. A semiconductor device comprising: first access line; a second access line intersecting the first access line; a memory cell connected between the first access line and the second access line and comprising a variable resistance layer; a crystal blocking member located between the memory cell and the first access line; and An amorphous barrier is located between the crystal barrier and the memory unit. 15 . The semiconductor device according to claim 14 , further comprising a resistance barrier located between the crystal barrier and the first access line.

16. The semiconductor device according to claim 15, wherein: The resistance barrier includes a tungsten silicon nitride layer.

17. The semiconductor device according to claim 14, wherein: The amorphous barrier includes at least one of metal oxynitride, graphene oxide, and reduced graphene oxide.

18. The semiconductor device according to claim 14, wherein: The crystal stopper includes at least one of metal nitride and graphene.

19. A method for manufacturing a semiconductor device, the method comprising: forming a first conductive layer; forming a blocking structure on the first conductive layer, the blocking structure comprising an amorphous blocking member; forming a first electrode layer on the blocking structure; as well as A variable resistance layer is formed on the first electrode layer.

20. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming a diffusion barrier on the first conductive layer; and The amorphous barrier is formed on the diffusion barrier.

21. The manufacturing method according to claim 20, wherein: In forming the amorphous barrier, a surface of the diffusion barrier is oxidized to form the amorphous barrier.

22. The manufacturing method according to claim 19, wherein: In forming the barrier structure, at least one diffusion barrier and at least one amorphous barrier are alternately stacked, and the at least one amorphous barrier includes the amorphous barrier.

23. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming a metal nitride layer on the first conductive layer; and A metal oxynitride layer is formed by oxidizing the metal nitride layer.

24. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming graphene on the first conductive layer; and Graphene oxide is formed on the graphene.

25. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming graphene on the first conductive layer; and Reduced graphene oxide is formed on the graphene.

26. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming a resistance barrier on the first conductive layer; and The amorphous barrier is formed on the resistance barrier.

27. The manufacturing method according to claim 19, wherein: Forming the blocking structure includes: forming a resistance barrier on the first conductive layer; forming a diffusion barrier on the resistance barrier; and The amorphous barrier is formed on the diffusion barrier.

28. The manufacturing method according to claim 27, wherein: The resistance barrier includes a tungsten silicon nitride layer.

29. The manufacturing method according to claim 27, wherein: The diffusion barrier includes a metal nitride, and the amorphous barrier includes a metal oxynitride.

30. The manufacturing method according to claim 27, wherein: The diffusion barrier includes graphene, and the amorphous barrier includes graphene oxide.

31. The manufacturing method according to claim 27, wherein: The diffusion barrier includes graphene, and the amorphous barrier includes reduced graphene oxide.

32. The manufacturing method according to claim 19, further comprising: forming a second electrode layer on the variable resistance layer; as well as A second conductive layer is formed on the second electrode layer.

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