Method for forming semiconductor device
By forming a low-density first insulating layer and a high-density second insulating layer in the trench of the semiconductor device, the recessing problem caused by the grinding process is solved, and a more efficient planarization treatment is achieved, and the impact on the spacer layer is reduced.
Patent Information
- Application Number
- CN202411965126.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-08
AI Technical Summary
In the two-layer stacked memory cell structure, the grinding process can easily cause serious defects to the underlying structure, such as the problem of depression caused by grinding.
By forming a first insulating layer with low density in the trench and forming a second insulating layer with high density on its surface, the planarization process is performed to expose the surface of the device structure.
Due to the high density of the second insulating layer, the grinding rate is low, and it is not easy to form depressions, thereby improving the defects caused by the planarization process. At the same time, the low density growth process of the first insulating layer has low temperature requirements and reduces the impact on the spacer layer.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device. Background Art
[0002] Phase Change Memory (PCM) is based on 3D crosspoint (3D Xpoint) technology. With its higher capacity than DRAM and lower latency and addressing capability than NAND, it has become one of the most promising and promising candidates in the field of non-volatile memory.
[0003] In a two-layer stacked memory cell structure, a grinding process is required to expose the address lines in the lower stacked layer. However, the grinding process can easily cause serious defects to the lower structure, such as a problem of depression caused by grinding. Summary of the invention
[0004] An embodiment of the present application provides a method for forming a semiconductor device, which can improve the defects caused by the planarization process to at least partially solve the above-mentioned technical problems.
[0005] An embodiment of the present application provides a semiconductor device, including: providing a substrate; forming a plurality of device structures on the substrate, with grooves between adjacent device structures; forming a spacer layer in the groove, the surface of the spacer layer being lower than the top surface of the device structure on a side away from the substrate; forming a first insulating layer on the surface of the spacer layer; forming a second insulating layer on the surface of the first insulating layer, the density of the second insulating layer being greater than the density of the first insulating layer; and performing a planarization process on at least the second insulating layer until the surface of the device structure is exposed.
[0006] In some embodiments, the process of forming the first insulating layer includes a first deposition process having a first process temperature; the process of forming the second insulating layer includes a second deposition process having a second process temperature, and the second process temperature is higher than the first process temperature.
[0007] In some embodiments, the first process temperature is less than or equal to 250°C; and the second process temperature is greater than 250°C.
[0008] In some embodiments, the first deposition process includes a first plasma deposition process having a first RF power; the second deposition process includes a second plasma deposition process having a second RF power, and the second RF power is greater than the first RF power.
[0009] In some embodiments, a material of the first insulating layer includes silicon oxide; a material of the second insulating layer includes silicon oxide.
[0010] In some embodiments, the hardness of the first insulating layer is less than the hardness of the second insulating layer.
[0011] In some embodiments, a method of forming a first insulating layer on the surface of the spacer layer and forming a second insulating layer on the surface of the first insulating layer includes: forming the first insulating layer on the surface of the spacer layer in the groove; and forming a second insulating layer covering the first insulating layer and the device structure.
[0012] In some embodiments, the spacer layer includes a thermal insulation layer and a sidewall protection layer, and the method of forming the spacer layer includes: forming the sidewall protection layer on the sidewall of the device structure; and forming the thermal insulation layer located between adjacent device structures on the surface of the sidewall protection layer.
[0013] In some embodiments, a method of forming a first insulating layer on the surface of the spacer layer and forming a second insulating layer on the surface of the first insulating layer includes: forming the first insulating layer in the groove and on the surface of the device structure; forming the second insulating layer on the surface of the first insulating layer; and the planarization treatment is also performed on the first insulating layer until the surface of the device structure is exposed.
[0014] In some embodiments, the material of the sidewall protection layer includes oxygen, silicon, nitrogen and hydrogen, and the material of the thermal insulation layer includes oxygen, silicon and carbon.
[0015] In the method for forming a semiconductor device of the embodiment of the present application, a first insulating layer with low density is formed in the groove, and a second insulating layer with high density is formed on the first insulating layer. During the planarization process, since the second insulating layer has high density and low grinding rate, it is not easy to form depressions, so defects caused by the planarization process can be improved. At the same time, since the film quality of the insulating layer is strongly related to the growth temperature, the density of the first insulating layer in contact with the spacer layer is low, so the growth process of the first insulating layer has low temperature requirements, thereby reducing the impact on the spacer layer.
[0016] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.
[0018] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.
[0019] Figure 1 is a schematic structural diagram of a semiconductor device during the formation process provided by an embodiment of the present application;
[0020] Figure 2 is a schematic flow chart of a method for forming a semiconductor device provided in some embodiments of the present application;
[0021] Figure 3 to Figure 8 It is a schematic diagram of the structure of a semiconductor device during the formation process provided by some embodiments of the present application. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0023] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of a semiconductor device during the formation process provided by an embodiment of the present application.
[0024] In the embodiment, the method for forming the semiconductor device includes: forming a plurality of device structures 20 on a substrate 10, with a groove T between adjacent device structures 20; forming a spacer layer 30 in the groove T, wherein the surface of the spacer layer 30 is lower than the top surface 201 of the device structure 20 away from the substrate 10; and forming an insulating layer 40 on the surface of the spacer layer 30.
[0025] The insulating layer may include silicon dioxide, and the growth temperature of silicon dioxide is greater than 250°C. As the reaction temperature increases, the film quality of the insulating layer 40 will increase accordingly, and the etching rate and the chemical mechanical polishing rate will decrease, which can reduce the defects caused by the chemical mechanical polishing process. However, high temperature conditions are likely to affect the spacer layer 30.
[0026] Therefore, some embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a substrate and forming a plurality of device structures on the substrate, wherein there are grooves between adjacent device structures; forming a spacer layer in the groove, wherein the surface of the spacer layer is lower than the top surface of the device structure on a side away from the substrate; forming a first insulating layer on the surface of the spacer layer; forming a second insulating layer on the surface of the first insulating layer, wherein the density of the second insulating layer is greater than the density of the first insulating layer; and flattening the second insulating layer until the surface of the stacked structure is exposed.
[0027] Compared to Figure 1 Embodiments, some embodiments of the present application provide a method for forming a semiconductor device by forming a low-density first insulating layer in a groove, and forming a high-density second insulating layer on the first insulating layer. During the planarization process, due to the high density of the second insulating layer and the low grinding rate, it is not easy to form a depression, so the defects caused by the planarization process can be improved. At the same time, since the film quality of the insulating layer is strongly related to the growth temperature, the density of the first insulating layer in contact with the spacer layer is low, so the growth process of the first insulating layer has low temperature requirements, thereby reducing the impact on the spacer layer.
[0028] The following describes the method for forming a semiconductor device provided in some embodiments of the present application in combination with the process.
[0029] See also Figure 2 , Figure 2 1 is a schematic flow chart of a method for forming a semiconductor device provided in some embodiments of the present application, wherein the method for forming a semiconductor device comprises:
[0030] Step S1: providing a substrate;
[0031] Step S2: forming a plurality of device structures on the substrate, with grooves between adjacent device structures;
[0032] Step S3: forming a spacer layer in the groove;
[0033] Step S4: forming a first insulating layer on the surface of the spacer layer;
[0034] Step S5: forming a second insulating layer on the surface of the first insulating layer, wherein the density of the second insulating layer is greater than the density of the first insulating layer;
[0035] Step S6: performing a planarization process on the second insulating layer until the surface of the stacked structure is exposed.
[0036] The method for forming the semiconductor device is described below in conjunction with the structural diagram.
[0037] See also Figure 3 to Figure 8 , Figure 3 to Figure 8 It is a schematic diagram of the structure of a semiconductor device during the formation process provided by some embodiments of the present application.
[0038] Step S1: Provide a substrate 10, see Figure 3 .
[0039] In some embodiments, the substrate 10 may be a semiconductor substrate, for example, silicon (Si), germanium (Ge), a SiGe substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI).
[0040] Step S2: forming a plurality of device structures 20 on the substrate 10, with trenches T between adjacent device structures 20. Figure 3 .
[0041] In some embodiments, the method of forming the multiple device structures 20 includes: forming a device stack on a substrate 10; etching the device stack to form a plurality of trenches T spaced apart along a first direction X, wherein the trenches T separate the device stack into a plurality of device structures 20 spaced apart along the first direction X.
[0042] The trench T extends along a second direction Y, the second direction Y and the first direction X are both parallel to the surface of the substrate 10, and the second direction Y is different from the first direction X. For example, the first direction X may be perpendicular to the second direction Y, and the Z direction represents a direction perpendicular to X and Y.
[0043] In some embodiments, the device structure 20 includes a memory cell structure 21 and a conductive layer 22 located on a side of the memory cell structure 21 away from the substrate 10. The conductive layer 22 extends along the first direction X and serves as a bit line of the memory cell structure 21.
[0044] In some embodiments, the method for forming the semiconductor device includes: forming another conductive layer 23 between the substrate and the device structure 20. The another conductive layer 23 extends along the second direction Y and serves as a word line of the memory cell structure 21.
[0045] Taking the phase change memory as an example, the memory cell structure 21 may include a first electrode layer 211, a gate layer 212, a second electrode layer 213, a phase change memory layer 214, and a third electrode layer 215 in a stacked arrangement. The materials of the first electrode layer 211, the second electrode layer 213, and the third electrode layer 215 may be the same, and may include carbon; the material of the gate layer 212 may include ZnxTey, GexTey, NbxOy, SixAsy, AsxTey, etc. The material of the phase change memory layer 214 may include a material such as a chalcogenide-based material, which includes any one of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) forming Group VIA of the periodic table.
[0046] Taking a select-only memory as an example, the memory cell structure 21 may include a first electrode layer 211 , a gate layer 212 , and a second electrode layer 213 .
[0047] Step S3: forming a spacer layer 30 in the trench T, wherein the surface of the spacer layer 30 is lower than the top surface 201 of the device structure 20 away from the substrate 10, see Figure 3 and Figure 4 .
[0048] In some embodiments, Figure 4 As shown, the spacer layer 30 includes a heat insulating layer 31 and a sidewall protection layer 32. The method of forming the spacer layer 30 includes: forming the sidewall protection layer 32 on the sidewall of the device structure 20; and forming the heat insulating layer 31 between adjacent device structures 20 on the surface of the initial sidewall protection layer 32.
[0049] The surface of the side wall protection layer 32 is lower than the top surface 201 , and the surface of the heat insulation layer 31 is lower than the top surface 201 .
[0050] In some embodiments, the method for forming the sidewall protection layer 32 and the heat insulation layer 31 includes the following steps.
[0051] like Figure 3 As shown, an initial sidewall protection layer 32 a is formed on the sidewalls of the device structure 20 , and an initial thermal insulation layer 31 a is formed on the substrate 10 and on the surface of the device structure 20 .
[0052] like Figure 4 As shown, the initial thermal insulation layer 31a and the sidewall protection layer 32 are etched back to expose the top surface 201 of the device structure 20, and the sidewall protection layer 32 and the thermal insulation layer 31 are formed respectively, and the surface of the sidewall protection layer 32 and the surface of the thermal insulation layer 31 are both higher than or flush with the surface of the conductive layer 22 in contact with the storage unit structure 21.
[0053] That is, the etch-back process forms a top groove R between adjacent device structures 20 , and the sidewall protection layer 32 and the thermal insulation layer 31 are located below the top groove R.
[0054] It can be understood that the surface of the sidewall protection layer 32 refers to the upper surface of the sidewall protection layer 32 (i.e., the surface away from the substrate 10), and the surface of the thermal insulation layer 31 refers to the upper surface of the thermal insulation layer 31 (i.e., the surface away from the substrate 10). The surface of the conductive layer 22 in contact with the memory cell structure 21 refers to the lower surface of the conductive layer 22 (i.e., the surface close to the substrate 10).
[0055] Among them, the upper surface of the sidewall protection layer 32 and the upper surface of the thermal insulation layer 31 are both higher than or flush with the lower surface of the conductive layer 22, which can improve the protection effect of the sidewall protection layer 32 on the storage unit structure 21 and improve the thermal insulation effect between adjacent storage unit structures 21.
[0056] In some embodiments, the material of the sidewall protection layer 32 may include oxygen, silicon, nitrogen and hydrogen, and the material of the thermal insulation layer 31 may include oxygen, silicon and carbon. For example, the sidewall protection layer 32 may include SiO2 and Si x N y H z Alternating layered structure.
[0057] Step S4: forming a first insulating layer 41 on the surface of the spacer layer 30, see Figure 5 to Figure 7 .
[0058] It is understood that the first insulating layer 41 may contact all exposed surfaces of the spacer layer 30 , thereby playing a role in protecting the spacer layer 30 .
[0059] In some embodiments, step S4 includes: forming the first insulating layer 41 on the surface of the spacer layer 30 in the trench T.
[0060] like Figure 5 As shown, the surface of the first insulating layer 41 may be lower than the top surface 201 of the device structure 20 , that is, the first insulating layer 41 only covers the surface of the spacer layer 30 but does not fill the top groove R.
[0061] like Figure 6 As shown, the surface of the first insulating layer 41 may be flush with the top surface 201 of the device structure 20 .
[0062] In some embodiments, step S4 includes: forming the first insulating layer 41 in the trench T and on the surface of the device structure 20 .
[0063] like Figure 7 As shown, the surface of the first insulating layer 41 may be higher than the top surface 201 of the device structure 20 , that is, the first insulating layer 41 is still located on the top surface 201 of the device structure 20 .
[0064] In some embodiments, the process of forming the first insulating layer 41 includes a first deposition process having a first process temperature.
[0065] In some embodiments, the first process temperature is less than or equal to 250°C.
[0066] In some embodiments, the first deposition process includes a first plasma deposition process having a first radio frequency power.
[0067] Step S5: forming a second insulating layer 42 on the surface of the first insulating layer 41, wherein the density of the second insulating layer 42 is greater than the density of the first insulating layer 41, see Figure 5 to Figure 7 .
[0068] In some embodiments, step S5 includes: forming a second insulating layer 42 covering the first insulating layer 41 and the device structure 20 .
[0069] like Figure 5 and Figure 6 As shown, the second insulating layer 42 is formed on the surface of the first insulating layer 41 and the top surface 201 of the device structure 20 .
[0070] In some embodiments, step S5 includes: forming the second insulating layer 42 on the surface of the first insulating layer 41 .
[0071] like Figure 7 As shown, the second insulating layer 42 is formed on the surface of the first insulating layer 41 .
[0072] In some embodiments, the process of forming the second insulating layer 42 includes a second deposition process, the second deposition process has a second process temperature, and the second process temperature is higher than the first process temperature.
[0073] Since the first insulating layer 41 can isolate the sidewall protection layer 32 from the second insulating layer 42 and the heat insulating layer 31 from the second insulating layer 42 , the influence of the high temperature growth process of the second insulating layer 42 on the sidewall protection layer 32 and the heat insulating layer 31 can be reduced.
[0074] In some embodiments, the second process temperature may be greater than 250°C.
[0075] In some embodiments, the second deposition process includes a second plasma deposition process, the second plasma deposition process has a second radio frequency power, and the second radio frequency power is greater than the first radio frequency power. In this way, the oxygen activity is low when the first insulating layer 41 is formed, and it is not easy to react with the sidewall protection layer 32 and the thermal insulation layer 31; at the same time, the oxygen activity is high when the second insulating layer 42 is formed, the film quality is better, the density is higher, and the hardness is higher, which is conducive to the subsequent planarization process.
[0076] In some embodiments, the material of the first insulating layer 41 may include silicon dioxide, and the material of the second insulating layer 42 may also include silicon dioxide. Due to different temperature conditions and radio frequency powers, the density of the second insulating layer 42 may be greater than the density of the first insulating layer 41, and the hardness of the second insulating layer 42 may be greater than the hardness of the first insulating layer 41, thereby reducing the depth of the recess in a subsequent planarization process.
[0077] In some embodiments, the material of the first insulating layer 41 is the same as the material of the second insulating layer 42 , for example, both may be silicon dioxide.
[0078] Growing a silicon dioxide layer on the thermal insulation layer at a high temperature (second process temperature) will cause severe oxidation of the thermal insulation layer during the growth process, while low temperature will only slightly oxidize the thermal insulation layer. Therefore, the method for forming a semiconductor device provided in the embodiment of the present application can reduce the modification of the thermal insulation layer and improve the stability of the thermal insulation layer composition and the stability of the thermal insulation performance by adopting a first process temperature lower than the second process temperature.
[0079] The silicon dioxide layer grown by high temperature (second process temperature) is more likely to damage the sidewall protection layer 32 due to the increase of O activity, and oxygen ions are more likely to penetrate the sidewall protection layer 32 to affect the bottom storage unit structure 21. The growth of the silicon dioxide layer under low temperature (second process temperature) is more friendly to the sidewall protection layer 32 and the bottom storage unit structure 21, with lower damage, and basically no impact on the storage unit structure 21. Therefore, the method for forming a semiconductor device provided in the embodiment of the present application can reduce the damage to the sidewall protection layer 32 and reduce the impact on the storage unit structure 21 by adopting a first process temperature lower than the second process temperature.
[0080] Step S6: Planarize the second insulating layer 42 until the surface of the device structure is exposed. Figure 8 .
[0081] It can be understood that the second insulating layer 42 is planarized until the surface of the stacked structure is exposed, which means that the second insulating layer 42 formed in step S5 will cover the upper part of the device structure 20 .
[0082] In some embodiments, the planarization process includes a chemical mechanical polishing process. It is understandable that in actual processes, the chemical mechanical polishing process is prone to cause concavity problems due to different film stresses at different locations. Figure 8 A recess is formed in the remaining portion of the first insulating layer 41.
[0083] Since the object to be polished includes the second insulating layer 42 with a higher density, the hardness of the second insulating layer 42 is relatively high and the polishing rate is relatively low, the concavity problem caused by the chemical mechanical polishing process can be improved.
[0084] In some embodiments, Figure 5 After the structure in the embodiment is planarized, the top groove R may include the remaining first insulating layer 41 and the remaining second insulating layer 42 (eg Figure 8 shown).
[0085] In some embodiments, Figure 6 and Figure 7 After the structure in the embodiment is planarized, the top groove R may include a remaining portion of the first insulating layer 41 .
[0086] like Figure 7 As shown, the first insulating layer 41 is also located on the surface of the device structure 20, and the surface of the first insulating layer 41 is higher than the top surface 201 of the device structure 20. In step S6, the planarization process is also performed on the first insulating layer 41 until the surface of the device structure 20 is exposed.
[0087] After step S6 , the method for forming a semiconductor device may further include: forming an upper device structure on the device structure 20 .
[0088] The method for forming the upper device structure can refer to the method for forming the device structure 20 described in the above embodiment, and the formation method includes an etching process, which can easily etch the insulating layer 40 in the top groove R, thereby affecting the insulating layer below, and then affecting the spacer layer 30 below the insulating layer, and even the device structure 20 of the lower layer.
[0089] In some embodiments, Figure 8 As shown, the top groove R comprises the first insulating layer 41 and the second insulating layer 42. Since the etching rate of the second insulating layer 42 is low, it is not easy to cause over-etching in the subsequent etching process of forming the upper device structure, that is, the etching depth of the insulating layer 40 in the top groove R is small, thereby strengthening the protection of the underlying thermal insulation layer and the sidewall protection layer 32, and further strengthening the protection of the underlying device structure 20.
[0090] The silicon dioxide layer grown at the second process temperature has a low etching rate and a low chemical mechanical polishing rate. The silicon dioxide layer grown at the first process temperature has a low film quality, resulting in an increased etching rate and chemical mechanical polishing rate, which easily causes a large recess depth and subsequent over-etching problems.
[0091] Based on this principle, in some embodiments of the present application, a method for forming a semiconductor device is provided, in which a second insulating layer 42 is formed on the surface of the first insulating layer 41 at a second process temperature. Since the chemical mechanical polishing rate is low, the depth of the recess formed by the chemical mechanical polishing can be reduced. Since the etching rate of the second insulating layer 42 is low, in some embodiments, the etching depth of the insulating layer 40 (including the first insulating layer 41 and the second insulating layer 42) in the top groove R is relatively small, so that the protection of the lower side wall protection layer 32 and the thermal insulation layer 31 can be strengthened.
[0092] Some embodiments of the present application provide a method for forming a semiconductor device, which reduces the modification of the thermal insulation layer and the damage to the sidewall protection layer 32 by making the first insulating layer 41 in contact with the sidewall protection layer 32 and the thermal insulation layer have a lower density and makes the main object of the planarization treatment (the second insulating layer 42) have a higher density, thereby ensuring the normal operation of the storage unit structure 21 and improving the defects caused by the planarization treatment process.
[0093] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0095] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.
[0096] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of device structures on the substrate, with grooves between adjacent device structures; forming a spacer layer in the trench, wherein a surface of the spacer layer is lower than a top surface of a side of the device structure away from the substrate; forming a first insulating layer on the surface of the spacer layer; forming a second insulating layer on the surface of the first insulating layer, wherein the density of the second insulating layer is greater than the density of the first insulating layer; At least the second insulating layer is planarized until the surface of the device structure is exposed.
2. The method for forming a semiconductor device according to claim 1, wherein: The process of forming the first insulating layer includes a first deposition process, wherein the first deposition process has a first process temperature; The process of forming the second insulating layer includes a second deposition process, the second deposition process has a second process temperature, and the second process temperature is higher than the first process temperature.
3. The method for forming a semiconductor device according to claim 2, wherein: The first process temperature is less than or equal to 250°C; the second process temperature is greater than 250°C.
4. The method for forming a semiconductor device according to claim 2, wherein: The first deposition process includes a first plasma deposition process having a first radio frequency power; the second deposition process includes a second plasma deposition process having a second radio frequency power, and the second radio frequency power is greater than the first radio frequency power.
5. The method for forming a semiconductor device according to claim 1, wherein: The material of the first insulating layer includes silicon oxide; the material of the second insulating layer includes silicon oxide.
6. The method for forming a semiconductor device according to claim 1, wherein: The hardness of the first insulating layer is smaller than the hardness of the second insulating layer.
7. The method for forming a semiconductor device according to claim 1, wherein: The method of forming a first insulating layer on the surface of the spacer layer and forming a second insulating layer on the surface of the first insulating layer comprises: forming the first insulating layer on the surface of the spacer layer in the groove; A second insulating layer is formed covering the first insulating layer and the device structure.
8. The method for forming a semiconductor device according to claim 1, wherein: The method of forming a first insulating layer on the surface of the spacer layer and forming a second insulating layer on the surface of the first insulating layer comprises: forming the first insulating layer in the trench and on the surface of the device structure; forming the second insulating layer on the surface of the first insulating layer; The planarization process is also performed on the first insulating layer until the surface of the device structure is exposed.
9. The method for forming a semiconductor device according to claim 1, wherein: The spacer layer includes a heat insulation layer and a side wall protection layer, and the method for forming the spacer layer includes: forming the sidewall protection layer on the sidewall of the device structure; The heat insulation layer located between adjacent device structures is formed on the surface of the sidewall protection layer.
10. The method for forming a semiconductor device according to claim 8, wherein: The material of the sidewall protection layer includes oxygen, silicon, nitrogen and hydrogen, and the material of the heat insulation layer includes oxygen, silicon and carbon.