Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The embodiment of the present invention discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a unit cell located in the core area of ​​the device, a first electrode structure and a second electrode structure; the unit cell includes a first region, and the unit cell also includes a first surface and a second surface arranged opposite to each other; the first region is arranged on the first surface; the first electrode structure is located on the first surface; the first electrode structure and the first region are electrically connected; a blocking structure is arranged at the edge of the first electrode structure, and the blocking structure is used to buffer stress and block stress propagation; the second electrode structure is located on the second surface. The technical solution of the embodiment of the present invention reduces the internal stress of the semiconductor device, prevents the semiconductor device from cracking, and improves the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] However, during the manufacturing and packaging process of silicon carbide semiconductor devices or gallium nitride semiconductor devices, stress concentration occurs due to factors such as temperature changes, differences in material properties, and manufacturing processes. This stress may cause physical damage to the chip, such as cracks, which in turn affects the performance and reliability of the chip. Therefore, how to reduce the internal stress of semiconductor devices has become one of the research focuses. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle, so as to reduce the internal stress of the semiconductor device, prevent the semiconductor device from cracking, and improve the reliability of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising:

[0006] A unit cell, a first electrode structure and a second electrode structure located in the core area of ​​the device; the unit cell includes a first region, and the unit cell also includes a first surface and a second surface arranged opposite to each other; the first region is arranged on the first surface;

[0007] The first electrode structure is located on the first surface; the first electrode structure is electrically connected to the first region; a blocking structure is provided at the edge of the first electrode structure, and the blocking structure is used to buffer stress and block stress propagation;

[0008] The second electrode structure is located on the second surface.

[0009] Optionally, the first electrode structure includes a first electrode, an insulating layer and a second electrode;

[0010] The first electrode is located on the first surface;

[0011] The insulating layer is located at a side of the first electrode away from the first surface, and the insulating layer is provided with a contact hole;

[0012] The second electrode is located on a side of the insulating layer away from the first electrode and reaches the first electrode through the contact hole;

[0013] The blocking structure is located at an edge of the first electrode; and / or the blocking structure is located at an edge of the second electrode.

[0014] Optionally, the blocking structure includes a first blocking unit, and the first blocking unit is located on a side surface of the first electrode and / or a side surface of the second electrode.

[0015] Optionally, the first blocking unit includes a toothed structure, and the toothed structure includes a plurality of protrusions arranged at intervals.

[0016] Optionally, the blocking structure further includes a second blocking unit, the second blocking unit is located on a side of the first electrode away from the first surface; and / or the second blocking unit is located on a side of the second electrode away from the insulating layer.

[0017] Optionally, the second blocking unit includes at least one groove, and the groove is arranged around an edge of the first electrode and / or an edge of the second electrode.

[0018] Optionally, the semiconductor device further includes a first common electrode wiring, the first common electrode wiring is located in a terminal area surrounding the core area of ​​the device, and the first common electrode wiring includes a surrounding portion and a connecting portion;

[0019] The surrounding portion is arranged around the edge of the second electrode and is spaced apart from the second electrode;

[0020] The connecting portion is used to connect the surrounding portion and the second electrode;

[0021] The unit cell includes a silicon carbide Schottky diode unit cell or a gallium nitride Schottky diode unit cell;

[0022] The first electrode includes an anode;

[0023] The second electrode structure includes a cathode.

[0024] Optionally, the semiconductor device further includes a first common electrode wiring and a second common electrode wiring; the first common electrode wiring and the second common electrode wiring are located in a terminal area surrounding the core area of ​​the device;

[0025] The first common electrode wiring includes a surrounding portion and a connecting portion; the surrounding portion is arranged around the edge of the second electrode and is spaced apart from the second electrode; the connecting portion is used to connect the surrounding portion and the second electrode;

[0026] The second common electrode wiring is located between the surrounding portion and the second electrode, and is insulated from the first electrode and the second electrode;

[0027] The unit cell includes a silicon carbide metal-oxide semiconductor field effect transistor unit cell, or a gallium nitride metal-oxide semiconductor field effect transistor unit cell;

[0028] The first electrode is a source electrode;

[0029] The semiconductor device further includes a third electrode structure, the third electrode structure is located on the first surface or extends from the first surface into the unit cell, the third electrode structure includes a dielectric insulating layer and a gate electrode, and the second common electrode wiring is connected to the gate electrode of the unit cell;

[0030] The second electrode structure includes a drain electrode.

[0031] Optionally, the first electrode structure also includes a redundant insulating layer and a redundant second electrode, the redundant insulating layer is located on a side of the second electrode away from the insulating layer, the redundant second electrode is located on a side of the redundant insulating layer away from the second electrode, the redundant insulating layer, the second electrode and the insulating layer are provided with redundant contact holes, the redundant second electrode reaches the first electrode through the redundant contact holes; the redundant second electrode and the second electrode are insulated.

[0032] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0033] A unit cell is formed in the core area of ​​the device, wherein the unit cell includes a first region, and the unit cell also includes a first surface and a second surface that are arranged opposite to each other; the first region is arranged on the first surface;

[0034] A first electrode structure is formed on the first surface, the first electrode structure is electrically connected to the first region; a blocking structure is arranged at the edge of the first electrode structure, the blocking structure is used to buffer stress and block stress propagation;

[0035] A second electrode structure is formed on the second surface.

[0036] Optionally, forming a first electrode structure on the first surface includes:

[0037] forming a first electrode on the first surface;

[0038] forming a blocking structure at an edge of the first electrode;

[0039] An insulating layer is formed on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole;

[0040] forming a second electrode on a side of the insulating layer away from the first electrode, the second electrode reaching the first electrode through the contact hole;

[0041] or,

[0042] forming a first electrode on the first surface;

[0043] An insulating layer is formed on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole;

[0044] forming a second electrode on a side of the insulating layer away from the first electrode, the second electrode reaching the first electrode through the contact hole;

[0045] forming a blocking structure at an edge of the second electrode;

[0046] or,

[0047] forming a first electrode on the first surface;

[0048] forming a blocking structure at an edge of the first electrode;

[0049] An insulating layer is formed on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole;

[0050] forming a second electrode on a side of the insulating layer away from the first electrode, the second electrode reaching the first electrode through the contact hole;

[0051] A blocking structure is formed at an edge of the second electrode.

[0052] Optionally, forming the blocking structure at an edge of the first electrode and / or an edge of the second electrode includes:

[0053] Optionally, a first blocking unit is formed on a side surface of the first electrode and / or a side surface of the second electrode.

[0054] Optionally, forming a first blocking unit on a side of the first electrode includes:

[0055] A tooth-like structure is formed on a side surface of the first electrode and / or a side surface of the second electrode, wherein the tooth-like structure includes a plurality of protrusions arranged at intervals.

[0056] Forming a tooth-shaped structure on a side surface of the first electrode and / or a side surface of the second electrode comprises:

[0057] Spin-coating a photoresist on the side of the first electrode;

[0058] Expose and develop the photoresist, perform thermal hardening on the photoresist, and solidify the patterned photoresist;

[0059] Performing dry etching on the side surface of the first electrode to form a plurality of protrusions arranged at intervals;

[0060] removing the photoresist;

[0061] and / or, spin coating a photoresist on the side of the second electrode;

[0062] Expose and develop the photoresist, perform thermal hardening on the photoresist, and solidify the patterned photoresist;

[0063] performing dry etching on the side surface of the second electrode to form a plurality of protrusions arranged at intervals;

[0064] The photoresist is removed.

[0065] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used for carrying the semiconductor device.

[0066] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0067] The power conversion circuit comprises a circuit board and at least one of the semiconductor devices mentioned above, and the semiconductor device is electrically connected to the circuit board.

[0068] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0069] In the semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiments of the present invention, during the manufacturing process of the first electrode structure electrically connected to the first region, stress concentration is likely to occur inside the first electrode structure due to factors such as temperature changes, differences in material properties and manufacturing processes. A graphical process is usually required to obtain a first electrode structure of a preset shape, and the edge of the first electrode structure is likely to introduce stress generation points. A blocking structure is provided at the edge of the first electrode structure, which is used to buffer stress and block stress propagation, so that the streamline of the movement trajectory of stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure, thereby preventing the first electrode structure and even the entire semiconductor device from cracking, and preventing defects in the first region, thereby improving the reliability of the semiconductor device.

[0070] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0072] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0073] Figure 2 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0074] Figure 3 yes Figure 1 and Figure 2 A schematic diagram of a top view structure of a part of the area;

[0075] Figure 4 is a schematic structural diagram of a blocking structure located at a partial edge of a first electrode in an SBD semiconductor device provided according to an embodiment of the present invention;

[0076] Figure 5 is a schematic structural diagram of a SBD semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a second electrode;

[0077] Figure 6 is a schematic structural diagram of a MOSFET semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a first electrode;

[0078] Figure 7 is a schematic structural diagram of a MOSFET semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a second electrode;

[0079] Figure 8 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0080] Fig. 9 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0081] Fig.10 is a stress cloud diagram of a semiconductor device provided by an embodiment of the present invention in which a tooth-shaped structure is arranged on the side of the first electrode structure;

[0082] Fig.11 A stress cloud diagram of a semiconductor device in the prior art in which no tooth-shaped structure is provided on the side of the first electrode structure;

[0083] Fig.12 yes Fig.10 and Fig.11 Schematic diagram of distribution curves of stress trajectories corresponding to the two structures propagating from the stress generating point of the cloud diagram to the side of the first electrode structure;

[0084] Fig.13 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0085] Figure 14-Figure 20It is a cross-sectional view corresponding to the steps of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0086] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0087] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0088] In order to reduce the internal stress of semiconductor devices, prevent the semiconductor devices from cracking, and improve the reliability of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0089] Figure 1 It is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention. Figure 2 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention. Figure 3 yes Figure 1 and Figure 2 A schematic diagram of the top view of some areas in the structure. Figure 1 and Figure 2 As shown, the semiconductor device includes: a unit cell 100 located in the device core area 200, a first electrode structure 300 and a second electrode structure 400, the unit cell 100 includes a first region 30, and the unit cell 100 also includes a first surface 101 and a second surface 102 arranged opposite to each other; the first region 30 is arranged on the first surface 101; the first electrode structure 300 is located on the first surface 101; the first electrode structure 300 and the first region 30 are electrically connected; Figure 3As shown, a blocking structure 70 is disposed at the edge of the first electrode structure 300 , and the blocking structure 70 is used to buffer stress and block stress propagation; the second electrode structure 400 is located on the second surface 102 .

[0090] It should be noted that Figure 3 The dotted line box area is the entire device core area 200. Figure 3 The upper left corner is part of the entire device core area 200. Therefore, Figure 3 Only a partial edge of the first electrode structure 300 is shown. Figure 3 The area pointed by the red arrow is an enlarged view of the red framed area.

[0091] In an embodiment of the present invention, a semiconductor device includes a plurality of unit cells. Figure 1 The Schottky barrier diode (Schottky Barrier Diode, SBD) shown in FIG. 1 is a semiconductor structure that realizes the electrical function of the Schottky barrier diode. Alternatively, the semiconductor device of the embodiment of the present invention includes Figure 2 The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) shown is a semiconductor structure that realizes the electrical function of MOSFET.

[0092] exist Figure 1 In the illustrated SBD semiconductor device, taking an N-type SBD semiconductor device as an example, the first region 30 is a P+ active region, the first electrode structure 300 is used to access an anode electrical signal, and the second electrode structure 400 is used to access a cathode electrical signal.

[0093] Figure 2 In the MOSFET semiconductor device shown, taking an N-type MOSFET semiconductor device as an example, the first region 30 includes an N+ active region 301 and a P+ active region 302, and the first electrode structure 300 is used to access the source electrical signal. The second electrode structure 400 is used to access the drain electrical signal. In the MOSFET semiconductor device, the first surface 101 of the unit cell 100 also includes a body region 303. The semiconductor structure also includes a third electrode structure 900, and the third electrode structure 900 is used to access the gate electrical signal. The third electrode structure 900 includes a dielectric insulating layer 901 and a gate electrode 902, and the interlayer insulating layer 903 is used to insulate the third electrode structure 900 and the first electrode structure 300. In other embodiments, the first region 30 may also include only the N+ active region 301. Figure 2The planar MOSFET semiconductor device is shown. In other embodiments, a single trench or double trench MOSFET semiconductor device is also included. In the single trench MOSFET semiconductor device, the third electrode structure 900 is a trench structure. In the double trench MOSFET semiconductor device, the third electrode structure 900 is a trench structure, and the first electrode structure 300 is a trench structure.

[0094] For example, Figure 1 and Figure 2 In the present invention, the unit cell 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the unit cell 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the unit cell 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0095] In the technical solution provided by the embodiment of the present invention, during the manufacturing process of the first electrode structure 300 electrically connected to the first region 30, stress concentration is likely to occur inside the first electrode structure 300 due to factors such as temperature changes, differences in material properties and manufacturing processes. And a graphic process is usually required to obtain the first electrode structure 300 of a preset shape, and the edge of the first electrode structure 300 is likely to introduce stress generation points. A blocking structure 70 is provided at the edge of the first electrode structure 300, and the blocking structure 70 is used to buffer stress and block stress propagation, so that the streamline of the movement trajectory of stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0096] Optionally, based on the above technical solution, Figure 1 and Figure 2 As shown, the first electrode structure 300 includes a first electrode 40, an insulating layer 50 and a second electrode 60; the first electrode 40 is located on the first surface 101; the insulating layer 50 is located on the side of the first electrode 40 away from the first surface 101, and the insulating layer 50 is provided with a contact hole 80; the second electrode 60 is located on the side of the insulating layer 50 away from the first electrode 40, and reaches the first electrode 40 through the contact hole 50; the blocking structure 70 is located at the edge of the first electrode 40; and / or, the blocking structure 70 is located at the edge of the second electrode 60.

[0097] exist Figure 1In the illustrated SBD semiconductor device, the first electrode 40 is an anode, and the second electrode 60 is used to obtain an anode electrical signal, which reaches the first electrode 40 through a contact hole 80 and transmits the anode electrical signal to the first region 30 .

[0098] Figure 2 In the MOSFET semiconductor device shown, the first electrode 40 is a source, and the second electrode 60 is used to obtain a source electrical signal, which reaches the first electrode 40 through a contact hole 80 and transmits the source electrical signal to the first region 30 .

[0099] Specifically, in the first electrode structure 300, part of the second electrode 60 is located in the contact hole 80 of the insulating layer 50. Figure 2 The first electrode 40 is located on one side of the interlayer insulating layer 903. The opening etched in the interlayer insulating layer 903 is used to place the first electrode 40, and the contact hole 80 is used to place the second electrode 60. Therefore, during the manufacturing process of the first electrode 40 and the second electrode 60, due to factors such as temperature changes, material property differences, and etching processes, stress concentration is likely to occur on the side of the first electrode 40 close to the interlayer insulating layer 903 and on the side of the second electrode 60 located at the contact hole 80. And a graphic process is usually required to obtain the first electrode 40 and the second electrode 60 of a preset shape, and the edges of the first electrode 40 and the second electrode 60 are likely to introduce stress generation points. A blocking structure 70 is provided at the edge of the first electrode 40 or the edge of the second electrode 60 or the edges of the first electrode 40 and the second electrode 60. The blocking structure 70 is used to buffer stress and block stress propagation, so that the movement trajectory of stress is streamlined, which has the effect of reducing local stress and reducing the stress intensity of internal stress concentration points. It can also prevent cracks from extending to stress concentration points inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0100] in, Figure 4 It is a schematic structural diagram of a blocking structure located at a partial edge of a first electrode in an SBD semiconductor device provided according to an embodiment of the present invention. Figure 5 It is a schematic structural diagram of a SBD semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a second electrode. Figure 6 It is a schematic structural diagram of a MOSFET semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a first electrode. Figure 7 It is a schematic structural diagram of a MOSFET semiconductor device provided according to an embodiment of the present invention in which a blocking structure is located at a partial edge of a second electrode.

[0101] It should be noted that Figure 4-Figure 7 1 is a schematic diagram of a top view of a part of the device core region 200 . Figure 4-Figure 7 The dotted line box area is the entire device core area 200. Figure 4-Figure 7 The upper left corner is part of the entire device core area 200. Therefore, Figure 4 and Figure 6 Only a portion of the edge of the first electrode 40 is shown. Figure 5 and Figure 7 Only a portion of the edge of the second electrode 60 is shown.

[0102] refer to Figure 4 and Figure 5 as well as Figure 6 and Figure 7 The blocking structure 70 includes a first blocking unit 701 , and the first blocking unit 701 is located on a side of the first electrode 40 and / or a side of the second electrode 60 .

[0103] in, Figure 4 and Figure 6 In the embodiment, the first barrier unit 701 is located on the side of the first electrode 40 . Figure 5 and Figure 7 In the embodiment, the first barrier unit 701 is located on the side of the second electrode 60 .

[0104] Specifically, the side of the first electrode 40 is prone to introduce stress generation points. The first blocking unit 701 is located on the side of the first electrode 40. The first blocking unit 701 is used to buffer stress and block the stress from propagating on the side of the first electrode 40, so that the movement trajectory of the stress is streamlined, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0105] The side of the second electrode 60 is prone to introduce stress generation points. The first blocking unit 701 is located on the side of the second electrode 60. The first blocking unit 701 is used to buffer the stress and block the stress from propagating on the side of the second electrode 60, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0106] The sides of the first electrode 40 and the second electrode 60 are prone to introduce stress generating points. The first blocking unit 701 is located on the sides of the first electrode 40 and the second electrode 60. The first blocking unit 701 is used to buffer stress and block the stress from propagating on the sides of the first electrode 40 and the second electrode 60, so that the streamline of the stress movement trajectory is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0107] Based on the above technical solution, Figure 4 and Figure 5 as well as Figure 6 and Figure 7 The first blocking unit 701 includes a tooth-like structure, and the tooth-like structure includes a plurality of protrusions 703 arranged at intervals.

[0108] Among them, reference Figure 4 and Figure 6 The protrusions 703 are arranged at intervals on the side of the first electrode 40. Figure 5 and Figure 7 The protrusions 703 are arranged at intervals on the side surfaces of the second electrode 60 .

[0109] Specifically, the protrusions 703 are arranged at intervals on the side of the first electrode 40, which increases the length of the side of the first electrode 40, so that the first blocking unit 701 has the effect of buffering stress and blocking the stress from propagating on the side of the first electrode 40, making the stress movement trajectory streamline smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0110] The protrusions 703 are arranged at intervals on the side of the second electrode 60, which increases the length of the side of the second electrode 60, so that the first blocking unit 701 has the effect of buffering stress and blocking the stress from propagating on the side of the second electrode 60, making the stress movement trajectory streamline smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0111] The protrusion 703 is arranged at intervals on the side of the first electrode 40 and the side of the second electrode 60, which increases the length of the side of the first electrode 40 and the side of the second electrode 60, so that the first blocking unit 701 has the effect of buffering stress and blocking the stress from propagating on the side of the first electrode 40 and the side of the second electrode 60, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0112] The edge of the protrusion 703 may be surrounded by a straight line or a curved line, which is not limited in the embodiment of the present invention.

[0113] Among them, the protrusions 703 are arranged at intervals, and the length and width of the protrusions 703 can be set to 2-6μm, the length and width of the area 702 between the two protrusions 703 can also be set to 2-6μm, and the length and width of multiple protrusions 703 and the area 702 between multiple protrusions 703 are set to the same size, which can simplify the preparation process of the toothed structure and improve the preparation efficiency of semiconductor devices.

[0114] Optionally, based on the above technical solution, refer to Figure 4 and Figure 5 as well as Figure 6 and Figure 7 The blocking structure 70 further includes a second blocking unit 704 , which is located on a side of the first electrode 40 away from the first surface 101 ; and / or, the second blocking unit 704 is located on a side of the second electrode 60 away from the insulating layer 50 .

[0115] In the embodiment of the present invention, the second blocking unit 704 is different from the first blocking unit 701 , and is located on a side of the first electrode 40 away from the first surface 101 ; and / or, the second blocking unit 704 is located on a side of the second electrode 60 away from the insulating layer 50 .

[0116] Among them, reference Figure 4 and Figure 6 , the second blocking unit 704 is located on a side of the first electrode 40 away from the first surface 101. Figure 5 and Figure 7 , the second blocking unit 704 is located on a side of the second electrode 60 away from the insulating layer 50 .

[0117] Specifically, the second blocking unit 704 is located on the side of the first electrode 40 away from the first surface 101. The second blocking unit 704 has the effect of buffering stress and blocking the stress from propagating from the edge of the first electrode 40 on the side away from the first surface 101 to the central area of ​​the device core area 200, so that the movement trajectory of the stress is streamlined, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first area 30, thereby improving the reliability of the semiconductor device.

[0118] The second blocking unit 704 is located on the side of the second electrode 60 away from the insulating layer 50. The second blocking unit 704 has the effect of buffering stress and blocking the stress from propagating from the edge of the second electrode 60 on the side away from the insulating layer 50 to the central area of ​​the device core area 200, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first area 30, thereby improving the reliability of the semiconductor device.

[0119] The second blocking unit 704 is located on a side of the first electrode 40 away from the first surface 101, and the second blocking unit 704 is located on a side of the second electrode 60 away from the insulating layer 50. The second blocking unit 704 has the effect of buffering stress and blocking stress from propagating from the edge to the central area of ​​the device core area 200 on the side of the first electrode 40 away from the first surface 101 and the side of the second electrode 60 away from the insulating layer 50, so that the streamline of the stress movement trajectory is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0120] Optionally, based on the above technical solution, Figure 4 and Figure 5 as well as Figure 6 and Figure 7As shown, the second blocking unit 704 includes at least one groove, and the groove is arranged around the edge of the first electrode 40 and / or the edge of the second electrode 60. Among them, one groove is shown in the figure as an example. The more the number of grooves, the more significant the effect of the second blocking unit 704 in buffering stress and blocking stress from propagating from the edge to the central area of ​​the device core area 200 on the side of the first electrode 40 away from the first surface 101 and / or the side of the second electrode 60 away from the insulating layer 50. The depth of the groove is less than the thickness of the first electrode 40 and the second electrode 60.

[0121] It should be noted that the first barrier unit 701 and the second barrier unit 704 in the embodiment of the present invention can be prepared by photolithography and etching.

[0122] Optionally, based on the above technical solution, Figure 8 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention. Fig. 9 FIG. 1 is a schematic diagram of a structure of another semiconductor device provided according to an embodiment of the present invention. Figure 8 and Fig. 9 The first electrode structure 300 further includes a redundant insulating layer 51 and a redundant second electrode 61. The redundant insulating layer 51 is located on a side of the second electrode 60 away from the insulating layer 50. The redundant second electrode 61 is located on a side of the redundant insulating layer 51 away from the second electrode 60. The redundant insulating layer 51, the second electrode 60 and the insulating layer 50 are provided with a redundant contact hole 81. The redundant second electrode 61 reaches the first electrode 40 through the redundant contact hole 81. The redundant second electrode 61 and the second electrode 60 are insulated. For example, Figure 6 and Figure 7 As shown, a hole wall insulating layer 82 is disposed on the side wall of the redundant contact hole 81 , and the hole wall insulating layer 82 is used to achieve the insulating setting of the redundant second electrode 61 and the second electrode 60 .

[0123] Specifically, when cracks appear on the second electrode 60 due to strong stress, the redundant second electrode 61 can be used to replace the second electrode 60 to access the electrical signal.

[0124] refer to Figure 5 The semiconductor device further includes a first common electrode wiring L1, which is located in the terminal area surrounding the device core area 200, and includes a surrounding portion 801 and a connecting portion 802; the surrounding portion 801 is arranged around the edge of the second electrode 60 and is spaced apart from the second electrode 60; the connecting portion 802 is used to connect the surrounding portion 801 and the second electrode 60; the unit cell 100 includes a silicon carbide Schottky diode unit cell or a gallium nitride Schottky diode unit cell; the first electrode 40 includes an anode; and the second electrode structure 400 includes a cathode. Figure 4In the embodiment, the first common electrode wiring L1 and the first electrode 40 are insulated from each other.

[0125] Specifically, for a semiconductor device including a silicon carbide Schottky diode unit cell or a gallium nitride Schottky diode unit cell, the first common electrode wiring L1 is used to provide an electrical signal to the second electrode 60 , so as to provide an anode electrical signal to the semiconductor device.

[0126] Optionally, based on the above technical solution, see Figure 7 The semiconductor device further comprises a first common electrode wiring L1 and a second common electrode wiring L2; the first common electrode wiring L1 and the second common electrode wiring L2 are located in a terminal area surrounding the device core area 200; the first common electrode wiring L1 comprises a surrounding portion 801 and a connecting portion 802; the surrounding portion 801 is arranged around the edge of the second electrode 60 and is spaced apart from the second electrode 60; the connecting portion 802 is used to connect the surrounding portion 801 and the second electrode 60; the second common electrode wiring L2 is located between the surrounding portion 801 and the second electrode 60 and is spaced apart from the first electrode 40 The second electrode 60 is insulated; the unit cell 100 includes a silicon carbide metal-oxide semiconductor field effect transistor unit cell, or a gallium nitride metal-oxide semiconductor field effect transistor unit cell; the first electrode 40 is a source; the semiconductor device also includes a third electrode structure 900, the third electrode structure 900 is located on the first surface 101 or extends from the first surface 101 to the unit cell 100, the third electrode structure 900 includes a dielectric insulating layer 901 and a gate electrode 902, and the second common electrode trace L2 is connected to the gate electrode 902 of the unit cell; the second electrode structure 400 includes a drain. Among them, Figure 6 In the embodiment, the first common electrode wiring L1 and the first electrode 40 are insulated from each other.

[0127] Specifically, for a semiconductor device including a silicon carbide metal-oxide semiconductor field effect transistor unit cell, or a gallium nitride metal-oxide semiconductor field effect transistor unit cell, the first common electrode wiring L1 is used to provide an electrical signal to the second electrode 60 to provide a source electrical signal to the semiconductor device, and the second common electrode wiring L2 is used to provide an electrical signal to the gate electrode 902 to provide a gate electrical signal to the semiconductor device.

[0128] Fig.10 This is a stress cloud diagram of a semiconductor device provided by an embodiment of the present invention in which a tooth-shaped structure is arranged on the side of the first electrode structure. Fig.11 It is a stress cloud diagram of a semiconductor device in the prior art in which no tooth-shaped structure is provided on the side of the first electrode structure. Fig.12 yes Fig.10 and Fig.11 Schematic diagram of distribution curves of stress trajectories corresponding to the two structures propagating from the stress generating point of the cloud diagram to the side of the first electrode structure.

[0129] in, Fig.12 The data corresponding to point A0 is the coordinate of the stress occurrence point, and the stress trajectory from point A0 to point A1 corresponds to Fig.10 and Fig.11 The corresponding stress change when the stress generating point propagates from top to bottom. Fig.12 It can be seen that the first blocking unit 701 of the toothed structure represented by the blue curve is arranged on the side of the first electrode structure 300, which increases the length of the side of the first electrode structure 300, so that the first blocking unit 701 has the effect of buffering stress and blocking the propagation of stress on the side of the first electrode 40, and quickly prevents the stress propagation downward from the stress generating point, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 or even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device. Among them, when the stress propagates to the X0 position of the horizontal axis, the stress value of point A2 of the blue curve is less than the stress value of point A3 of the green curve.

[0130] Optionally, the unit cell 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0131] The unit cell 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The unit cell 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0132] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0133] Fig.13 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig.13 As shown, the method for manufacturing the semiconductor device includes:

[0134] S110, forming a unit cell in the core area of ​​the device, the unit cell comprising a first region, and the unit cell further comprising a first surface and a second surface arranged opposite to each other; the first region is arranged on the first surface.

[0135] The semiconductor device formed by the embodiment of the present invention includes Figure 1 Alternatively, the semiconductor device formed by the embodiment of the present invention includes Figure 2 MOSFET shown.

[0136] refer to Fig.14 and Fig.15 A unit cell 100 is formed in the device core region 200 , and the unit cell 100 includes a first region 30 . The unit cell 100 also includes a first surface 101 and a second surface 102 that are oppositely disposed. The first region 30 is disposed on the first surface 101 . Fig.14 Taking the formation of an N-type SBD semiconductor device as an example, the first region 30 is a P+ active region. Fig.15 Taking the formation of an N-type MOSFET semiconductor device as an example, the first region 30 includes an N+ active region 301 and a P+ active region 302. The unit cell 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the unit cell 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the unit cell 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0137] S120, forming a first electrode structure on the first surface, the first electrode structure being electrically connected to the first region; a blocking structure is disposed at an edge of the first electrode structure, the blocking structure being used to buffer stress and block stress propagation.

[0138] refer to Figure 1 and Figure 3 as well as Figure 2 and Figure 3 A first electrode structure 300 is formed on the first surface 101, and the first electrode structure 300 is electrically connected to the first region 30; a blocking structure 70 is disposed at the edge of the first electrode structure 300, and the blocking structure 70 is used to buffer stress and block stress propagation. The first electrode structure 300 is used to access the anode electrical signal.

[0139] S130, forming a second electrode structure on the second surface.

[0140] refer to Figure 1 and Figure 2 as well as Figure 2 and Figure 3 A second electrode structure 400 is formed on the second surface 102. The second electrode structure 400 is used to access a cathode electrical signal.

[0141] In the technical solution provided by the embodiment of the present invention, during the manufacturing process of the first electrode structure 300 electrically connected to the first region 30, stress concentration is likely to occur inside the first electrode structure 300 due to factors such as temperature changes, differences in material properties and manufacturing processes. And a graphic process is usually required to obtain the first electrode structure 300 of a preset shape, and the edge of the first electrode structure 300 is likely to introduce stress generation points. A blocking structure 70 is provided at the edge of the first electrode structure 300, and the blocking structure 70 is used to buffer stress and block stress propagation, so that the streamline of the movement trajectory of stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0142] Optionally, forming the first electrode structure on the first surface includes: forming a first electrode on the first surface; forming a blocking structure at an edge of the first electrode; forming an insulating layer on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole; forming a second electrode on a side of the insulating layer away from the first electrode, wherein the second electrode reaches the first electrode through the contact hole;

[0143] Alternatively, a first electrode is formed on the first surface; an insulating layer is formed on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole; a second electrode is formed on a side of the insulating layer away from the first electrode, wherein the second electrode reaches the first electrode through the contact hole; and a blocking structure is formed at an edge of the second electrode;

[0144] Alternatively, a first electrode is formed on the first surface; a blocking structure is formed at the edge of the first electrode; an insulating layer is formed on a side of the first electrode away from the first surface, and a contact hole is provided in the insulating layer; a second electrode is formed on a side of the insulating layer away from the first electrode, and the second electrode reaches the first electrode through the contact hole; and a blocking structure is formed at the edge of the second electrode.

[0145] Specifically, refer to Figure 1 and Figure 3 as well as Figure 2 and Figure 3 , forming a first electrode structure 300 on the first surface 101 includes: forming a first electrode 40 on the first surface 101; forming a blocking structure 70 at an edge of the first electrode 40; forming an insulating layer 50 on a side of the first electrode 40 away from the first surface 101, the insulating layer 50 being provided with a contact hole 80; forming a second electrode 60 on a side of the insulating layer 50 away from the first electrode 40, the second electrode 60 reaching the first electrode 40 through the contact hole 80;

[0146] Alternatively, a first electrode 40 is formed on the first surface 101; an insulating layer 50 is formed on a side of the first electrode 40 away from the first surface 101, and a contact hole 80 is provided on the insulating layer 50; a second electrode 60 is formed on a side of the insulating layer 50 away from the first electrode 40, and the second electrode 60 reaches the first electrode 40 through the contact hole 80; and a blocking structure 70 is formed at an edge of the second electrode 60;

[0147] Alternatively, a first electrode 40 is formed on the first surface 101; a blocking structure 70 is formed at an edge of the first electrode 40; an insulating layer 50 is formed on a side of the first electrode 40 away from the first surface 101, and the insulating layer 50 is provided with a contact hole 80; a second electrode 60 is formed on a side of the insulating layer 50 away from the first electrode 40, and the second electrode 60 reaches the first electrode 40 through the contact hole 80; and a blocking structure 70 is formed at an edge of the second electrode 60.

[0148] exist Figure 1 In the semiconductor device for forming an SBD, the first electrode 40 is an anode, and the second electrode 60 is used to obtain an anode electrical signal, which reaches the first electrode 40 through the contact hole 80 and transmits the anode electrical signal to the first region 30. Figure 4 , is a schematic diagram of a structure in which a blocking structure 70 is located at a portion of an edge of a first electrode 40 in forming an SBD semiconductor device according to an embodiment of the present invention. Figure 5 , is a schematic structural diagram of a blocking structure 70 located at a partial edge of a second electrode 60 in forming an SBD semiconductor device according to an embodiment of the present invention.

[0149] Optionally, forming a blocking structure at the edge of the first electrode includes: forming a first blocking unit on a side of the first electrode;

[0150] Forming a blocking structure at the edge of the second electrode includes: forming a first blocking unit on a side of the second electrode.

[0151] refer to Figure 4 and Figure 6 , a first barrier unit 701 is formed on the side of the first electrode 40 , so that the first barrier unit 701 is located on the side of the first electrode 40 .

[0152] refer to Figure 5 and Figure 7 , a first barrier unit 701 is formed on the side of the second electrode 60 , so that the first barrier unit 701 is located on the side of the second electrode 60 .

[0153] The side of the first electrode 40 is prone to introduce stress generation points. The first blocking unit 701 is located on the side of the first electrode 40. The first blocking unit 701 is used to buffer stress and block the stress from propagating on the side of the first electrode 40, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0154] The side of the second electrode 60 is prone to introduce stress generation points. The first blocking unit 701 is located on the side of the second electrode 60. The first blocking unit 701 is used to buffer the stress and block the stress from propagating on the side of the second electrode 60, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0155] Optionally, forming the first blocking unit on the side of the first electrode includes: forming a tooth-shaped structure on the side of the first electrode, the tooth-shaped structure including a plurality of protrusions arranged at intervals;

[0156] Forming the first blocking unit on the side of the second electrode includes: forming a tooth-shaped structure on the side of the second electrode, wherein the tooth-shaped structure includes a plurality of protrusions arranged at intervals.

[0157] Specifically, refer to Figure 4 and Figure 6 , a tooth-like structure is formed on the side of the first electrode 40, and the tooth-like structure includes a plurality of protrusions 703 arranged at intervals. The protrusions 703 are arranged at intervals on the side of the first electrode 40, which increases the length of the side of the first electrode 40, so that the first blocking unit 701 has the effect of buffering stress and blocking the propagation of stress on the side of the first electrode 40, making the movement trajectory streamline of the stress smooth, having the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0158] refer to Figure 5 and Figure 7, a tooth-like structure is formed on the side of the second electrode 60, and the tooth-like structure includes a plurality of protrusions 703 arranged at intervals. The protrusions 703 are arranged at intervals on the side of the second electrode 60, which increases the length of the side of the second electrode 60, so that the first blocking unit 701 has the effect of buffering stress and blocking the propagation of stress on the side of the second electrode 60, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects in the first region 30, thereby improving the reliability of the semiconductor device.

[0159] in, Figure 16-Figure 17 The schematic structural diagram corresponding to the process of forming the protrusion 703 on the side of the first electrode 40 and / or the second electrode 60 is shown.

[0160] refer to Fig.16 , a first electrode 40 or a second electrode 60 is formed in the device core region 200 .

[0161] refer to Fig.17 , spin-coat the photoresist 500 on the surface of the first electrode 40 or the second electrode 60 .

[0162] refer to Fig.18 The patterned photoresist 500 is cured by exposing and developing the photoresist 500 and performing a thermal hardening treatment on the photoresist 500 .

[0163] refer to Fig.19 , dry-etching the first electrode 40 or the second electrode 60 to form a protrusion 703.

[0164] refer to Fig. 20 , remove the photoresist 500.

[0165] Optionally, forming a blocking structure at an edge of the first electrode includes:

[0166] forming a second blocking unit on a side of the first electrode away from the first surface;

[0167] Forming a blocking structure at an edge of the second electrode comprises:

[0168] A second blocking unit is formed on a side of the second electrode away from the insulating layer.

[0169] Specifically, refer to Figure 4 and Figure 6 , a second blocking unit 704 is formed on a side of the first electrode 40 away from the first surface 101; Figure 5 and Figure 7A second blocking unit 704 is formed on a side of the second electrode 60 away from the insulating layer 50. The second blocking unit 704 has the effect of buffering stress and blocking the stress from propagating from the edge of the first electrode 40 on the side away from the first surface 101 to the central area of ​​the device core area 200, so that the movement trajectory of the stress is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point, and can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby preventing the first electrode structure 300 and even the entire semiconductor device from cracking, and preventing defects from occurring in the first area 30, thereby improving the reliability of the semiconductor device.

[0170] The second blocking unit 704 has the effect of buffering stress and blocking the stress from propagating from the edge of the second electrode 60 on the side away from the insulating layer 50 to the central area of ​​the device core area 200, so that the streamline of the stress movement trajectory is smooth, which has the effect of reducing local stress and reducing the stress intensity of the internal stress concentration point. It can also prevent cracks from extending to the stress concentration point inside the first electrode structure 300, thereby avoiding the cracking of the first electrode structure 300 and even the entire semiconductor device, and avoiding defects in the first area 30, thereby improving the reliability of the semiconductor device.

[0171] Optionally, forming the second blocking unit on a side of the first electrode away from the first surface includes: forming at least one groove on a side of the first electrode away from the first surface, wherein the groove surrounds an edge of the first electrode;

[0172] Forming the second blocking unit on a side of the second electrode away from the insulating layer includes: forming at least one groove on a side of the second electrode away from the insulating layer, wherein the groove surrounds an edge of the second electrode.

[0173] Specifically, refer to Figure 4 and Figure 6 At least one groove is formed on the side of the first electrode 40 away from the first surface 101, and the groove surrounds the edge of the first electrode 40; Figure 5 and Figure 7 At least one groove is formed on the side of the second electrode 60 away from the insulating layer 50, and the groove surrounds the edge of the second electrode 60. The more grooves are formed, the more significant the effect of the second blocking unit 704 in buffering stress and blocking stress from propagating from the edge to the central area of ​​the device core region 200 on the side of the first electrode 40 away from the first surface 101 and / or the side of the second electrode 60 away from the insulating layer 50. The first blocking unit 701 and the second blocking unit 704 in the embodiment of the present invention can be prepared by photolithography and etching.

[0174] The method of forming at least one groove on the side of the first electrode 40 away from the first surface 101 and forming at least one groove on the side of the second electrode 60 away from the insulating layer 50 can also be performed by patterning the first electrode 40 and the second electrode 60 through photolithography and etching processes to form the grooves.

[0175] Optionally, forming a first electrode structure on the first surface further includes:

[0176] A redundant insulating layer is formed on a side of the second electrode away from the insulating layer; a redundant second electrode is formed on a side of the redundant insulating layer away from the second electrode; the redundant insulating layer, the second electrode and the insulating layer are provided with redundant contact holes, and the redundant second electrode reaches the first electrode through the redundant contact holes; the redundant second electrode and the second electrode are insulated.

[0177] Specifically, refer to Figure 8 and Fig. 9 A redundant insulating layer 51 is formed on a side of the second electrode 60 away from the insulating layer 50; a redundant second electrode 61 is formed on a side of the redundant insulating layer 51 away from the second electrode 60; the redundant insulating layer 51, the second electrode 60 and the insulating layer 50 are provided with a redundant contact hole 81, and the redundant second electrode 61 reaches the first electrode 40 through the redundant contact hole 81; the redundant second electrode 61 and the second electrode 60 are insulated.

[0178] Exemplarily, the sidewall of the redundant contact hole 81 is provided with a hole wall insulating layer 82, and the hole wall insulating layer 82 is used to achieve the insulation setting of the redundant second electrode 61 and the second electrode 60. When the second electrode 60 is cracked due to strong stress, the redundant second electrode 61 can be used to replace the second electrode 60 to access the electrical signal.

[0179] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0180] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0181] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0182] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0183] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0184] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0185] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A unit cell, a first electrode structure and a second electrode structure located in a core region of the device; The unit cell includes a first region, and the unit cell also includes a first surface and a second surface that are arranged opposite to each other; The first area is disposed on the first surface; The first electrode structure is located on the first surface; the first electrode structure is electrically connected to the first region; A blocking structure is provided at the edge of the first electrode structure, and the blocking structure is used to buffer stress and block stress propagation; The second electrode structure is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The first electrode structure includes a first electrode, an insulating layer, and a second electrode; The first electrode is located on the first surface; The insulating layer is located on a side of the first electrode away from the first surface, and the insulating layer is provided with a contact hole; The second electrode is located on a side of the insulating layer away from the first electrode and reaches the first electrode through the contact hole; The blocking structure is located at an edge of the first electrode; and / or the blocking structure is located at an edge of the second electrode.

3. The semiconductor device according to claim 2, characterized in that The blocking structure includes a first blocking unit, and the first blocking unit is located on a side of the first electrode and / or a side of the second electrode.

4. The semiconductor device according to claim 3, characterized in that The first blocking unit includes a tooth structure including a plurality of protrusions disposed at intervals.

5. The semiconductor device according to claim 2 or 3, characterized in that: The blocking structure further includes a second blocking unit; The second blocking unit is located at a side of the first electrode away from the first surface; And / or, the second blocking unit is located on a side of the second electrode away from the insulating layer.

6. The semiconductor device according to claim 5, characterized in that The second blocking unit includes at least one groove, and the groove is arranged around an edge of the first electrode and / or an edge of the second electrode.

7. The semiconductor device according to claim 2, characterized in that It also includes a first common electrode wiring, the first common electrode wiring is located in a terminal area surrounding the core area of ​​the device, and the first common electrode wiring includes a surrounding portion and a connecting portion; The surrounding portion is arranged around the edge of the second electrode and is spaced apart from the second electrode; The connecting portion is used to connect the surrounding portion and the second electrode; The unit cell includes a silicon carbide Schottky diode unit cell or a gallium nitride Schottky diode unit cell; The first electrode comprises an anode; The second electrode structure includes a cathode.

8. The semiconductor device according to claim 2, wherein: It also includes a first common electrode routing and a second common electrode routing; the first common electrode routing and the second common electrode routing are located in a terminal area surrounding the core area of ​​the device; The first common electrode wiring includes a surrounding portion and a connecting portion; the surrounding portion is arranged around the edge of the second electrode and is spaced apart from the second electrode; the connecting portion is used to connect the surrounding portion and the second electrode; The second common electrode wiring is located between the surrounding portion and the second electrode, and is insulated from the first electrode and the second electrode; The unit cell includes a silicon carbide metal-oxide semiconductor field effect transistor unit cell, or a gallium nitride metal-oxide semiconductor field effect transistor unit cell; The first electrode is a source electrode; The semiconductor device further includes a third electrode structure, the third electrode structure is located on the first surface or extends from the first surface into the unit cell, the third electrode structure includes a dielectric insulating layer and a gate electrode, and the second common electrode wiring is connected to the gate electrode of the unit cell; The second electrode structure includes a drain.

9. The semiconductor device according to claim 2, characterized in that The first electrode structure also includes a redundant insulating layer and a redundant second electrode, the redundant insulating layer is located on a side of the second electrode away from the insulating layer, the redundant second electrode is located on a side of the redundant insulating layer away from the second electrode, the redundant insulating layer, the second electrode and the insulating layer are provided with redundant contact holes, the redundant second electrode reaches the first electrode through the redundant contact holes; the redundant second electrode and the second electrode are insulated.

10. A method for manufacturing a semiconductor device, characterized in that: include: Forming a unit cell in the core area of ​​the device, the unit cell comprising a first region, and the unit cell further comprising a first surface and a second surface arranged opposite to each other; the first region is arranged on the first surface; forming a first electrode structure on the first surface, the first electrode structure being electrically connected to the first region; and a blocking structure, the blocking structure being used to buffer stress and block stress propagation; A second electrode structure is formed on the second surface.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Forming a first electrode structure on the first surface includes: forming a first electrode on the first surface; forming the blocking structure at an edge of the first electrode; forming an insulating layer on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole; forming a second electrode on a side of the insulating layer away from the first electrode, wherein the second electrode reaches the first electrode through the contact hole; or, forming a first electrode on the first surface; forming an insulating layer on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole; forming a second electrode on a side of the insulating layer away from the first electrode, wherein the second electrode reaches the first electrode through the contact hole; forming the blocking structure at an edge of the second electrode; or, forming a first electrode on the first surface; forming the blocking structure at an edge of the first electrode; forming an insulating layer on a side of the first electrode away from the first surface, wherein the insulating layer is provided with a contact hole; forming a second electrode on a side of the insulating layer away from the first electrode, wherein the second electrode reaches the first electrode through the contact hole; The blocking structure is formed at an edge of the second electrode.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming the blocking structure at an edge of the first electrode and / or an edge of the second electrode comprises: A first barrier unit is formed on a side surface of the first electrode and / or a side surface of the second electrode.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: Forming a first blocking unit on a side of the first electrode includes: A tooth-like structure is formed on a side surface of the first electrode and / or a side surface of the second electrode, wherein the tooth-like structure includes a plurality of protrusions arranged at intervals.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: A tooth-like structure is formed on a side surface of the first electrode and / or a side surface of the second electrode, comprising: Spin-coating a photoresist on the side of the first electrode; Expose and develop the photoresist, perform thermal hardening on the photoresist, and solidify the patterned photoresist; Performing dry etching on the side surface of the first electrode to form a plurality of protrusions arranged at intervals; removing the photoresist; and / or, spin coating a photoresist on the side of the second electrode; Expose and develop the photoresist, perform thermal hardening on the photoresist, and solidify the patterned photoresist; performing dry etching on the side surface of the second electrode to form a plurality of protrusions arranged at intervals; The photoresist is removed.

15. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 9, wherein the substrate is used for carrying the semiconductor device.

16. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

17. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 16, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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