Semiconductor device and manufacturing method

Abstract

In general, embodiments of the present disclosure relate to semiconductor devices and methods of manufacture. A semiconductor device according to an embodiment includes a cell region and a terminal region adjacent to the cell region. A first insulating film is provided on a first main surface of the semiconductor section. A first semiconductor region of a first conductivity type provided in the semiconductor portion, a gate electrode, and a gate insulating film covering the gate electrode are provided in the cell region. From the cell region to the termination region, a second semiconductor region of the second conductivity type provided between the first semiconductor region and the first main surface is in contact with at least a portion of the bottom surface of the gate insulating film. A first member is provided between the second semiconductor region and the first insulating film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Japanese patent application No. 2023-173731 filed on October 5, 2023, and all the contents of that application are incorporated herein by reference. Technical Field

[0003] In general, embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Art

[0004] Insulated gate bipolar transistor (IGBT) is a semiconductor device that can achieve high breakdown voltage and low on-resistance. The IGBT chip has a withstand voltage holding structure in the peripheral part of the chip to ensure the breakdown voltage. An example of such a withstand voltage holding structure is a guard ring structure. The guard ring is usually formed as a p-type diffusion layer on an n-type Si substrate and is formed by ion implantation and high temperature annealing. In addition, a structure is known in which a trench is covered with a deep p-type diffusion layer even at the outermost periphery of a cell area.

[0005] However, the high temperature annealing process for forming the guard ring may cause defects such as slippage of the Si wafer during the process that degrade the device characteristics. Therefore, there is a need for a semiconductor device that improves reliability by suppressing defects in the Si wafer and improves performance by forming a diffusion layer as a withstand voltage holding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view showing the semiconductor device according to the first embodiment.

[0007] Figure 2 is along Figure 1 Cross-sectional view taken along line AA'.

[0008] Figure 3 AA′ is a cross-sectional view showing a semiconductor device according to a first modification example of the first embodiment.

[0009] Figure 4 AA′ is a cross-sectional view showing a semiconductor device according to a second modification example of the first embodiment.

[0010] Figure 5 AA′ is a cross-sectional view showing a semiconductor device according to a third modification example of the first embodiment.

[0011] Figure 6 is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0012] Fig. 7Ais a cross-sectional view showing a semiconductor device according to a third embodiment.

[0013] Figure 7B is a cross-sectional view showing a semiconductor device according to a third embodiment.

[0014] Figure 7C is a cross-sectional view showing a semiconductor device according to a third embodiment.

[0015] Figure 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

[0016] Fig. 9 is a cross-sectional view showing a semiconductor device according to a fifth embodiment.

[0017] Fig.10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment.

[0018] Fig.11A is a cross-sectional view showing a step of forming a first surface in the method of manufacturing a semiconductor device according to the first embodiment.

[0019] Fig. 11B 1 is a cross-sectional view showing a step of forming a diffusion layer on the first surface in the method of manufacturing the semiconductor device according to the first embodiment.

[0020] Fig. 11C 1 is a cross-sectional view showing a step of forming an insulating member on the first main surface and the first surface in the method of manufacturing the semiconductor device according to the first embodiment.

[0021] Fig.11D 1 is a cross-sectional view showing a process of digging out a remaining insulating member in the method of manufacturing the semiconductor device according to the first embodiment.

[0022] Fig.11E 1 is a cross-sectional view showing a process of forming a first insulating film after forming a gate electrode and a gate insulating film in a cell region in the method of manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.11F is a cross-sectional view showing a process of forming a second electrode, a third electrode, a first conductive region, and a second conductive region in the method of manufacturing the semiconductor device according to the first embodiment.

[0024] Fig.11G is a cross-sectional view showing a structure formed on the second main surface in the method of manufacturing the semiconductor device according to the first embodiment.

[0025] Fig.12is a cross-sectional view showing a process of forming a second semiconductor region and a third semiconductor region in the method of manufacturing the semiconductor device according to the third embodiment.

[0026] Fig.13 4 is a cross-sectional view showing a process of forming a second semiconductor region and a third semiconductor region by implanting impurities from the first surface in the method of manufacturing the semiconductor device according to the fourth embodiment.

[0027] Fig.14A is a cross-sectional view showing an example of a method of making the depths of the second semiconductor region and the third semiconductor region different in the method of manufacturing the semiconductor device according to the fourth embodiment.

[0028] Fig. 14B is a cross-sectional view showing an example of a method of making the depths of the second semiconductor region and the third semiconductor region different in the method of manufacturing the semiconductor device according to the fourth embodiment.

[0029] Fig.15A is a cross-sectional view showing a step of forming a second bottom surface in the method of manufacturing the semiconductor device according to the fifth embodiment.

[0030] Fig. 15B is a cross-sectional view showing a step of digging a part of the second bottom surface to form the second bottom surface in the method of manufacturing the semiconductor device according to the fifth embodiment.

[0031] Fig. 15C is a cross-sectional view showing a process of forming a second semiconductor region and a third semiconductor region in the method of manufacturing the semiconductor device according to the fifth embodiment.

[0032] Fig.16A is a cross-sectional view showing a process of forming a second semiconductor region and a third semiconductor region in the method of manufacturing the semiconductor device according to the sixth embodiment.

[0033] Fig. 16B is a cross-sectional view showing a step of forming the second surface in the method of manufacturing the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0035] In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, etc. are not necessarily the same as the actual ones. In addition, even when representing the same part, the size or ratio may be shown differently from each other according to the drawings.

[0036] Furthermore, in the present specification and each drawing, the same elements as those described above with respect to the previously described drawings are denoted by the same reference numerals, and a detailed description thereof is appropriately omitted.

[0037] The direction from the first electrode 21 to the second electrode 22 is defined as the Z direction (first direction). The direction orthogonal to the Z direction is defined as the X direction (second direction), and the direction intersecting the X direction and the Z direction is defined as the Y direction (third direction). Figure 2 The semiconductor device 101 shown is a cross-sectional view on the XZ plane. In addition, in this embodiment, the X direction, the Y direction, and the Z direction are shown to be in an orthogonal relationship, but are not limited to being orthogonal, and may be in a relationship where these directions intersect each other. For ease of explanation, the positive direction in the Z direction is referred to as "up", and the negative direction in the Z direction is referred to as "down". However, the "up" and "down" directions are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0038] In the following description, the symbol n + , n and n - and p + , p and p - represents the relative level of impurity concentration in each conductivity type. That is, n + Indicates that the concentration of n-type impurities is relatively higher than n, n - Indicates that the n-type doping concentration is relatively lower than n. In addition, p + Indicates the p-type impurity concentration relative to p, p - Indicates that the p-type doping concentration is relatively lower than p. In addition, n + Type and n - Type can be referred to as n type, p + Type and p - The type can be referred to as p-type.

[0039] The depth refers to the length measured from the first main surface 10a in the Z direction. In addition, it does not necessarily refer to the local length at the position shown in the drawings, but may also refer to the maximum length of the target area in the Z direction.

[0040] A semiconductor device according to an embodiment includes a cell region and a termination region adjacent to the cell region. The semiconductor device includes a first insulating film disposed on a first main surface of a semiconductor portion and a first electrode disposed on a second main surface opposite to the first main surface. In the cell region, a second electrode disposed on the first insulating film and electrically connected to the semiconductor portion through a first conductive region, a first semiconductor region of a first conductivity type disposed in the semiconductor portion, a gate electrode disposed in the semiconductor portion and in contact with the first main surface, and a gate insulating film covering the gate electrode are disposed. From the cell region to the termination region, a second semiconductor region of a second conductivity type disposed between the first semiconductor region and the first main surface contacts at least a portion of the bottom surface of the gate insulating film. A first component is disposed between the second semiconductor region and the first insulating film.

[0041] (First Embodiment)

[0042] Figure 1 is a plan view showing a semiconductor device according to this embodiment. Figure 2 is shown along Figure 1 A cross-sectional view of the cross section taken along line AA'.

[0043] like Figure 1 and Figure 2 As shown in FIG. 1 , a cell region CR and a termination region ER arranged around and adjacent to the cell region CR are provided in a semiconductor device 101. Figure 1 In FIG. 1 , the region within the dashed line is the cell region CR, and the region outside the dashed line is the termination region ER. When the semiconductor device 101 operates, the portion through which current mainly flows is the cell region SR, and the portion arranged around the cell region CR is the termination region ER.

[0044] Will refer to Figure 2 The configuration of the semiconductor device 101 according to the first embodiment is described. Figure 2 The direction from the cell region CR to the termination region ER in the X direction is referred to as a termination direction.

[0045] Figure 2 The semiconductor device 101 shown in the figure includes a semiconductor portion 10, a first electrode 21, and a first insulating film 41 in a cell region CR and a terminal region ER. The semiconductor portion 10 has a first semiconductor region 11 of a first conductivity type. The semiconductor portion 10 is, for example, a semiconductor formed of Si. The first semiconductor region 11 is, for example, an n-type drift layer. For example, the first semiconductor region 11 is formed by doping Si with phosphorus (P). The first semiconductor region 11 includes a first semiconductor layer 11a and a second semiconductor layer 11b. The first semiconductor layer 11a is disposed farther from the first main surface 10a of the semiconductor portion 10 than the second semiconductor layer 11b. For example, the first semiconductor layer 11a is formed of n-type.+ The second semiconductor layer 11b is formed of a n-type semiconductor.

[0046] The first electrode 21 is provided on the second main surface 10b of the semiconductor portion 10. The first insulating film 41 is provided on the first main surface 10a of the semiconductor portion 10. The semiconductor portion 10, the first electrode 21 and the first insulating film 41 have a structure common to the cell region CR and the termination region ER.

[0047] Next, we will describe Figure 2 The structure of the termination region ER shown in FIG. The termination region ER includes a second semiconductor region 12 of the second conductivity type and an insulating member 42 (first member 40). That is, Figure 2 A case where the first member 40 formed of an insulating material forms the insulating member 42 is shown.

[0048] The second semiconductor region 12 is formed between the first semiconductor region 11 and the first main surface 10a of the semiconductor portion 10. The second semiconductor region 12 is formed from the cell region CR to the termination region ER. That is, a part of the second semiconductor region 12 is included in the cell region CR. The second semiconductor region 12 is, for example, a p-type diffusion layer, and is formed by implanting, for example, boron (B) into the semiconductor portion 10.

[0049] The insulating component 42 is at least partially formed between the second semiconductor region 12 and the first main surface 10a. In the terminal direction from the cell region to the terminal region, the second semiconductor region 12, the insulating component 42 (first component 40) and the second semiconductor region 12 are arranged in order. The insulating component 42 is in contact with the first insulating film 41. The second semiconductor region 12 and the first insulating film 41 may be partially in contact with each other. The insulating component 42 is, for example, an oxide film containing silicon oxide. In addition, the first insulating film 41 and the insulating component 42 may be formed of the same material or different materials.

[0050] The first surface 10c refers to a surface including the interface between the insulating member 42 and the second semiconductor region 12. Figure 2 , when the insulating member 42 is in contact with the third semiconductor region 13 but not in contact with the first semiconductor region 11, the first face 10c is an interface between the insulating member 42 and the second semiconductor region 12. On the other hand, the insulating member 42 and the first semiconductor region 11 may be partially in contact with each other, and the first face 10c may include an interface between the insulating member 42 and the second semiconductor region 12. The first face 10c is closer to the first electrode 21 in the Z direction than the first main face 10a.

[0051] Figure 2The example in which the insulating member 42 is provided on the first surface 10c and the insulating member 42 is not provided on the first main surface 10a is shown. However, the shape of the insulating member 42 is not limited to Figure 2 , and the insulating part 42 may also be provided on the first main surface 10a. For example, the insulating part 42 having a uniform thickness may be provided on the first main surface 10a. When the first insulating film 41 and the insulating part 42 are formed of the same material, the portion provided above the first main surface 10a may be defined as the first insulating film 42. Hereinafter, a description will be given with reference to the accompanying drawings in which the insulating part 42 is provided on the first surface 10c and is not provided on the first main surface 10a, but the shape of the insulating part 42 is not limited thereto.

[0052] Next, we will describe Figure 2 The structure of the cell region CR shown in FIG. In the cell region CR, the second electrode 22 is provided on the first insulating film 41. The second electrode 22 is electrically connected to the semiconductor portion 10 through the first conductive region 51. The second electrode 22 and the first conductive region 51 are formed of, for example, a metal containing Al.

[0053] The cell region CR includes a gate electrode 31 and a gate insulating film 32. The gate electrode 31 and the gate insulating film 32 are provided in the semiconductor portion 10 and are in contact with the first main surface 10a. The gate insulating film 32 covers the gate electrode 31. The gate electrode 31 and the gate insulating film 32 extend in the Y direction, and a plurality of gate electrodes 31 and a plurality of gate insulating films 31 may be provided in the X direction. The plurality of gate electrodes 31 need not all be electrically connected to each other. The plurality of gate electrodes 31 may include a portion whose potential is controlled (via a gate pad not shown in the drawings) and a portion whose potential is not controlled.

[0054] Next, description will be given of an example of a structure formed in the cell region CR in the semiconductor portion 10. As described below, for example, an IGBT is formed in the cell region CR.

[0055] In the cell region CR, the semiconductor portion 10 includes a fourth semiconductor region 14 of the second conductivity type, a fifth semiconductor region 15 of the second conductivity type, and a sixth semiconductor region 16 of the first conductivity type. The fourth semiconductor region 14 is provided between the first electrode 21 and the first semiconductor region 11 and is formed by, for example, p + The fourth semiconductor region 14 is, for example, a collector region formed by doping Si with B (boron). For example, the fourth semiconductor region 14 is in ohmic contact with the first electrode 21.

[0056] The fifth semiconductor region 15 is provided on the first semiconductor region 11. The fifth semiconductor region 15 is, for example, a p-type diffusion layer and is formed by, for example, doping Si with B (boron). The fifth semiconductor region 15 is in contact with at least a portion of the gate insulating film 32.

[0057] The sixth semiconductor region 16 is selectively provided on the fifth semiconductor region 15. The sixth semiconductor region 16 is an emitter region formed of, for example, an n-type semiconductor. For example, the sixth semiconductor region 16 is formed by doping Si with phosphorus (P). The sixth semiconductor region 16 is in contact with at least a portion of the first conductive region 51 and the gate insulating film 32.

[0058] For example, an IGBT is formed as described above in the cell region CR of the semiconductor device 101. The IGBT formed as described above forms an inversion layer in the fifth semiconductor region 15 that is opposed to the gate electrode 31 via the gate insulating film 32 by controlling the potential of the gate electrode 31. When current flows from the first semiconductor region 11 to the sixth semiconductor region 16 through the inversion layer of the fifth semiconductor region 15, the IGBT is turned on. So far, an example of a structure formed in the cell region CR has been described.

[0059] Next, the second semiconductor region 12 will be described in more detail. First, the Figure 2 An example of a method of forming the second semiconductor region 12 and the insulating member 42 is shown. The manufacturing method will be described in detail later.

[0060] The first face 10c is formed on the first main face 10a of the semiconductor portion 10. The first face 10c is provided by digging out the first main face 10a using, for example, chemical dry etching (CDE). The first face 10c can be formed by reactive ion etching (RIE) or wet etching.

[0061] The first surface 10c may have a bottom portion including a portion perpendicular to the Z direction. Figure 2 As shown in FIG. 1 , the first surface 10c has a first bottom 10c1. Figure 2 The shape of the first face 10c other than the shape shown may be, for example, a bowl-like shape or a shape having multiple bottoms.

[0062] The second semiconductor region 12 of the second conductivity type is formed so that at least a portion of the second semiconductor region 12 is in contact with the first surface 10c provided in the semiconductor portion 10. The second semiconductor region 12 is, for example, a diffusion layer formed of a p-type semiconductor, and is formed by doping B (boron) and performing an annealing process. The shape of the second semiconductor region 12 is not limited to Figure 2The interface between the second semiconductor region 12 and the first semiconductor region 11 is rounded, for example, by diffusion of dopants.

[0063] The insulating member 42 is provided in contact with the second semiconductor region 12 on the first face 10c. The insulating member 42 is provided at least partially between the first insulating film 41 and the second semiconductor region 12. The insulating member 42 is an oxide film containing silicon oxide such as SiO2 (silicon dioxide). The insulating member 42 is formed by, for example, CVD. For example, the second semiconductor region 12 and the insulating member 42 are formed by the above-mentioned process.

[0064] In addition, the terminal region ER may have a third electrode 23 disposed on the first insulating film 41 and a second conductive region 52 electrically connecting the third electrode 24 and the second semiconductor region 12 to each other. By providing the third electrode 23 and the second conductive region 52, the electric field dispersed from the cell region CR to the terminal region ER by the second semiconductor region 12 can be further dispersed in the direction of the third electrode 22. The third electrode 23 serves as a field plate and increases the breakdown voltage by reducing the electric field inside the semiconductor, and prevents charges from accumulating in the interlayer insulating film due to the influence of the external environment to improve reliability. The third electrode 23 and the second conductive region 52 are formed of, for example, a metal containing Al.

[0065] Next, the positional relationship between the second semiconductor region 12 and the gate insulating film 32 will be described. The second semiconductor region 12 is formed from the cell region CR to the terminal region ER, and the second semiconductor region 12 is in contact with the gate insulating film 32 closest to the terminal region ER. In addition, the second semiconductor region 12 is in contact with at least a portion of the bottom surface 32a of the gate insulating film 32. That is, the second semiconductor region 12 is in contact with at least a portion of the bottom surface 32a of the gate insulating film 32 closest to the terminal region ER among the plurality of gate insulating films 32 provided in the cell region CR.

[0066] like Figure 2 As shown in , the entire bottom surface 32a may be in contact with the second semiconductor region 12. When the entire bottom surface 32a is in contact with the second semiconductor region 12, the electric field concentration on the bottom surface 32a can be further suppressed, which is preferable.

[0067] In addition, the second semiconductor region 12 may extend to the cell region CR outside the gate insulating film 32 closest to the termination region ER. For example, the second semiconductor region 12 may contact the fifth semiconductor region 15 formed between the gate insulating films 32 .

[0068] Next, the structure of the second semiconductor region 12 and the gate insulating film 32 will be further described. In the following description, the depth refers to the length in the Z direction measured from the first main surface 10a. In addition, it does not necessarily refer to the local length at the position shown in the drawings, but may refer to the maximum length of the target region in the Z direction. For example, when the second semiconductor region 12 has a bowl-like shape, that is, when the length of the second semiconductor region 12 in the Z direction varies in the X direction and the Z direction length has a maximum value at a predetermined position in the X direction, the depth h2 of the second semiconductor region 12 refers to the maximum length of the second semiconductor region 12 in the Z direction.

[0069] The depth h1 of the gate insulating film 32 is the length of the bottom surface 32a from the first main surface 10a in the Z direction. The shape of the bottom surface 32a is not limited to Figure 2 The shape shown in the figure may also be circular. For example, the depth h2 of the second semiconductor region 12 is formed to be greater than h1. By forming h2 greater than h1, the bottom surface 32a can be completely covered with the second semiconductor region 12. On the other hand, even when h2 is less than h1, a part of the circular bottom surface 32a, for example, can be covered, and a predetermined effect of suppressing the electric field concentration on the bottom surface 32a can be obtained. From the perspective of improving the breakdown voltage, h2 is preferably greater than h1.

[0070] So far, reference has been made to Figure 1 and Figure 2 The semiconductor device 101 according to the first embodiment is described.

[0071] Hereinafter, the effects of the semiconductor device 101 according to the present embodiment will be described. In the semiconductor device 101 according to the present embodiment, the first face 10c is provided in the semiconductor portion 10, and the second semiconductor region 12 is at least partially in contact with the bottom face 32a of the gate insulating film 32. The bottom face 32a and the second semiconductor region 12 are in contact with each other, and the electric field is dispersed to the second semiconductor region 12, thereby suppressing the concentration of the electric field on the bottom face 32a.

[0072] The bottom surface 32a is a portion where the electric field is easily concentrated when the semiconductor device formed in the cell region CR performs switching, for example, when the IGBT is turned off. In the semiconductor device 101 according to the present embodiment, the second semiconductor region 12 is provided at least partially between the first semiconductor region 11 and the bottom surface 32a of the gate insulating film 32. As a result, the electric field is dispersed to the second semiconductor region 12, and the concentration of the electric field on the bottom surface 32a of the gate insulating film 32 is suppressed. By suppressing the concentration of the electric field, the breakdown voltage can be increased.

[0073] The second semiconductor region 12 may be in contact with the entire bottom surface 32a. In other words, the second semiconductor region 12 may completely cover the bottom surface 32a. By completely covering the bottom surface 32a with the second semiconductor region 12, the concentration of the electric field on the bottom surface 32a can be further suppressed.

[0074] In addition, the second semiconductor region 12 has an effect of promoting carrier discharge when the semiconductor device 101 is switched. For example, when the IGBT is turned off, holes are discharged through the second semiconductor region 12. The structure in which h2 is formed to be greater than h1 and the second semiconductor region 12 is in contact with the fifth semiconductor region 15 can further promote the discharge of holes through the second semiconductor region 12, thereby further reducing the switching loss of the semiconductor device 101.

[0075] Furthermore, according to the semiconductor device 101 of the present embodiment, by providing the first face 10c, the length of the second semiconductor region 12 measured along the Z direction from the first bottom 10c1 of the first face 10c is smaller than the length of the second semiconductor region 12 measured along the Z direction from the first main face 10a. That is, when the first semiconductor region 12 having the same depth h2 is formed by providing the first face 10c, the required amount of diffusion length of the dopant is smaller than the case where the second semiconductor region 12 having the depth h2 is formed without providing the first face 10c.

[0076] In order to make the dopant diffuse deeper, annealing treatment needs to be performed at a higher temperature for a longer time, but high temperature treatment may cause defects in the Si wafer. In addition, long-term treatment inhibits the improvement of manufacturing efficiency. By providing the first surface 10c, even if the diffusion length of the dopant is small, the second semiconductor region 12 having a depth in contact with the bottom surface 32a can be formed. That is, since the ions injected into the first semiconductor region 11 from the first surface 10c are Figure 3 The semiconductor material diffuses in the X direction and the Z direction as shown, so that the second semiconductor region 12 reaching the depth of the bottom surface 32 a can be formed.

[0077] Due to the diffusion of the implanted ions, the second semiconductor region 12 can be formed not only directly below the first surface 10c but also near the first surface 10c by performing a low-temperature annealing process in a short time. That is, a diffusion layer that suppresses the electric field concentration on the bottom surface 32a can be formed by annealing at a relatively low temperature, while causing less damage to the Si wafer. In addition, since the annealing process can be performed in a shorter time, the manufacturing efficiency can be improved.

[0078] As described above, in the semiconductor device 101, the second semiconductor region 12 is at least partially in contact with the bottom surface 32a of the gate insulating film 32, and the electric field generated on the bottom surface 32a can be dispersed in the terminal direction to the second semiconductor region 12. The electric field concentration on the bottom surface 32a when the IGBT is turned off is suppressed, and a carrier discharge path is formed, so that the breakdown resistance of the semiconductor device 101 can be improved.

[0079] In addition, by providing the first surface 10c, the heat required for diffusing dopants to form the depth of the second semiconductor region 12 can be reduced. That is, since the annealing process can be performed at a lower temperature, the risk of defects in the Si wafer can be reduced. In addition, since a diffusion layer with a sufficient depth can be formed by annealing in a shorter time, the manufacturing efficiency can be improved.

[0080] (First Modification of First Embodiment)

[0081] Figures 3 to 5 A modification of the first embodiment is shown. Figure 3 A first variation is shown, Figure 4 A second variation is shown, and Figure 5 A third modification example is shown.

[0082] First, a first modification example will be described. Figure 3 .according to Figure 3 In the first modification shown in FIG. 1 , a conductive member 50 (first member 40 ) is provided between the second semiconductor region 12 and the first insulating film 41 . That is, Figure 3 The case where the first member 40 is formed of a conductive material to form a conductive member 50 is shown. The conductive member 50 may include, for example, polysilicon. For example, after forming the second semiconductor region 12 by implanting impurities from the first face 10c, the conductive member 50 is formed on the first face 10c.

[0083] The second conductive region 52 is not necessarily in contact with the second semiconductor region 12, and may be in contact with the conductive member 50. That is, the third electrode 23 is electrically connected to the second semiconductor region 12 through the second conductive region 52 and the conductive member 50.

[0084] exist Figure 2 In the semiconductor device 101 according to the first embodiment shown, an example in which the insulating member 42 is formed on the first face 10 c has been shown, but a conductive material may be provided on the first face 10 c without being limited to the insulating material.

[0085] In the following, the Figure 3Effects of the semiconductor device 101 of the first modification shown. Since the conductive member 50 is provided between the second semiconductor region 12 and the first insulating film 41, it is not necessary to form a second conductive region 52 that is long in the Z direction compared to the semiconductor device 101 according to the first embodiment. By simplifying the process of forming the second conductive region 52, manufacturing efficiency can be improved.

[0086] The second conductive region 52 is formed by digging the first insulating film 41 by etching, for example, to form an opening and embedding a conductive material in the opening. Figure 2 Compared with the case where the second conductive region 52 is formed to contact the first surface 10c as shown in FIG. Figure 3 When the second conductive region 52 is formed to contact the conductive member 50 as shown in , the aspect ratio of the opening formed by digging the first insulating film 41 is reduced. Here, the aspect ratio is a ratio obtained by dividing the depth of the opening by the width of the opening, and can be restated as, for example, the following description: Figure 3 In the ratio, the length in the Z direction is divided by the length in the X direction.

[0087] The smaller the aspect ratio of the opening, the easier it is to embed the conductive material by, for example, CVD. In other words, the risk of embedding defects due to a large aspect ratio can be reduced. Figure 3 As shown in Figure 2 The process of forming the second conductive region 52 is easier when the second conductive region 52 is in contact with the conductive member 50 than when the second conductive region 52 is formed as shown in FIG.

[0088] In addition, in order to form a shorter termination region ER in the X direction, the length of the second semiconductor region 12 in the X direction may be shortened. For example, the area in which the second semiconductor region 12 and the first insulating film 41 contact each other on the first main surface 10a is reduced. When the second semiconductor region 12 is formed shorter in the X direction, according to Figure 2 In the structure shown, the second conductive region 52 may have to be formed in contact with the first surface 10 c . Therefore, it is necessary to embed an opening having a large aspect ratio, which may make the formation of the second conductive region 52 difficult.

[0089] On the other hand, according to Figure 3 According to the structure of the first modification example shown, even when the second semiconductor region 12 is formed shorter in the X direction, the second conductive region 52 can be formed to reach the conductive member 50 electrically connected to the second semiconductor region 12. Therefore, regardless of the arrangement of the second semiconductor region 12, it is sufficient to form the second conductive region 52 in contact with the conductive member 50 electrically connected to the second semiconductor region 12, thereby facilitating design.

[0090] As described above, even when the termination region ER is formed short in the X direction, Figure 3 The semiconductor device according to the first modification example shown easily forms the second conductive region 52. That is, by reducing the area of ​​the termination region ER and increasing the area of ​​the cell region CR, the performance of the semiconductor device can be improved.

[0091] In addition, Figure 2 Compared with the case where the insulating member 42 is formed as shown, the conductive member 50 can widen the current path flowing through the semiconductor device 101. Since the carriers passing through the second semiconductor region 12 can also pass through the conductive member 50, the conductivity is improved. Since the conductivity is improved and the movement of the carriers is promoted, the potential of the second semiconductor region 12 is easily stabilized. Since the potential of the second semiconductor region 12 is stable, the effect of improving the breakdown resistance or breakdown voltage of the semiconductor device 101 can be stably obtained through the second semiconductor region 12.

[0092] In the following description, the case where the insulating member 42 is formed between the semiconductor portion 10 and the first insulating film 41 instead of the conductive member 50 will be described, but the material formed on the first face 10c is not limited to the insulating material. That is, in the following description, the case where the first member 40 is the insulating member 42 formed of an insulating material will be described, but the first member 40 may be the conductive member 50.

[0093] (Second Modification of First Embodiment)

[0094] Next, a second modification example will be described. Figure 4 . Figure 4 An example is shown in which the depth of the second semiconductor region 12 gradually decreases in the terminal direction. Here, the gradual decrease in depth means that Figure 2 Compared to the first embodiment shown, the second semiconductor region 12 extends longer in the terminal direction, with the depth decreasing continuously or stepwise. This structure of the terminal region is called a variant of the lateral doping (VLD) structure.

[0095] In addition, Figure 4 In addition to the shape of the second semiconductor region 12 shown, for example, a portion where the depth of the second semiconductor region 12 is constant in the terminal direction may be included in a portion where the depth of the second semiconductor region 12 decreases in the terminal direction. Since the portion where the depth of the second semiconductor region 12 is constant in the terminal direction is included, the second semiconductor region 12 can extend longer in the terminal direction. Since the second semiconductor region 12 extends longer in the terminal direction, the electric field generated in the semiconductor portion 10 can be dispersed in the terminal direction.

[0096] For example, the ratio of the portion where the resist is provided in the terminal direction and the portion where the resist is not provided in the ion implantation process can be changed to form a Figure 4 The diffusion layer with a gradually decreasing depth in the terminal direction shown. Specifically, by increasing the proportion of the resist set in the terminal direction, ions can be injected, thereby reducing the amount of ions injected in the terminal direction. Alternatively, by controlling the thickness of the resist, the amount of ions injected in the terminal direction can be reduced.

[0097] So far, we have described Figure 4 The second modified example of the first embodiment shown in FIG. Figure 4 The effect of the semiconductor device shown. Figure 4 In the semiconductor device of the embodiment of the present invention, the depth of the second semiconductor region 12 gradually decreases in the terminal direction. Since the second semiconductor region 12 extends while decreasing in depth in the terminal direction, Figure 2 The interface between the second semiconductor region 12 and the first semiconductor region 11 extends in the terminal direction compared to the second semiconductor region 12 shown in FIG. By gradually extending the electric field in the terminal direction and dispersing points where the electric field concentration occurs, the breakdown voltage of the semiconductor device 101 can be increased.

[0098] Furthermore, according to the present embodiment, compared with the case where a plurality of guard ring regions are formed in the terminal direction, the necessary length of the terminal structure for suppressing breakdown in the terminal direction can be shortened. By shortening the terminal structure, the area of ​​the cell region CR can be made larger relative to the area of ​​the chip, thereby improving the performance of the semiconductor device. Figure 4 The second modification example of the semiconductor device 101 according to the first embodiment is described.

[0099] (Third Modification of First Embodiment)

[0100] Finally, refer to Figure 5 A third modification example of the semiconductor device 101 according to the first embodiment will be described. Figure 5 In the embodiment, the electrical connection between the second conductive region 52 and the second semiconductor region 12 is not made on the first surface 10 c but is made on the first main surface 10 a .

[0101] The second semiconductor region 12 contacts the first main surface 10a further than the first surface 10c in the terminal direction. The second conductive region 52 penetrates the first insulating film 41 in the Z direction and reaches the first main surface 10a. The second conductive region 52 and the second semiconductor region 12 are electrically connected to each other on the first main surface 10a. The second conductive region 52 is, for example, a metal containing Al.

[0102] according to Figure 5In the third variation shown in FIG. 1 , when forming the second conductive region 52, the opening for embedding the second conductive region 52 only needs to reach the first main surface 10a. Therefore, the depth removed by etching can be less than Figure 3 The depth in the second modification shown in FIG. Since the first surface 10c located deeper than the first main surface 10a does not need to be etched, the etching efficiency is improved compared with the second modification. Figure 5 A third modification example of the semiconductor device 101 according to the first embodiment is described.

[0103] As described in the first modification, a structure in which the insulating member 42 is formed on the first face 10 c will be described below, but a conductive material such as the conductive member 50 may be formed on the first face 10 c.

[0104] In addition, as shown in the second modification example and the third modification example, as long as the third electrode 23 and the second semiconductor region 12 can be electrically connected to each other, Figure 4 As shown in FIG. 1 , a second conductive region 52 is provided on the first surface 10c, or as shown in FIG. Figure 5 As shown in FIG. 5 , a second conductive region 52 is arranged on the first main surface 10 a .

[0105] (Second Embodiment)

[0106] Figure 6 2 is a cross-sectional view showing a semiconductor device 102 according to a second embodiment. Description of the same parts as those in the first embodiment will be omitted, and different parts will be described.

[0107] The semiconductor device 102 according to the present embodiment is different from the semiconductor device 101 according to the first embodiment in the structure of the termination region ER. The semiconductor device 102 includes a third semiconductor region 13 of the second conductivity type. The third semiconductor region 13 and the second semiconductor region 12 are provided separately from each other. The third semiconductor region 13 is a structure for improving the breakdown voltage of the semiconductor device 102 as a guard ring region.

[0108] In addition, a fourth electrode 24 electrically connected to the third semiconductor region 13 is formed through the third conductive region 53. The third semiconductor region 13, the third conductive region 53, and the fourth electrode 24 extend in the Y direction, and one third semiconductor region 13, one third conductive region 53, and one fourth electrode 24 are provided in the X direction. The second semiconductor region 12 and the third semiconductor region 13 are spaced apart from each other in the X direction, and the third semiconductor region 13 is in contact with the first main surface 10a of the semiconductor portion 10.

[0109] The third semiconductor region 13 is formed of, for example, a p-type semiconductor and is formed by doping B (boron). The third conductive region 53 and the fourth electrode 24 are formed of, for example, a metal containing Al. The third conductive region 53 and the fourth electrode 24 may be formed of the same material or different materials.

[0110] Although two third semiconductor regions 13, two third conductive regions 53, and two fourth electrodes 24 are shown in FIG7 , one third semiconductor region 13, one third conductive region 53, and one fourth electrode 24 may be provided, or three or more third semiconductor regions 13, three or more third conductive regions 53, and three or more fourth electrodes 24 may be provided. The plurality of third semiconductor regions 13 provided have, for example, the same depth h3. That is, the plurality of third semiconductor regions 13 may be formed in the same process.

[0111] For example, the depth h3 of the third semiconductor region 13 is smaller than the depth h2 of the second semiconductor region 12. For example, the second semiconductor region 12 and the third semiconductor region 13 can be formed in the same process.

[0112] The third semiconductor region 13 is in contact with the first main surface 10a. For example, the depth h3 of the third semiconductor region 13 is smaller than the depth h2 of the second semiconductor region 12. For example, the second semiconductor region 12 and the third semiconductor region 13 are formed by the same process. Even when the second semiconductor region 12 and the third semiconductor region 13 are formed by the same process, since the insulating member 42 is provided between the first main surface 10a and the second semiconductor region 12, the depth measured from the first main surface 10a can be made larger in the second semiconductor region 12.

[0113] The third semiconductor region 13 and the fourth electrode 24 are electrically connected to each other through the third conductive region 53. The fourth electrode 24 functions as a field plate and improves breakdown voltage by reducing the electric field inside the semiconductor and prevents charges from accumulating in the interlayer insulating film due to the influence of the external environment to improve reliability.

[0114] As described below, by providing the third electrode 23, the second conductive region 52, the fourth electrode 24, and the third conductive region 53, the breakdown voltage of the semiconductor device 102 can be increased. On the other hand, even if the third electrode 23, the second conductive region 52, the fourth electrode 24, and the third conductive region 53 are not provided, the third semiconductor region 13 has a predetermined effect of increasing the breakdown voltage of the semiconductor device 102.

[0115] Hereinafter, the effects of the semiconductor device 102 according to the present embodiment will be described. According to the semiconductor device 102 of the present embodiment, since the third semiconductor region 13 is provided, for example, the electric field generated in the semiconductor portion 10 in the IGBT off state is dispersed in the terminal direction in the third semiconductor region 13. Therefore, since the electric field concentration at the terminal of the cell region CR is suppressed, the breakdown voltage can be improved.

[0116] For example, in Figure 6 In the structure including the fourth electrode and the third conductive region 53 shown, the electric field generated in the semiconductor portion 10 in the IGBT off state can also be dispersed from the third semiconductor region 13 to the fourth electrode 24, thereby further improving the breakdown voltage of the semiconductor device 102.

[0117] Furthermore, when a plurality of third semiconductor regions 13 are provided, the electric field dispersed in the third semiconductor regions 13 in the semiconductor portion 10 is also dispersed in the terminal direction between the third semiconductor regions 13. Since the electric field is dispersed in the terminal direction in the plurality of third semiconductor regions 13 provided, the breakdown voltage of the semiconductor device 102 can be increased.

[0118] In addition, similar to the semiconductor device 101 according to the first embodiment, the second semiconductor region 12 improves the breakdown resistance. For example, by promoting the discharge of carriers when the IGBT is turned off, the destruction of the semiconductor device 102 can be suppressed.

[0119] (Third Embodiment)

[0120] Fig. 7A , 7B 7C is a cross-sectional view showing a semiconductor device 103 according to the third embodiment. Description of the same parts as those in the first embodiment will be omitted, and different parts will be described.

[0121] The semiconductor device 103 according to the present embodiment is different from the second embodiment in that the entire third semiconductor region 13 is provided under the insulating member 42. The insulating member 42 is located between the first insulating film 41 and the first surface 10c. The insulating member 42 is provided in contact with the second semiconductor region 12 and the third semiconductor region 13.

[0122] The depth h3 of the third semiconductor region 13 is common to, for example, a plurality of third semiconductor regions 13 provided. The third semiconductor regions 13 having the common depth h3 can be formed in the same process. In addition, h2 and h3 are, for example, the same. The second semiconductor region 12 and the third semiconductor region 13 can be formed in the same process.

[0123] The third conductive region 53 penetrates the first insulating film 41 and the insulating member 42 and contacts the third semiconductor region 13. The fourth electrode 24 and the third semiconductor region 13 face each other via the first insulating film 41 and the insulating member 42, and are electrically connected to each other through the third conductive region 53. The fourth electrode and the third conductive region 53 are formed of, for example, a metal containing Al.

[0124] So far, references have been Fig. 7A The semiconductor device 103 according to the third embodiment is described. Figure 7B and Figure 7C The structure of the electrode and the conductive region provided in the third semiconductor region 13 is shown. Fig. 7A First, we will describe Figure 7B .

[0125] exist Figure 7B In the embodiment, the fourth electrode 24 is provided on the first insulating film 41, and the fifth electrode 25 is provided between the insulating member 42 and the first insulating film 42. A third conductive region 53 is provided to electrically connect the third semiconductor region 13 and the fourth electrode 24 to each other, and a fourth conductive region 54 is provided to connect the fourth electrode 24 and the fifth electrode 25 to each other.

[0126] The fifth electrode 25 is electrically connected to the third semiconductor region 13 through the fourth conductive region 54, the fourth electrode 24 and the third conductive region 53. Figure 7B In the structure shown in , the electric field generated in the semiconductor portion 10 can also be dispersed between the fifth electrode 25 and the third semiconductor region 13. The fifth electrode 25 is formed of, for example, polycrystalline silicon.

[0127] Next, we will describe Figure 7C .exist Figure 7C In the embodiment, the fifth electrode 25 is provided between the first insulating film 41 and the insulating part 42, and the fifth electrode 25 is electrically connected to the third semiconductor region 13 through the fifth conductive region 55. For example, the fifth conductive region 55 is formed after the insulating part 42 is formed, and the fifth electrode 25 is formed to cover the fifth conductive region 55. Then, the first insulating film 41 is formed.

[0128] Figure 7C The structure shown in can also disperse the electric field generated in the semiconductor portion 10 from the third semiconductor region 13 to the fifth electrode 25. The fifth electrode 25 is formed of, for example, polysilicon. The fifth conductive region 55 is formed of, for example, a metal containing Al.

[0129] like Figure 7C As shown in , providing the fifth electrode 25 between the first insulating film 41 and the insulating member 42 and connecting the fifth electrode 24 to the third semiconductor region 13 does not necessarily require the fourth electrode 24 .

[0130] In the above Fig. 7A , 7B In FIG. 7 or 7C, the structure in which the insulating member 42 is provided between the first insulating film 41 and the third semiconductor region 13 to disperse the electric field above the third semiconductor region 13 is the same.

[0131] Hereinafter, the effects of the semiconductor device 103 according to the present embodiment will be described. According to the semiconductor device 103 of the present embodiment, the third semiconductor region 13 formed on the first face 10c is in contact with the insulating member 42, which is different from the semiconductor device 102 according to the second embodiment. The third semiconductor region 13 is provided below the first face 10c. Therefore, the diffusion length of the dopant in the Z direction required to form the third semiconductor region 13 of the same depth in the semiconductor device 103 is smaller than the diffusion length in the semiconductor device 102 according to the second embodiment.

[0132] Compared with the semiconductor device 102 according to the second embodiment, the semiconductor device 103 according to the present embodiment has a structure in which the depth h3 of the third semiconductor region 13 is equal to the sum of the thickness of the insulating member 42 in the Z direction and the thickness of the third semiconductor region 13 in the Z direction. Therefore, the required amount of the diffusion length of the dopant is smaller than the amount of the diffusion length of the dopant in the semiconductor device 102 according to the second embodiment.

[0133] In other words, in the semiconductor device 103 according to the present embodiment, even if the diffusion length of the dopant is shorter than that of the semiconductor device 102 according to the second embodiment, a deeper third semiconductor region 13 can be formed. Since the third semiconductor region 13 having the same depth as the second semiconductor region 12 can be formed by performing annealing at a temperature lower than that in the case of the structure shown in the semiconductor device 102 according to the second embodiment, defects of the Si wafer can be further suppressed.

[0134] In addition, since the third semiconductor region 13 is formed in the same process as the second semiconductor region 12, for example, the third semiconductor region 13 having the same depth h3 as h2 can be obtained. By forming the third semiconductor region 13 deeper than in the case of the semiconductor device 102 according to the second embodiment, the dispersion of the electric field to the third semiconductor region 13 is promoted in the semiconductor portion 10. That is, the third semiconductor region 13 can be formed by a low temperature annealing process, and the breakdown voltage of the semiconductor device 103 can be improved.

[0135] (Fourth Embodiment)

[0136] Figure 81 is a cross-sectional view showing a semiconductor device 104 according to a fourth embodiment. Description of the same parts as those in the third embodiment will be appropriately omitted.

[0137] The semiconductor device 104 according to the present embodiment includes a gate wiring section 330 located on the insulating member 42 in the termination region ER. The gate wiring section 330 is electrically connected to at least one of the plurality of gate electrodes 31 formed in the cell region CR. Figure 8 In the embodiment, the gate wiring portion 33 is not connected to the gate electrode 31, but is connected to the gate electrode 31. Figure 8 In the cross-section shown, which is different from the cross-section, it is electrically connected to the gate electrode 31.

[0138] That is to say, Figure 1 In the top view shown, for example, the gate wiring section 33 is formed to surround the cell region CR, but Figure 8 Only the cross section in the direction in which the cell region CR and the termination region ER are adjacent to each other in the X direction is shown. Figure 8 In a different cross section (for example, in a direction in which the cell region CR and the termination region ER are adjacent to each other in the Y direction), it is electrically connected to at least a portion of the gate electrode 31 .

[0139] The gate wiring portion 33 is formed of, for example, a metal containing Al. For example, the gate wiring portion 33 can be formed in the same process as the fifth electrode 25 .

[0140] although Figure 8 The case where the gate wiring portion 33 is formed only above the second semiconductor region 12 is shown, but in addition to the gate wiring portion 33, a field plate may be further provided as shown in Fig. 7. In the XZ plane, the gate wiring portion 33 and the field plate may be formed, or the gate wiring portion 33 may be formed in a portion of the terminal region ER surrounding the cell region CR, and the field plate may be formed in a portion thereof.

[0141] Hereinafter, the effects of the semiconductor device 104 according to the present embodiment will be described. According to the semiconductor device 104 of the present embodiment, the gate wiring portion 33 is formed on the insulating member 42 to control the voltage of the gate electrode 31. By forming the gate wiring portion 33 over the second semiconductor region 12 in the termination region, it is not necessary to form the gate wiring portion 33 in the cell region CR. For example, since the emitter of the IGBT can be widely formed in the cell region SR, the on-resistance can be reduced.

[0142] In addition, the gate wiring portion 33 on the insulating member 42 can be formed by, for example, the same process as the process of forming the fifth electrode 25 on the third semiconductor region 13. That is, according to the semiconductor device 104 of the present embodiment, since the gate wiring portion 33 is arranged in the termination region ER, the wiring on the first main surface 10a can be efficiently formed. Therefore, the performance of the semiconductor device 104 can be improved.

[0143] (Fifth Embodiment)

[0144] Fig. 9 1 is a cross-sectional view showing a semiconductor device 105 according to a fifth embodiment. Description of the same parts as those in the third embodiment will be appropriately omitted.

[0145] In the semiconductor device 105 according to the present embodiment, the first surface 10c formed below the insulating member 42 has a plurality of bottoms. The bottom is a portion at least partially parallel to the first main surface 10a. The plurality of bottoms include a first bottom 10c1 and a second bottom 10c2. The second semiconductor region 12 is in contact with the first bottom 10c1, and the third semiconductor region 13 is in contact with the second bottom 10c2.

[0146] For example, the first bottom portion 10c1 is formed deeper than the second bottom portion 10c2. Then, the second semiconductor region 12 provided below the first bottom portion 10c1 is formed deeper than the third semiconductor region 13 provided below the first bottom portion 10c1. For example, the second semiconductor region 12 and the third semiconductor region 13 are formed in the same process. In other words, the second semiconductor region 12 and the third semiconductor region 13 can be formed simultaneously by the process of forming the diffusion layer. Since the first bottom portion 10c1 is formed deeper than the second bottom portion 10c2, even if the second semiconductor region 12 and the third semiconductor region 13 are formed in the same process, h2 can be made greater than h3.

[0147] The number of the bottoms of the first face 10c may be three or more. For example, a plurality of third semiconductor regions 13 provided in bottoms having different depths may be included in the third semiconductor region 13. By providing a plurality of bottoms on the first face 10c, a plurality of third semiconductor regions 13 having different depths may be formed in the same process. A structure may be adopted in which the depths of the plurality of third semiconductor regions 13 are different from each other and the depth of the third semiconductor region 13 decreases in the terminal direction.

[0148] In addition, if Fig. 9As shown in , although the plurality of third semiconductor regions 13 provided is a preferred structure for suppressing electric field concentration, the third semiconductor region 13 may be omitted and a VLD structure may be adopted in which the second semiconductor region 12 is extended in the terminal direction. That is, the second semiconductor region 12 may be provided as a single diffusion layer having a plurality of bottoms on the first surface 10c. By controlling the depth of the plurality of bottoms provided, for example, the second semiconductor region 12 with a reduced depth in the terminal direction may be formed by a single process.

[0149] Hereinafter, the effects of the semiconductor device 105 according to the present embodiment will be described. According to the semiconductor device 105 of the present embodiment, although it is necessary to add a process for providing a plurality of bottoms (e.g., a first bottom 10c1 and a second bottom 10c2) on the first face 10c, the second semiconductor region 12 and the third semiconductor region 13 can be formed in the same process. In addition, the difference between the depth h2 of the second semiconductor region 12 and the depth h3 of the third semiconductor region 13 can be controlled by the depth difference between the first bottom 10c1 and the second bottom 10c2 of the first face 10c.

[0150] The difference between h2 and h3 can be controlled in the process of forming the first face 10c. In other words, the diffusion of the dopant for forming the second semiconductor region 12 and the diffusion of the dopant for forming the third semiconductor region 13 can be performed in the same process. The depths h2 and h3 can be different from each other without adding a new process in the process of forming the diffusion layer. In the semiconductor device 103 according to the third embodiment shown in FIG7, in order to make the depths of the second semiconductor region 12 and the third semiconductor region 13 different, it is necessary to divide the formation of the diffusion layer into two or more processes. On the other hand, according to the semiconductor device 105 of this embodiment, the diffusion layer can be formed in the same process.

[0151] (Sixth Embodiment)

[0152] Fig.10 1 is a cross-sectional view showing a semiconductor device 106 according to a sixth embodiment. Description of the same parts as those in the fifth embodiment will be appropriately omitted.

[0153] In addition to the first surface 10c, Fig.10The semiconductor device 106 shown in also includes a second face 10d formed separately from the first face 10c. The second face 10d is a face including an interface between the insulating component 42 and the third semiconductor region 13. Separating the first face 10c and the second face 10d from each other means that the first main face 10a is between the first face 10c and the second face 10a. In other words, between the first face 10c and the second face 10d formed by digging the first main face 10a, the first main face 10a that has not been dug is inserted. A plurality of second faces 10d can be provided while being separated in the X direction.

[0154] At least a portion of the second surface 10d may have a bottom portion parallel to the first major surface 10a. The shape of the second surface 10d is not limited to Fig.10 The shape shown, for example, could be a bowl shape.

[0155] The second semiconductor region 12 is a diffusion layer provided in contact with the first surface 10 c , and the third semiconductor region 13 is a diffusion layer provided in contact with the second surface 10 d .

[0156] For example, a plurality of second surfaces 10d are formed in the same process. The first surface 10c and the second surface 10d can be etched in at most two separate processes to form the first surface 10c and the second surface 10d. Compared with the fifth embodiment, the number of etching processes does not need to be increased.

[0157] An insulating member 42 is provided between the first surface 10c and the first insulating film 41 and between the second surface 10d and the first insulating film 41. The insulating member 42 is a Fig.10 All of the plurality of insulating films are shown as being spaced apart in the X direction.

[0158] At least a portion of the second surface 10d is in contact with the third semiconductor region 13. For example, the second surface 10d is partially in contact with the third semiconductor region 13 and partially in contact with the first semiconductor region 11. The second surface 10d may be formed across a plurality of divided third semiconductor regions 13.

[0159] The fifth electrode 25 is provided on the insulating member 42. The fifth electrode 25 faces the second surface 10d via the insulating member 42. The fifth electrode 25 is formed of, for example, polycrystalline silicon.

[0160] The depth h2 of the second semiconductor region 12 is greater than the depth h3 of the third semiconductor region 13. For example, the second semiconductor region 12 and the third semiconductor region 13 are formed by the same process.

[0161] Hereinafter, the effect of the semiconductor device 106 according to the present embodiment will be described. In addition to the first face 10c, the semiconductor device 106 according to the present embodiment further includes a second face 10d formed separately from the first face. By forming the insulating member 42 and the fifth electrode 25 on the second face 10d, the breakdown voltage can be improved. In addition, the first main face 10a and the third semiconductor region 13 are partially in contact with each other, and the third semiconductor region 13 having a depth different from the second semiconductor region 12 contacting the first face 10c can be formed in the same process as the process of forming the second semiconductor region 12.

[0162] The second semiconductor region 12 is mainly formed by impurities injected from the first surface 10c. On the other hand, the third semiconductor region 13 is mainly formed by impurities injected from the first main surface 10a. Therefore, while forming the second semiconductor region 12 and the third semiconductor region 13 in the same process including impurity injection, a deeper second semiconductor region 12 can be formed.

[0163] In addition, a structure is possible in which the fifth electrode 25 is opposed to the second surface 10d in the Z direction via the insulating member 42. The second surface 10d is in contact with the third semiconductor region 13, and the fifth electrode 25 serves as a field plate and improves the breakdown voltage by reducing the electric field inside the semiconductor and prevents charges from accumulating in the interlayer insulating film due to the influence of the external environment, thereby improving reliability.

[0164] That is, according to the semiconductor device 106 of the present embodiment, the following effects can be obtained. First, the electric field can be dispersed by the fifth electrode 25 to improve the breakdown voltage of the semiconductor device 106. In addition, the insulating member 42 is formed by digging the first semiconductor region 11, and the fifth electrode 25 is formed on the insulating member 42. Therefore, compared with the case where an insulating film is formed on the first main surface 10a and an electrode is further formed on the insulating film, the step between the cell region CR and the terminal region ER in the Z direction is reduced, which is advantageous in a process such as photolithography.

[0165] According to the semiconductor device of at least one of the first to sixth embodiments described above, the depth h2 of the second semiconductor region 12 provided below the first surface 10c can be made greater than the depth h1 of the gate insulating film 32 of the cell region CR. Since the bottom surface 32a of the gate insulating film 31 and the second semiconductor region 12 are in contact with each other, the electric field concentration on the bottom surface 32a can be suppressed, and the breakdown resistance can be improved by forming a carrier discharge path. In addition, since the second semiconductor region 12 in contact with the bottom surface 32a can be formed by a low-temperature short-time annealing process, the reliability reduction due to defects generated in the Si wafer can be suppressed, and the manufacturing efficiency can be improved.

[0166] Hereinafter, a method of manufacturing a semiconductor device will be described.

[0167] According to an embodiment, a method for manufacturing a semiconductor device includes: a process of forming a first surface by selectively excavating a first main surface of a semiconductor part; a process of forming a second semiconductor region of a second conductivity type by injecting impurities from the first surface into a first semiconductor region of a first conductivity type of the semiconductor part and performing an annealing treatment; a process of forming a first part on the first surface; a process of forming a gate insulating film in the first semiconductor region from the first main surface, wherein the gate insulating film has a bottom surface at least partially in contact with the second semiconductor region; a process of forming a gate electrode covered by the gate insulating film; and a process of forming a first insulating film on the first main surface.

[0168] First, refer to FIG. 11A to FIG. 11G The method for manufacturing the semiconductor device 101 according to the first embodiment will be described. Since the configuration of the cell region CR is not much different from that of a general semiconductor device, part of the description will be omitted. For example, the cell region CR is formed in parallel with the process of manufacturing the termination region ER. For example, an IGBT is formed in the cell region CR.

[0169] First, if Fig.11A As shown in FIG. 1 , a resist 70 is selectively provided on the first main surface 10a of the semiconductor portion 10. Then, in a portion where the resist 70 is not provided, a first surface 10c is formed by digging a portion of the first semiconductor region 11 from the first main surface 10a toward the negative direction of the Z direction. The first surface 10c is the bottom surface of a recessed portion formed by etching the first semiconductor region 11 using a method including, for example, any of the following methods: RIE, wet etching, or chemical dry etching (CDE). The first surface 10c may have Fig.11A The shape shown in or the bowl shape.

[0170] Then, remove Fig.11A , and as shown in FIG. Fig. 11B As shown in , the resist 70% is set again, and from the surface including at least a portion of the first face 10c, the second semiconductor region 12 is formed in the first semiconductor region 11. The second semiconductor region 12 is, for example, a diffusion layer formed of a p-type semiconductor, and is formed in the first semiconductor region 11 formed of an n-type semiconductor. For example, the second semiconductor region 12 is formed by implanting and diffusing boron (B). For example, the method for diffusing the dopant is an annealing process.

[0171] Then, if Fig. 11CAs shown in FIG. 1 , an insulating member 42 is formed on the first main surface 10a and the first surface 10c of the semiconductor portion 10. The insulating member 42 is formed by, for example, chemical vapor deposition (CVD). The insulating member 42 is an oxide film containing silicon oxide (for example, SiO2). The insulating member 42 is formed at least in the portion where the semiconductor portion 10 is dug, and the insulating member 42 is removed when the first surface 10c is formed.

[0172] Then, if Fig.11D As shown in , the remaining insulating member 42 is removed. The process of removing the remaining portion of the insulating member 42 is performed by, for example, wet etching. At least the portion remaining on the first face 10c without being removed is again referred to as the insulating member 42. Fig.11D FIG. 4 shows a state where the insulating member 42 does not remain on the first main surface 10 a , but the insulating member 42 may also remain on the first main surface 10 a . Figure 2 The insulating member 42 of the structure shown.

[0173] Then, if Fig.11E As shown in FIG. , in the unit region CR, for example, Fig.11E The fifth semiconductor region 15 and the sixth semiconductor region 16 are formed as shown. The fifth semiconductor region 15 is a p-type diffusion layer formed by implanting boron, for example. The sixth semiconductor region 16 is an n-type emitter region formed by selectively implanting phosphorus, for example, on the fifth semiconductor region 15.

[0174] After forming the fifth semiconductor region 15 and the sixth semiconductor region 16, the semiconductor portion 10 is excavated to form a gate insulating film 32 and a gate electrode 31. For example, the gate insulating film 32 is an oxide film containing silicon oxide and is formed by CVD in a portion excavated by CDE. The gate electrode 31 is formed of, for example, polycrystalline silicon.

[0175] In the gate insulating film 32, the bottom surface 32a of the gate insulating film 32 closest to the termination region ER at least partially contacts the second semiconductor region 12 that has been formed in the previous process. For example, the entire bottom surface 32a may contact the second semiconductor region 12.

[0176] When the semiconductor portion 10 is dug to form the gate insulating film 32 closest to the termination region ER, at least a portion of the semiconductor portion 10 including the already formed second semiconductor region 12 is dug.

[0177] After forming a structure including gate electrode 31 and gate insulating film 32 in cell region CR, first insulating film 41 is provided on cell region CR and termination region ER on first main surface 10a of semiconductor portion 10 and insulating member 42. First insulating film 41 is an oxide film containing silicon oxide (eg, SiO2).

[0178] Then, if Fig.11F As shown in FIG. 1 , a second conductive region 52 is formed in the terminal region ER. This process is performed by selectively digging the first insulating film 41 and the insulating member 42 and embedding the conductive material. The first insulating film 41 and the insulating member 42 are selectively removed by, for example, reactive ion etching (RIE). The conductive material is, for example, a metal containing Al. For example, the conductive material is provided by sputtering or chemical vapor deposition (CVD).

[0179] The third electrode 23 is provided on the first insulating film 41. For example, the third electrode 23 is formed by sputtering. The second conductive region 52 and the third electrode 23 may be formed of materials having the same conductivity type or may be formed of different materials. The third electrode 23 is formed of, for example, a metal containing Al.

[0180] Alternatively, the second conductive region 52 may be formed in the same process as the process of forming the first insulating film 41 and then forming the second conductive region 52. Fig.11F The first conductive region 51 of the unit region CR shown in FIG. can be formed in the same process as the process of forming the third electrode 23. Fig.11G The second electrode 22 in the cell region CR is shown in FIG.

[0181] Fig.11G Shows Fig.11F The structure of the second main surface 10b side is not omitted. For example, the structure of the second main surface 10b side is formed as follows, and an IGBT is formed in the cell region CR.

[0182] A fourth semiconductor region 14 is formed on a second main surface 10b opposite to the first main surface 10a. For example, the fourth semiconductor region 14 is a collector region obtained by injecting B (boron) from the second main surface 10b. Then, a first electrode 21 is provided on the second main surface 10b. The first electrode 21 has a structure shared with the cell region CR and the terminal region ER. When an IGBT is formed in the cell region CR, the first electrode 21 is a collector and the second electrode 22 is an emitter.

[0183] At least a portion of the second electrode 22 or the third electrode 23 provided on the first main surface 10a is covered with a protective film 60. For example, the protective film 60 is formed by coating polyimide. FIG. 11A to FIG. 11G The method for manufacturing the semiconductor device 101 according to the first embodiment is described.

[0184] Then, refer to Fig.12 A method for manufacturing the semiconductor device 102 according to the second embodiment will be described. FIG. 11A to FIG. 11G1 and 2 show different parts of the method for manufacturing the semiconductor device 101 according to the first embodiment. Fig.12 The process of implanting dopants to form the second semiconductor region 12 and the third semiconductor region 13 is shown.

[0185] Fig.12 The process shown in Fig. 11B , a process of implanting dopants at positions where resist 70 is provided. A plurality of portions where resist 70 is not provided are provided in the X direction. Resist 70 is not formed on at least a portion of the first surface 10c. In addition, in the terminal direction starting from the first surface 10c, a portion of the first main surface 10a is not covered with resist 70.

[0186] Impurities are injected into the first semiconductor region 11 from a portion where the resist 70 is not provided, thereby forming the second semiconductor region 12 and the third semiconductor region 13. For example, the second semiconductor region 12 and the third semiconductor region 13 are p-type diffusion layers formed in the n-type first semiconductor region 11. The second semiconductor region 12 and the third semiconductor region 13 can be formed by the same diffusion layer formation process.

[0187] The process of providing the insulating member 42 or the first insulating film 41 after forming the second semiconductor region 12 and the third semiconductor region 13 is similar to the process in FIG. 11 , and thus the description thereof will be omitted. However, for example, in the same process as the second conductive region 52, the insulating member 42 or the first insulating film 41 is formed. Figure 6 The third conductive region 53 is shown. For example, in the same process as the third electrode 23, a Figure 6 The fourth electrode 24 shown in FIG. So far, reference has been made to Fig.12 The method for manufacturing the semiconductor device 103 according to the third embodiment is described.

[0188] Next, we will refer to Fig.13 The process of forming the third semiconductor region 13 in the method for manufacturing the semiconductor device 103 according to the third embodiment will be described below. Fig.13 As shown in , by providing a plurality of portions on the first surface 10c where the resist 70 is not provided, the second semiconductor region 12 and the third semiconductor region 13 can be formed on the first surface 10c. The second semiconductor region 12 and the third semiconductor region 13 can be obtained by the same process. Impurities can be injected simultaneously to form the second semiconductor region 12 and the third semiconductor region 13. Fig.13 The method for forming the diffusion layer shown is to obtain Fig. 7A , Figure 7B or Figure 7C 2 shows a structure of a semiconductor device 103 according to a third embodiment.

[0189] In addition, for example, the process of forming the second conductive region 52 on the second semiconductor region 12 may be performed simultaneously. Fig. 7A The process of forming the third conductive region 53 shown in FIG. For example, the process of forming the third electrode 23 may be performed simultaneously. Fig. 7A The third conductive region 53 is formed of a metal including Al, for example. For example, the first insulating film 41 and the insulating member 42 are excavated by CDE, and a conductive material is embedded by CVD to form the third conductive region 53. For example, the fourth electrode 24 is formed by sputtering. The fourth electrode 24 is formed of, for example, the same material as the third conductive region 53.

[0190] Next, we will refer to Fig.14A and Fig. 14B An example of a method of making the depths of the second semiconductor region 12 and the third semiconductor region 13 of the semiconductor device 103 according to the third embodiment different will be described. Fig.14A A process of forming the second semiconductor region 12 is shown. Fig. 14B The step of forming the third semiconductor region 13 is shown.

[0191] First, if Fig.14A As shown in FIG. 1 , a resist 70 is provided. By implanting impurities into a portion where the resist 70 is not provided, the second semiconductor region 12 is formed.

[0192] Then, remove Fig.14A 70 shown in part or all of the resist 70, and as shown in Fig. 14B The third semiconductor region 13 is formed by injecting impurities from the portion where the resist 70 is not provided. Fig. 14B The acceleration voltage when implanting impurities in the process shown can be Fig.14A The acceleration voltage in the process is different. As the acceleration voltage during the injection increases, the impurities can reach a deeper position in the first semiconductor region 11. That is, Fig.14A The depth of the diffusion layer formed by the process Fig. 14B The thickness of the diffusion layer formed in the process may be different. The depth h2 of the second semiconductor region 12 and the depth h3 of the third semiconductor region 13 may be different.

[0193] For example, Fig. 14B The case where h2 is formed to be larger than h3 is shown. Fig. 14B In the embodiment, the resist 70 covers the second semiconductor region 12, but the second semiconductor region 12 does not need to be covered by the resist 70. Fig.14A In the second semiconductor region 12 into which the impurities have been implanted, Fig. 14B The process shown in Figure 1 injects impurities. Fig. 14BIn the process, impurities are further injected into the second semiconductor region 12, and the amplitude relationship of h2 being greater than h3 is also maintained.

[0194] In addition, h3 may be larger than h2. For example, the third semiconductor region 13 may be formed first, and then the second semiconductor region 12 may be formed shallower than the third semiconductor region 13. By performing the process of implanting impurities in two or more separate processes, the depths of the second semiconductor region 12 and the third semiconductor region 13 may be different from each other.

[0195] So far, reference has been made to Fig.14A and 14B An example of a method of making the depths of the second semiconductor region 12 and the third semiconductor region 13 of the semiconductor device 104 according to the fourth embodiment different is described.

[0196] Next, we will refer to Fig.15A , Fig. 15B and Fig. 15C A method for manufacturing the semiconductor device 105 according to the fifth embodiment is described. In addition, a process of providing the first face 10c having a plurality of bottoms will be described in detail, and since the rest of the description is the same as the previous description, the rest of the description will be omitted.

[0197] like Fig.15A As shown in FIG. 1 , the second bottom portion 10 c 2 is formed by providing a resist 70 on the first main surface 10 a and performing etching.

[0198] Then, remove Fig.15A 70 shown in part or all of the resist 70, and as shown in Fig. 15B By selectively removing the first semiconductor region 11 in the portion where the resist 70 is not provided, the first bottom portion 10c1 deeper than the second bottom portion 10c2 is formed.

[0199] Then, remove Fig. 15B 70 shown in part or all of the resist 70, and as shown in Fig. 15C As shown in , the resist is set again to form the second semiconductor region 12 and the third semiconductor region 13. The second semiconductor region 12 and the third semiconductor region 13 can be formed by the same process. Since the first bottom 10c1 and the second bottom 10c2 have different depths, the depth h2 of the second semiconductor region 12 and the depth h3 of the third semiconductor region 13 can be made different.

[0200] The second semiconductor region 12 contacts the first bottom 10c1, and the third semiconductor region 13 contacts the second bottom 10c2. For example, when the first bottom 10c1 is deeper than the second bottom 10c2, the depth h2 of the second semiconductor region 12 can be greater than the depth h3 of the third semiconductor region 13.

[0201] according to Fig.15A , Fig. 15B and Fig. 15C The method for manufacturing a semiconductor device shown in the figure can control the difference between the depth h2 of the second semiconductor region 12 and the depth h3 of the third semiconductor region 13 by the difference in depth of the first bottom 10c1 or the second bottom 10c2 of the first surface 10c provided on the first main surface 10a. In addition, the second semiconductor region 12 and the third semiconductor region 13 can be formed in the same process. Fig.15A , Fig. 15B and Fig. 15C The method for manufacturing the semiconductor device according to the fifth embodiment is described.

[0202] 15, the process for providing the first face 10c having a plurality of bottoms may be performed by, for example, the following process (not shown): Furthermore, a case where the first bottom 10c1 is deeper than the second bottom 10c2 will be described.

[0203] First, the portion other than the portion where the first bottom portion 10c1 is to be provided is covered with a resist 70, and the first semiconductor region 11 is etched. Then, the portion where the second bottom portion 10c2 is to be provided is not covered with the resist 70, and the second bottom portion 10c2 is formed by performing a shallower etching than the previous process. In the process of forming the second bottom portion 10c2, the portion where the first bottom portion 10c1 is to be formed may be covered with the resist or may not be covered. As described above, by the method of first forming a deeper bottom portion, a plurality of bottom portions having different depths can also be formed.

[0204] Finally, refer to Fig.16A and Fig. 16B Description based on Fig.10 A method for manufacturing the semiconductor device 106 according to the sixth embodiment is shown. Fig.16A The process of forming the first surface 10 c to form the second semiconductor region 12 and the third semiconductor region 13 is shown. Fig. 16B The step of forming the second surface 10d is shown.

[0205] First, in Fig.16A In the embodiment of the present invention, the step of forming the first surface 10 c is omitted. For example, the first surface 10 c is formed by selectively forming a resist on the first main surface 10 a and etching the resist.

[0206] like Fig.16A As shown in the figure, the second semiconductor region 12 and the third semiconductor region 13 are formed by forming a resist 70 on the first surface and selectively injecting impurities from the surface including the first surface 10c. The second semiconductor region 12 is mainly formed by the impurities injected from the first main surface 10a. On the other hand, the third semiconductor region 13 is mainly formed by the impurities injected from the first main surface 10a. The second semiconductor region 12 and the third semiconductor region 13 can be formed by the same process.

[0207] Then, in Fig. 16B In the embodiment, the resist 70 is formed again on the surface including the first main surface 10a and the first surface 10c, and the portion where the resist 70 is not provided is selectively excavated to form the second surface 10d. The second surface 10d is formed by excavating the first semiconductor region 11 using a method including, for example, any of the following methods: RIE, wet etching, or chemical dry etching (CDE).

[0208] For example, Fig. 16B As shown in , a plurality of second faces 10d are formed in the X direction. The plurality of second faces 10d can be formed by the same process. In addition, the second faces 10d are in contact with the third semiconductor region 13. The depth of the first face 10c and the depth of the second face 10d may be different.

[0209] So far, reference has been made to Fig.16A and Fig. 16B The method for manufacturing the semiconductor device 106 according to the sixth embodiment is described.

[0210] As described above, the embodiments have been described with reference to specific examples. However, the embodiments are not limited to these specific examples. That is, those obtained by those of ordinary skill in the art by appropriately changing the design of these specific examples are also included in the protection scope of the embodiments of the present invention, as long as these aspects have the characteristics of these embodiments. The elements included in each specific example described above and their arrangement, materials, conditions, shapes, sizes, etc. are not limited to those illustrated and can be appropriately changed.

[0211] In addition, the elements included in each of the embodiments described above can be combined as much as possible technically, as long as these combinations include the features of the embodiments of the present invention, their combinations are also included in the protection scope of these embodiments. In addition, within the conceptual scope of these embodiments, a person of ordinary skill in the art can conceive of various modifications and corrections, and it should be understood that these modifications and corrections also fall within the protection scope of the embodiments of the present invention.

[0212] Although some embodiments of the present invention have been described, these embodiments are only used as examples and are not intended to limit the scope of protection of the present invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the gist of the present invention. These embodiments or their modifications are included in the protection scope or gist of the present invention, and are included in the present invention described in the claims and their equivalents.

Claims

1. A semiconductor device having a cell region and a termination region adjacent to the cell region, the semiconductor device comprising: a semiconductor portion having a first main surface and a second main surface opposite to the first main surface; a first insulating film disposed on the first main surface; a first electrode disposed on the second main surface; a first semiconductor region of a first conductivity type disposed in the semiconductor portion; a second electrode disposed on the first insulating film and electrically connected to the semiconductor portion through the first conductive region; a gate electrode disposed in the semiconductor portion in the cell region; a gate insulating film covering the gate electrode; A second semiconductor region of a second conductivity type, provided between the first semiconductor region from the cell region to the terminal region and the first main surface, and in contact with at least a portion of the bottom surface of the gate insulating film; as well as A first member is provided between the second semiconductor region and the first insulating film.

2. The semiconductor device according to claim 1, wherein A first face including an interface between the first member and the second semiconductor region is closer to the first electrode than the first main face.

3. The semiconductor device according to claim 1, wherein The second semiconductor region, the first component, and the second semiconductor region are arranged in this order along a terminal direction from the cell region to the terminal region.

4. The semiconductor device according to claim 1, wherein The first member is formed of an insulating material.

5. The semiconductor device according to claim 1, wherein The first member is formed of a conductive material.

6. The semiconductor device according to claim 1, wherein In the terminal area, it is further provided that: a third electrode disposed on the first insulating film, and The second conductive region is located between the third electrode and the second semiconductor region, and electrically connects the third electrode and the second semiconductor region to each other.

7. The semiconductor device according to claim 6, wherein: In the terminal area, it is further provided that: A third semiconductor region of the second conductivity type is provided farther from the cell region than the second semiconductor region and is located between the first semiconductor region and the first main surface.

8. The semiconductor device according to claim 7, further comprising: a fourth electrode disposed on the first insulating film; as well as The third conductive region is located between the fourth electrode and the third semiconductor region, and electrically connects the fourth electrode and the third semiconductor region to each other.

9. The semiconductor device according to claim 8, wherein: The first member is also provided between the third semiconductor region and the first insulating film.

10. The semiconductor device according to claim 9, further comprising: a fifth electrode disposed between the first member and the first insulating film; as well as The fourth conductive region is located between the fifth electrode and the fourth electrode, and electrically connects the fifth electrode and the fourth electrode to each other.

11. The semiconductor device according to claim 1, further comprising: The gate wiring portion is provided on the first member and is electrically connected to at least a part of the plurality of gate electrodes.

12. The semiconductor device according to claim 7, wherein: a first surface including an interface between the first component and the second semiconductor region including a first bottom and a second bottom, at least a portion of the first bottom being parallel to the first main surface, the second bottom having a different depth from the first bottom, At least a portion of the second semiconductor region is in contact with the first bottom portion, At least a portion of the third semiconductor region is in contact with the second bottom portion.

13. The semiconductor device according to claim 7, wherein: a second face including an interface between the first component and the third semiconductor region is spaced apart from the first face including an interface between the first component and the second semiconductor region and is formed to be divided into a plurality of parts, The fifth electrode faces the second surface with the first member interposed therebetween.

14. The semiconductor device according to claim 1, wherein The semiconductor unit further includes: A fourth semiconductor region of the second conductivity type is provided between the second main surface and the first semiconductor region, In the unit area, it is further arranged that: a fifth semiconductor region of the second conductivity type disposed on the first semiconductor region; and a sixth semiconductor region of the first conductivity type selectively disposed on the fifth semiconductor region, The gate insulating film is in contact with the fifth semiconductor region and the sixth semiconductor region, and the first conductive region is in contact with the sixth semiconductor region.

15. A method for manufacturing a semiconductor device, comprising: a step of forming a first surface by selectively digging out the first main surface of the semiconductor portion; A step of forming a second semiconductor region of a second conductivity type by implanting impurities from the first surface into a first semiconductor region of a first conductivity type of the semiconductor portion and performing an annealing process; forming a first component on the first surface; forming a gate insulating film in the first semiconductor region from the first main surface, wherein the gate insulating film has a bottom surface at least partially in contact with the second semiconductor region; a step of forming a gate electrode covered with the gate insulating film; and The step of forming a first insulating film on the first main surface.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: In the step of forming the second semiconductor region by implanting impurities into the first semiconductor region from the first surface and performing the annealing process, a third semiconductor region of the second conductivity type spaced apart from the second semiconductor region is also formed.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The process of forming the first surface includes: forming a first bottom and a second bottom, wherein at least a portion of the first bottom is parallel to the first main surface, and the second bottom has a different depth from the first bottom, The step of implanting impurities into the semiconductor portion from the first surface includes: and injecting impurities into the semiconductor portion from the first bottom portion and the second bottom portion.

18. The method for manufacturing a semiconductor device according to claim 16, further comprising: After forming the third semiconductor region by implanting impurities from the first main surface, forming a second surface at least partially in contact with the third semiconductor region by selectively digging the first main surface; as well as The step of forming the first member on the first surface and the second surface.

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