Method for manufacturing selectively activated p-GaN gate HEMT device

Abstract

The invention discloses a method for manufacturing a selectively activated p-GaN gate HEMT device, and relates to the technical field of semiconductor devices, the method comprises the following steps: S1, an epitaxial wafer is selected, the epitaxial wafer comprises a substrate layer, a buffer layer, a channel layer and a barrier layer, and two-dimensional electron gas is formed on a heterojunction interface of the channel layer and the barrier layer to serve as a conductive channel; s2, a p-GaN layer with the thickness ranging from 50 nm to 140 nm is deposited on the epitaxial wafer, the Mg doping concentration ranges from 5 * 10 < 17 > cm <-3 > to 5 * 10 < 20 > cm <-3 >, and Mg impurities are not activated; s3, depositing an n-GaN layer in a partial region of the p-GaN layer obtained in the step S2 to serve as a barrier layer so as to inhibit activation of a part of the p-GaN layer; according to the manufacturing method of the selectively activated p-GaN gate HEMT device, the manufacturing efficiency is remarkably improved, the cost is reduced, the influence of etching damage on the two-dimensional electron gas density and the dynamic characteristics of the device in the manufacturing process of a conventional enhanced GaN HEMT device can be effectively reduced, the cut-off frequency of the device can be improved, the dynamic on-resistance and parasitic capacitance of the device can be reduced, and the reliability of the device can be improved. And the reliability of the device is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for manufacturing a selectively activated p-GaN gate HEMT device. Background Art

[0002] In the field of modern semiconductor devices, new wide bandgap semiconductor materials represented by GaN have become an ideal choice for power semiconductor devices due to their superior intrinsic properties. GaN materials have the characteristics of wide bandgap, high electron mobility, high breakdown field strength, high saturation electron velocity and high thermal conductivity, which give them obvious advantages in high-power and high-frequency applications. In addition, the unique spontaneous polarization and piezoelectric polarization effects of GaN materials enable the formation of a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface, thereby achieving efficient conduction of the device channel.

[0003] Based on the heterojunction characteristics of GaN materials, traditional GaN high electron mobility transistor (HEMT) devices are generally depletion-type (normally open) structures. In practical applications, this device requires a negative voltage power supply to maintain the off state, which not only increases the complexity of circuit design, but also has the risk of circuit error opening, further increasing system power consumption. In contrast, since the enhanced GaN HEMT device is in the off state at zero gate voltage, it does not require negative voltage drive, which can significantly reduce additional power consumption and simplify circuit design, and is a more ideal solution. In order to realize the enhanced GaN HEMT, p-GaN cap layer technology has become the mainstream method. This technology forms enhanced characteristics by growing a layer of p-GaN layer on the surface of the device, and does not require additional processing of the gate. Its advantages are stable performance, high repeatability, and strong reliability. It has become an important technical approach for the commercialization of GaN power devices. However, the traditional p-GaN dry etching process has great limitations. First, the etching process is prone to damage the surface and introduce defects, affecting device performance and reliability. Secondly, the etching accuracy has a significant impact on device performance. Etching depth that is too shallow or too deep will lead to the depletion of the two-dimensional electron gas, thereby reducing the saturated output current of the device. In addition, it is difficult to achieve a T-shaped gate electrode shape using traditional dry etching processes, which limits the design requirements of RF devices such as short gate feet and wide gate heads, and cannot meet the needs of high-frequency applications. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a selectively activated p-GaN gate HEMT device to solve the problems existing in the prior art.

[0005] To achieve the above object, the present invention provides the following technical solution: a method for manufacturing a selectively activated p-GaN gate HEMT device, the method comprising:

[0006] S1. Selecting an epitaxial wafer, wherein the epitaxial wafer comprises a substrate layer, a buffer layer, a channel layer, and a barrier layer, wherein a two-dimensional electron gas is formed at a heterojunction interface between the channel layer and the barrier layer as a conductive channel;

[0007] S2, depositing a p-GaN layer with a thickness of 50nm-140nm on the epitaxial wafer, and a Mg doping concentration of 5×10 17 -5×10 20 cm -3 , Mg impurities are not activated;

[0008] S3, depositing an n-GaN layer on a portion of the p-GaN layer obtained in step S2, wherein the n-GaN layer serves as a barrier layer to inhibit activation of the p-GaN layer, the thickness of the n-GaN layer is 5 nm to 200 nm, and the Si doping concentration is 1×10 16 -1×10 20 cm -3 ;

[0009] S4, performing a thermal annealing treatment on the epitaxial wafer obtained in step S3, activating Mg impurities in the p-GaN layer not covered by the n-GaN layer in a N2 atmosphere, and forming a p-GaN gate;

[0010] S5. Prepare a gate metal electrode on the p-GaN gate. The structure of the gate metal electrode is Ni / Au or TiN or W from bottom to top, forming a Schottky contact with the p-GaN gate. The conductive channel of the two-dimensional electron gas is regulated by the p-GaN gate and the gate metal electrode.

[0011] Preferably, between step S4 and step S5 or after step S5, the following steps are further included:

[0012] A source electrode and a drain electrode are prepared on the surface of the barrier layer on both sides of the p-GaN gate and the gate metal electrode, wherein the source electrode and the drain electrode respectively form an ohmic contact with the two-dimensional electron gas;

[0013] The metal structures of the source electrode and the drain electrode are Ti, Al, Ni and Au in sequence.

[0014] Preferably, a layer of SiO2 with a thickness of 30nm-50nm is deposited on the surface of the epitaxial wafer, and chemical mechanical polishing is used to remove the SiO2 and the remaining n-GaN layer.

[0015] Preferably, the length of the p-GaN gate in S4 is 10 nm-1 μm, and the gate metal electrode and the p-GaN gate form a "T"-shaped gate structure, which is used for high-frequency radio frequency devices.

[0016] Preferably, mesa etching or ion implantation is added between S2 and S3 or between S3 and S4 to achieve device isolation.

[0017] Preferably, each epitaxial layer of the epitaxial wafer is grown by metal organic chemical vapor deposition method, and the mesa etching is achieved by inductively coupled plasma technology.

[0018] Preferably, the temperature of the thermal annealing treatment in S4 is 700° C.-850° C., the holding time is 30 seconds-35 seconds, and the annealing atmosphere is nitrogen.

[0019] Preferably, the Mg doping concentration of the p-GaN layer is 2.5×10 18 -1×10 20 cm 3 The Si doping concentration of the n-GaN layer is specifically 3×10 17 -8×10 20 cm 3 .

[0020] Preferably, the gate metal electrode in S5 is deposited by electron beam evaporation technology, and the metal materials are Ni / Au in sequence, wherein the thickness of Ni is 30nm-50nm, and the thickness of Au is 100nm-150nm.

[0021] Preferably, a mask region of the n-GaN layer is precisely defined between S3 and S4 by a photolithography process.

[0022] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0023] The selectively activated p-GaN gate HEMT device manufacturing method forms a shielding effect on the p-GaN layer by depositing an n-GaN layer in a partial area of ​​the p-GaN layer, and combines a thermal annealing process to accurately activate the Mg doping in the unshielded p-GaN layer, thereby achieving selective activation of the local area, significantly improving the performance of the p-GaN gate, and avoiding the device performance degradation problem that may be caused by full activation. By introducing chemical mechanical polishing and inductively coupled plasma technology to replace the traditional dry etching process, the physical damage and defect density on the surface of the p-GaN and n-GaN layers are reduced, and the performance stability and long-term reliability of the device are improved. The prepared source electrode and drain electrode adopt a metal combination of Ti / Al / Ni / Au, which can form an excellent ohmic contact with the two-dimensional electron gas, effectively reduce the contact resistance, improve the conductivity of the device, and improve the power efficiency. The p-GaN gate length (10nm to 1μm) and the T-shaped structure design of the gate metal electrode are determined to meet the special requirements of high-frequency RF devices for short gate feet and wide gate heads, and the gain and efficiency of the device in a high-frequency environment are improved. The gate metal electrode is deposited by electron beam evaporation process, and the Ni / Au metal combination realizes a stable Schottky contact. The thickness of the metal layer is precisely controllable, which further improves the preparation accuracy and conductivity of the gate electrode. The mask area of ​​the n-GaN layer is precisely defined by the photolithography process. Combined with the mesa etching technology, the structural dimensions of the n-GaN layer and the p-GaN layer are highly controllable, which greatly improves the repeatability of the manufacturing process and the consistency of the device. Each epitaxial layer is grown by metal organic chemical vapor deposition technology. The process is mature and suitable for mass production. Combined with precise thermal annealing and photolithography technology, the manufacturing efficiency is significantly improved and the cost is reduced. It can effectively reduce the influence of etching damage on the two-dimensional electron gas density and the dynamic characteristics of the device during the manufacturing process of conventional enhancement-mode GaN HEMT devices, which is beneficial to improve the cut-off frequency of the device, reduce the dynamic on-resistance and parasitic capacitance of the device, and enhance the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the device structure formed after steps S1 and S2 of the present invention;

[0025] Figure 2 is a schematic diagram of the device structure formed after step S3 of the present invention;

[0026] Figure 3 is a schematic diagram of the device structure formed after step S4 of the present invention;

[0027] Figure 4 , Figure 5 Schematic diagram of the device structure of the process between steps S4 and S5 of the present invention;

[0028] Figure 6A schematic diagram of the device structure formed after the step of claim 2 of the present invention;

[0029] Figure 7 A schematic diagram of the device structure formed after the step of claim 5 of the present invention;

[0030] Figure 8 is a schematic diagram of the device structure formed after step S5 of the present invention;

[0031] Fig. 9 It is a top view of the device structure formed after step S5.

[0032] In the figure: 1. substrate layer; 2. buffer layer; 3. channel layer; 4. barrier layer; 5. p-GaN layer; 6. n-GaN layer; 7. p-GaN gate; 8. source electrode; 9. drain electrode; 10. gate metal electrode. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] like Figure 1-Figure 9 As shown, the present invention provides a technical solution: a method for manufacturing a selectively activated p-GaN gate HEMT device, comprising the following steps:

[0035] S1. Selecting an epitaxial wafer: Selecting an epitaxial wafer 11, the epitaxial wafer 11 comprises a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4, wherein a two-dimensional electron gas is formed at a heterojunction interface between the channel layer 3 and the barrier layer 4 as a conductive channel.

[0036] S2, p-GaN layer deposition: a p-GaN layer 5 with a thickness of 50nm-140nm is deposited on the epitaxial wafer 11, and the Mg doping concentration is 5×10 17 -5×10 20 cm －3 , Mg impurities are not activated.

[0037] S3, n-GaN layer deposition: n-GaN layer 6 is deposited on a part of the p-GaN layer 5 obtained in step S2. The n-GaN layer 6 serves as a barrier layer to inhibit the activation of the p-GaN layer 5. The thickness of the n-GaN layer 6 is 5nm-200nm, and the Si doping concentration is 1×10 16 -1×10 20 cm －3 .

[0038] S4, thermal annealing: thermal annealing is performed on the epitaxial wafer 11 obtained in step S3 to activate the Mg impurities in the p-GaN layer 5 not covered by the n-GaN layer 6 in a N2 atmosphere to form a p-GaN gate 7.

[0039] S5. Preparation of gate metal electrode: A gate metal electrode 10 is prepared on the p-GaN gate 7. The structure of the gate metal electrode 10 is Ni / Au or TiN or W from bottom to top, forming a Schottky contact with the p-GaN gate 7. The conductive channel of the two-dimensional electron gas is regulated by the p-GaN gate 7 and the gate metal electrode 10.

[0040] The p-GaN layer 5 is selectively covered by the n-GaN layer 6 to ensure that only the Mg impurities in the uncovered area are activated during the thermal annealing process, forming a p-GaN gate 7 with local functions. The gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7, and the functional control of the HEMT device is achieved by effectively regulating the conductive channel of the two-dimensional electron gas. Through the blocking effect of the n-GaN layer 6, only the p-GaN layer 5 needs to be locally activated to reduce energy consumption. The Schottky contact improves the current control capability and high-frequency performance of the device, which is suitable for high-power and high-frequency scenarios. The selective activation technology is used to avoid the complexity of activating the entire p-GaN layer and improve the process efficiency.

[0041] In one possible implementation, source and drain electrodes are prepared: source electrode 8 and drain electrode 9 are prepared on the surface of barrier layer 4 on both sides of p-GaN gate 7 and gate metal electrode 10, and source electrode 8 and drain electrode 9 respectively form ohmic contact with two-dimensional electron gas. The metal structures of source electrode 8 and drain electrode 9 are Ti, Al, Ni and Au, respectively. Source electrode 8 and drain electrode 9 form a low-resistance channel through ohmic contact with the two-dimensional electron gas, supporting efficient transmission of electrons in channel layer 3, and the multi-layer metal structure optimizes contact performance and ensures good conductivity and reliability. The multi-layer structure of Ti, Al, Ni and Au significantly reduces contact resistance and optimizes electron transmission efficiency. The thermal stability and mechanical strength of the electrode are improved through multi-layer metal selection.

[0042] In one possible implementation, a layer of SiO2 is deposited on the surface of the epitaxial wafer 11 with a thickness of 30nm-50nm, and then chemical mechanical polishing is used to remove the SiO2 and the remaining n-GaN layer 6. After the p-GaN gate 7 is formed, a SiO2 protective layer is deposited to cover the surface of the epitaxial wafer 11. The SiO2 layer and the residual n-GaN layer 6 are selectively removed by chemical mechanical polishing technology, so that the surface of the p-GaN gate 7 is cleaned while ensuring the integrity of other areas. Precise control of chemical mechanical polishing can avoid damage to the p-GaN layer 5, thereby ensuring the quality and functionality of the gate area. The residual n-GaN layer 6 and surface impurities are effectively removed, and the surface conditions of the p-GaN gate 7 are optimized. The high precision of chemical mechanical polishing is used to achieve precise control of the surface material and improve process reliability. By cleaning the gate surface, the contact performance between the metal electrode and the p-GaN gate 7 is improved.

[0043] In one possible implementation, the length of the p-GaN gate 7 is 10nm-1μm, and the gate metal electrode 10 and the p-GaN gate 7 form a "T"-type gate structure for high-frequency RF devices. By designing the p-GaN gate 7 to be 10nm-1μm in length, the gate region size of the HEMT device is optimized to ensure good capacitance characteristics and gate control performance in high-frequency applications. The gate metal electrode 10 adopts a "T"-type gate design, which improves the mechanical stability and thermal dissipation performance of the electrode while reducing the gate resistance. The top extension of the "T"-type gate structure can be used as a heat dissipation layer to improve the power capacity and thermal management performance of the RF device. By shortening the gate length, the switching speed and high-frequency performance of the device are improved. The "T"-type gate design is used to enhance the heat dissipation capability and improve the stability under high-power conditions. It is suitable for application scenarios that require high frequency and low power consumption, such as 5G communications.

[0044] In one possible implementation, a mesa etching or ion implantation step is added between steps S2 and S3 or between steps S3 and S4. Mesa etching or ion implantation is used to partially etch the surface of the p-GaN layer 5 or the n-GaN layer 6 to form a more defined hierarchical structure and regional separation. Through the etching process, the contact characteristics of the p-GaN gate 7 with the surrounding layers can be adjusted to optimize the gate control effect and interface quality. This etching step can also provide a smoother surface for subsequent photolithography mask or metal electrode deposition, thereby improving process accuracy. Through etching technology, a clear boundary between the p-GaN gate 7 region and the n-GaN layer 6 is ensured, thereby improving device performance. Etching cleans up surface defects and residual materials, thereby improving the deposition effect and contact performance of the gate metal electrode 10. A smoother and more regular surface is provided for subsequent process steps, thereby reducing the error rate in the process.

[0045] In a possible embodiment, each epitaxial layer is grown by a metal organic chemical vapor deposition method, and the mesa etching is achieved by inductively coupled plasma technology. The epitaxial layers of the epitaxial wafer 11, including the buffer layer 2, the channel layer 3, the barrier layer 4, the p-GaN layer 5 and the n-GaN layer 6, are grown by the MOCVD method, ensuring the uniformity and high-quality crystal structure of the material. The mesa etching adopts ICP technology, which uses the high energy and high directionality of high-density plasma to achieve precise etching of the epitaxial layer surface to form a clear etching boundary. ICP technology can also regulate the etching rate to avoid excessive damage to the underlying material and improve the processing quality. High quality of epitaxial layer: MOCVD process ensures high uniformity and excellent crystal properties of epitaxial wafers and reduces defect density. High etching accuracy: The high directionality and high selectivity of ICP technology ensure the clarity of etching boundaries and optimize the integrity of the structure and device performance. Wide applicability: Both MOCVD and ICP technologies are mature processes, suitable for large-scale production, and have high process repeatability.

[0046] In a possible implementation, the thermal annealing treatment temperature in step S4 is 700°C-850°C, the holding time is 30 seconds-35 seconds, and the annealing atmosphere is nitrogen. During the thermal annealing process, the Mg impurities in the p-GaN layer 5 not covered by the n-GaN layer 6 are activated in a high-temperature nitrogen atmosphere to form a p-type conductive region (p-GaN gate 7). The optimization of the annealing temperature range (700°C-850°C) and the holding time (30 seconds-35 seconds) ensures the activation efficiency of the p-GaN layer 5 while avoiding thermal damage to the underlying structure. The use of pure nitrogen as the annealing atmosphere avoids the potential impact of oxidation or hydrogenation on the performance of the p-GaN layer 5. By precisely controlling the annealing temperature and time, the full activation of the Mg impurities in the p-GaN layer 5 is ensured, and the conductive performance of the p-GaN gate 7 is improved. The use of a nitrogen atmosphere avoids the introduction of impurities and the degradation of material properties, and ensures the reliability of the process. The optimized annealing parameters reduce the impact of the heat treatment on other layers in the epitaxial wafer 11 and improve the overall performance stability of the device.

[0047] In a possible implementation, the Mg doping concentration of the p-GaN layer 5 is 2.5×10 18 -1×10 20 cm －3 , the Si doping concentration of the n-GaN layer 6 is 3×10 17 -8×10 20 cm －3 The Mg doping concentration of the p-GaN layer 5 is adjusted to ensure that it has an appropriate hole concentration after activation, thereby optimizing the conductivity and gate control capability of the p-GaN gate 7. The Si doping concentration range of the n-GaN layer 6 is optimized to be 3×10 17 -8×10 20cm －3 , to provide an effective blocking effect, inhibit the activation of the p-GaN layer 5 in a specific area, and form a clear functional partition. By controlling the doping concentration, the electron gas channel can be precisely regulated to optimize device performance. Optimized conductive performance: The Mg doping concentration range of the p-GaN layer 5 ensures that the hole concentration after activation meets high performance requirements. Clear functional areas: The optimized doping concentration of the n-GaN layer 6 inhibits the local activation of the p-GaN layer 5, significantly improving the clarity and stability of the functional partition. Enhanced high-frequency characteristics: Through precise control of the doping concentration, the switching characteristics of the electron gas channel are optimized, and the high-frequency performance of the HEMT device is improved.

[0048] In a possible implementation, the gate metal electrode 10 in step S5 is deposited by electron beam evaporation technology, and the metal materials are Ni / Au in sequence, wherein the thickness of Ni is 30nm-50nm, and the thickness of Au is 100nm-150nm. The gate metal electrode 10 is deposited on the surface of the p-GaN gate 7 by electron beam evaporation technology to ensure the thickness uniformity and surface quality of the metal layer. Ni, as a Schottky contact layer, forms a stable Schottky barrier with the p-GaN gate 7 to regulate the conductive channel of the two-dimensional electron gas. Au, as a protective layer and a conductive layer, provides excellent electrical properties and oxidation resistance while ensuring thermal stability. The Schottky contact of the Ni / Au structure has low work function difference and high stability, which improves the gate control effect. Electron beam evaporation technology can accurately control the metal thickness and deposition rate, ensuring the repeatability of the process and the formation of a high-quality metal layer. The addition of the Au layer significantly improves the oxidation resistance of the electrode and extends the service life of the device.

[0049] In one possible implementation, the mask area of ​​the n-GaN layer 6 is precisely defined between steps S3 and S4 by a photolithography process. A mask pattern is made on the surface of the n-GaN layer 6 by a photolithography process to clearly define the boundaries of the activation area and the blocking area. The photolithography mask process uses steps such as resist coating, exposure, development, and etching to ensure the precise position and boundary quality of the mask area. The definition of the mask area provides a basis for the selective activation of the p-GaN layer 5 during the subsequent thermal annealing process, ensuring the accuracy and effect of the activation. Accurate activation area: The photolithography process defines the mask area of ​​the n-GaN layer 6, achieves high-precision control of the activation area, and improves the consistency and stability of the device. High process compatibility: The photolithography process is highly compatible with conventional semiconductor process flows and is easy to integrate into large-scale production. Flexible structural design: Through the design of the mask pattern, the coverage area of ​​the n-GaN layer 6 can be flexibly adjusted to meet the design requirements of different devices.

[0050] An embodiment is also provided, in which the transistor structure used in the present invention comprises: a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a p-GaN layer 5, wherein the p-GaN layer 5 is selectively activated to obtain a p-GaN gate 7, a source electrode 8 and a drain electrode 9 are arranged above the barrier layer 4, and a gate metal electrode 10 is arranged above the p-GaN gate 7;

[0051] The material of substrate layer 1 is Si, with a thickness of 200μm; the material of buffer layer 2 is GaN, with a thickness of 5000nm; the material of channel layer 3 is GaN, with a thickness of 200nm. The material of barrier layer 4 is AlGaN, with a thickness of 15nm, an Al component of 0.21, and a Ga component of 0.79. The structures of source electrode 8 and drain electrode 9 are Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 120 / 45 / 55nm. Source electrode 8 and drain electrode 9 form ohmic contacts with barrier layer 4. The thickness of p-GaN layer 5 is 90nm, and the Mg doping concentration is 2.5×10 19 cm -3 The thickness of the n-GaN layer 5 is 10 nm, and the Si doping concentration is 3×10 18 cm -3 The structure of the gate metal electrode 10 is Ni / Au from bottom to top, and the thickness is 30 / 120nm respectively. The gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7. The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas under the gate so that the GaN transistor can achieve enhancement mode operation.

[0052] A method for manufacturing a selectively activated p-GaN gate HEMT device comprises the following steps:

[0053] 1. Use Si substrate for material epitaxy, and sequentially grow composite buffer layer, channel layer, barrier layer, p-GaN layer and n-GaN layer, such as Figure 1 As shown;

[0054] 2. Clean the epitaxial wafer obtained in step 1 by soaking it in a piranha solution of H2SO4:H2O2=7:3 for 1 minute to remove oxides and impurities on the surface of the epitaxial wafer, and then perform organic cleaning, that is, ultrasonically clean it in acetone solution and isopropanol solution for five minutes each;

[0055] 3. Carry out the operations of coating, pre-baking and exposure on the cleaned epitaxial wafer; adopt the AZ5214 photoresist inversion process and expose the photoresist pattern other than the p-GaN gate through the MA6 photolithography machine;

[0056] 4. Remove the n-GaN in the gate area by ICP dry etching, such as Figure 2As shown;

[0057] 5. Perform a rapid thermal annealing treatment on the epitaxial wafer at 700°C for 35 min in a N2 atmosphere to activate the Mg impurities in the gate region of the p-GaN layer 5 to obtain a p-GaN gate 7, as shown in FIG. Figure 3 As shown;

[0058] 6. Deposit a layer of SiO2 on the surface of the epitaxial wafer with a thickness of 50nm. Figure 4 As shown; chemical mechanical polishing (CMP) is used to remove SiO2 together with the remaining n-GaN layer 6, as shown Figure 5 As shown;

[0059] 7. Use AZ6112 photoresist and expose it through MA6 photolithography machine to prepare the photoresist pattern of the mesa; use ICP dry etching to remove the part outside the mesa, the etching depth is 200nm, and complete the device isolation, such as Figure 6 As shown;

[0060] 8. Using AZ5214 photoresist reversal process, the photoresist pattern other than the source and drain electrodes is prepared by exposure through MA6 photolithography machine; multilayer metal Ti / Al / Ni / Au is grown by electron beam evaporation, wherein the thickness of Ti is 20nm, the thickness of Al is 120nm, the thickness of Ni is 45nm, and the thickness of Au is 55nm, and the source electrode 8 and the drain electrode 9 are formed after stripping, as shown in FIG. Figure 7 As shown;

[0061] 9. Perform rapid thermal annealing for 32 seconds in a N2 atmosphere at 820°C, so that the source electrode 8 and the drain electrode 9 form an ohmic contact with the AlGaN barrier layer;

[0062] 10. The AZ5214 photoresist inversion process is used on the surface of the p-GaN gate 7, and the photoresist pattern other than the gate metal electrode is prepared by exposure through the MA6 photolithography machine, and Ni / Au is grown by electron beam evaporation, wherein the thickness of Ni is 30nm and the thickness of Au is 120nm; after stripping, the gate metal electrode 10 is prepared, as shown in FIG. Figure 8 As shown; the gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7, and the two-dimensional electron gas in the channel below is depleted through the p-GaN gate 7, thereby obtaining a selectively activated p-GaN gate HEMT device.

[0063] An embodiment is also provided, in which the transistor structure used in the present invention comprises: a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a p-GaN layer 5, wherein the p-GaN layer 5 is selectively activated to obtain a p-GaN gate 7, a source electrode 8 and a drain electrode 9 are arranged above the barrier layer 4, and a gate metal electrode 10 is arranged above the p-GaN gate 7;

[0064] The material of substrate layer 1 is Sapphire with a thickness of 500μm; the material of buffer layer 2 is AlN with a thickness of 2000nm; the material of channel layer 3 is GaN with a thickness of 300nm. The thickness of barrier layer 4 is 20nm, the Al component is 0.25, and the Ga component is 0.75. The structure of source electrode 8 and drain electrode 9 is Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 120 / 40 / 50nm. Source electrode 8 and drain electrode 9 form ohmic contact with barrier layer 4. The thickness of p-GaN layer 5 is 100nm, and the Mg doping concentration is 1×10 18 cm -3 The thickness of the n-GaN layer 5 is 5 nm, and the Si doping concentration is 6×10 20 cm -3 The structure of the gate metal electrode 10 is Ni / Au from bottom to top, and the thickness is 30 / 120nm respectively. The gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7. The heterojunction interface formed by the channel layer 3 and the barrier layer 4 generates a two-dimensional electron gas as a conductive channel, which is regulated by the p-GaN gate 7 and the gate metal electrode 10. The p-GaN gate 7 can deplete the two-dimensional electron gas under the gate so that the GaN transistor can achieve enhancement mode operation.

[0065] A method for manufacturing a selectively activated p-GaN gate HEMT device comprises the following steps:

[0066] 1. Use Si substrate for material epitaxy, and grow buffer layer, channel layer, barrier layer, p-GaN layer and n-GaN layer in sequence, such as Figure 1 As shown;

[0067] 2. Clean the epitaxial wafer obtained in step 1 by soaking it in a piranha solution of H2SO4:H2O2=7:3 for 1 minute to remove oxides and impurities on the surface of the epitaxial wafer, and then perform organic cleaning, that is, ultrasonically clean it in acetone solution and isopropanol solution for five minutes each;

[0068] 3. Carry out the operations of coating, pre-baking and exposure on the cleaned epitaxial wafer; adopt the AZ5214 photoresist inversion process and expose the photoresist pattern other than the p-GaN gate through the MA6 photolithography machine;

[0069] 4. Remove the n-GaN in the gate area by ICP dry etching, such as Figure 2 As shown;

[0070] 5. Perform a rapid thermal annealing treatment on the epitaxial wafer at 700°C for 35 min in a N2 atmosphere to activate the Mg impurities in the gate region of the p-GaN layer 5 to obtain a p-GaN gate 7, as shown in FIG. Figure 3 As shown;

[0071] 6. Deposit a layer of SiO2 on the surface of the epitaxial wafer with a thickness of 30nm. Figure 4 As shown; chemical mechanical polishing (CMP) is used to remove SiO2 together with the remaining n-GaN layer 6, as shown Figure 5 As shown;

[0072] 7. Use AZ6112 photoresist and expose it through MA6 photolithography machine to prepare the photoresist pattern of the mesa; use ICP dry etching to remove the part outside the mesa, the etching depth is 200nm, and complete the device isolation, such as Figure 6 As shown;

[0073] 8. Using AZ5214 photoresist reversal process, the photoresist pattern other than the source and drain electrodes is prepared by exposure through MA6 photolithography machine; multilayer metal Ti / Al / Ni / Au is grown by electron beam evaporation, wherein the thickness of Ti is 20nm, the thickness of Al is 120nm, the thickness of Ni is 40nm, and the thickness of Au is 50nm, and the source electrode 8 and the drain electrode 9 are formed after stripping, as shown in FIG. Figure 7 As shown;

[0074] 9. Perform rapid thermal annealing for 30 seconds in a N2 atmosphere at 850°C, so that the source electrode 8 and the drain electrode 9 form an ohmic contact with the AlGaN barrier layer;

[0075] 10. The AZ5214 photoresist inversion process is used on the surface of the p-GaN gate 7, and the photoresist pattern other than the gate metal electrode is prepared by exposure through the MA6 photolithography machine, and Ni / Au is grown by electron beam evaporation, wherein the thickness of Ni is 30nm and the thickness of Au is 120nm; after stripping, the gate metal electrode 10 is prepared, as shown in FIG. Figure 8 As shown; the gate metal electrode 10 forms a Schottky contact with the p-GaN gate 7, and the two-dimensional electron gas in the channel below is depleted through the p-GaN gate 7, thereby obtaining a selectively activated p-GaN gate HEMT device.

[0076] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a selectively activated p-GaN gate HEMT device, characterized in that: The method comprises: S1. Selecting an epitaxial wafer (11), wherein the epitaxial wafer (11) comprises a substrate layer (1), a buffer layer (2), a channel layer (3), and a barrier layer (4), wherein a two-dimensional electron gas is formed at a heterojunction interface between the channel layer (3) and the barrier layer (4) as a conductive channel; S2, depositing a p-GaN layer (5) with a thickness of 50nm-140nm on the epitaxial wafer (11), and a Mg doping concentration of 5×10 17 -5×10 20 cm -3 , Mg impurities are not activated; S3, depositing an n-GaN layer (6) on a portion of the p-GaN layer (5) obtained in step S2, wherein the n-GaN layer (6) serves as a barrier layer to inhibit activation of the p-GaN layer (5), the thickness of the n-GaN layer (6) is 5 nm to 200 nm, and the Si doping concentration is 1×10 16 -1×10 20 cm -3 ; S4, performing a thermal annealing treatment on the epitaxial wafer (11) obtained in step S3, activating Mg impurities in the p-GaN layer (5) not covered by the n-GaN layer (6) in a N2 atmosphere, and forming a p-GaN gate (7); S5. A gate metal electrode (10) is prepared on the p-GaN gate (7). The structure of the gate metal electrode (10) is Ni / Au or TiN or W from bottom to top, and forms a Schottky contact with the p-GaN gate (7). The conductive channel of the two-dimensional electron gas is regulated by the p-GaN gate (7) and the gate metal electrode (10).

2. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: Between step S4 and step S5 or after step S5, the following steps are also included: A source electrode (8) and a drain electrode (9) are prepared on the surface of the barrier layer (4) on both sides of the p-GaN gate (7) and the gate metal electrode (10), wherein the source electrode (8) and the drain electrode (9) respectively form an ohmic contact with the two-dimensional electron gas; The metal structures of the source electrode (8) and the drain electrode (9) are Ti, Al, Ni and Au respectively.

3. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: A layer of SiO2 with a thickness of 30nm-50nm is deposited on the surface of the epitaxial wafer (11), and the SiO2 and the remaining n-GaN layer (6) are removed by chemical mechanical polishing.

4. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: The length of the p-GaN gate (7) in the S4 is 10 nm-1 μm, and the gate metal electrode (10) and the p-GaN gate (7) form a "T"-shaped gate structure, which is used for high-frequency radio frequency devices.

5. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: Mesa etching or ion implantation is added between S2 and S3 or between S3 and S4 to achieve device isolation.

6. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: Each epitaxial layer of the epitaxial wafer (11) is grown by a metal organic chemical vapor deposition method, and the mesa etching is achieved by an inductively coupled plasma technology.

7. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: The temperature of the thermal annealing treatment in S4 is 700° C.-850° C., the holding time is 30 seconds-35 seconds, and the annealing atmosphere is nitrogen.

8. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: The Mg doping concentration of the p-GaN layer (5) is specifically 2.5×10 18 -1×10 20 cm 3 The Si doping concentration of the n-GaN layer (6) is specifically 3×10 17 -8×10 20 cm 3 .

9. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: The gate metal electrode (10) in S5 is deposited by electron beam evaporation technology, and the metal materials are Ni / Au in sequence, wherein the thickness of Ni is 30nm-50nm, and the thickness of Au is 100nm-150nm.

10. The method for manufacturing a selectively activated p-GaN gate HEMT device according to claim 1, characterized in that: The mask area of ​​the n-GaN layer (6) is precisely defined between S3 and S4 by photolithography.

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