GaN high electron mobility transistor and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a GaN high-electron-mobility transistor and a preparation method thereof. The transistor structure sequentially comprises a substrate 1, a composite buffer layer 2, a channel layer 3, an isolation layer 4, a barrier layer 5, a cap layer 6, a source electrode 7, a gate electrode 8, a nano deep groove array 9 and a drain electrode 10 from bottom to top, under the gate electrode 8, the cap layer 6, the barrier layer 5, the channel layer 3 and part of the III-N composite buffer layer 2 are removed in part of the region through etching to form a nano deep groove array structure 9, and the nano deep groove array structure 9 is filled with metal and is connected with the gate electrode 8. The nano deep groove array 9 filled with metal and connected with the gate electrode 8 can effectively extract holes accumulated in the composite buffer layer 2, so that hole accumulation in the composite buffer layer caused by high drain voltage during off-state work is inhibited, the long-term stability and reliability of the device are improved, and the preparation process is simple, easy to implement and outstanding in effect.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a GaN high electron mobility transistor and a method for preparing the same. Background Art

[0002] Gallium nitride (GaN), as a typical representative of the third generation of semiconductor materials, has attracted much attention in high-power and high-frequency device applications due to its excellent characteristics such as high breakdown electric field, wide bandgap and high electron mobility. In the GaN-based heterojunction structure, the two-dimensional electron gas (2DEG) generated at the interface has a high carrier concentration and high mobility, achieving low on-resistance, thereby effectively reducing the power loss of the device. With these advantages, GaN devices have become a research hotspot for high-power, high-frequency microwave technology and optoelectronic applications.

[0003] However, in GaN HEMT devices, due to the presence of a high concentration of electron gas in the channel, under gate bias, the high concentration of 2DEG will be concentrated near the channel, causing the electric field in the gate region near the drain to increase rapidly, forming a spike electric field. The spike electric field will stimulate the generation of electron-hole pairs in the channel layer and the buffer layer. High-energy electrons will quickly flow to the 2DEG channel. When a positive voltage is applied to the drain, electrons will flow to the drain to form a current, while a large number of holes are easily trapped in the buffer layer. The accumulation of holes induced by the high electric field may be captured by the trap state in the buffer layer, resulting in the accumulation of charge in the buffer layer. In high-frequency and high-power devices, the accumulation of holes may shield the electrons in the 2DEG channel, causing current attenuation and current collapse. The accumulation of holes may also affect the threshold voltage, thereby affecting the switching characteristics of the device. In short, the accumulation of holes in the buffer layer caused by the spike electric field will affect the electrical performance and reliability of the device.

[0004] At present, this problem can usually be effectively alleviated through structural optimization and material selection. In terms of structural optimization, a field plate structure is introduced near the gate to reduce the peak electric field; in terms of material selection, the buffer layer material is optimized and a high-resistance buffer layer material with low trap density is used. Although the field plate structure can reduce the peak electric field and increase the breakdown voltage of the device, the manufacturing process is complicated and will introduce additional parasitic capacitance, resulting in a decrease in the switching speed of the device and affecting the high-frequency characteristics. Although the optimization of the buffer layer material can ensure the reliability of the device and the stability of its performance, optimizing the trap state density of the buffer layer so that it can reduce current collapse while being in a high-resistance state is also a technical difficulty. Summary of the invention

[0005] In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the purpose of this application is to provide a GaN high electron mobility transistor and a method for preparing the same, which can be achieved by etching an array of nano-deep grooves under the gate, the etching depth reaches the buffer layer, the filling metal is connected to the gate metal, and the holes accumulated in the buffer layer are extracted by gate induction to enhance the reliability of the device. The method has a simple preparation process, low cost, easy implementation, and outstanding effect.

[0006] In order to achieve the above purpose, the technical solution adopted in this application is:

[0007] A GaN high electron mobility transistor comprises a substrate 1, a composite buffer layer 2, a channel layer 3, an isolation layer 4, a barrier layer 5, and a cap layer 6 which are sequentially arranged from bottom to top; a source electrode 7 and a drain electrode 10 are arranged at both ends of the surface of the cap layer 6, and a gate electrode 8 is arranged between the source electrode 7 and the drain electrode 10; below the gate electrode 8, the cap layer 6, the barrier layer 5, the channel layer 4 and a part of the III-nitride composite buffer layer 2 are etched and removed in a partial area to form a nano-deep groove array 9 structure, and the nano-deep groove array 9 is filled with metal and connected to the gate electrode 8; the nano-deep groove array 9 filled with metal and connected to the gate electrode 8 can effectively extract the holes accumulated in the composite buffer layer 2, thereby suppressing the hole accumulation in the composite buffer layer caused by the high drain voltage during off-state operation, and improving the long-term stability and reliability of the device.

[0008] In one embodiment of the present application, based on the above-mentioned solution, the material of the substrate 1 is one of silicon, silicon carbide, sapphire, diamond, gallium nitride, and aluminum nitride, and the thickness of the substrate 1 is 50 μm-1500 μm.

[0009] In one embodiment of the present application, based on the aforementioned scheme, the material of the composite buffer layer 2 is Group III nitride, and the thickness of the composite buffer layer 2 is 500nm-1500nm; the material of the channel layer 3 is gallium nitride, and the thickness of the channel layer 3 is 50nm-500nm; the material of the channel layer 4 is aluminum nitride, and the thickness of the channel layer 3 is 0nm-3nm; the material of the barrier layer 5 is aluminum gallium nitride or aluminum nitride, and the thickness of the barrier layer 5 is 5nm-30nm; the material of the cap layer 6 is gallium nitride or silicon nitride, and the thickness of the cap layer 6 is 0nm-5nm.

[0010] According to one aspect of the present application, a method for preparing a GaN high electron mobility transistor is provided, comprising the following steps:

[0011] S1: Photolithography of source electrode 7 and drain electrode 10 regions on the GaN heterogeneous crystal round material;

[0012] S2: Depositing metal in the source electrode 7 and the drain electrode 10 region, and forming an ohmic contact after annealing;

[0013] S3: photolithography a nano-array pattern in the gate region, and etching the nano-pattern using a dry etching process, the etching depth reaching the gallium nitride buffer layer, to form a nano-deep groove array;

[0014] S4: depositing metal to fill the nano-deep trench array;

[0015] S5: Photolithography is performed to form the gate region, gate metal is deposited, and device preparation is completed.

[0016] In one embodiment of the present application, based on the aforementioned scheme, in step S2, the annealing process is rapid thermal annealing or furnace tube annealing or box annealing in a nitrogen atmosphere, the annealing temperature is 350°C-900°C, and the annealing time is 10 seconds-6 minutes.

[0017] In one embodiment of the present application, in step S2, before depositing the source and drain electrode metals, acid washing is used to eliminate the negative impact of oxides on ohmic contacts.

[0018] In one embodiment of the present application, based on the above-mentioned scheme, in the step S3, an electron beam lithography process or an ultraviolet exposure lithography machine is used to photolithography each of the nano patterns, and the nano pattern is one of a circle, a triangle, a quadrilateral, and a hexagon; the dry etching process is: using RIE, ICP or ECR dry etching method, etching with a mixed gas including Cl2 or BCl3, or Cl2 or BCl3 plus O2 or Ar gas assisted etching to form a nano deep groove array pattern, and the etching depth reaches about the buffer layer, about 0-100nm below the channel layer.

[0019] In one embodiment of the present application, based on the aforementioned scheme, in step S4, the deposited metal is deposited by electron beam evaporation, magnetron sputtering or electroplating process, and the filling metal is a Ti / Al metal stack, or a Ta / Al metal stack, or a Hf / Al metal stack, or a Ti / Au metal stack, or a Ni / Au metal stack, or a Ti / Cu metal stack.

[0020] In one embodiment of the present application, based on the above-mentioned solution, in the step S5, metal deposition is performed by electron beam evaporation or magnetron sputtering process to obtain the gate electrode region.

[0021] Compared with the prior art, the beneficial effects of this application are:

[0022] 1. This application forms a nano-array pattern under the gate area, fills the metal to connect the gate metal, and extracts the holes accumulated in the buffer layer through gate induction. This reduces the phenomenon of hole accumulation in the buffer layer caused by the peak electric field near the gate, and effectively alleviates the device current collapse problem caused by the hole accumulation effect.

[0023] 2. The preparation method provided in the present application alleviates the accumulation phenomenon of charges formed in the buffer layer, further improves the voltage resistance of the device, further enhances the electrical performance and reliability of the device, and meets the needs of high-power and high-frequency applications.

[0024] 3. The preparation process of the present application is simple, compatible with existing processes, low in cost, and conducive to large-scale promotion. It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0026] Figure 1 is a structural diagram of a GaN heterojunction material according to an embodiment of the present application;

[0027] Figure 2 A side plan view of a GaN high electron mobility transistor according to an embodiment of the present application;

[0028] Figure 3 is an overall structural diagram of a GaN high electron mobility transistor according to an embodiment of the present application;

[0029] Figure 4 It is a schematic flow chart of a method for preparing a GaN high electron mobility transistor according to an embodiment of the present application.

[0030] Reference numerals:

[0031] Substrate 1, composite buffer layer 2, channel layer 3, isolation layer 4, barrier layer 5, cap layer 6, source electrode 7, gate electrode 8, nano-deep trench array 9, drain electrode 10. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0033] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0034] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or micro-control node devices.

[0035] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0036] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0037] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0038] Example

[0039] According to one aspect of the present application, an embodiment of the present application provides a GaN high electron mobility transistor, which can be referred to Figure 1 , Figure 2 and Figure 3 As shown, the detailed introduction of GaN high electron mobility transistor is as follows:

[0040] See also Figure 1 , 2 , Figure 1 is a schematic structural diagram of a GaN heterojunction epitaxial material provided in an embodiment of the present application, Figure 2 Schematic diagram of a GaN high electron mobility transistor structure provided in an embodiment of the present application. The GaN heterojunction epitaxial material provided in this embodiment includes a substrate layer 1, a composite buffer layer 2, a channel layer 3, an isolation layer 4, a barrier layer 5, and a cap layer 6 from bottom to top, wherein the composite buffer layer is composed of aluminum nitride, aluminum gallium nitride with varying aluminum components, and gallium nitride. The channel layer 3 and the barrier layer 5 form a heterojunction structure, and a two-dimensional electron gas with high concentration and high mobility is formed at the interface. The positions of the source electrode 7 and the drain electrode 10 are shown in FIG. Figure 2 As shown, the gate electrode 8 is located on the cap layer and the nanostructure 10 . Figure 3 is a side plan view of the GaN high electron mobility transistor structure prepared in the embodiment of the present application, Figure 4 This is the overall process flow chart of the GaN high electron mobility transistor prepared in this application.

[0041] In one embodiment of the present application, the substrate layer 1 may be made of silicon, silicon carbide, sapphire, diamond, gallium nitride, or aluminum nitride, with a thickness of 50-1500 μm. In this example, a silicon substrate with a thickness of 800 μm is selected.

[0042] In one embodiment of the present application, the composite buffer layer 2, in this embodiment, the materials selected in the composite buffer layer are aluminum nitride, aluminum gallium nitride with varying aluminum components, and gallium nitride, and the total thickness of the composite buffer layer is 1.5 μm.

[0043] In one embodiment of the present application, the channel layer 3, the isolation layer 4 and the barrier layer 5 are III-N materials, the channel layer 3 and the isolation layer 4 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed at the heterojunction interface formed by the channel layer 3 and the isolation layer 4 and on the side close to the isolation layer 4, serving as a conductive channel of the GaN high electron mobility transistor.

[0044] In the embodiment of the present application, the material of the channel layer 3 is gallium nitride, indium gallium nitride or aluminum nitride, which can be selected according to specific performance and cost requirements. In this embodiment, the material of the channel layer 3 is gallium nitride with a thickness of 150nm.

[0045] The isolation layer 4 of the present application is located between the channel layer 3 and the barrier layer 5, and is made of aluminum nitride with a thickness of 1 nm. The insertion of the isolation layer 4 can improve the electron density and mobility of the two-dimensional electron gas, which is beneficial to improving the output characteristics of the device.

[0046] The barrier layer 5 of the present application has a thickness of 5-30nm, is located on the channel layer 3, and is generally made of aluminum gallium nitride, indium gallium nitride, or aluminum nitride. The material type can be selected according to cost and performance requirements. In this embodiment, the barrier layer 5 has a thickness of 23nm, and is made of aluminum gallium nitride with an Al component of 25%.

[0047] The cap layer 6 of the present application is located on the barrier layer 5 , and the material is generally gallium nitride or silicon nitride, with a thickness of 0-5 nm. In this embodiment, the cap layer is 3 nm of gallium nitride.

[0048] The embodiment of the present application utilizes a dry etching process to form a nano-arrayed nano-patterned groove under the gate electrode for filling metal to connect the gate electrode 8, and arranges the gate electrode 8 on the nano-deep groove array 9, and arranges the source electrode 7 and the drain electrode 10 on the cap layer 6 structure.

[0049] According to one aspect of an embodiment of the present application, a method for preparing a GaN high electron mobility transistor is also provided, comprising the following steps:

[0050] S1: Photolithography of source electrode 7 and drain electrode 10 regions on the GaN heterogeneous crystal round material;

[0051] S2: Depositing metal in the source electrode 7 and the drain electrode 10 region, and forming an ohmic contact after annealing;

[0052] S3: photolithography a nano-array pattern in the gate region, and etching the nano-pattern using a dry etching process, the etching depth reaching the gallium nitride buffer layer, to form a nano-deep groove array;

[0053] S4: depositing metal to fill the nano-deep trench array;

[0054] S5: Photolithography is performed to form the gate region, gate metal is deposited, and device preparation is completed.

[0055] The following, combined Figure 3 , Figure 4 , several embodiments of preparing the above device are given:

[0056] Embodiment 1:

[0057] A method for preparing a GaN high electron mobility transistor in this embodiment includes the following steps:

[0058] Step 1, cleaning the GaN heterojunction epitaxial material;

[0059] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen.

[0060] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate the device. In this embodiment, ICP dry etching process is used to achieve device isolation.

[0061] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0062] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0063] Step 4: deposit source and drain ohmic contact metal, and form source and drain electrodes by wet stripping process.

[0064] Specifically, before depositing the ohmic metal, the sample is immersed in a BOE solution for 30 seconds to remove the influence of oxides on the ohmic contact; Ti / Al / Ni / Au ohmic metal is deposited by electron beam evaporation or magnetron sputtering process, and the thickness of the bottom metal Ti is 20nm, the thickness of the metal Al is 120nm, the thickness of the metal Ni is 40nm, and the thickness of the metal Au is 50nm.

[0065] Step 5: Photolithography of nano-array patterns in the gate region.

[0066] Specifically, an electron beam lithography process or an ultraviolet exposure lithography device is used to form a circular pattern with a diameter of 500 nm in the gate region, and the distance between the nanocircles is 300 nm.

[0067] Step 6, using ICP dry etching process, using Cl2 / BCl3 mixed gas, using photoresist as a mask, etching nano-circular patterns, the etching depth reaches the gallium nitride heterojunction buffer layer, about 0-50nm below the channel layer, forming a circular nano-deep groove array.

[0068] Step 7: deposit metal to fill the nano-deep groove array.

[0069] Specifically, the sample was immersed in BOE solution for 30 seconds before metal deposition to remove the influence of etching derivatives produced by dry etching on the structure-induced extraction of holes. The metal was filled by magnetron sputtering process. In this embodiment, the filled metal was Ti / Au, the Ti metal thickness was 20nm, and the Au metal thickness was 50nm. The metal did not fill the circular nano-deep groove array in order to avoid the influence of the device reliability degradation caused by the cracking of the semiconductor material due to the thermal expansion coefficient after the metal was filled.

[0070] Step 8: Photolithography defines the gate area and deposits gate metal.

[0071] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering, and the gate metal is connected to the circular nano pattern. When the device is working, the holes accumulated in the buffer layer due to the peak electric field near the gate are induced and extracted through the structure. In this embodiment, the gate metal Ni / Au is deposited by electron beam evaporation, and the thickness of the metal Ni is 40nm and the thickness of the metal Au is 300nm.

[0072] Embodiment 2:

[0073] A method for preparing a GaN high electron mobility transistor in this embodiment includes the following steps:

[0074] Step 1, cleaning the GaN heterojunction epitaxial material;

[0075] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen.

[0076] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate the device. In this embodiment, Ar ion implantation is used to achieve device isolation.

[0077] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0078] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0079] Step 4: deposit source and drain ohmic contact metal, and form source and drain electrodes by wet stripping process.

[0080] Specifically, before depositing the ohmic metal, the sample is immersed in a dilute HCl solution for 2 minutes to remove the influence of oxides on the ohmic contact; Ti / Al / Ni / Au ohmic metal is deposited by electron beam evaporation or magnetron sputtering process, and the thickness of the bottom metal Ti is 20nm, the thickness of the metal Al is 120nm, the thickness of the metal Ni is 40nm, and the thickness of the metal Au is 50nm.

[0081] Step 5: Photolithography of nano-array patterns in the gate region.

[0082] Specifically, an electron beam lithography process or an ultraviolet exposure lithography device is used to form a square pattern with a side length of 400 nm in the gate region, and the distance between the nano-square patterns is 250 nm.

[0083] Step 6, using ECR dry etching process, using Cl2 / BCl3 mixed gas, using photoresist as a mask, etching the nano square pattern, the etching depth reaches the gallium nitride heterojunction buffer layer, about 0-50nm below the channel layer, forming a square nano deep groove array.

[0084] Step 7: deposit metal to fill the nano-deep groove array.

[0085] Specifically, the sample was immersed in BOE solution for 30 seconds before depositing the metal to remove the etching derivatives produced by dry etching and the influence of the structure on the extraction of holes. The metal was filled by magnetron sputtering process. In this embodiment, the filling metal was Ti / TiN, the Ti metal thickness was 20nm, and the TiN metal thickness was 50nm. The metal did not fill the square nano-deep groove array in order to avoid the influence of the device reliability degradation caused by the cracking of the semiconductor material due to the thermal expansion coefficient after the metal was filled.

[0086] Step 8: Photolithography defines the gate area and deposits gate metal.

[0087] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering, and the gate metal is connected to the circular nano pattern. When the device is working, the holes accumulated in the buffer layer due to the peak electric field near the gate are induced and extracted through the structure. In this embodiment, the gate metal Ni / Au is deposited by electron beam evaporation, and the thickness of the metal Ni is 40nm and the thickness of the metal Au is 300nm.

[0088] Embodiment three:

[0089] A method for preparing a GaN high electron mobility transistor in this embodiment includes the following steps:

[0090] Step 1, cleaning the GaN heterojunction epitaxial material;

[0091] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen.

[0092] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate the device. In this embodiment, Ar ion implantation is used to achieve device isolation.

[0093] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0094] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0095] Step 4: deposit source and drain ohmic contact metal, and form source and drain electrodes by wet stripping process.

[0096] Specifically, before depositing the ohmic metal, the sample is immersed in a BOE solution for 30 seconds to remove the influence of oxides on the ohmic contact; Ti / Al / Ni / Au ohmic metal is deposited by electron beam evaporation or magnetron sputtering process, and the thickness of the bottom metal Ti is 20nm, the thickness of the metal Al is 120nm, the thickness of the metal Ni is 40nm, and the thickness of the metal Au is 50nm.

[0097] Step 5: Photolithography of nano-array patterns in the gate region.

[0098] Specifically, an electron beam lithography process or an ultraviolet exposure lithography device is used to form a regular hexagonal pattern with a diameter of 200 nm in the gate region, and the distance between the nano regular hexagons is 200 nm.

[0099] Step 6, using ICP dry etching process, using Cl2 / BCl3 mixed gas, using photoresist as a mask, etching nano regular hexagonal pattern, the etching depth reaches the gallium nitride heterojunction buffer layer, about 0-50nm below the channel layer, forming a regular hexagonal nano deep groove array.

[0100] Step 7: deposit metal to fill the nano-deep groove array.

[0101] Specifically, the sample was soaked in BOE solution for 30 seconds before metal deposition to remove the influence of etching derivatives produced by dry etching on the structure-induced extraction of holes. The metal was filled by magnetron sputtering process. In this embodiment, the filled metal was Ti / Au, the Ti metal thickness was 20nm, and the Au metal thickness was 50nm. The metal did not fill the regular hexagonal nano-deep groove array in order to avoid the influence of the device reliability degradation caused by the cracking of the semiconductor material due to the thermal expansion coefficient after the metal was filled.

[0102] Step 8: Photolithography defines the gate area and deposits gate metal.

[0103] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering, and the gate metal is connected to the regular hexagonal nano-pattern. When the device is working, the holes accumulated in the buffer layer due to the peak electric field near the gate are extracted by induction through the structure. In this embodiment, the gate metal Ta / Al is deposited by electron beam evaporation, and the thickness of the metal Ta is 50nm and the thickness of the metal Al is 300nm.

[0104] Embodiment 4:

[0105] A method for preparing a GaN high electron mobility transistor in this embodiment includes the following steps:

[0106] Step 1, cleaning the GaN heterojunction epitaxial material;

[0107] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen.

[0108] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate the device. In this embodiment, ICP dry etching process is used to achieve device isolation.

[0109] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0110] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure nitrogen. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0111] Step 4: deposit source and drain ohmic contact metal, and form source and drain electrodes by wet stripping process.

[0112] Specifically, before depositing the ohmic metal, the sample is immersed in a BOE solution for 30 seconds to remove the influence of oxides on the ohmic contact; Ti / Al / Ni / Au ohmic metal is deposited by electron beam evaporation or magnetron sputtering process, and the thickness of the bottom metal Ti is 20nm, the thickness of the metal Al is 120nm, the thickness of the metal Ni is 40nm, and the thickness of the metal Au is 50nm.

[0113] Step 5: Photolithography of nano-array patterns in the gate region.

[0114] Specifically, an electron beam lithography process or an ultraviolet exposure lithography device is used to form a regular triangle pattern with a diameter of 300 nm in the gate region, and the distance between the nano regular triangles is 200 nm.

[0115] Step 6, using ICP dry etching process, using Cl2 / BCl3 mixed gas, using photoresist as a mask, etching nano regular triangle pattern, the etching depth reaches the gallium nitride heterojunction buffer layer, about 0-50nm below the channel layer, forming a regular triangle nano deep groove array.

[0116] Step 7: deposit metal to fill the nano-deep groove array.

[0117] Specifically, the sample was immersed in BOE solution for 30 seconds before depositing the metal to remove the etching derivatives produced by dry etching and the influence of the structure on the extraction of holes. The metal was filled by magnetron sputtering process. In this embodiment, the filling metal was Ti / Au, the Ti metal thickness was 20nm, and the Au metal thickness was 50nm. The metal did not fill the regular triangular nano-deep groove array in order to avoid the influence of the device reliability degradation caused by the cracking of the semiconductor material due to the thermal expansion coefficient after the metal was filled.

[0118] Step 8: Photolithography defines the gate area and deposits gate metal.

[0119] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering, and the gate metal is connected to the regular triangle nano pattern. When the device is working, the holes accumulated in the buffer layer due to the peak electric field near the gate are extracted by induction through the structure. In this embodiment, the gate metal Ti / Al is deposited by electron beam evaporation, and the thickness of the metal Ti is 40nm and the thickness of the metal Al is 300nm.

[0120] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0121] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be performed without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A GaN high electron mobility transistor, characterized in that: The invention comprises a substrate 1, a composite buffer layer 2, a channel layer 3, an isolation layer 4, a barrier layer 5, and a cap layer 6 which are arranged in sequence from bottom to top, wherein a source electrode 7 and a drain electrode 10 are arranged at both ends of the surface of the cap layer 6, and a gate electrode 8 is arranged between the source electrode 7 and the drain electrode 10; below the gate electrode 8, the cap layer 6, the barrier layer 5, the channel layer 4 and a part of the III-nitride composite buffer layer 2 are etched away in a partial area to form a nano-deep groove array 9 structure, and the nano-deep groove array 9 is filled with metal and connected to the gate electrode 8; the nano-deep groove array 9 filled with metal and connected to the gate electrode 8 can effectively extract the holes accumulated in the composite buffer layer 2, thereby suppressing the hole accumulation in the composite buffer layer caused by the high drain voltage during off-state operation, and improving the long-term stability and reliability of the device.

2. A GaN high electron mobility transistor according to claim 1, characterized in that: The channel layer 3, the isolation layer 4 and the barrier layer 5 are group III nitrides, and the channel layer 3 and the isolation layer 4 form a heterojunction. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface formed by the channel layer 3 and the isolation layer 4 and on the side close to the isolation layer 4, serving as a conductive channel of the GaN high electron mobility transistor.

3. A GaN high electron mobility transistor according to claim 1, characterized in that: The material of the substrate 1 is one of silicon, silicon carbide, sapphire, diamond, gallium nitride, and aluminum nitride, and the thickness of the substrate 1 is 50 μm-1500 μm.

4. A GaN high electron mobility transistor according to claim 1, characterized in that: The material of the composite buffer layer 2 is group III nitride, with a thickness of 500nm-1500nm; the material of the channel layer 3 is gallium nitride, with a thickness of 50nm-500nm; the material of the channel layer 4 is aluminum nitride in group III nitride, with a thickness of 0nm-3nm; the material of the barrier layer 5 is aluminum gallium nitrogen or aluminum nitride in group III nitride, with a thickness of 5nm-30nm; the material of the cap layer 6 is gallium nitride or silicon nitride, with a thickness of 0nm-5nm.

5. A method for preparing a GaN high electron mobility transistor, characterized in that: The following steps are involved: S1: Photolithography of source electrode 7 and drain electrode 10 regions on the GaN heterogeneous crystal round material; S2: Depositing metal in the source electrode 7 and the drain electrode 10 region, and forming an ohmic contact after annealing; S3: photolithography a nano-array pattern in the gate region, and etching the nano-pattern using a dry etching process, the etching depth reaching the gallium nitride buffer layer, to form a nano-deep groove array; S4: depositing metal to fill the nano-deep trench array; S5: Photolithography is performed to form the gate region, gate metal is deposited, and device preparation is completed.

6. The method for preparing a GaN high electron mobility transistor according to claim 5, characterized in that: In the step S2, the annealing process is rapid thermal annealing, furnace annealing or box annealing in a nitrogen atmosphere, the annealing temperature is 350°C-900°C, and the annealing time is 10 seconds-6 minutes.

7. The method for preparing a GaN high electron mobility transistor according to claim 5, characterized in that: In the step S4, each of the nano patterns is photolithographically processed by an electron beam lithography process or an ultraviolet exposure lithography machine, and the nano pattern is one of a circle, a triangle, a quadrilateral, and a hexagon; the dry etching process is: using RIE, ICP or ECR dry etching method, etching with a mixed gas including Cl2 or BCl3, or Cl2 or BCl3 plus O2 or Ar gas assisted etching, to form a nano deep groove array pattern, and the etching depth is about the buffer layer, about 1-100nm below the channel layer.

8. The method for preparing a GaN high electron mobility transistor according to claim 5, characterized in that: In step S4, the deposited metal adopts electron beam evaporation, magnetron sputtering or electroplating process, and the filling metal is a Ti / Al metal stack, or a Ta / Al metal stack, or a Hf / Al metal stack, or a Ti / Au metal stack, or a Ni / Au metal stack, or a Ti / Cu metal stack.

9. The method for preparing a GaN high electron mobility transistor according to claim 8, characterized in that: In the step S5, gate metal is deposited by electron beam evaporation or magnetron sputtering.

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