Diamond gate-all-around field-effect transistor and preparation method thereof

Abstract

The present invention discloses a diamond ring-gate field-effect transistor and a preparation method thereof, which relate to the technical field of semiconductor devices, comprising a diamond substrate layer; a ring-gate structure suspended above the diamond substrate layer, the ring-gate structure comprising a nanowire, a gate electrode and the ring-gate electrode coated thereon; the nanowire comprising, from the inside to the outside, a diamond core, a diamond terminal surface, a dielectric layer and a ring-gate electrode, vertically passing through the gate electrode and being fully wrapped therein; a source electrode and a drain electrode, the source electrode and the drain electrode being respectively located on either side of the gate electrode, forming ohmic contact with the diamond terminal surface; a two-dimensional hole gas formed at the interface between the diamond terminal surface and the dielectric layer; the diamond ring-gate field-effect transistor and the preparation method thereof can effectively alleviate the electrostatic problem caused by reducing the feature size, while ensuring the high performance of the transistor, laying a solid foundation for the development of future miniaturized devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a diamond gate-all-around field effect transistor and a preparation method thereof. Background Art

[0002] As an ultra-wide bandgap semiconductor material, diamond, with its unique physical and chemical properties, shows great potential in high-temperature, high-frequency, and high-power electronic devices. Its indirect bandgap of 5.47 eV at room temperature offers significant advantages in electronic device design, particularly in applications requiring high voltages and high power densities. Diamond's high breakdown electric field, high power handling capacity, and extremely high thermal conductivity provide improved heat dissipation in electronic devices, thereby enhancing device stability and reliability. Diamond's high thermal conductivity, approximately five times that of copper, is one of its most compelling properties, making it an excellent choice for applications with demanding heat dissipation requirements. For example, in high-power electronic devices, diamond can rapidly dissipate heat, effectively preventing device failure due to overheating. Furthermore, diamond's high hardness and chemical stability ensure its stable performance in harsh environments, making it particularly valuable in industrial and military applications.

[0003] However, existing diamond field-effect transistors (DFETs) face numerous challenges in practical applications. First, the high activation energy of doped DFETs results in low carrier concentration, limiting their performance in microwave power devices. Second, hydrogen-terminated DFETs, which form carbon-hydrogen chemical bonds on the diamond surface through hydrogen plasma treatment, have advanced the development of diamond devices. However, the process must avoid photoresist contamination, excessive plasma energy, or deposition of dielectrics in oxygen-containing atmospheres, severely limiting the choice of gate dielectric materials and further optimization of device performance. Furthermore, as transistor sizes continue to shrink, conventional DFETs face numerous challenges caused by short channel effects (SCEs). These issues include increased leakage current, performance degradation, and weakened gate control capabilities, limiting device performance improvements. Furthermore, further scaling also raises the issue of electrostatic discharge, which places higher technical demands on the overall performance of the transistor. Therefore, the shortcomings of DFETs in doping activation energy, process adaptability, and scalability have been addressed. Summary of the Invention

[0004] The object of the present invention is to provide a diamond gate-all-around field effect transistor and a method for preparing the same, so as to solve the problems of the prior art diamond field effect transistor in terms of doping activation energy, process adaptability and size scaling.

[0005] To achieve the above-mentioned object, the present invention provides the following technical solution: a diamond gate-all-around field-effect transistor, comprising:

[0006] a diamond substrate layer;

[0007] A gate-ring structure suspended above the diamond substrate layer, the gate-ring structure comprising a nanowire, a gate electrode and a gate-ring electrode covering the nanowire;

[0008] The nanowire includes a diamond core, a diamond terminal surface, a dielectric layer, and a ring gate electrode from the inside out, vertically passing through the gate electrode and being fully wrapped by it;

[0009] a source electrode and a drain electrode, the source electrode and the drain electrode being respectively located on both sides of the gate electrode and forming an ohmic contact with the surface of the diamond terminal;

[0010] A two-dimensional void is formed at the interface between the diamond terminal surface and the dielectric layer.

[0011] Preferably, the thickness of the gate electrode is 50 nm-500 nm.

[0012] Preferably, the diamond terminal surface is hydrogen-terminated or silicon-terminated.

[0013] Preferably, the thickness of the dielectric layer is 3 nm-50 nm.

[0014] Preferably, the thickness of the ring gate electrode is 10nm-100nm.

[0015] Preferably, the thickness of the source electrode is 50nm-500nm.

[0016] Preferably, the cross-sectional shape of the nanowire is polygonal, circular, elliptical or irregularly circular.

[0017] A method for preparing a diamond gate-all-around field-effect transistor, using the diamond gate-all-around field-effect transistor, the method comprising:

[0018] S1, select a diamond substrate layer;

[0019] S2. Forming diamond cores in the shape of nanowires on the surface of the diamond substrate layer by photolithography, specifically comprising: coating the surface of the diamond substrate layer with a photoresist and forming a mask; etching the surface of the diamond substrate layer using a dry etching process to form diamond cores of the nanowires; and removing the mask to retain the nanowire structure.

[0020] S3, pre-treating the surface of the diamond core and performing hydrogen termination or silicon termination treatment to form a two-dimensional hole gas (2DHG) termination surface on the surface of the diamond core;

[0021] S4, depositing a dielectric material on the terminal surface of the nanowire in all directions to form a dielectric layer, wherein the thickness of the dielectric layer ranges from 3 nm to 50 nm;

[0022] S5, depositing metal material in all directions around the periphery of the dielectric layer to form a ring gate electrode;

[0023] S6. forming a gate electrode on the diamond substrate layer by photolithography, so that the nanowire vertically passes through the gate electrode and is fully wrapped by it;

[0024] S7. Remove part of the dielectric layer and deposit the source electrode and drain electrode on both sides of the gate electrode through photolithography to form ohmic contact with the terminal surface of the nanowire.

[0025] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0026] This diamond gate-all-around field-effect transistor and its fabrication method achieve a high-carrier-concentration conductive path by forming a two-dimensional hole gas (2DHG) on the surface of diamond nanowires, overcoming the low carrier concentration problem of conventional doped diamond field-effect transistors due to high activation energy. This structure improves the device's performance in high-frequency, high-power applications. The gate-all-around structure fully encapsulates the nanowires, effectively mitigating the short channel effect (SCE) caused by the reduced size of conventional field-effect transistors. It also enhances the gate's ability to control carriers, thereby improving the transistor's on / off ratio and reliability. The source and drain electrodes form ohmic contacts with the diamond terminal surface, ensuring a low-impedance current path, optimizing electron transfer efficiency, and significantly enhancing the device's operating performance and stability. Diamond material itself has extremely high thermal conductivity. The rationally designed gate-all-around structure and nanowire cross-sectional shape further optimize the heat dissipation path, thereby improving the device's heat dissipation efficiency and reliability under high power density conditions. Standard photolithography and dry etching processes are used to precisely control the nanowire shape and size while achieving high process repeatability. In addition, through the process design of omnidirectional deposition of dielectric layers and ring-gate electrodes, the process limitations of photoresist contamination and high-energy plasma are avoided, thereby expanding the selection range of gate dielectric materials and improving device performance. In the scenario of further miniaturization, the ring-gate structure of the present invention can effectively alleviate the electrostatic problems caused by reducing the feature size, while ensuring the high performance of the transistor, laying a solid foundation for the development of future miniaturized devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0028] Figure 2 It is a top view of the overall structure of the present invention;

[0029] Figure 3 Flow chart of the method of the present invention.

[0030] In the figure: 1. Diamond substrate layer; 2. Ring gate structure; 21. Source electrode; 22. Drain electrode; 23. Gate electrode; 3. Nanowire; 31. Diamond terminal surface; 32. Dielectric layer; 33. Ring gate electrode; 34. Diamond core. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] like Figure 1 and Figure 2 As shown, the present invention provides a technical solution: a diamond ring-gate field-effect transistor, comprising a diamond substrate layer 1; a ring-gate structure 2 suspended above the diamond substrate layer 1, the ring-gate structure 2 comprising a nanowire 3, a gate electrode 23 and a ring-gate electrode 33 coated thereon; the nanowire 3 comprises, from the inside to the outside, a diamond core 34, a diamond terminal surface 31, a dielectric layer 32 and a ring-gate electrode 33, vertically passing through the gate electrode 23 and being fully wrapped therein; a source electrode 21 and a drain electrode 22, the source electrode 21 and the drain electrode 22 being respectively located on both sides of the gate electrode 23, forming ohmic contact with the diamond terminal surface 31; a two-dimensional hole gas is formed at the interface between the diamond terminal surface 31 and the dielectric layer 32.

[0033] The diamond substrate layer 1 provides high thermal conductivity and excellent insulation properties for the rectifier transistor, ensuring the device's high-frequency operational stability. The ring-gate structure 2, suspended above the diamond substrate layer 1, achieves precise electric field control of the transistor channel through its unique nanowire structure and ring-gate design. The diamond core within the nanowire 3 provides high conductivity and structural support. Its surface, the diamond terminal surface 31, interacts with the dielectric layer 32 to form a two-dimensional hole gas, forming the transistor channel. The gate electrode 23 wraps around the periphery of the nanowire 3 and, by regulating the gate voltage, influences the density of the two-dimensional hole gas, thereby switching the channel on and off. The source electrode 21 and drain electrode 22 each form ohmic contacts with the diamond terminal surface 31, ensuring efficient electron transport in the channel. The formation of two-dimensional hole gas significantly improves the carrier mobility of the channel, enabling efficient electron transport. The diamond substrate layer 1 provides high thermal conductivity, significantly reducing heat accumulation during high-frequency operation and ensuring device stability. The ring gate structure 2 fully encloses the gate electrode 23, improving the uniformity and control precision of the channel electric field and reducing the possibility of electric field runaway. The vertical structure design of the nanowire 3 reduces the lateral size of the device, laying the foundation for high integration and miniaturization.

[0034] In one possible embodiment, the material of the gate electrode 23 is one or more of aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), tungsten (W), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or cobalt (Co), with a thickness of 50-500 nm. The gate electrode 23 uses the above-mentioned high-performance conductive materials, and its excellent conductivity and thermal stability ensure effective regulation of the electric field. By selecting a single metal such as aluminum, titanium, nickel or a combination thereof, the physical and chemical properties of the gate electrode 23 can be optimized to adapt to different working environments or requirements. The thickness of the gate electrode ranges from 50-500 nm, which can be optimized based on both resistance and manufacturing process: a smaller thickness reduces the amount of metal used and reduces the lateral size of the transistor. A larger thickness enhances the mechanical strength and durability of the electrode, avoiding damage caused by thermal effects or mechanical stress. The high conductivity of the selected material significantly reduces the resistance of the gate electrode, improving the response speed and control accuracy of the transistor. A variety of materials are available, allowing the design of the gate electrode to be optimized for specific application scenarios (such as high temperature, high frequency or harsh chemical environment). The excellent processability and moderate thickness range of these materials facilitate the fabrication of gate electrodes using conventional processes such as evaporation and sputtering. Materials such as tungsten (W) and titanium nitride (TiN) offer excellent thermal stability, making them suitable for use in high-power, high-temperature environments. Materials such as tantalum (Ta) and tantalum nitride (TaN) exhibit excellent durability when optimized in thickness, preventing electrode layer failure due to mechanical fatigue.

[0035] In one possible embodiment, the diamond terminal surface 31 is a hydrogen terminal or a silicon terminal. The treatment of the diamond terminal surface 31 is an important step in ensuring the formation of two-dimensional hole gas. When hydrogen termination is used, hydrogen atoms combine with carbon atoms on the diamond surface to form stable C-H bonds, which significantly reduces the surface state density. At the same time, the surface electronegativity difference triggers band bending, promoting the generation of two-dimensional hole gas. When silicon termination is used, silicon atoms form C-Si bonds with the diamond surface, which not only stabilizes the surface structure, but also optimizes the density and distribution of channel carriers by adjusting the interface charge distribution. The choice of hydrogen termination and silicon termination can flexibly adjust device performance according to specific application requirements, such as improving carrier mobility or enhancing environmental adaptability. Diamond termination surfaces using hydrogen termination or silicon termination have the following advantages: hydrogen termination significantly reduces the surface scattering effect, ensuring that the two-dimensional hole gas has a higher mobility, thereby improving the conduction performance of the transistor. Compared with hydrogen termination, silicon termination is more stable to high temperature and chemical environment, and is suitable for working in harsh environments. By selecting different termination methods, channel conductivity characteristics (such as carrier concentration and mobility) can be optimized to meet the requirements of high-frequency, high-power, or high-stability applications. Both hydrogen and silicon terminations can be achieved through mature processes such as plasma treatment or chemical modification, resulting in simple preparation and amenability to large-scale production.

[0036] In one possible embodiment, the material of the dielectric layer 32 is one or more combinations of aluminum oxide (Al2O3), molybdenum trioxide (MoO3), tungsten trioxide (WO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), rhenium dioxide (ReO2) or silicon nitride (SiNx), with a thickness of 3nm-50nm. The function of the dielectric layer 32 is to isolate the ring gate electrode 33 from the diamond terminal surface 31 in the nanowire 3, while optimizing the interface properties to support the formation and stability of two-dimensional hole gas. The above materials all have high dielectric constants (High-k), which can effectively enhance the gate control capability, reduce parasitic capacitance, and improve transistor performance. Aluminum oxide (Al2O3) and silicon nitride (SiNx) have excellent insulation properties and chemical stability, and are suitable for high-frequency and high-power scenarios. Molybdenum trioxide (MoO3) and tungsten trioxide (WO3) help to increase the charge density of the channel due to their high dielectric constants and electron affinity. Hafnium oxide (HfO2) and zirconium oxide (ZrO2) provide excellent dielectric properties and thermal stability, and are particularly suitable for applications in harsh environments. The thickness of the dielectric layer is controlled between 3-50nm, ensuring effective electric field coupling between the channel and the gate while meeting the insulation requirements. By adopting high dielectric constant materials, the control efficiency of the gate electrode on the two-dimensional hole gas in the channel is significantly improved, reducing leakage current. High dielectric materials and optimized thickness design effectively reduce parasitic capacitance, thereby reducing the power consumption of transistors, which is suitable for the development of high-efficiency electronic devices. The thermal stability and chemical corrosion resistance of materials such as hafnium oxide and zirconium oxide ensure long-term and reliable operation of transistors in high temperatures or harsh environments. The selectivity of multiple materials and their combinations enables the dielectric layer to adapt to the needs of different scenarios, such as high-frequency signal processing, high-power switching or miniaturized circuits. The above materials all support conventional deposition processes (such as ALD, CVD), are highly compatible with existing semiconductor manufacturing technologies, and are convenient for large-scale mass production.

[0037] In one possible embodiment, the material of the ring gate electrode 33 is one or more of titanium nitride (TiN), platinum (Pt), aluminum (Al), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN) or cobalt (Co), with a thickness of 10nm-100nm. As the core of the transistor control part, the material and thickness of the ring gate electrode 33 directly affect the electric field regulation capability, gate leakage current characteristics and device stability. The materials are all metals or metal compounds with high conductivity, corrosion resistance or high temperature stability, ensuring reliable performance under extreme conditions. Titanium nitride (TiN) and tantalum nitride (TaN) are suitable for high power and high temperature environments due to their excellent thermal stability and chemical inertness; platinum (Pt) and gold (Au) provide high conductivity and low contact resistance, suitable for high frequency circuits; aluminum (Al), nickel (Ni), tungsten (W) and tantalum (Ta) have good processing performance and stability, and are suitable for a wide range of application scenarios. The thickness of the ring gate electrode ranges from 10nm to 100nm, ensuring that while meeting the requirements of conductivity and mechanical strength, the device is not too large or performance degradation caused by uneven thickness is avoided. The ring gate electrode fully covers the gate structure, and precise electric field control is achieved through highly conductive materials to improve the switching performance of the transistor. The selected materials have good corrosion resistance and thermal stability, adapt to high temperature, high humidity or other harsh conditions, and extend the life of the device. The use of highly conductive materials such as gold (Au) or platinum (Pt) significantly reduces the resistance of the ring gate electrode and improves the response speed of the transistor. The above materials support common deposition processes such as sputtering and evaporation, and the thickness is easy to control, which is convenient for large-scale production. The optional combination of different materials allows the ring gate electrode to be optimized according to the specific application scenario, adapting to a variety of device requirements from high frequency to high power.

[0038] In one possible embodiment, the material of the source electrode 21 and the drain electrode 22 is one or more of gold (Au), titanium (Ti), platinum (Pt), nickel (Ni) or tungsten (W), with a thickness of 50nm-500nm. The source electrode 21 and the drain electrode 22 directly form an ohmic contact with the diamond terminal surface 31, providing a key channel for carrier injection and extraction of the device. By selecting a metal material with high conductivity and good contact properties with the diamond material (such as Au, Pt, Ti, Ni or W), the contact resistance can be effectively reduced and the carrier migration efficiency can be enhanced. In addition, the thickness of the source and drain electrodes ranges from 50 to 500nm to ensure a balance between performance optimization and mechanical stability: a smaller thickness (50-100nm) is suitable for miniaturized applications and reduces parasitic effects; a larger thickness (300-500nm) is suitable for high-power scenarios and improves heat dissipation and resistance to mechanical stress. The excellent properties of the metal materials are as follows: gold (Au) and platinum (Pt) provide excellent conductivity and chemical stability, and are suitable for high-frequency devices and high-humidity environments; titanium (Ti) and nickel (Ni) have good contact performance and mechanical strength, and are suitable for high-power and high-stress applications; tungsten (W) has a high melting point and high heat resistance, and is suitable for high-temperature environments.

[0039] The good interface properties between the selected metal material and the diamond surface significantly reduce the contact resistance, improve the carrier injection efficiency, and enhance the device performance. Appropriate electrode thickness design (such as 300nm-500nm) significantly improves the thermal conductivity and reduces the heat accumulation caused by high-power operation. The use of high-strength metals (such as W, Ti) combined with appropriate thickness can effectively improve the mechanical fatigue resistance of the electrode and extend the life of the device. Gold (Au) and platinum (Pt) significantly improve the high-frequency response capability of the device due to their low resistance and high conductivity, making them suitable for high-speed circuit applications. The above materials all support existing metal deposition processes (such as evaporation, sputtering, etc.), and the manufacturing process is mature and the cost is controllable.

[0040] In one possible embodiment, the cross-sectional shape of the nanowire 3 is polygonal, circular, elliptical, or irregularly circular. The cross-sectional shape of the nanowire 3 directly affects the electric field distribution, carrier transport path, and interface properties with surrounding materials. Specifically, it provides a larger surface area, resulting in stronger electric field coupling with the dielectric layer 32 and the ring-gate electrode 33, and is suitable for enhancing the control of the two-dimensional hole gas. It also provides a more uniform electric field distribution and a short, symmetrical carrier transport path, which helps improve mobility and signal response speed. It also provides stronger electric field control capabilities in one dimension, meeting the needs of optimizing electron transport in a specific direction. The irregularity of the surface shape can increase the influence of surface states on carriers, enabling special functions or performance adjustments, such as enhancing scattering effects to adjust mobility. Different cross-sectional shapes can be flexibly adjusted according to actual application requirements to balance performance, cost, and manufacturing difficulty. By adjusting the cross-sectional shape, the electric field distribution and carrier behavior can be optimized to meet the performance requirements of different scenarios, such as high-frequency, high-power, or miniaturized applications. Polygonal and elliptical cross-sectional shapes improve gate control capabilities and are particularly suitable for high-performance field-effect transistors that require precise control. Circular or elliptical cross-sections are easier to achieve using conventional nanofabrication techniques, reducing manufacturing difficulty and cost. Irregular circular cross-sections can be used to explore new functional devices, such as achieving special carrier transport or storage properties by engineering surface states.

[0041] The specific structure, from bottom to top, includes: a diamond substrate layer 1, a ring-gate structure 2; the ring-gate structure 2 includes a gate electrode 23 and a nanowire 3; the nanowire 3 is a multilayer structure, comprising, from the inside out, a diamond core 34, a diamond terminal surface 31, a dielectric layer 32, and a ring-gate electrode 33; the nanowire 3 is suspended above the diamond substrate layer 1 and vertically passes through the gate electrode 23, i.e., the gate electrode 23 completely wraps the nanowire 3; the source electrode 21 and the drain electrode 22 are located on either side of the gate electrode 23, forming ohmic contacts with the diamond terminal surface 31 respectively; a two-dimensional hole gas (2DHG) is formed near the interface between the diamond terminal surface 31 and the dielectric layer 32, serving as the conductive channel of the diamond ring-gate field-effect transistor, and is regulated by the gate electrode 23 and the ring-gate electrode 33. The design of the ring-gate electrode 33 makes the gate electrode 23 more effective in regulating the conductive channel, resulting in higher transconductance, higher on-state current, and lower off-state leakage. The gate electrode 23 is made of Al and has a thickness of 300nm. The diamond termination surface 31 is hydrogen terminated. The dielectric layer 32 is made of Al2O3 and has a thickness of 10 nm. The ring gate electrode 33 is made of TiN and has a thickness of 50 nm. The source or drain electrode is made of Au and has a thickness of 200 nm.

[0042] It also includes a diamond substrate layer 1 and a ring gate structure 2; the ring gate structure 2 includes a source electrode 21, a drain electrode 22 and a gate electrode 23; the source electrode 21 and the drain electrode 22 constitute one or more nanowires 3, which are suspended above the diamond substrate layer 1 and vertically pass through the gate electrode 23, that is, the gate electrode 23 fully wraps the nanowire 3 composed of the source electrode 21 and the drain electrode 22; the nanowire 3 is a multi-layer structure, including, from the inside to the outside, a surface-modified terminal surface 31, a dielectric layer 32, and an electrode metal layer 33; a two-dimensional hole gas 2DHG is formed inside the terminal surface 31; the electrode metal layer 33 is the metal layer of the source electrode 21 and the drain electrode 22; the nanowire etching depth is 50nm and the shape is diamond.

[0043] A method for preparing a diamond-gated-all-around field-effect transistor is also provided. The diamond-gated-all-around field-effect transistor is used, and the method comprises:

[0044] S1, select a diamond substrate layer 1;

[0045] S2. Forming nanowire-shaped diamond cores 34 on the surface of the diamond substrate layer 1 by photolithography, specifically comprising: coating the surface of the diamond substrate layer 1 with a photoresist and forming a mask; etching the surface of the diamond substrate layer 1 using a dry etching process to form the nanowire diamond cores 34; and removing the mask to retain the nanowire structure.

[0046] S3, pre-treating the surface of the diamond core 34 and performing hydrogen termination or silicon termination treatment to form a two-dimensional hole gas 2DHG terminal surface 31 on the surface of the diamond core;

[0047] S4, depositing dielectric material on the terminal surface 31 of the nanowire in all directions to form a dielectric layer 32, wherein the thickness of the dielectric layer is in the range of 3 nm to 50 nm;

[0048] S5, depositing metal material all around the periphery of the dielectric layer 32 to form a ring gate electrode 33;

[0049] S6. Forming a gate electrode 23 on the diamond substrate layer 1 by photolithography, so that the nanowire 3 vertically passes through the gate electrode 23 and is fully wrapped by it;

[0050] S7 , removing part of the dielectric layer 32 , and depositing the source electrode 21 and the drain electrode 22 on both sides of the gate electrode 23 by photolithography to form ohmic contacts with the terminal surface 31 of the nanowire 3 .

[0051] This fabrication method achieves the construction of a high-performance diamond gate-all-around field-effect transistor through a precise process flow: Nanowire Formation S2: Using photolithography and dry etching techniques, the diamond core 34 of the nanowire is precisely constructed, ensuring controllable shape, size, and arrangement, laying the foundation for subsequent processes. Terminal Surface Treatment S3: Hydrogen or silicon termination is used to manipulate the surface state of the diamond core, ensuring the formation and stability of a two-dimensional hole gas (2DHG). Gate-all-around Structure Construction S4-S6: Uniform deposition of a dielectric layer and a metal gate-all-around on the nanowire surface, utilizing a fully encapsulated structure to efficiently control the channel electric field and improve device performance. Electrode Fabrication S7: Photolithographic deposition of source and drain electrodes creates ohmic contact with the terminal surface, reducing contact resistance and ensuring efficient electron injection and extraction. Photolithography and dry etching techniques ensure high precision in the size and shape of the nanowire and other structures, improving device consistency and performance stability. The fully encapsulated gate-all-around electrode design enables precise control of the two-dimensional hole gas, significantly improving gate efficiency and transistor performance. The terminal surface treatment, combined with optimized source and drain electrode materials and processes, significantly reduces contact resistance and enhances carrier mobility. This method is compatible with existing semiconductor manufacturing technologies, suitable for large-scale production, and scalable. The use of diamond materials combined with optimized terminal treatment and electrode deposition processes enables stable device operation in high-temperature, high-power environments.

[0052] Specifically, step 1: selecting a substrate, selecting a single crystal diamond substrate layer 1 prepared by a high temperature and high pressure (HPHT) method;

[0053] Step 2: Nanowire Etching: After forming a rectangular shape on the surface of the diamond substrate 1 through a series of steps including resist coating, pre-baking, exposure, post-baking, and development, electron beam evaporation is used to form a metallic Au masking layer with a thickness of 50-150 nm. Inductively coupled plasma etching (ICP) is then used to form grooves with an etching depth of 100 nm. The plasma bombardment angle is then adjusted to etch the inverted triangular shape of the nanowire 3. Finally, a mixed solution of potassium iodide (KI) and iodine (I2) is used to wet-etch and remove the Au masking layer.

[0054] Step 3: Terminal surface treatment: The nanowires 3 are pretreated, including screening, pickling, and cleaning with acetone, anhydrous ethanol, and deionized water. The sample is then placed in an MPCVD chamber in a hydrogen plasma atmosphere for 15 minutes, with an H2 flow rate of 600 sccm, a power of 2 kW, and a chamber temperature of 900°C. The sample is then cooled to room temperature in the hydrogen plasma atmosphere and removed to form a terminal surface 31 with two-dimensional voids.

[0055] Step 4: Dielectric layer deposition: Atomic layer deposition (ALD) is used to deposit an Al2O3 dielectric layer 32 at 120°C to fully wrap the nanowires 3, with a thickness of 20 nm.

[0056] Step 5: Deposition of the electrode metal layer: using the atomic layer deposition (ALD) method, Au is deposited on the periphery of the dielectric layer 32 as the electrode metal layer 33 with a thickness of 100 nm.

[0057] Step 6: Gate electrode growth, coating, pre-baking, exposure, post-baking and development form a gate metal pattern, and then use electron beam evaporation to evaporate a single layer of Al metal with a thickness of 120nm. After a lift-off process, a gate metal electrode is formed.

[0058] S7. Fabrication of source and drain electrodes: Using photolithography technology and photoresist as a mask, BOE is used to remove the dielectric layer 32 in some areas, and the source electrode metal Au and the drain electrode metal Au are deposited. After stripping, the source electrode 21 and the drain electrode 22 are fabricated.

[0059] The terminal surface 2 uses silicon terminals. After the diamond substrate layer 1 is hydrogen terminated, the sample is placed in an ultra-high vacuum system equipped with a Si sublimation source. First, the sample is heated at 450°C for 45 minutes to remove adsorbents on the hydrogen-terminated diamond surface. When the sample temperature returns to room temperature, the Si sublimation source is electrically heated to achieve molecular beam deposition of Si on the diamond surface. The current is 50A and the deposition rate is 200 nm. The thickness of the deposited Si element is 0.5nm, which is equivalent to 1.85ML. After the deposition is completed, the sample is subjected to in-situ vacuum annealing at 920℃ for 12 minutes. Through this treatment, the C-H structure on the surface of the entire diamond sample can be transformed into a C-Si structure. C-Si diamond has a lower interface state density, higher threshold voltage, higher hole mobility, etc. than C-H diamond. After the sample is taken out and the surface Si is oxidized, it becomes a C-Si-O / SiO2 structure. The dielectric layer 32 of this embodiment is a 20nm thick MoO3 layer deposited by the ALD method. The source electrode and drain electrode metals of this embodiment are Ti / Pt / Au with a thickness of 150nm. The gate metal of this embodiment is 80nm Al.

[0060] The preparation method further comprises the steps of: selecting a substrate, preparing a single crystal diamond substrate layer 1 by a high temperature and high pressure (HPHT) method;

[0061] Step 2: Groove etching: After forming a groove shape on the surface of the diamond substrate layer 1 through steps such as coating, pre-baking, exposure, post-baking and development, electron beam evaporation is used to form a metal Au material masking layer with a thickness of 20nm. ICP etching is used to form a groove with an etching depth of 150nm and an inverted trapezoidal shape. Finally, a mixed solution of potassium iodide (KI) and iodine (I2) is used to wet etch and remove Au;

[0062] Step 3: Terminal surface treatment: The diamond substrate 1 is pretreated, including screening, pickling, and cleaning with acetone, anhydrous ethanol, and deionized water. The diamond substrate 1 is placed in a hydrogen plasma in an MPCVD reaction chamber. H2 is introduced into the reaction chamber at a flow rate of 700 sccm and a pressure of 100 mbar. The reaction chamber is maintained at a temperature of 875°C and a microwave power of 2 kW for 15 minutes to form a terminal surface 31 with two-dimensional void gas.

[0063] Step 4: Dielectric layer deposition: A MoO3 dielectric layer 32 is deposited at 120°C using an atomic layer deposition (ALD) method to fully wrap the nanowires 3 with a thickness of 20 nm.

[0064] Step 5: Electrode metal layer deposition: Using atomic layer deposition (ALD), Ti / Pt / Au is deposited around the dielectric layer 32 to form the electrode metal layer 33, with a thickness of 150 nm. This completes the fabrication of the nanowire 3, with the source electrode 21 and drain electrode 22 formed.

[0065] Step 6: Gate electrode growth, coating, pre-baking, exposure, post-baking and development form a gate metal pattern, and then use electron beam evaporation to evaporate Al single layer metal with a thickness of 80nm, and after the lift-off process, form the gate metal electrode.

[0066] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A diamond gate-all-around field-effect transistor, characterized in that: include: a diamond substrate layer (1); A ring-gate structure (2) suspended above the diamond substrate layer (1), the ring-gate structure (2) comprising a nanowire (3), a gate electrode (23) and a ring-gate electrode (33) covering the gate electrode; The nanowire (3) includes, from the inside out, a diamond core (34), a diamond terminal surface (31), a dielectric layer (32), and a ring gate electrode (33), vertically passing through the gate electrode (23) and being fully wrapped by it; a source electrode (21) and a drain electrode (22), wherein the source electrode (21) and the drain electrode (22) are respectively located on both sides of the gate electrode (23) and form an ohmic contact with the diamond terminal surface (31); A two-dimensional void gas is formed at the interface between the diamond terminal surface (31) and the dielectric layer (32).

2. The diamond gate-all-around field-effect transistor according to claim 1, characterized in that: The thickness of the gate electrode (23) is 50nm-500nm.

3. The diamond gate-all-around field-effect transistor according to claim 1, wherein: The diamond terminal surface (31) is hydrogen-terminated or silicon-terminated.

4. The diamond gate-all-around field-effect transistor according to claim 1, wherein: The thickness of the dielectric layer (32) is 3nm-50nm.

5. The diamond gate-all-around field-effect transistor according to claim 1, characterized in that: The thickness of the ring gate electrode (33) is 10nm-100nm.

6. The diamond gate-all-around field-effect transistor according to claim 1, characterized in that: The thickness of the source electrode (21) is 50nm-500nm.

7. The diamond gate-all-around field-effect transistor according to claim 1, characterized in that: The cross-sectional shape of the nanowire (3) is polygonal, circular, elliptical or irregularly circular.

8. A method for preparing a diamond gate-all-around field effect transistor, for preparing the diamond gate-all-around field effect transistor according to any one of claims 1 to 7, characterized in that: The method comprises: S1, selecting a diamond substrate layer (1); S2, forming a nanowire-shaped diamond core (34) on the surface of the diamond substrate layer (1) by photolithography, specifically comprising: coating a photoresist on the surface of the diamond substrate layer (1) to form a mask; etching using a dry etching process to form a nanowire-shaped diamond core (34); removing the mask to retain the nanowire structure; S3, pre-treating the surface of the diamond core (34), and performing hydrogen termination or silicon termination treatment to form a two-dimensional hole gas (2DHG) termination surface (31) on the surface of the diamond core; S4, depositing dielectric material on the terminal surface (31) of the nanowire in all directions to form a dielectric layer (32), wherein the thickness of the dielectric layer ranges from 3 nm to 50 nm; S5, depositing metal material in all directions around the periphery of the dielectric layer (32) to form a ring gate electrode (33); S6. Forming a gate electrode (23) on the diamond substrate layer (1) by photolithography, so that the nanowire (3) vertically passes through the gate electrode (23) and is fully wrapped by it; S7, removing part of the dielectric layer (32), and depositing a source electrode (21) and a drain electrode (22) on both sides of the gate electrode (23) by a photolithography process, so as to form an ohmic contact with the terminal surface (31) of the nanowire (3).

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