Vertical gallium nitride-based fin-type radio frequency junction field effect transistor and preparation method thereof

Abstract

The invention discloses a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method, and relates to the technical field of semiconductor devices, the vertical gallium nitride-based fin-type radio frequency junction field effect transistor comprises a substrate layer, a nucleating layer, a buffer layer and a drain contact layer which are sequentially stacked from bottom to top; the channel layer is arranged on the drain electrode contact layer and consists of a fin part channel layer and a non-fin part channel layer; the source electrode contact layer is arranged on the fin part channel layer; the P-type gates are arranged on the two sides of the fin part channel layer and part of the surface of the non-fin part channel layer; the gate electrode is arranged on the P-type gate extension part and forms ohmic contact or Schottky contact with the P-type gate; the drain electrode is arranged on the drain electrode contact layer and forms ohmic contact with the drain electrode contact layer; according to the vertical gallium nitride-based fin type radio frequency junction field effect transistor and the preparation method thereof, enhancement type work is facilitated, the voltage endurance capability of the gate electrode is improved, the gate signal input dynamic range is expanded, and the long-term reliability of a device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, based on the prediction of Moore's Law, semiconductor technology has been widely used in many fields such as aerospace, wireless communications and electric vehicles. The performance of semiconductor devices has always been the focus of attention. Among them, silicon (Si), as the first generation of semiconductor materials, has long dominated semiconductor devices due to its mature process and superior physical properties. However, with the continuous advancement of technology, the performance of silicon materials has approached its physical limit, resulting in bottlenecks in improving the performance of semiconductor devices based on silicon materials. This problem also calls into question the continued effectiveness of Moore's Law.

[0003] In order to cope with the limitations of silicon materials, people gradually turn their attention to a new generation of semiconductor materials. Among them, gallium nitride (GaN), as a typical representative of the third generation of wide bandgap semiconductors, has shown great application potential in the field of high-power and high-frequency devices due to its advantages such as wide bandgap, high critical electric field strength, high electron saturation velocity and high breakdown electric field. At present, gallium nitride devices are mainly lateral structures, especially high electron mobility transistors (HEMT). However, lateral structure GaN devices have exposed the following problems in application: for high-power devices, in order to meet performance requirements, the width and number of gate electrodes need to be increased, resulting in a significant increase in device area and the introduction of more parasitic capacitance, affecting device performance; the conductive channel of lateral structure GaN HEMT devices depends on two-dimensional electron gas (2DEG), which is easily affected by surface states, reducing device stability; lateral structure devices are prone to charge concentration at both ends of the channel, resulting in severe local heat generation at both ends, low device breakdown voltage, and reduced reliability. Summary of the invention

[0004] The purpose of the present invention is to provide a vertical gallium nitride-based fin-type radio frequency junction field effect transistor and a preparation method thereof, so as to solve the problems existing in the prior art.

[0005] To achieve the above object, the present invention provides the following technical solution: a vertical gallium nitride-based fin-type radio frequency junction field effect transistor, comprising:

[0006] A substrate layer, a nucleation layer, a buffer layer, and a drain contact layer are stacked in sequence from bottom to top;

[0007] A channel layer, disposed on the drain contact layer, and consisting of a fin channel layer and a non-fin channel layer;

[0008] A source contact layer, disposed on the fin channel layer;

[0009] A P-type gate is arranged on both sides of the fin channel layer and a part of the surface of the non-fin channel layer;

[0010] A gate electrode, disposed on the P-type gate extension portion, and forming an ohmic contact or a Schottky contact with the P-type gate;

[0011] A drain electrode is disposed on the drain contact layer and forms an ohmic contact with the drain contact layer;

[0012] A source electrode is disposed on the source contact layer and forms an ohmic contact with the source contact layer;

[0013] Wherein, the materials of the buffer layer, the drain contact layer, the channel layer, the source contact layer and the P-type gate are group III nitride semiconductor materials.

[0014] Preferably, the drain contact layer is made of GaN, AlGaN or InGaN, has a thickness of 50 nm to 2 μm, and is doped with Si at a doping concentration of 1×10 17 Up to 1×10 21 cm -3 .

[0015] Preferably, the material of the channel layer is gallium nitride, AlGaN or InGaN, the thickness is 100nm to 10μm, the doping impurity is Si, and the doping concentration is 1×10 15 Up to 1×10 18 cm -3 .

[0016] Preferably, the height of the fin channel layer is 40 nm to 10 μm, and the width of the fin is 10 nm to 1 μm.

[0017] Preferably, the doping impurity of the P-type gate is Mg, and the doping concentration is 1×10 15 Up to 1×10 18 cm -3 , thickness is 5nm to 100nm, and height is 5nm to 1μm.

[0018] Preferably, the source contact layer is made of GaN, AlGaN or InGaN, has a thickness of 10 nm to 1 μm, and is doped with Si at a doping concentration of 1×10 17 Up to 1×10 21 cm -3 .

[0019] Preferably, the height of the P-type gate does not exceed the height of the fin channel layer.

[0020] A method for preparing a vertical gallium nitride-based fin-type radio frequency junction field effect transistor, using the vertical gallium nitride-based fin-type radio frequency junction field effect transistor, the method comprising:

[0021] S1, select the substrate layer;

[0022] S2, epitaxially growing a nucleation layer, a buffer layer, a drain contact layer, a channel layer, and a source contact layer on the substrate layer in sequence;

[0023] S3, etching the channel layer and the source contact layer to form a fin channel layer;

[0024] S4, regrowing P-GaN on a portion of the surface of the channel layer to form a P-type gate;

[0025] S5, etching the channel layer to expose both ends of the drain contact layer;

[0026] S6, preparing a source electrode above the source contact layer, and preparing drain electrodes at both ends of the drain contact layer;

[0027] S7. Prepare a gate electrode on the extended portion of the P-type gate.

[0028] The material of the substrate layer is silicon, sapphire or SiC, and the surface is chemically cleaned and used for epitaxial growth.

[0029] The material of the nucleation layer is AlN, and the epitaxial growth temperature is 950°C.

[0030] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0031] The vertical gallium nitride-based fin-type radio frequency junction field effect transistor and preparation method, by adopting a vertical structure design, significantly reduces the local heating problem caused by charge concentration in lateral structure devices, and improves the breakdown voltage and long-term stability of the device. At the same time, the vertical current path effectively distributes the power density, reducing the difficulty of heat dissipation. Through the innovative design of the fin channel layer, the device of the present invention effectively reduces the gate area while increasing the current density, reduces the parasitic capacitance, thereby improving the switching speed and performance in high-frequency applications. The use of a P-type gate structure and an optimized doping process effectively avoids the instability caused by the two-dimensional electron gas being affected by the surface state, and enhances the reliability of the conductive channel and the consistency of the device. The present invention proposes an epitaxial growth scheme compatible with a variety of substrate materials (such as silicon, sapphire or SiC), and at the same time achieves high-quality epitaxial layer growth by optimizing the materials and thickness of the nucleation layer and the buffer layer. This not only improves the adaptability of the material, but also reduces the process complexity and cost. The device adopts wide bandgap materials and innovative fin structure design, and exhibits excellent performance in high-power and high-frequency application scenarios (such as RF amplifiers and high-efficiency switching power supplies), meeting the needs of the next generation of high-power density devices. The introduction of a P-type gate between the gate electrode and the channel layer is beneficial to achieving enhanced operation, and improves the voltage resistance of the gate electrode, expands the dynamic range of the gate signal input, and improves the long-term reliability of the device. The P-type gate and gate electrode on the non-fin channel layer and the upper surface have a certain field plate effect, which improves the breakdown voltage of the device and suppresses the current collapse effect of the device. Compared with transistors with a lateral structure, the vertical gallium nitride-based fin-type RF transistor provided by the present invention only needs to increase the thickness of the non-fin part of the channel layer when the device voltage resistance needs to be improved. In this way, under the same voltage resistance and current conditions, the device requires a smaller area and has a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a vertical gallium nitride-based fin-type radio frequency transistor of the present invention;

[0033] Figure 2 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0034] Figure 3 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0035] Figure 4 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0036] Figure 5 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0037] Figure 6A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0038] Figure 7 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0039] Figure 8 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0040] Fig. 9 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0041] Fig.10 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0042] Fig.11 A schematic diagram of the process of preparing a vertical gallium nitride-based fin-type radio frequency transistor according to the present invention;

[0043] Fig.12 It is a top view of the structure of the vertical gallium nitride-based fin-type radio frequency transistor of the present invention.

[0044] In the figure: 1. substrate layer; 2. nucleation layer; 3. buffer layer; 4. drain contact layer; 5. channel layer; 51. fin channel layer; 52. non-fin channel layer; 6. source contact layer; 7. gate electrode; 71. P-type gate; 8. drain electrode; 9. source electrode. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] like Figure 1-Figure 12As shown, the present invention provides a technical solution: a vertical gallium nitride-based fin-type radio frequency junction field effect transistor includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, and a drain contact layer 4 stacked in sequence from bottom to top; a channel layer 5, composed of a fin channel layer 51 and a non-fin channel layer 52, arranged on the drain contact layer 4; a source contact layer 6, arranged on the fin channel layer 51; a P-type gate 71, arranged on both sides of the fin channel layer 51 and a part of the surface of the non-fin channel layer 52; a gate electrode 7, arranged on an extension portion of the P-type gate 71, forming an ohmic contact or a Schottky contact with the P-type gate 71; a drain electrode 8, arranged on the drain contact layer 4, forming an ohmic contact with the drain contact layer 4; a source electrode 9, arranged on the source contact layer 6, forming an ohmic contact with the source contact layer 6; wherein the materials of the buffer layer 3, the drain contact layer 4, the channel layer 5, the source contact layer 6 and the P-type gate 71 are group III nitride semiconductor materials.

[0047] The transistor uses a fin structure to achieve a vertical current path and optimize RF performance. The presence of the P-type gate 71 forms a local depletion control of the channel layer 5. The fin channel layer 51 increases the effective gate area of ​​the transistor, improving the gate control capability and current density. The ohmic contact between the drain contact layer 4 and the drain electrode 8 ensures low-resistance conduction, and the ohmic contact between the source contact layer 6 and the source electrode 9 achieves efficient current injection and enhances transistor performance. The overall structure adopts group III nitride materials with high breakdown voltage and low loss characteristics. The design of this structure realizes high-efficiency RF signal amplification function, with the advantages of high-frequency performance and low power consumption. The vertical structure simplifies the device layout and improves the heat dissipation performance and power density. The design of the P-type gate further improves the switching speed and control accuracy of the transistor, and the overall structure has higher stability under high temperature and high pressure conditions.

[0048] In a possible implementation manner, the drain contact layer 4 is made of GaN, AlGaN or InGaN, has a thickness of 50 nm to 2 μm, and is doped with Si at a doping concentration of 1×10 17 Up to 1×10 21 cm -3 . The drain contact layer 4 increases the electron concentration and reduces the resistance within the layer by doping Si elements, thereby achieving efficient drain current transmission. The material thickness is controlled between 50nm and 2μm, taking into account both the conductive properties and the integrity of the device structure. The above-mentioned doping concentration range and material combination make the drain contact layer have low resistance and high reliability, meet the requirements of high power and high frequency operation, and further enhance the RF performance of the transistor.

[0049] In a possible implementation manner, the material of the channel layer 5 is gallium nitride, AlGaN or InGaN, the thickness is 100 nm to 10 μm, the doping impurity is Si, and the doping concentration is 1×1015 Up to 1×10 18 cm -3 . The conductive characteristics of the channel layer 5 are optimized by doping control, and the thickness range is selected to ensure the balance between the stability of the current channel and the switching performance of the transistor. The optimization of the doping concentration provides adjustable performance suitable for different operating voltage and frequency conditions. The optimized channel layer material and doping concentration achieve the comprehensive performance of low leakage current, high switching speed and high breakdown voltage, significantly improving the RF output power and reliability of the device.

[0050] In one possible implementation, the height of the fin channel layer 51 is 40nm to 10μm, and the fin width is 10nm to 1μm. The fin channel layer 51 optimizes the electric field distribution and current density of the transistor through a specific height and width design. The taller fin structure increases the effective gate area and improves the gate control efficiency; the narrower fin width increases the gate's ability to control the electric field of the channel, thereby effectively suppressing the short channel effect. This design enables the transistor to have the advantages of high switching speed, high current density and low leakage current, while ensuring stability support in high-frequency applications. The fin structure also improves the power density and voltage resistance of the transistor.

[0051] In a possible implementation manner, the doping impurity of the P-type gate 71 is Mg, and the doping concentration is 1×10 15 Up to 1×10 18 cm -3 , thickness is 5nm to 100nm, and height is 5nm to 1μm. The P-type gate 71 forms P-type characteristics by doping Mg elements, providing a depletion or enhancement regulation mechanism for the channel layer. The optimization of the thickness and height range ensures the uniformity of the gate coverage area while reducing the parasitic capacitance of the device. This design enables the transistor to exhibit excellent control capabilities in different operating modes, ensuring high-speed switching characteristics and low-power operation. In addition, the presence of the P-type gate also improves the controllability of the switching threshold and anti-interference ability of the transistor.

[0052] In a possible implementation manner, the source contact layer 6 is made of GaN, AlGaN or InGaN, has a thickness of 10 nm to 1 μm, and is doped with Si at a doping concentration of 1×10 17 Up to 1×10 21 cm -3 The source contact layer 6 achieves high-concentration electron injection by doping Si, forming an ohmic contact with low contact resistance. The selection of materials and thickness takes into account both conductivity and device stability, supporting efficient source current injection. This structural design effectively reduces the source resistance, improves the power efficiency and output characteristics of the transistor, and improves the reliability and anti-interference ability of high-frequency operation.

[0053] In a possible implementation, the height of the P-type gate 71 does not exceed the height of the fin channel layer 51. By limiting the height of the P-type gate 71, it is ensured that it only exerts control on the effective area of ​​the channel layer, avoiding unnecessary parasitic effects caused by covering too much area, while maintaining the strength and uniformity of the gate electric field. This limiting design significantly reduces the parasitic capacitance of the device, improves the switching speed and high-frequency performance of the transistor, reduces leakage current and power consumption, and improves the overall performance stability.

[0054] A method for preparing a vertical gallium nitride-based fin-type radio frequency junction field effect transistor is also provided. The vertical gallium nitride-based fin-type radio frequency junction field effect transistor is used, and the method comprises:

[0055] S1, select substrate layer 1;

[0056] S2, epitaxially growing a nucleation layer 2, a buffer layer 3, a drain contact layer 4, a channel layer 5 and a source contact layer 6 in sequence on the substrate layer 1;

[0057] S3, etching the channel layer 5 and the source contact layer 6 to form a fin channel layer 51;

[0058] S4, regrowing P-GaN on a surface of a portion of the channel layer 5 to form a P-type gate 71;

[0059] S5, etching the channel layer 5 to expose both ends of the drain contact layer 4;

[0060] S6, preparing a source electrode 9 on the source contact layer 6, and preparing a drain electrode 8 at both ends of the drain contact layer 4;

[0061] S7 . Prepare a gate electrode 7 on the extended portion of the P-type gate 71 .

[0062] The preparation method uses selective etching and regrowth technology to accurately control the formation position of the fin structure and P-type gate of the channel layer, thereby realizing local control of the channel layer. The epitaxial growth process of steps S1-S2 ensures the high-quality growth and material integrity of each layer of the transistor. The etching process in step S3 defines the geometric parameters of the fin channel layer, which helps to optimize the electrical performance of the device. The P-GaN regrowth of S4 forms a P-type gate, which is used to control the depletion region of the channel layer. The electrode preparation steps of S6 and S7 ensure the ohmic contact and gate signal transmission capabilities of the device. The method provides a high-precision manufacturing process that realizes low power consumption, high efficiency and high-frequency performance of the transistor. The formation process of the fin structure simplifies the control of the vertical current path and improves the power density and heat dissipation performance of the device. The selective regrowth technology of the P-type gate ensures local control of the channel layer and improves the working efficiency and reliability of the device.

[0063] In one possible implementation, the material of the substrate layer 1 is silicon, sapphire or SiC, and the surface is chemically cleaned for epitaxial growth. By selecting different materials for the substrate layer 1, a stable lattice matching basis can be provided for epitaxial growth. Chemical cleaning treatment can remove oxides and other contaminants on the surface of the substrate, thereby improving the crystal quality and adhesion of the epitaxial growth layer. Silicon substrates have the advantages of low cost and good thermal conductivity; sapphire substrates have good electrical insulation and heat resistance; SiC substrates provide excellent thermal conductivity and lattice matching. The selection of different substrate materials meets the different requirements of the device in terms of cost, thermal conductivity and mechanical properties. The introduction of chemical cleaning treatment significantly improves the uniformity of the epitaxial layer and the defect density control capability, and ultimately improves the overall performance of the device.

[0064] In one possible implementation, the material of the nucleation layer 2 is Al N, and the epitaxial growth temperature is 950°C. The use of Al N material in the nucleation layer 2 can effectively reduce the stress caused by lattice mismatch during epitaxial growth, while optimizing the crystal quality of the subsequent epitaxial layer. The epitaxial growth temperature of 950°C ensures uniform deposition and low defect density of the Al N layer, providing a high-quality nucleation substrate. By using the Al N nucleation layer and precise temperature control, crystal defects and interface stress are greatly reduced, and the adhesion and crystal quality of the subsequent growth layer are improved, thereby improving the reliability and performance of the device.

[0065] In another embodiment, a vertical GaN-based fin-type RF junction field effect transistor includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, and a drain contact layer 4 stacked in sequence from bottom to top.

[0066] The channel layer 5 is disposed on the drain contact layer 4 and consists of a fin channel layer 51 and a non-fin channel layer 52;

[0067] A source contact layer 6 is disposed on the fin channel layer 51;

[0068] A P-type gate 71 is disposed on both sides of the fin channel layer 51 and a portion of the surface of the non-fin channel layer 52;

[0069] The gate electrode 7 is arranged at the extension portion of the P-type gate 71 and forms an ohmic contact or a Schottky contact with the P-type gate 71 in the channel layer;

[0070] The drain electrode 8 is disposed on the upper surface of the drain contact layer 4 and forms an ohmic contact with the drain contact layer 4 .

[0071] The source electrode 9 is disposed on the source contact layer 6 and forms an ohmic contact with the source contact layer 6 .

[0072] The materials of the buffer layer 3, drain contact layer 4, channel layer 5, source contact layer 6, and P-type gate 71 are all group III nitride semiconductor materials, which are one of GaN, AlN, InN, or a compound composed of multiple components; the fin channel layer 51 improves the control effect of the gate electrode 7 on the conductive channel, improves the transconductance of the device, suppresses the short channel effect, and is beneficial to achieving enhanced operation; the non-fin channel layer 52 has a certain field plate effect, improves the breakdown voltage of the device, and suppresses the current collapse effect of the device; the introduction of the P-type gate 71 between the gate electrode 7 and the channel layer 5 is beneficial to achieving enhanced operation, and improves the voltage resistance of the gate electrode 7, expands the dynamic range of the gate signal input, and improves the long-term reliability of the device.

[0073] The material of the drain contact layer 4 is gallium nitride, or AlGaN, or InGaN, with a thickness of 50nm-2μm, and the doping impurity is Si with a doping concentration of 1x10 17 -1 x10 21 cm -3 The material of the drain contact layer 4 is gallium nitride, with a thickness of 1 μm, and the doping impurity is Si with a doping concentration of 1x10 20 cm -3 The material of the channel layer 5 is gallium nitride, AlGaN, or InGaN, with a thickness of 100nm-10μm, and the doping impurity is Si with a doping concentration of 1x10 15 -1 x10 18 cm -3 The material of the channel layer 5 is GaN, the thickness is 5 μm, the doping impurity is Si, and the doping concentration is 5x10 17 cm -3 The height of the fin channel layer 51 is 40nm-5μm, and the fin width is 10nm-1μm; the height of the fin channel layer 51 is 500nm, and the fin width is 200nm. The doping impurity of the P-type gate 71 is Mg, and the doping concentration is 1x10 15 -1x10 18 cm -3 , with a thickness of 5nm-100nm and a height of 5nm-1μm; the doping impurity of the P-type gate 71 is Mg, and the doping concentration is 5x10 17 cm -3 , with a thickness of 50nm and a height of 300nm; the material of the source contact layer 6 is gallium nitride, or AlGaN, or InGaN, with a thickness of 10nm-1μm, and the doping impurity is Si, with a doping concentration of 1x10 17 -1x10 21 cm -3 The source contact layer is made of GaN with a thickness of 500 nm and doped with Si at a concentration of 1x10 20cm -3 The height of the P-type gate 71 does not exceed the height of the fin channel layer 51 .

[0074] A method for preparing a vertical gallium nitride-based fin-type radio frequency junction field effect transistor is also provided, the method comprising:

[0075] Select substrate layer 1. The material of the substrate layer is silicon, and chemical cleaning of the silicon substrate can be classified into the following steps: decontamination, etching, cleaning and drying.

[0076] A nucleation layer 2 is epitaxially grown on the substrate layer. The material of the nucleation layer is selected as AlN, for example, and the temperature of the MOCVD chamber is raised to 950 degrees Celsius. The substrate substrate is nitrided at 950 degrees Celsius to form AlN molecules on the surface of the sapphire substrate Al2O3 and grow an AlN nucleation layer to improve the quality of epitaxially grown GaN on the sapphire substrate.

[0077] The buffer layer 3 is epitaxially grown on the nucleation layer. The buffer layer is made of AlN, and the AlN film is formed by chemical reaction on the substrate surface under high temperature conditions by introducing NH3 and TMAL sources.

[0078] A drain contact layer 4 is epitaxially grown on the buffer layer; a channel layer 5 is epitaxially grown on the drain contact layer, and a source contact layer 6 is epitaxially grown on the channel layer 5. Using the MOCVD method, an epitaxial layer with a thickness of 1 μm and a doping concentration of 1x10 20 cm -3 Si-doped GaN is used as the drain contact layer; epitaxial growth thickness is 5 μm on the drain contact layer, and the doping concentration is 1x10 17 cm -3 Si-doped GaN is used as the channel layer; epitaxial growth thickness is 500nm on the channel layer, and the doping concentration is 1x10 20 cm -3 Si-doped GaN serves as the source contact layer.

[0079] The source contact layer 6 and the channel layer 5 are etched to form a fin channel layer 51. In a plasma system, dry etching is performed based on Cl2 / BCl3, starting from the source contact layer, etching 1μm, and etching the channel layer into a "convex" shape. In order to obtain a vertical and smooth channel sidewall, the device after dry etching needs to be wet-etched based on hot TMAH (for example: heating in a water bath at 85°C for 1h) to treat the sidewall surface. After treatment, the mesa should have neat edges and steep sidewalls, and the photoresist should be retained until the next step.

[0080] P-GaN is regrown on the surface of part of the channel layer 5 to form a P-type gate 71; a MOCVD method is used to deposit a 0.3um thick GaN layer with a doping concentration of 5x10 17 cm -3 Mg-doped GaN is used as a P-type pillar in the channel layer.

[0081] Etch the channel layer to expose both ends of the drain contact layer. Use photolithography technology, use photoresist as a mask, and transfer the pattern to the photosensitive film layer covering the semiconductor wafer. Then, use ICP dry etching technology and TMAH wet etching technology to etch the channel layer, so that the drain contact layer is exposed on the surface to prepare the drain electrode.

[0082] Prepare the source electrode on the source contact layer; prepare the drain electrode above the two ends of the drain contact layer. Use the photolithography process to make the source electrode and drain electrode patterns. Then use electron beam evaporation technology or magnetron sputtering technology to deposit the source metal in the source electrode area (above the source contact layer); and deposit the drain metal in the drain electrode area (on both sides above the drain contact layer).

[0083] A gate electrode 7 is made on the extended portion of the P-type gate 71. A photolithography process is used to make a gate electrode pattern. Then, electron beam evaporation technology or magnetron sputtering technology is used to deposit gate electrode metal in the gate electrode region. At this point, the preparation of the vertical gallium nitride-based fin-type RF transistor is completed. The preparation method of the vertical gallium nitride-based fin-type RF transistor provided in this embodiment has a simple manufacturing process, a relatively low process cost, and is compatible with existing processes.

[0084] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A vertical gallium nitride-based fin-type radio frequency junction field effect transistor, characterized in that: include: A substrate layer (1), a nucleation layer (2), a buffer layer (3), and a drain contact layer (4) are stacked in sequence from bottom to top; A channel layer (5), arranged on the drain contact layer (4), and consisting of a fin channel layer (51) and a non-fin channel layer (52); A source contact layer (6) is disposed on the fin channel layer (51); A P-type gate (71) is arranged on both sides of the fin channel layer (51) and on a portion of the surface of the non-fin channel layer (52); A gate electrode (7) is arranged on an extended portion of the P-type gate (71) and forms an ohmic contact or a Schottky contact with the P-type gate (71); A drain electrode (8) is disposed on the drain contact layer (4) and forms an ohmic contact with the drain contact layer (4); A source electrode (9) is disposed on the source contact layer (6) and forms an ohmic contact with the source contact layer (6); The materials of the buffer layer (3), the drain contact layer (4), the channel layer (5), the source contact layer (6) and the P-type gate (71) are group III nitride semiconductor materials.

2. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The material of the drain contact layer (4) is GaN, AlGaN or InGaN, the thickness is 50nm to 2μm, the doping impurity is Si, and the doping concentration is 1×10 17 Up to 1×10 21 cm -3 .

3. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The material of the channel layer (5) is gallium nitride, AlGaN or InGaN, the thickness is 100nm to 10μm, the doping impurity is Si, and the doping concentration is 1×10 15 Up to 1×10 18 cm -3 .

4. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The height of the fin channel layer (51) is 40nm to 10μm, and the fin width is 10nm to 1μm.

5. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The doping impurity of the P-type gate (71) is Mg, and the doping concentration is 1×10 15 Up to 1×10 18 cm -3 , thickness is 5nm to 100nm, and height is 5nm to 1μm.

6. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The source contact layer (6) is made of GaN, AlGaN or InGaN, has a thickness of 10 nm to 1 μm, and is doped with Si at a doping concentration of 1×10 17 Up to 1×10 21 cm -3 .

7. The vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 1, characterized in that: The height of the P-type gate (71) does not exceed the height of the fin channel layer (51).

8. A method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor, using the vertical GaN-based fin-type radio frequency junction field effect transistor according to any one of claims 1 to 7, characterized in that: The method comprises: S1, selecting a substrate layer (1); S2, epitaxially growing a nucleation layer (2), a buffer layer (3), a drain contact layer (4), a channel layer (5), and a source contact layer (6) in sequence on the substrate layer (1); S3, etching the channel layer (5) and the source contact layer (6) to form a fin channel layer (51); S4, regrowing P-GaN on a portion of the surface of the channel layer (5) to form a P-type gate (71); S5, etching the channel layer (5) to expose both ends of the drain contact layer (4); S6, preparing a source electrode (9) above the source contact layer (6), and preparing a drain electrode (8) at both ends of the drain contact layer (4); S7. Prepare a gate electrode (7) on the extended portion of the P-type gate (71).

9. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 8, characterized in that: The material of the substrate layer (1) is silicon, sapphire or SiC, and the surface is chemically cleaned for epitaxial growth.

10. The method for preparing a vertical GaN-based fin-type radio frequency junction field effect transistor according to claim 8, characterized in that: The material of the nucleation layer (2) is AlN, and the epitaxial growth temperature is 950°C.

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