Transistor and method for manufacturing the same

Abstract

The present disclosure provides a transistor and a manufacturing method thereof, belonging to the field of semiconductor devices. The transistor comprises: a buffer layer, a stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer, wherein the stress buffer layer, the low-temperature GaN layer, the high-temperature GaN layer, the channel layer and the barrier layer are sequentially stacked on the buffer layer; the buffer layer is an AlN buffer layer, the stress buffer layer is an AlGaN stress buffer layer, and the low-temperature GaN layer is an oxygen-doped GaN layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art

[0002] GaN-on-Si is widely used in semiconductors, such as transistors.

[0003] The related art provides a silicon-based gallium nitride transistor, which mainly includes a buffer layer, a stress buffer layer, a channel layer and a barrier layer.

[0004] Among them, the buffer layer is an AlN layer, and the stress buffer layer is an AlGaN layer. Although the stress buffer layer can improve the stress during the epitaxial growth of the transistor, due to the difference in lattice constants between AlN and AlGaN, stress and dislocations still exist in AlGaN, which affects the epitaxial quality of the transistor and affects the transistor's electrical properties such as withstand voltage. Summary of the invention

[0005] The present disclosure provides a transistor and a method for manufacturing the same, which belongs to the field of semiconductors. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, comprising:

[0007] A buffer layer, a stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer, wherein the stress buffer layer, the low-temperature GaN layer, the high-temperature GaN layer, the channel layer and the barrier layer are sequentially stacked on the buffer layer;

[0008] The buffer layer is an AlN buffer layer, the stress buffer layer is an AlGaN stress buffer layer, and the low-temperature GaN layer is an oxygen-doped GaN layer.

[0009] Optionally, the growth temperature of the low-temperature GaN layer is 500-800°C, and the growth temperature of the high-temperature GaN layer is 900-1100°C.

[0010] Optionally, the low-temperature GaN layer has a thickness of 15 to 30 nm.

[0011] Optionally, the low-temperature GaN layer includes a three-dimensional island structure arranged on the surface of the stress buffer layer, and the density of the three-dimensional island structure is 10 8 ~10 9 cm -3 .

[0012] Optionally, the oxygen intake ratio during the growth of the low-temperature GaN layer is 0.1-0.6 ppm.

[0013] Optionally, along the direction from the buffer layer to the low-temperature GaN layer (103), the Al component in the stress buffer layer gradually decreases.

[0014] Optionally, the buffer layer includes a low-temperature AlN sublayer and a high-temperature AlN sublayer, and the high-temperature AlN sublayer is located between the low-temperature AlN sublayer and the stress buffer layer.

[0015] In another aspect, a method for manufacturing a transistor is provided, the method comprising:

[0016] Making a buffer layer, wherein the buffer layer is an AlN buffer layer;

[0017] A stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer are sequentially formed on the buffer layer. The stress buffer layer is an AlGaN stress buffer layer, and the low-temperature GaN layer is an oxygen-doped GaN layer.

[0018] Optionally, manufacturing the low-temperature GaN layer and the high-temperature GaN layer includes:

[0019] Growing the low-temperature GaN layer on the stress buffer layer at a growth temperature of 500 to 800° C.;

[0020] The high temperature GaN layer is grown on the low temperature GaN layer in an environment where the growth temperature is 900-1100° C.

[0021] Optionally, the oxygen intake ratio during the growth of the low-temperature GaN layer is 0.1-0.6 ppm.

[0022] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0023] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a stress buffer layer, the buffer layer and the stress buffer layer are used to improve the epitaxial growth stress of the transistor, however, due to the difference in lattice constants between AlN and AlGaN, stress and dislocation still exist in AlGaN; for this reason, the transistor provided by the embodiment of the present disclosure also includes a low-temperature GaN layer and a high-temperature GaN layer, wherein, due to the relatively low growth temperature of the low-temperature GaN layer, the atomic plane diffusion ability is weak, and three-dimensional island crystal nuclei will appear on the surface of AlGaN, and the three-dimensional island crystal nuclei will make the growth direction of the stacking dislocation turn from perpendicular to the top surface of AlGaN to parallel to the top surface of AlGaN, thereby avoiding the stacking dislocation from entering the subsequent film layer growth. The low-temperature GaN layer is doped with oxygen, oxygen exists at the interface of AlGaN and GaN, Al is bonded with oxygen and nitrogen to form AlON, and polarity regulation can be achieved, so that the growth interface of the low-temperature GaN layer is completely transformed into a unified Ga metal polarity plane, which is conducive to reducing the grain boundary density. The high-temperature GaN layer can fill the low-temperature GaN layer on the one hand, and can also block defects and control stress on the other hand. The low-temperature GaN layer and the high-temperature GaN layer can improve the epitaxial quality of the transistor and optimize the voltage resistance and other electrical properties of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of the comparison of AlGaN lattices in the high-temperature AlN sublayer and the stress buffer layer provided in an embodiment of the present disclosure;

[0028] Figure 4 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;

[0029] Figure 5 is a flow chart of another method for manufacturing a transistor provided by an embodiment of the present disclosure;

[0030] Figure 6 It is a schematic diagram of leakage current in a transistor provided by the related art;

[0031] Figure 7 is a schematic diagram of leakage current in a transistor provided by an embodiment of the present disclosure;

[0032] Figure 8 It is a schematic diagram comparing dynamic resistance tests of a transistor provided by related art and a transistor provided by an embodiment of the present disclosure.

[0033] Reference numerals

[0034] 101: buffer layer; 1101: low-temperature AlN sublayer; 1102: high-temperature AlN sublayer; 102: stress buffer layer; 103: low-temperature GaN layer; 104: high-temperature GaN layer; 105: channel layer; 106: barrier layer; 107: substrate; 108: passivation layer; 109: gate; 110: source; 111: drain. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a buffer layer 101, a stress buffer layer 102, a low-temperature GaN layer 103, a high-temperature GaN layer 104, a channel layer 105 and a barrier layer 106, wherein the stress buffer layer 102, the low-temperature GaN layer 103, the high-temperature GaN layer 104, the channel layer 105 and the barrier layer 106 are sequentially stacked on the buffer layer 101.

[0037] The buffer layer 101 is an AlN buffer layer, the stress buffer layer 102 is an AlGaN stress buffer layer, and the low-temperature GaN layer 103 is an oxygen-doped GaN layer.

[0038] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a stress buffer layer, the buffer layer and the stress buffer layer are used to improve the epitaxial growth stress of the transistor, however, due to the difference in lattice constants between AlN and AlGaN, stress and dislocation still exist in AlGaN; for this reason, the transistor provided by the embodiment of the present disclosure also includes a low-temperature GaN layer and a high-temperature GaN layer, wherein, due to the relatively low growth temperature of the low-temperature GaN layer, the atomic plane diffusion ability is weak, and three-dimensional island crystal nuclei will appear on the surface of AlGaN, and the three-dimensional island crystal nuclei will make the growth direction of the stacking dislocation turn from perpendicular to the top surface of AlGaN to parallel to the top surface of AlGaN, thereby avoiding the stacking dislocation from entering the subsequent film layer growth. The low-temperature GaN layer is doped with oxygen, oxygen exists at the interface of AlGaN and GaN, Al is bonded with oxygen and nitrogen to form AlON, and polarity regulation can be achieved, so that the growth interface of the low-temperature GaN layer is completely transformed into a unified Ga metal polarity plane, which is conducive to reducing the grain boundary density. The high-temperature GaN layer can fill the low-temperature GaN layer on the one hand, and can also block defects and control stress on the other hand. The low-temperature GaN layer and the high-temperature GaN layer can improve the epitaxial quality of the transistor and optimize the voltage resistance and other electrical properties of the transistor.

[0039] In the embodiment of the present disclosure, the buffer layer 101 may include a low-temperature AlN sublayer 1101 and a high-temperature AlN sublayer 1102 , wherein the high-temperature AlN sublayer 1102 is located between the low-temperature AlN sublayer 1101 and the stress buffer layer 102 .

[0040] In this implementation, by providing the low-temperature AlN sublayer 1101 and the high-temperature AlN sublayer 1102 , the stress generated by the epitaxial growth is reduced on the basis of reducing the lattice mismatch.

[0041] In the disclosed embodiment, the growth temperature of the low-temperature AlN sublayer 1101 is 700-900°C, and the growth temperature of the high-temperature AlN sublayer 1102 is 900-1100°C.

[0042] Exemplarily, the growth temperature of the low-temperature AlN sublayer 1101 is 800°C, and the growth temperature of the high-temperature AlN sublayer 1102 is 1000°C.

[0043] In the disclosed embodiment, the thickness of the low-temperature AlN sublayer 1101 is 20-50 nm, and the thickness of the high-temperature AlN sublayer 1102 is 100-300 nm.

[0044] Exemplarily, the thickness of the low-temperature AlN sublayer 1101 is 30 nm, and the thickness of the high-temperature AlN sublayer 1102 is 200 nm.

[0045] In the embodiment of the present disclosure, the low temperature AlN sublayer 1101 includes a three-dimensional island structure, and the density of the three-dimensional island structure in the low temperature AlN sublayer 1101 is 5*10 6 ~5*10 9 cm -3 That is, the low-temperature AlN sublayer 1101 is a seed layer, and no thin film is formed.

[0046] For example, the density of the three-dimensional island structure in the low-temperature AlN sublayer 1101 is 10 8 cm -3 .

[0047] In the embodiment of the present disclosure, the high temperature AlN sublayer 1102 covers the low temperature AlN sublayer 1101 , so that the entire buffer layer 101 forms a thin film, providing an AlN layer with a smooth surface.

[0048] In other embodiments, the buffer layer 101 may also include only one AlN sublayer.

[0049] In the embodiment of the present disclosure, the composition of Al in the stress buffer layer 102 is graded.

[0050] Exemplarily, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the Al composition in the stress buffer layer 102 gradually decreases.

[0051] In this implementation, the composition gradient of Al in the stress buffer layer 102 is controlled to change the lattice constant difference between AlN and AlGaN, thereby alleviating the stress problem of epitaxial growth.

[0052] For example, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the molar amount of Al in the stress buffer layer 102 decreases from 0.6-0.8 to 0.06-0.08.

[0053] For example, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the molar amount of Al in the stress buffer layer 102 decreases from 0.7 to 0.07.

[0054] Figure 3 Schematic diagram of the comparison of AlGaN lattices in the high temperature AlN sublayer and the stress buffer layer provided by the embodiment of the present disclosure. Figure 3 As shown in Figure 2, as the Al content in AlGaN decreases, Figure 3 (a) The lattice constant of AlN is small, while that of AlGaN is large. Figure 3 (b) The lattice constant of AlN is consistent with that of AlGaN. Figure 3 (c) AlN has a large lattice constant and AlGaN has a small lattice constant. Although this can improve the stress problem, Figure 3 As shown in (c), an atomic arrangement is missing at a local position (B in the figure), forming a dislocation (A in the figure). After the interface is neatly arranged, subsequent atomic stacking is performed, and the missing atomic arrangement at the interface and subsequent epitaxy will still accumulate stress. The low-temperature GaN layer and high-temperature GaN layer provided by the embodiments of the present disclosure can further solve this problem.

[0055] In the disclosed embodiment, the growth temperature of the stress buffer layer 102 is 1150-1300° C.

[0056] Exemplarily, the growth temperature of the stress buffer layer 102 is 1200° C.

[0057] In the disclosed embodiment, the thickness of the stress buffer layer 102 is 100-300 nm.

[0058] Exemplarily, the thickness of the stress buffer layer 102 is 200 nm.

[0059] In other embodiments, the composition of Al in the stress buffer layer 102 may also remain constant.

[0060] In the disclosed embodiment, the growth temperature of the low-temperature GaN layer 103 is 500-800°C, and the growth temperature of the high-temperature GaN layer 104 is 900-1100°C.

[0061] Exemplarily, the growth temperature of the low-temperature GaN layer 103 is 700° C., and the growth temperature of the high-temperature GaN layer 104 is 1000° C.

[0062] In this implementation, the use of the above temperature to grow the low-temperature GaN layer 103 can form a three-dimensional GaN island structure of good quality, so that the growth direction of the stacking dislocation changes, thereby preventing the stacking dislocation from entering the subsequent film growth. The use of the above temperature to grow the high-temperature GaN layer allows the high-temperature GaN layer to better fill the low-temperature GaN layer, thereby achieving defect blocking and stress control.

[0063] In the disclosed embodiment, the thickness of the low-temperature GaN layer 103 is 15-30 nm.

[0064] Exemplarily, the thickness of the low-temperature GaN layer 103 is 25 nm.

[0065] In this implementation, the low-temperature GaN layer of the above thickness will neither cause abnormality in the entire epitaxial layer due to being too thick, nor conflict with the thickness required for polarity control due to being too thin.

[0066] In the disclosed embodiment, the thickness of the high temperature GaN layer 104 is 100-500 nm.

[0067] Exemplarily, the thickness of the high temperature GaN layer 104 is 300 nm.

[0068] In the embodiment of the present disclosure, the low-temperature GaN layer 103 includes a three-dimensional island structure arranged on the surface of the stress buffer layer 102, and the density of the three-dimensional island structure is 10 8 ~10 9 cm -3 .

[0069] For example, the density of the three-dimensional island structure of the low-temperature GaN layer 103 is 5*10 8 cm -3 .

[0070] After careful comparative experimental analysis, when the density of the three-dimensional island structure of the low-temperature GaN layer is low, subsequent epitaxy will show local growth in multiple locations, and even fog in severe cases; when the density of the three-dimensional island structure of the low-temperature GaN layer is high, the GaN film will quickly connect into a sheet, and the meaning of regulation will be lost. The above three-dimensional island structure density avoids the occurrence of the above problems.

[0071] In the disclosed embodiment, the oxygen flux ratio during the growth of the low-temperature GaN layer 103 is 0.1-0.6 ppm.

[0072] PPM refers to Parts Per Million. Oxygen intake ratio refers to the ratio of oxygen to the total gas intake during the growth process.

[0073] Exemplarily, the oxygen flux ratio during the growth of the low-temperature GaN layer 103 is 0.3 ppm.

[0074] In this implementation, the above-mentioned oxygen intake allows a small amount of oxygen to be introduced into the growth of the low-temperature GaN layer, and the suspended Al at the AlGaN interface will bond with oxygen and nitrogen to form AlON, so that the growth surface of the subsequent low-temperature GaN layer is a unified Ga polarity surface, rather than a mixed polarity surface of Al and Ga, thereby achieving polarity regulation.

[0075] In the embodiment of the present disclosure, the channel layer 105 is a GaN channel layer.

[0076] The channel layer 105 has a thickness of 10-80 nm, for example, 50 nm.

[0077] In the embodiment of the present disclosure, the barrier layer 106 may be a single layer or a composite layer.

[0078] For example, the barrier layer 106 is an AlGaN layer.

[0079] In the embodiment of the present disclosure, the thickness of the barrier layer 106 may be 20-30 nm, for example, 25 nm.

[0080] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer 106 is 0.2-0.3, for example, 0.25.

[0081] See also Figure 2 The transistor may further include a substrate 107 , on which a buffer layer 101 and a stress buffer layer 102 are sequentially stacked.

[0082] In the embodiment of the present disclosure, the substrate 107 may be a single crystal substrate or a composite substrate, and the size of the substrate 107 may be 2 inches to 8 inches.

[0083] Exemplarily, the substrate 107 is a Si substrate or a sapphire substrate.

[0084] See also Figure 2 The transistor may further include a passivation layer 108 , wherein the passivation layer 108 covers the barrier layer 106 .

[0085] By way of example, the passivation layer 108 may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride passivation layer.

[0086] See also Figure 2 The transistor may further include a gate 109 , a source 110 and a drain 111 .

[0087] The gate 109 is located on the passivation layer 108 .

[0088] The transistor is a high electron mobility transistor (HEMT). Current can be transmitted between the drain and the source through a conductive channel formed by a two-dimensional electron gas. The gate is connected to the gallium nitride structure through a gate dielectric layer. By controlling the gate voltage, the conduction and cutoff of the transistor conductive channel can be controlled.

[0089] In one example, the source electrode 110 and the drain electrode 111 pass through the passivation layer 108 and the barrier layer 106 , respectively, and are connected to the channel layer 105 .

[0090] In another example, the source 110 and the drain 111 respectively pass through the passivation layer 108 and are connected to the barrier layer 106 .

[0091] Figure 4 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure. Figure 4 The method steps include:

[0092] 301. Prepare a buffer layer, wherein the buffer layer is an AlN buffer layer.

[0093] 302. A stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer are sequentially fabricated on the buffer layer, wherein the stress buffer layer is an AlGaN stress buffer layer, and the low-temperature GaN layer is an oxygen-doped GaN layer.

[0094] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a stress buffer layer, the buffer layer and the stress buffer layer are used to improve the epitaxial growth stress of the transistor, however, due to the difference in lattice constants between AlN and AlGaN, stress and dislocation still exist in AlGaN; for this reason, the transistor provided by the embodiment of the present disclosure also includes a low-temperature GaN layer and a high-temperature GaN layer, wherein, due to the relatively low growth temperature of the low-temperature GaN layer, the atomic plane diffusion ability is weak, and three-dimensional island crystal nuclei will appear on the surface of AlGaN, and the three-dimensional island crystal nuclei will make the growth direction of the stacking dislocation turn from perpendicular to the top surface of AlGaN to parallel to the top surface of AlGaN, thereby avoiding the stacking dislocation from entering the subsequent film layer growth. The low-temperature GaN layer is doped with oxygen, oxygen exists at the interface of AlGaN and GaN, Al is bonded with oxygen and nitrogen to form AlON, and polarity regulation can be achieved, so that the growth interface of the low-temperature GaN layer is completely transformed into a unified Ga metal polarity plane, which is conducive to reducing the grain boundary density. The high-temperature GaN layer can fill the low-temperature GaN layer on the one hand, and can also block defects and control stress on the other hand. The low-temperature GaN layer and the high-temperature GaN layer can improve the epitaxial quality of the transistor and optimize the voltage resistance and other electrical properties of the transistor.

[0095] Figure 5 A flow chart of a method for manufacturing a transistor provided in an embodiment of the present disclosure, see Figure 5 , the method flow chart includes:

[0096] 401. Provide a substrate.

[0097] In the embodiment of the present disclosure, the substrate 107 may be a single crystal substrate or a composite substrate, and the size of the substrate 107 may be 2 inches to 8 inches.

[0098] Exemplarily, the substrate 107 is a Si substrate or a sapphire substrate.

[0099] Optionally, the method may further include:

[0100] The substrate is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber for nitride epitaxy, hydrogen is introduced as a carrier gas and the substrate temperature is raised to 1000° C. to 1100° C. to decompose the oxide on the substrate surface at high temperature to obtain a clean surface.

[0101] For example, a silicon substrate is placed in MOCVD, the substrate temperature is raised to 1050°C, and treated in a H2 atmosphere for 5 to 10 minutes to obtain a clean silicon surface.

[0102] 402. A buffer layer, a stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer are sequentially fabricated on the substrate.

[0103] In the embodiment of the present disclosure, the buffer layer 101 may include a low-temperature AlN sublayer 1101 and a high-temperature AlN sublayer 1102 , wherein the high-temperature AlN sublayer 1102 is located between the low-temperature AlN sublayer 1101 and the stress buffer layer 102 .

[0104] In this implementation, by providing the low-temperature AlN sublayer 1101 and the high-temperature AlN sublayer 1102 , the stress generated by the epitaxial growth is reduced on the basis of reducing the lattice mismatch.

[0105] In the disclosed embodiment, the growth temperature of the low-temperature AlN sublayer 1101 is 700-900°C, and the growth temperature of the high-temperature AlN sublayer 1102 is 900-1100°C.

[0106] Exemplarily, the growth temperature of the low-temperature AlN sublayer 1101 is 800°C, and the growth temperature of the high-temperature AlN sublayer 1102 is 1000°C.

[0107] In the disclosed embodiment, the thickness of the low-temperature AlN sublayer 1101 is 20-50 nm, and the thickness of the high-temperature AlN sublayer 1102 is 100-300 nm.

[0108] Exemplarily, the thickness of the low-temperature AlN sublayer 1101 is 30 nm, and the thickness of the high-temperature AlN sublayer 1102 is 200 nm.

[0109] In the embodiment of the present disclosure, the low temperature AlN sublayer 1101 includes a three-dimensional island structure, and the density of the three-dimensional island structure in the low temperature AlN sublayer 1101 is 5*10 6 ~5*10 9 cm -3 That is, the low-temperature AlN sublayer 1101 is a seed layer, and no thin film is formed.

[0110] For example, the density of the three-dimensional island structure in the low-temperature AlN sublayer 1101 is 10 8 cm -3 .

[0111] In the embodiment of the present disclosure, the high temperature AlN sublayer 1102 covers the low temperature AlN sublayer 1101 , so that the entire buffer layer 101 forms a thin film, providing an AlN layer with a smooth surface.

[0112] In other embodiments, the buffer layer 101 may also include only one AlN sublayer.

[0113] In the embodiment of the present disclosure, the composition of Al in the stress buffer layer 102 is graded.

[0114] Exemplarily, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the Al composition in the stress buffer layer 102 gradually decreases.

[0115] In this implementation, the composition gradient of Al in the stress buffer layer 102 is controlled to change the lattice constant difference between AlN and AlGaN, thereby alleviating the epitaxial growth stress problem.

[0116] For example, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the molar amount of Al in the stress buffer layer 102 decreases from 0.6-0.8 to 0.06-0.08.

[0117] For example, along the direction from the buffer layer 101 to the low-temperature GaN layer 103 , the molar amount of Al in the stress buffer layer 102 decreases from 0.7 to 0.07.

[0118] In the disclosed embodiment, the growth temperature of the stress buffer layer 102 is 1150-1300° C.

[0119] Exemplarily, the growth temperature of the stress buffer layer 102 is 1200° C.

[0120] In the disclosed embodiment, the thickness of the stress buffer layer 102 is 100-300 nm.

[0121] Exemplarily, the thickness of the stress buffer layer 102 is 200 nm.

[0122] In other embodiments, the composition of Al in the stress buffer layer 102 may also remain constant.

[0123] In the disclosed embodiment, the growth temperature of the low-temperature GaN layer 103 is 500-800°C, and the growth temperature of the high-temperature GaN layer 104 is 900-1100°C.

[0124] Exemplarily, the growth temperature of the low-temperature GaN layer 103 is 700° C., and the growth temperature of the high-temperature GaN layer 104 is 1000° C.

[0125] In this implementation, the use of the above temperature to grow the low-temperature GaN layer 103 can form a three-dimensional GaN island structure of good quality, so that the growth direction of the stacking dislocation changes, thereby preventing the stacking dislocation from entering the subsequent film growth. The use of the above temperature to grow the high-temperature GaN layer allows the high-temperature GaN layer to better fill the low-temperature GaN layer, thereby achieving defect blocking and stress control.

[0126] In the disclosed embodiment, the thickness of the low-temperature GaN layer 103 is 15-30 nm.

[0127] Exemplarily, the thickness of the low-temperature GaN layer 103 is 25 nm.

[0128] In this implementation, the low-temperature GaN layer of the above thickness will neither cause abnormality in the entire epitaxial layer due to being too thick, nor conflict with the thickness required for polarity control due to being too thin.

[0129] In the disclosed embodiment, the thickness of the high temperature GaN layer 104 is 100-500 nm.

[0130] Exemplarily, the thickness of the high temperature GaN layer 104 is 300 nm.

[0131] In the embodiment of the present disclosure, the low-temperature GaN layer 103 includes a three-dimensional island structure arranged on the surface of the stress buffer layer 102, and the density of the three-dimensional island structure is 10 8 ~10 9 cm -3 .

[0132] For example, the density of the three-dimensional island structure of the low-temperature GaN layer 103 is 5*10 8 cm -3 .

[0133] After careful comparative experimental analysis, when the density of the three-dimensional island structure of the low-temperature GaN layer is low, subsequent epitaxy will show local growth in multiple locations, and even fog in severe cases; when the density of the three-dimensional island structure of the low-temperature GaN layer is high, the GaN film will quickly connect into a sheet, and the meaning of regulation will be lost. The above three-dimensional island structure density avoids the occurrence of the above problems.

[0134] In the disclosed embodiment, the oxygen flux ratio during the growth of the low-temperature GaN layer 103 is 0.1-0.6 ppm.

[0135] PPM refers to Parts Per Million. Oxygen intake ratio refers to the ratio of oxygen to the total gas intake during the growth process.

[0136] Exemplarily, the oxygen flux ratio during the growth of the low-temperature GaN layer 103 is 0.3 ppm.

[0137] In this implementation, the above-mentioned oxygen intake allows a small amount of oxygen to be introduced into the growth of the low-temperature GaN layer, and the suspended Al at the AlGaN interface will bond with oxygen and nitrogen to form AlON, so that the growth surface of the subsequent low-temperature GaN layer is a unified Ga polarity surface, rather than a mixed polarity surface of Al and Ga, thereby achieving polarity regulation.

[0138] In the embodiment of the present disclosure, the channel layer 105 is a GaN channel layer.

[0139] The channel layer 105 has a thickness of 10-80 nm, for example, 50 nm.

[0140] In the embodiment of the present disclosure, the barrier layer 106 may be a single layer or a composite layer.

[0141] For example, the barrier layer 106 is an AlGaN layer.

[0142] In the embodiment of the present disclosure, the thickness of the barrier layer 106 may be 20-30 nm, for example, 25 nm.

[0143] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer 106 is 0.2-0.3, for example, 0.25.

[0144] In the embodiment of the present disclosure, step 402 may include:

[0145] In the first step, a low-temperature AlN sublayer is grown on the substrate at a growth temperature of 700-900°C.

[0146] The second step is to grow a high-temperature AlN sublayer on the low-temperature AlN sublayer in an environment where the growth temperature is 1150-1300° C.

[0147] The second step is to grow a stress buffer layer on the high temperature AlN sublayer at a growth temperature of 1150-1300° C.

[0148] The third step is to grow a low-temperature GaN layer on the stress buffer layer at a growth temperature of 500-800° C.

[0149] The fourth step is to grow a high-temperature GaN layer on the low-temperature GaN layer in an environment where the growth temperature is 900-1100° C.

[0150] The fifth step is to grow a channel layer on the high temperature GaN layer at a growth temperature of 1000-1100° C.

[0151] The sixth step is to grow a barrier layer on the channel layer at a growth temperature of 1000-1100° C.

[0152] 403. A passivation layer is formed on the barrier layer.

[0153] By way of example, the passivation layer 108 may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride passivation layer.

[0154] 404. Fabricate a gate on the surface of the passivation layer.

[0155] Exemplarily, step 405 may include:

[0156] A gate metal layer is formed on the surface of the passivation layer; and the gate metal layer is patterned to obtain a gate.

[0157] 405. Make source, drain and drain.

[0158] In one example, the source electrode and the drain electrode respectively pass through the passivation layer and the barrier layer and are connected to the channel layer.

[0159] Exemplarily, step 405 may include:

[0160] A source groove and a drain groove are respectively formed on the passivation layer and the barrier layer, and both the source groove and the drain groove are connected to the channel layer; a source and a drain are respectively formed in the source groove and the drain groove.

[0161] In another example, the source and the drain respectively pass through the passivation layer and are connected to the barrier layer.

[0162] Exemplarily, step 405 may include:

[0163] A source groove and a drain groove are respectively opened on the passivation layer, and both the source groove and the drain groove are connected to the barrier layer; a source and a drain are respectively made in the source groove and the drain groove.

[0164] The prepared wafers are processed through various process flows to produce power device chips, and then the corresponding resistance, capacitance, current and voltage tests are carried out.

[0165] In the embodiments disclosed herein, in order to achieve high-quality GaN growth on a heterogeneous substrate and prevent the problems of uneven thickness and poor stability caused by warping of the bottom layer during MOCVD high-temperature growth, a multi-layer buffer layer and high and low temperature GaN layers are combined together to improve the uniformity and consistency of growth.

[0166] In addition, stacking dislocations are blocked through interface transformation and lattice gradient, which reduces the generation of leakage channels and facilitates stress management. The layered processing of heterogeneous substrates and heterojunction epitaxial layers reduces the low grain boundary density. Dislocation blocking is achieved through sequential growth of the interface, and the transformed interface state also improves the periodic structure of the lattice.

[0167] Figure 6 It is a schematic diagram of leakage current in a transistor provided by the related art. Figure 7 Schematic diagram of leakage current in a transistor provided by an embodiment of the present disclosure.

[0168] exist Figure 6 and Figure 7 In the figure, the horizontal axis is voltage, the unit is V, the vertical axis is current, the unit is A, the upper curve is the leakage current curve, and the lower curve is the gate leakage current curve.

[0169] from Figure 6 and Figure 7 It can be seen that the withstand voltage of the transistor provided by the related art is 1050V, and the withstand voltage of the transistor provided by the embodiment of the present disclosure is 1180V.

[0170] Figure 8 FIG. 1 is a schematic diagram comparing dynamic resistance tests of transistors provided by related technologies and transistors provided by embodiments of the present disclosure. Figure 8 As shown, the dynamic resistance of the transistor (original structure) provided by the related art is 1.28 ohms, and the dynamic resistance of the transistor (new structure) provided by the embodiment of the present disclosure is 1.16 ohms.

[0171] See also Figure 6 to Figure 8 After testing, it was found that the breakdown voltage of the new structure used in the embodiments of the present disclosure was equivalent to or better than that of the comparative structure, the gate leakage current was 1 to 2 orders of magnitude smaller, and the on-state voltage and dynamic resistance performance were better.

[0172] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: A buffer layer (101), a stress buffer layer (102), a low-temperature GaN layer (103), a high-temperature GaN layer (104), a channel layer (105) and a barrier layer (106), wherein the stress buffer layer (102), the low-temperature GaN layer (103), the high-temperature GaN layer (104), the channel layer (105) and the barrier layer (106) are sequentially stacked on the buffer layer (101); The buffer layer (101) is an AlN buffer layer, the stress buffer layer (102) is an AlGaN stress buffer layer, and the low-temperature GaN layer (103) is an oxygen-doped GaN layer.

2. The transistor according to claim 1, characterized in that The growth temperature of the low-temperature GaN layer (103) is 500-800°C, and the growth temperature of the high-temperature GaN layer (104) is 900-1100°C.

3. The transistor according to claim 1, characterized in that The thickness of the low-temperature GaN layer (103) is 15-30 nm.

4. The transistor according to any one of claims 1 to 3, characterized in that: The low-temperature GaN layer (103) comprises a three-dimensional island structure arranged on the surface of the stress buffer layer (102), and the density of the three-dimensional island structure is 10 8 ~10 9 cm -3 .

5. The transistor according to any one of claims 1 to 3, characterized in that: When the low-temperature GaN layer (103) is grown, the oxygen intake ratio is 0.1-0.6 ppm.

6. The transistor according to any one of claims 1 to 3, characterized in that: Along the direction from the buffer layer (101) to the low-temperature GaN layer (103), the Al component in the stress buffer layer (102) gradually decreases.

7. The transistor according to any one of claims 1 to 3, characterized in that: The buffer layer (101) comprises a low-temperature AlN sublayer (1101) and a high-temperature AlN sublayer (1102), wherein the high-temperature AlN sublayer (1102) is located between the low-temperature AlN sublayer (1101) and the stress buffer layer (102).

8. A method for manufacturing a transistor, characterized in that: The method comprises: Making a buffer layer, wherein the buffer layer is an AlN buffer layer; A stress buffer layer, a low-temperature GaN layer, a high-temperature GaN layer, a channel layer and a barrier layer are sequentially formed on the buffer layer. The stress buffer layer is an AlGaN stress buffer layer, and the low-temperature GaN layer is an oxygen-doped GaN layer.

9. The method according to claim 8, characterized in that The method comprises: manufacturing the low-temperature GaN layer and the high-temperature GaN layer, comprising: Growing the low-temperature GaN layer on the stress buffer layer at a growth temperature of 500 to 800° C.; The high temperature GaN layer is grown on the low temperature GaN layer in an environment where the growth temperature is 900-1100° C.

10. The method according to claim 8 or 9, characterized in that: The oxygen intake ratio during the growth of the low-temperature GaN layer is 0.1-0.6 ppm.

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