A vertical heterojunction transistor and a method for manufacturing the same

Abstract

The present application provides a vertical heterogeneous transistor and a manufacturing method thereof, wherein the transistor comprises a drift layer, a heterogeneous structure layer, a trench gate and a current control layer. The heterogeneous structure layer is located on the drift layer and has a two-dimensional electron gas. The trench gate runs through the heterogeneous structure layer. The current control layer is located between the drift layer and the heterogeneous structure layer, and comprises a current blocking region, a high resistance region and a current aperture region. Under preset conditions, the channel formed along the sidewall of the trench gate is connected to the current aperture region, and the current blocking region and the high resistance region block the passage of current; and the high resistance region also introduces a depletion region on the side of the trench gate close to the drift layer to reduce the electric field strength on the side of the trench gate close to the drift layer. The high resistance region in the transistor can improve the electric field concentration phenomenon on the side of the trench gate close to the drift layer, increase the breakdown voltage of the transistor, and can also realize the shutdown of the transistor with other structures, and reduce the gate leakage current of the transistor. The manufacturing method is simple in process and compatible with traditional processes.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices and relates to a vertical heterojunction transistor and a method for manufacturing the same. Background Art

[0002] Power device is a semiconductor switching device. An ideal power device needs to have a small on-resistance and a high blocking voltage when turned off. A typical GaN power device is a high electron mobility transistor (HEMT). HEMT uses AlGaN / GaN heterojunction to form a two-dimensional electron gas. It has high electron mobility and can achieve faster switching speeds and higher operating frequencies.

[0003] Since HEMT is a lateral device, its breakdown voltage is closely related to the gate-drain spacing, and a large chip area is required to achieve a high breakdown voltage. Therefore, from a cost perspective, a vertical structure is more suitable for making high-voltage power devices. Figure 1 , shows a schematic structural diagram of a GaN current aperture vertical electron transistor (CAVET), the CAVET includes a drain metal 101, a substrate 102 and a drift region 103 stacked in sequence, a current blocking layer 104 and a current aperture 105 formed in the drift region 103, a channel material layer 106, a barrier material layer 107, a source metal 108 and a planar gate 109a located on the drift region 103, the CAVET combines the high carrier mobility of a high electron mobility transistor (HEMT) with the advantages of a vertical device structure, because the AlGaN / GaN heterojunction formed by the channel material layer 106 and the barrier material layer 107 can form a two-dimensional electron gas without intentional doping, that is, a natural depletion structure. To further realize an enhanced CAVET structure, please refer to Figure 2 , shows a schematic diagram of the structure of a groove gate CAVET, which usually adopts a groove gate CAVET structure, but this structure has an electric field concentration phenomenon in the edge area of ​​the current blocking layer 104 and the groove gate 109b, which can easily cause the device to break down prematurely, thereby causing work failure.

[0004] Therefore, how to provide a vertical heterojunction transistor and a method for manufacturing the same to improve the breakdown voltage and reliability of the vertical heterojunction transistor has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application.

[0006] Application Contents

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a vertical heterojunction transistor and a method for manufacturing the same, so as to solve the technical problem that the breakdown voltage of the recessed gate CAVET device in the prior art needs to be improved.

[0008] To achieve the above objectives and other related objectives, in a first aspect, a vertical heterojunction transistor is provided, comprising:

[0009] drift layer;

[0010] A heterostructure layer, located on the drift layer, wherein the heterostructure layer has a two-dimensional electron gas;

[0011] A trench gate penetrating the heterostructure layer;

[0012] A current control layer is located between the drift layer and the heterostructure layer, and the current control layer includes a current blocking region, a high resistance region and a current aperture region. Under preset conditions, a channel formed along the sidewall of the trench gate is connected to the current aperture region, and the current blocking region and the high resistance region block the passage of current; and the high resistance region also introduces a depletion region on the side of the trench gate close to the drift layer to reduce the electric field strength on the side of the trench gate close to the drift layer.

[0013] Optionally, in a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region; and the trench gate is adjacent to the high resistance region.

[0014] Optionally, in the direction from the drift layer to the heterostructure layer, a projection of a side of the high resistance region close to the trench gate is located within a range of a projection of a side of the trench gate close to the high resistance region.

[0015] Optionally, the resistivity of the high resistance region is greater than 10 9 Ω·cm; the material of the high resistance region includes at least one of a first ion-doped GaN, a second ion-doped GaN and an insulating compound, the first ion-doped GaN is doped with at least one of N ions, Ar ions and H ions, and the conductivity type of the second ion-doped GaN is different from the conductivity type of the current aperture region.

[0016] Optionally, the width of the current aperture region in a direction perpendicular to the drift layer to the heterostructure layer is in the range of 0.5 μm to 1.5 μm; the doping concentration of the current aperture region is in the range of 10 15 / cm 3 ~10 17 / cm 3 .

[0017] Optionally, the trench gate includes a trench and a gate at least partially filled in the trench, and along the direction from the drift layer to the heterostructure layer, the depth of the trench is less than the sum of the thickness of the heterostructure layer and the thickness of the current control layer.

[0018] In a second aspect, a method for manufacturing a vertical heterojunction transistor is provided, comprising the following steps:

[0019] Formation of drift layer;

[0020] forming a current control layer on the drift layer, wherein the current control layer comprises a current blocking region, a high resistance region and a current aperture region;

[0021] forming a heterostructure layer on the drift layer, wherein the heterostructure layer has a two-dimensional electron gas, and the current control layer is located between the drift layer and the heterostructure layer;

[0022] forming a trench gate on the drift layer, wherein the trench gate penetrates the heterostructure layer;

[0023] Under preset conditions, the channel formed along the sidewall of the trench gate is connected to the current aperture region, and the current blocking region and the high resistance region block the passage of current; and the high resistance region also introduces a depletion region on the side of the trench gate close to the drift layer to reduce the electric field strength on the side of the trench gate close to the drift layer.

[0024] Optionally, in a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region, and forming a current control layer on the drift layer comprises the following steps:

[0025] forming a current blocking region and forming a high resistance region;

[0026] A current aperture region is formed, and in a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region.

[0027] Optionally, the method for forming the current blocking region includes one of an ion implantation method and a groove etching and filling method; the method for forming the high resistance region includes one of an ion implantation method and a groove etching and filling method.

[0028] Optionally, forming the current blocking region and the high resistance region are performed in the same step.

[0029] As described above, the vertical heterojunction transistor of the present application includes a drift layer, a current control layer and a trench gate, wherein the current control layer includes a current blocking region, a high resistance region and a current aperture region. The high resistance region cooperates with other structures in the transistor (for example, the trench gate and the current blocking layer) to realize the shutoff of the current channel in the current aperture region. In addition, the normal shutoff of the transistor is realized, and the high resistance region can also reduce the gate leakage current of the transistor in the off state. In addition, the high resistance region also helps to reduce the electric field strength of the trench gate close to the drift layer side, avoids the occurrence of premature device breakdown caused by the electric field concentration of the trench gate close to the drift layer side, and improves the breakdown voltage strength and reliability of the transistor.

[0030] The method for manufacturing a vertical heterogeneous transistor structure of the present application manufactures a current control layer between a drift layer and a heterogeneous structure layer, wherein the current control layer includes a high resistance region, a current blocking region and a current aperture region, wherein the high resistance region can be manufactured by an ion implantation method or a groove etching and filling method, and the high resistance region can also be manufactured in the same step as the current blocking region, so as to manufacture a vertical heterogeneous transistor structure with effectively improved breakdown voltage and reliability, and the process is simple and compatible with traditional processes, and is suitable for large-scale applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of a planar CAVET in the related art.

[0032] Figure 2 It is a structural schematic diagram of a groove-type CAVET in the related art.

[0033] Figure 3 It is a schematic diagram of the structure of a CAVET with a SIPOS field plate in the related art.

[0034] Figure 4 It is a schematic diagram of the structure of a vertical heterojunction transistor provided in an embodiment of the present application.

[0035] Figure 5 yes Figure 4 Schematic diagram of the on-state of the vertical heterojunction transistor shown in FIG.

[0036] Figure 6 yes Figure 4 Schematic diagram of the off state of the vertical heterojunction transistor shown.

[0037] Figure 7 yes Figure 2 Schematic diagram of the electric field intensity distribution inside the groove-type CAVET shown.

[0038] Figure 8 yes Figure 4 The electric field intensity distribution inside the vertical heterojunction transistor shown in .

[0039] Fig. 9 yes Figure 2 The electron density distribution of the groove-type CAVET in the off state is shown.

[0040] Fig.10 yes Figure 4 The electron density distribution of the vertical heterojunction transistor shown in the figure is in the off state.

[0041] Fig.11 yes Figure 4 A magnified schematic diagram of area A in the middle.

[0042] Fig.12 It is a schematic diagram of the structure of another vertical heterojunction transistor provided in an embodiment of the present application.

[0043] Description of reference numerals:

[0044] 101-drain metal, 102-substrate, 103-drift region, 104-current blocking layer, 105-current aperture, 106-channel material layer, 107-barrier material layer, 108-source metal, 109a-planar gate, 109b-groove gate, 110-SIPOS field plate, 111-silicon dioxide layer, 112-polysilicon gate, 113-gate metal, 114-Al2O3 layer;

[0045] 10-drift layer, 20-current control layer, 21-current blocking region, 22-high resistance region, 23-current aperture region, 30-heterostructure layer, 31-channel layer, 32-barrier layer, 40-trench gate, 41-trench, 42-gate, 43-gate dielectric, 50-substrate, 60-first metal layer, 70-second metal layer. DETAILED DESCRIPTION

[0046] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0047] See also Figures 3 to 12It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In order to solve the technical problems mentioned in the background technology, please refer to Figure 3 , Figure 3 A schematic diagram of the structure of a groove gate CAVET transistor with a semi-insulating polysilicon (SIPOS) field plate is shown. In order to form a SIPOS field plate 110 inside the transistor, it is necessary to first form a deep trench in the drift region 103 of the transistor, and form a SIPOS field plate 110 on the opposite side walls of the deep trench, and then fill the deep trench with a silicon dioxide layer 111 and a polysilicon gate 112. The SIPOS field plate 110 is connected to the gate metal 113 (i.e., gate electrode) of the transistor at one end in the longitudinal direction, and the other end of the SIPOS field plate is connected to the substrate 102 in the longitudinal direction. In addition, a thin Al2O3 layer 114 is also provided between the drift region 103 and the SIPOS field plate 110. When the transistor is in the off state, the uniform potential on the SIPOS field plate 110 and the deep trench can effectively adjust the electric field distribution in the drift region 103, making the longitudinal electric field distribution in the drift region 103 more balanced, while reducing the electric field peak at the junction of the current blocking region 104 and the drift region 103, thereby alleviating the electric field concentration phenomenon inside the groove-type CAVET. However, the structure of the transistor is relatively complex, the preparation process is relatively difficult and the production cost is relatively high, and it is not suitable for practical application and large-scale production.

[0049] Embodiment 1

[0050] The present application provides a vertical heterojunction transistor (hereinafter referred to as "transistor"), see Figure 4 , Figure 4 A schematic structural diagram of a transistor provided in an embodiment of the present application is shown. The transistor includes a drift layer 10 , a heterostructure layer 30 , a trench gate 40 and a current control layer 20 .

[0051] Specifically, the heterostructure layer 30 and the trench gate 40 are located on the drift layer 10, and the heterostructure layer 30 has a two-dimensional electron gas. The trench gate 40 penetrates the heterostructure layer 30. The current control layer 20 is located between the drift layer 10 and the heterostructure layer 30. The current control layer 20 includes a current blocking region 21, a high resistance region 22 and a current aperture region 23. Under preset conditions, the channel formed along the sidewall of the trench gate 40 is connected to the current aperture region 23. The current blocking region 21 and the high resistance region 22 block the passage of current. The high resistance region 22 is also used to introduce a depletion region on the side of the trench gate 40 close to the drift layer 10 to reduce the electric field strength on the side of the trench gate 40 close to the drift layer 10. The preset condition refers to when the gate voltage of the transistor is greater than the threshold voltage.

[0052] In the present application, please refer to Figure 5 , Figure 5 Schematic diagram of the transistor provided in the embodiment of the present application in the on state. Figure 4 When the gate voltage is greater than the threshold voltage, electrons are accumulated along the sidewalls of the trench gate 40 to form a channel. In the direction from the drift layer 10 to the heterostructure layer 30, the channel is electrically connected between the two-dimensional electron gas and the current aperture region 23, so that the current flows into the drift layer 10 through the channel and the current aperture region 23 in sequence, so as to realize the smooth flow of current inside the transistor, thereby realizing the conduction of the transistor. Please continue to refer to Figure 6 , Figure 6 Schematic diagram of the transistor provided by the embodiment of the present application in the off state. When the transistor is in the reverse bias state, the depletion region ( Figure 6 The region indicated by the dotted line in the middle) pinches off the current channel in the current aperture region 23, thereby turning off the transistor.

[0053] In the present application, please refer to Figure 7 and Figure 8 ,in, Figure 7 Shows Figure 2 The electric field strength distribution inside the transistor is shown in the figure. Figure 8 Shows Figure 4 The electric field strength distribution inside the transistor is shown. Figure 7 and Figure 8It can be seen that in the embodiment of the present application, the high resistance region 22 is provided on the side of the trench gate 40 close to the drift layer 10, and a new depletion region is introduced through the high resistance region 22, which effectively reduces the electric field strength on the side of the trench gate 40 close to the drift layer 10 and the electric field strength on the side of the current blocking region 21 close to the drift layer 10 (the electric field strength on the side of the trench gate 40 close to the drift layer 10 is reduced by Figure 7 As shown in the figure, it is higher than 1.54*10 6 Reduce to Figure 8 is close to 0), which helps to reduce the electric field strength on the side of the trench gate 40 close to the drift layer, making the internal electric field distribution of the transistor more uniform and improving the breakdown voltage of the transistor.

[0054] Also, see Fig. 9 and Fig.10 ,in, Fig. 9 Shows Figure 2 The electron density distribution diagram of the transistor in the off state is shown. Fig.10 Shows Figure 4 The electron density distribution of the transistor in the off state is shown. Fig. 9 and Fig.10 It can be seen that in the off state, the current aperture region 23 in the transistor provided in the embodiment of the present application is substantially completely depleted (the electron density is 1.0*10 -14 The amount of the gate current is not enough to form a current on the side of the trench gate 40 close to the drift layer 10, which helps to reduce the gate leakage current. Figure 2 In the transistor structure shown, along the current aperture 105 ( Fig. 9 Not marked, please refer to Figure 2 ) from the center of the current aperture 105 to the edge of the current aperture 105, the electron density gradually decreases (i.e., it is distributed in a step-like manner), which indicates that the electrons are gradually exhausted from the center of the current aperture 105 to the edge of the current aperture 105, resulting in a certain number of electrons still existing at the edge of the current aperture 105, increasing the risk of generating gate leakage current. Therefore, based on the setting of the high resistance region 22, the transistor provided in the embodiment of the present application can effectively reduce the gate leakage current and improve the working performance of the device.

[0055] In the embodiment of the present application, on the one hand, the high resistance region 22, the trench gate 40, and the current blocking region 21 produce a synergistic effect, and the depletion region introduced by the three realizes the pinching off of the current channel in the current aperture region 23, thereby realizing the normal shutdown of the transistor; and at the same time reducing the gate leakage current. On the other hand, the high resistance region 22 is also used to reduce the electric field strength of the trench gate 40 close to the drift layer 10, avoiding the occurrence of premature device breakdown caused by the electric field concentration on the side of the trench gate 40 close to the drift layer 10, and improving the breakdown voltage strength and reliability of the transistor.

[0056] In an optional embodiment, if Figure 4 As shown, in the direction perpendicular to the drift layer 10 to the heterostructure layer 30 , the current aperture region 23 is located between the current blocking region 21 and the high resistance region 22 , and the trench gate 40 is adjacent to the high resistance region 22 .

[0057] In an optional embodiment, if Figure 4 As shown, the trench gate 40 includes a trench 41 and a gate 42 at least partially filled in the trench 41, along the direction from the drift layer 10 to the current control layer 20 (ie Figure 4 The Y direction), the depth of the groove 41 ( Figure 4 (shown in a) is smaller than the thickness of the heterogeneous structure layer 30 ( Figure 4 b) and the thickness of the current control layer 20 ( Figure 4 The sum of (shown in c).

[0058] In the embodiment of the present application, on the one hand, in order to ensure that the transistor can achieve enhancement mode and the transistor can be turned on and off normally, the channel formed along the sidewall of the trench gate 40 must be connected to the current aperture region 23. Therefore, the depth a of the trench 41 needs to be greater than or equal to the thickness b of the heterostructure layer 30 (that is, the trench 41 needs to completely penetrate the heterostructure layer 30 in the direction from the drift layer 10 to the current control layer 20), so as to avoid the presence of other structural layers between the trench gate 40 and the current control layer 20 to hinder the connection between the channel and the current aperture region 23. On the other hand, the depth a of the trench 41 also needs to be less than the sum of the thickness b of the heterostructure layer 30 and the thickness b of the current control layer 20, so that the depletion region formed by the high resistance region 22 and the current blocking region 21 on the side of the trench gate 40 close to the drift layer 10 in the transistor off state can effectively pinch off the current aperture region 23 and the channel, thereby reducing the leakage of the device in the off state. If the depth a of the trench 41 is too large, the trench 41 will further extend into the drift layer 10, causing the electric field distribution at the side wall of the trench gate 40 to change. When the transistor is in the off state, due to the increase in the electric field strength at the side wall of the trench gate 40, a new leakage current path may be formed, thereby affecting the leakage performance of the transistor in the off state.

[0059] Based on the above, it is necessary to control the appropriate depth of the trench 41 in the application so that the high resistance region 22 and the current blocking region 21 located on the side of the trench gate 40 close to the drift layer 10 can form an effective depletion region when the transistor is turned off, thereby effectively pinching off the current aperture region 23 and the channel, and reducing the leakage of the device in the off state. Therefore, the side of the trench gate 40 close to the drift layer 10 can be exactly adjacent to the side of the current control layer 20 away from the drift layer 10 (such as Figure 4 Alternatively, see Fig.11 , Fig.11 A schematic structural diagram of another transistor provided in an embodiment of the present application is shown, where a side of the trench gate 40 close to the drift layer 10 may also be located in the current control layer 20 .

[0060] In an optional embodiment, the trench gate 40 also covers the gate dielectric 43 on the inner wall of the trench 41, and the material of the gate dielectric 43 includes at least one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide. In the direction from the drift layer 10 to the heterostructure layer 30, the thickness of the gate dielectric 43 ranges from 5μm to 50μm (including end values), and can be 15μm, 25μm or 35μm. The formation method of the gate dielectric 43 includes at least one of plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD) and low pressure chemical vapor deposition (LPCVD).

[0061] For an alternative embodiment, see Fig.11 , displayed as Figure 4In the enlarged schematic diagram of the A area, in the direction from the drift layer 10 to the heterostructure layer 30, the projection of one side of the high resistance region 22 close to the trench gate 40 is located within the range of the projection of one side of the trench gate 40 close to the high resistance region 22. When this condition is met, the current can flow along the channel formed along the sidewall of the trench gate 40 to the current aperture region 23. If this condition is not met, the portion of the high resistance region 22 protruding outside the trench gate 40 along the direction perpendicular to the drift layer 10 to the heterostructure layer 30 may hinder the smooth connection between the channel and the current aperture region 23 to a certain extent, thereby affecting the conduction performance of the device. The projection of one side of the high resistance terminal region 22 close to the trench gate 40 is located within the range of the projection of one side of the trench gate 40 close to the high resistance terminal region 22, including the following three situations: the edges of the two do not overlap at all, the edges of the two partially overlap, and the edges of the two completely overlap. For example, as Fig.11 As shown, along the direction perpendicular to the drift layer 10 to the heterostructure layer 30, the width of the high resistance region 22 close to the trench gate 40 is ( Fig.11 h in the figure) is less than or equal to the width of the side of the trench gate 40 close to the high resistance region 22 ( Fig.11 As shown in i). It should be noted that the morphology of the groove 41 and the high resistance region 22 shown in the cross-sectional view in the embodiment of the present application are both rectangular in shape. In actual application, the groove 41 can also be a trapezoidal groove 41, and the high resistance region 22 can also be a trapezoid or a polygon. In the case where the morphology of the groove 41 and the high resistance region 22 in the cross-sectional view are both rectangular, it can be considered that along the direction perpendicular to the drift layer 10 to the heterostructure layer 30, the width of the high resistance region 22 as a whole (rather than a specific surface) is less than or equal to the width of the groove 41 (rather than the bottom of the groove 41).

[0062] In an optional embodiment, if Figure 4 As shown, the width of the high resistance region 22 in the direction perpendicular to the drift layer 10 to the heterostructure layer 30 ( Figure 4 The range of the current aperture region 23 (as shown in d) is 0.5μm to 3μm (including the endpoint values), and can be 1.0μm, 1.5μm, 2.0μm or 2.5μm. Since the current aperture region 23 is formed based on the area between the high resistance region 22 and the current blocking region 21, if the current blocking region 21 has the same structure, if the width d of the high resistance region 22 along the direction perpendicular to the drift layer 10 to the heterostructure layer 30 is too large, it may cause the current aperture region 23 to be too narrow, thereby affecting the conduction performance and reliability of the transistor. In one embodiment, along the direction from the drift layer 10 to the heterostructure layer 30, the width of the current aperture region 23 ( Figure 4The range of (as shown in e) is 0.5 μm to 1.5 μm (including the endpoint values), and can be 0.8 μm or 1.2 μm.

[0063] In an optional embodiment, the thickness of the high resistance region 22 in the direction from the drift layer 10 to the heterostructure layer 30 is ( Figure 4 The range of thickness f of the high resistance region 22 in the above direction is 0.2 μm to 1.5 μm (including the end value), which can be 0.5 μm, 0.8 μm or 1.2 μm. When the thickness f of the high resistance region 22 in the above direction is less than 0.2 μm, the depletion region introduced by the high resistance region 22 has limited improvement on the electric field concentration phenomenon in the area where the trench gate 40 is close to the drift layer 10, and when the thickness f of the high resistance region 22 in the above direction is greater than 1.5 μm, the chip area and cost will be increased, which is not conducive to the practical application of the transistor.

[0064] In an optional embodiment, the resistivity of the high resistance region 22 is greater than 10 9 Under the condition of meeting this resistivity, the high resistance region 22 can effectively prevent the current from passing through the high resistance region 22 and entering the drift layer 10, thereby achieving depletion and reducing current leakage.

[0065] In an optional embodiment, the material of the high resistance region 22 includes at least one of a first ion-doped GaN, a second ion-doped GaN and an insulating compound. Among them, the first ion-doped GaN is doped with at least one of N ions, Ar ions and H ions. The conductivity type of the second ion-doped GaN is different from the conductivity type of the current aperture region 23. For example, the insulating compound includes one of SiO2, SiNx (x>0) and Al2O3. The insulating compounds listed above are relatively common materials in semiconductor devices. In practical applications, other types of insulating compounds can also be used, which are not specifically limited here. Since the formation method of the high resistance region 22 can be an ion implantation method or a trench etching and filling method, the material type of the high resistance region 22 formed by different methods may be different. For example, the material of the high resistance region 22 formed by the ion implantation method can be a first ion-doped GaN, that is, by ion implanting appropriate ions (for example, Ar ions) in the GaN material layer (for example, the material of the drift layer is GaN), the ion implantation area resistance of the GaN material layer meets the resistivity requirement of the high resistance region 22. For another example, the material of the high resistance region 22 formed by the trench etching filling method can be an insulating compound material (e.g., SiO2) or a second ion-doped GaN. For example, when the conductivity type of the current aperture region 23 is N-type, the conductivity type of the second ion-doped GaN is P-type (i.e., P-type GaN), and the P-type GaN can be obtained by intentionally doping P-type ions during the GaN film deposition process, and the P-type ions include Mg ions. In order to meet the resistivity requirements of the high resistance region 22, the doping concentration range of the P-type ions is 10 15 / cm 3 ~10 17 / cm 3 (including the endpoint values).

[0066] In an optional embodiment, the thickness of the drift layer 10 in the direction from the drift layer 10 to the heterostructure layer 30 is in the range of 1 μm to 50 μm (including the end values), and can be 10 μm, 20 μm, 30 μm or 40 μm. The ion doping concentration of the drift layer 10 is in the range of 10 15 / cm 3 ~10 16 / cm 3 (including the endpoint values).

[0067] In an optional embodiment, the doping concentration of the current aperture region 23 is greater than the doping concentration of the drift layer 10, which helps to improve the conduction characteristics of the device. The doping concentration of the current aperture region 23 is in the range of 10 16 / cm 3 ~10 17 / cm 3 (including the endpoint values).

[0068] In an optional embodiment, along the direction from the drift layer 10 to the heterostructure 30, the thickness of the current blocking layer 21 is ( Figure 4 The width of the current blocking layer 21 ( Figure 4 The range of (as shown in h) is 0.5μm to 3μm (including the endpoint values), and can be 0.8μm, 1.5μm or 2.2μm. Under the above conditions, effective blocking of current can be achieved to ensure the working stability of the transistor.

[0069] In an optional embodiment, the transistor further includes a substrate 50, and the substrate 50 is located on a side of the drift layer 10 away from the current control layer 20. The material of the substrate 50 may be a wide bandgap semiconductor material such as GaN and SiC, and the conductivity type of the substrate 50 is the same as the conductivity type of the drift layer 10. In one embodiment, the doping concentration of the substrate 50 is greater than the doping concentration of the drift layer 10. For example, the conductivity type of the substrate 50 is N-type, and the doping concentration range of N-type ions in the substrate 50 is 10 19 / cm 3 ~10 21 / cm 3 (including endpoint values), for example, the N-type ions in the substrate 50 are Si ions.

[0070] In an optional embodiment, the heterostructure layer 30 includes a channel layer 31 and a barrier layer 32, the channel layer 31 is located between the barrier layer 32 and the current control layer 20, wherein the material of the channel layer 31 includes GaN, and the material of the barrier layer 32 includes AlGaN (for example, the composition range of Al in AlGaN is 0.1 to 0.3) to form a GaN-AlGaN heterojunction, thereby forming a two-dimensional electron gas.

[0071] In an optional embodiment, the transistor further includes a first metal layer 60 and a second metal layer 70, wherein the first metal layer 60 penetrates at least a portion of the heterostructure layer 30 (for example, at least intercepts the two-dimensional electron gas in the heterostructure layer 30), and the second metal layer 70 is located on a side of the substrate 50 away from the drift layer 10. In one embodiment, the first metal layer 60 completely penetrates the heterostructure layer 30 to connect with the current blocking region 21. The first metal layer 60 can be used as a source metal of the transistor, and the second metal layer 70 can be used as a drain metal of the transistor.

[0072] In an optional embodiment, the transistor includes a plurality of cell structures, for example, Figure 4The figure shows a cross-sectional view of a single cell structure, in which the current blocking region 21 in each cell structure is arranged around the high resistance region 22, and in this case, each cell has a ring-shaped current aperture region 23. Alternatively, the current blocking region 21, the current aperture region 23 and the high resistance region 22 in each cell structure are arranged in sequence in a direction perpendicular to the drift layer 10 to the heterostructure layer 30, and in this case, each cell has a double current aperture region. That is, the high resistance region 22 provided in the embodiment of the present application can be applied to transistors with different cell structures, and the structure is flexible and diversified to meet the needs of different application scenarios.

[0073] The vertical heterojunction transistor in the embodiment of the present application includes a drift layer, a current control layer and a trench gate, wherein the current control layer includes a current blocking region, a high resistance region and a current aperture region. The high resistance region cooperates with other structures in the transistor (for example, the trench gate and the current blocking layer) to realize the shutoff of the current channel in the current aperture region. In addition, the normal shutoff of the transistor is realized, and the high resistance region can also reduce the gate leakage current of the transistor in the off state. In addition, the high resistance region also helps to reduce the electric field strength of the trench gate close to the drift layer side, avoids the occurrence of premature device breakdown caused by the electric field concentration of the trench gate close to the drift layer side, and improves the breakdown voltage strength and reliability of the transistor.

[0074] Embodiment 2

[0075] The present application also provides a method for manufacturing a vertical heterojunction transistor, which can be used to manufacture the enhanced vertical transistor described in the first embodiment or other suitable transistors. Figure 4 , the preparation method comprises the following steps:

[0076] forming a drift layer 10;

[0077] A current control layer 20 is formed on the drift layer 10, wherein the current control layer 20 includes a current blocking region 21, a high resistance region 22 and a current aperture region 23;

[0078] A heterostructure layer 30 is formed on the drift layer 10, wherein the heterostructure layer 30 has a two-dimensional electron gas, and the current control layer 20 is located between the drift layer 10 and the heterostructure layer 30;

[0079] forming a trench gate 40 on the drift layer 10 , wherein the trench gate 40 penetrates the heterostructure layer 30 ;

[0080] Under preset conditions, the channel formed along the sidewall of the trench gate 40 is connected to the current aperture region 23, and the current blocking region 21 and the high resistance region 22 block the passage of current; and the high resistance region 22 also introduces a depletion region on the side of the trench gate 40 close to the drift layer 10 to reduce the electric field strength on the side of the trench gate 40 close to the drift layer 10.

[0081] In an optional embodiment, the manufacturing method further comprises the following steps:

[0082] Formation of the initial drift layer ( Figure 4 not shown);

[0083] A process is performed on one side of the initial drift layer to form a current control layer 20, and the portion of the initial drift layer that remains after the current control layer 20 is formed serves as the drift layer 10. As will be seen from the following text, during the production process of the current control layer 20, it may be necessary to form the current control layer 20 based on a portion of the initial drift layer, and the structure of the initial drift layer may change before and after the formation of the current control layer 20. Therefore, to avoid ambiguity, a distinction is made here between the initial drift layer and the drift layer 10. Of course, an additional structural layer may also be epitaxially grown on the drift layer 10 to serve as the basis for the formation of the current control layer 20.

[0084] In the optional embodiment, please refer to Figure 4 In a direction perpendicular to the drift layer 10 to the heterostructure layer 30, the current aperture region 23 is located between the current blocking region 21 and the high resistance region 22, and forming the current control layer 20 on the drift layer 10 includes the following steps:

[0085] forming a current blocking region 21 and forming a high resistance region 22;

[0086] A current aperture region 23 is formed. In a direction perpendicular to the drift layer 10 to the heterostructure layer 30 , the current aperture region 23 is located between the current blocking region 21 and the high resistance region 22 .

[0087] In an optional embodiment, the method for forming the current blocking region 21 includes one of an ion implantation method and a groove etching and filling method, and the method for forming the high resistance region 22 includes one of an ion implantation method and a groove etching and filling method. To avoid ambiguity, the "groove etching and filling method" described herein is to first form a groove based on etching of the base layer, and then fill (for example, deposit) the corresponding material in the groove to obtain the current blocking region 21 or the high resistance region 22. For example, the method for forming the current blocking region 21 and the method for forming the high resistance region 22 are both ion implantation methods, or the method for forming the current blocking region 21 and the method for forming the high resistance region 22 are both groove etching and filling methods, or the method for forming the current blocking region 21 is ion implantation methods, and the method for forming the high resistance region 22 is groove etching and filling methods, or the method for forming the current blocking region 21 is groove etching and filling methods, and the method for forming the high resistance region 22 is ion implantation methods.

[0088] In an optional embodiment, when the method for forming the current blocking region 21 is the same as the method for forming the high resistance region 22, the current blocking region 21 and the high resistance region 22 are formed in the same step, which helps to save process steps and reduce process difficulty. Of course, the current blocking region 21 and the high resistance region 22 can also be formed in steps using the same method.

[0089] For example, in one embodiment, when the method for forming the current blocking region 21 and the method for forming the high resistance region 22 are both ion implantation methods, an ion implantation mask layer (not shown) is formed on one side of the initial drift layer and the ion implantation mask layer is patterned to form a first implantation window (not shown) and a second implantation window (not shown), the first implantation window being used to define the pattern of the current blocking region 21, and the second implantation window being used to define the pattern of the high resistance region 22; based on the patterned ion implantation mask layer, one or more ion implantations are performed on a preset area of ​​the initial drift layer to synchronously form the current blocking region 21 and the high resistance region 22.

[0090] For another example, in one embodiment, when the method for forming the current blocking region 21 is an ion implantation method or a groove etching and filling method, and the method for forming the high resistance region 22 is an ion implantation method, the heterogeneous structure layer 30 is formed above the drift layer 10 after the current blocking region 21 is formed; and etching is performed to form a groove 41 that at least penetrates the heterogeneous structure layer 30; a high resistance region injection mask layer (not shown) is formed on the structure layer after the groove 41 is formed, and the high resistance region injection mask layer is patterned to form an injection window (not shown), the injection window exposes at least a portion of the bottom wall of the groove 41, and ion implantation is performed based on the injection window to form a high resistance region 22 located on the side of the groove 41 close to the drift layer 10.

[0091] The method for manufacturing a vertical heterogeneous transistor provided in an embodiment of the present application is to manufacture a current control layer between a drift layer and a heterogeneous structure layer, wherein the current control layer includes a high resistance region, a current blocking region and a current aperture region, wherein the high resistance region can be manufactured by an ion implantation method or a groove etching and filling method, and the high resistance region can also be manufactured in the same step as the current blocking region, so as to manufacture a vertical heterogeneous transistor structure with effectively improved breakdown voltage and reliability, and the process is simple and compatible with traditional processes, and is suitable for large-scale applications.

[0092] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A vertical heterojunction transistor, characterized in that: include: drift layer; A heterostructure layer, located on the drift layer, wherein the heterostructure layer has a two-dimensional electron gas; A trench gate penetrating the heterostructure layer; A current control layer, located between the drift layer and the heterostructure layer, the current control layer comprising a current blocking region, a high resistance region and a current aperture region; Under preset conditions, the channel formed along the sidewall of the trench gate is connected to the current aperture region, and the current blocking region and the high resistance region block the passage of current; and the high resistance region also introduces a depletion region on the side of the trench gate close to the drift layer to reduce the electric field strength on the side of the trench gate close to the drift layer.

2. The vertical heterojunction transistor according to claim 1, characterized in that: In a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region; and the trench gate is adjacent to the high resistance region.

3. The vertical heterojunction transistor according to claim 2, characterized in that: In the direction from the drift layer to the heterostructure layer, a projection of a side of the high resistance region close to the trench gate is located within a range of a projection of a side of the trench gate close to the high resistance region.

4. The vertical heterojunction transistor according to claim 1, characterized in that: The resistivity of the high resistance region is greater than 10 9 Ω·cm; the material of the high resistance region includes at least one of a first ion-doped GaN, a second ion-doped GaN and an insulating compound, the first ion-doped GaN is doped with at least one of N ions, Ar ions and H ions, and the conductivity type of the second ion-doped GaN is different from the conductivity type of the current aperture region.

5. The vertical heterojunction transistor according to claim 1, characterized in that: The width of the current aperture region in the direction perpendicular to the drift layer to the heterostructure layer is in the range of 0.5 μm to 1.5 μm; the doping concentration of the current aperture region is in the range of 10 15 / cm 3 ~10 17 / cm 3 .

6. The vertical heterojunction transistor according to claim 1, characterized in that: The trench gate includes a trench and a gate at least partially filled in the trench. In the direction from the drift layer to the heterostructure layer, the depth of the trench is less than the sum of the thickness of the heterostructure layer and the thickness of the current control layer.

7. A method for manufacturing a vertical heterojunction transistor, characterized in that: The following steps are involved: Formation of drift layer; forming a current control layer on the drift layer, wherein the current control layer comprises a current blocking region, a high resistance region and a current aperture region; forming a heterostructure layer on the drift layer, wherein the heterostructure layer has a two-dimensional electron gas, and the current control layer is located between the drift layer and the heterostructure layer; forming a trench gate on the drift layer, wherein the trench gate penetrates the heterostructure layer; Under preset conditions, the channel formed along the sidewall of the trench gate is connected to the current aperture region, and the current blocking region and the high resistance region block the passage of current; and the high resistance region also introduces a depletion region on the side of the trench gate close to the drift layer to reduce the electric field strength on the side of the trench gate close to the drift layer.

8. The method for manufacturing a vertical heterojunction transistor according to claim 7, characterized in that: In a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region, and forming a current control layer on the drift layer comprises the following steps: forming a current blocking region and forming a high resistance region; A current aperture region is formed, and in a direction perpendicular to the drift layer to the heterostructure layer, the current aperture region is located between the current blocking region and the high resistance region.

9. The method for manufacturing a vertical heterojunction transistor according to claim 8, characterized in that: The method for forming the current blocking region includes one of an ion implantation method and a groove etching and filling method; the method for forming the high resistance region includes one of an ion implantation method and a groove etching and filling method.

10. The method for manufacturing a vertical heterojunction transistor according to claim 8, characterized in that: The current blocking region and the high resistance region are formed in the same step.

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