Fin FET device and manufacturing method thereof

Abstract

The invention discloses a Fin FET device and a manufacturing method thereof, and relates to the technical field of semiconductor devices, and the Fin FET device comprises a semiconductor substrate; the fin-shaped structure is located on the semiconductor substrate and extends in a first direction; the well region is located at the lower part of the fin-shaped structure; the STI structures are located on the semiconductor substrate and located between the adjacent well regions; the gate stack structure extends in a second direction intersecting with the first direction, crosses the upper part of the fin-shaped structure and is in contact with the side wall and the top of the upper part of the fin-shaped structure respectively; the source region and the drain region are located on the upper portion of the fin-shaped structure and located on the two sides of the gate stack structure; wherein the STI structure is provided with an air gap, the air gap extends in the second direction, and the part, located on the surface of the STI structure, of the gate stack structure is opposite to the air gap in the STI structure. According to the invention, the air gap is arranged in the STI structure, so that the parasitic capacitance of the Fin FET device is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a FinFET device and a manufacturing method thereof. Background Art

[0002] FinFET (Fin Field Effect Transistor) is a new type of complementary metal oxide semiconductor (CMOS) transistor, which was developed to deal with the short channel effect encountered by traditional planar transistors at the nanoscale. FinFET is a three-dimensional transistor structure whose design allows the performance and switching characteristics of the transistor to be maintained at a smaller size.

[0003] The basic structure of a FinFET consists of a vertical silicon fin similar to a "fin" surrounded by a gate on both sides and the top. This fin forms the channel of the transistor, with the source and drain located on both sides of the fin. Compared with traditional planar transistors, the gate of a FinFET surrounds more area of ​​the channel, providing better gate control and can turn current on and off more efficiently.

[0004] With the continuous advancement of FinFET technology, reducing the resistance-capacitance delay (RC delay) is the key to improving the speed and efficiency of circuits. In traditional technology, copper (Cu) metal interconnection is usually used to reduce the resistance-capacitance delay problem, but the effect is not obvious. Summary of the invention

[0005] In view of the above problems, the purpose of the present application is to provide a Fin FET device and a manufacturing method thereof, by providing an air gap in the STI structure to reduce the parasitic capacitance of the Fin FET device, thereby effectively solving the resistance-capacitance delay problem.

[0006] According to one aspect of the present invention, a Fin FET device is provided, comprising: a semiconductor substrate; a fin-shaped structure located on the semiconductor substrate, wherein the fin-shaped structure extends in a first direction; a well region located at the bottom of the fin-shaped structure; an STI structure located on the semiconductor substrate and between adjacent well regions; a gate stack structure extending in a second direction intersecting with the first direction, the gate stack structure spanning the upper part of the fin-shaped structure and contacting the sidewall and the top of the upper part of the fin-shaped structure respectively; and a source region and a drain region located on the upper part of the fin-shaped structure and on both sides of the gate stack structure; wherein the STI structure has an air gap, the air gap extends in a second direction intersecting with the first direction, and a portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap in the STI structure.

[0007] Optionally, the air gap extending in the second direction is interrupted by the fin-shaped structure extending in the first direction.

[0008] Optionally, the gate dielectric layer, the STI structure and the air gap in the STI structure constitute a first isolation dielectric between the gate conductor and the substrate; the gate conductor, the first isolation dielectric and the substrate constitute a first parasitic capacitor.

[0009] Optionally, the fin structure extends over a length L in the first direction, the air gap has a width W1 in the first direction, the gate stack structure has a width W2 in the first direction, and W2≦W1≦L / 3.

[0010] Optionally, a dielectric layer is further included, and the dielectric layer is located between adjacent gate conductors; wherein an air gap is formed in the dielectric layer, and the air gap of the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

[0011] Optionally, the dielectric layer and the air gap in the dielectric layer constitute a second isolation dielectric, and the adjacent gate conductor and the second isolation dielectric constitute a second parasitic capacitor.

[0012] According to another aspect of the present invention, a method for manufacturing a Fin FET device is provided, comprising: forming a fin-shaped structure in a semiconductor substrate, wherein the fin-shaped structure extends in a first direction; forming a hard mask layer on the upper portion of the fin-shaped structure, and doping the lower portion of the fin-shaped structure through the hard mask layer to form a well region; forming an STI structure on the semiconductor substrate, wherein the STI structure is located between adjacent fin-shaped structures and exposes the upper portion of the fin-shaped structure; forming an air gap in the STI structure; forming a gate stack structure and a source region and a drain region, wherein the gate stack structure extends in a second direction intersecting with the first direction, the gate stack structure spans the upper portion of the fin-shaped structure and contacts the sidewalls and the top of the upper portion of the fin-shaped structure respectively, and the source region and the drain region are located on the upper portion of the fin-shaped structure and on both sides of the gate stack structure; wherein the air gap extends in the second direction intersecting with the first direction, and a portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

[0013] Optionally, the method for forming an air gap in an STI structure includes: forming a groove in the STI structure, the groove extending from the surface of the STI structure toward the interior thereof, the groove extending in a second direction intersecting the first direction, and being interrupted by a fin-shaped structure extending in the first direction; quickly filling a dielectric layer on the top of the groove to quickly seal the groove to form an air gap.

[0014] Optionally, the method further includes: forming a dielectric layer between adjacent gate conductors; flattening the surface of the dielectric layer using a CMP process; forming a groove in the dielectric layer extending from the surface of the dielectric layer to the interior thereof; and quickly filling the dielectric layer on the top of the groove to quickly seal the groove to form an air gap.

[0015] Optionally, the air gaps of the dielectric layer are located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

[0016] The unexpected technical effects of this application are:

[0017] The embodiment of the present application forms an air gap in the STI structure to reduce the overall dielectric constant of the first isolation medium, thereby reducing the first parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem.

[0018] In a preferred embodiment, by aligning the gate stack structure with the air gap in the STI structure and setting the size of the air gap, the lateral size of the air gap is reduced while the first parasitic capacitance is reduced as much as possible to prevent the size of the air gap from being too large and affecting the firmness and stability of the Fin FET device.

[0019] In a preferred embodiment, the air gap extends in a second direction intersecting the first direction, but the air gap is only located in the STI structure and not in the fin structure, but is separated by the fin structure to prevent the air gap from affecting the fin structure and the well region formed by the fin structure, thereby affecting the conductive performance of the Fin FET device.

[0020] In a preferred embodiment, an air gap is formed in the dielectric layer to reduce the dielectric constant of the entire second isolation dielectric, thereby reducing the second parasitic capacitance, thereby effectively solving the resistance-capacitance delay (RC delay) problem of the FinFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0022] Figure 1a A schematic diagram of a Fin FET device provided in an embodiment of the present application is shown;

[0023] Figure 1b Shows Figure 1a Cross-sectional view along AA direction;

[0024] Figure 1c Shows Figure 1a Schematic diagram omitting the dielectric layer;

[0025] Figure 1d Shows Figure 1c Cross-sectional view along AA direction;

[0026] Figure 2a to Figure 2s 1 is a schematic diagram of the steps of an exemplary method for manufacturing a FinFET device provided in an embodiment of the present application, wherein:

[0027] Figure 2aA schematic diagram showing an embodiment of the present application of forming a first hard mask layer on a semiconductor substrate and forming an auxiliary structure on the first hard mask layer;

[0028] Figure 2b A schematic diagram showing the formation of a second hard mask layer in an embodiment of the present application is shown;

[0029] Figure 2c A schematic diagram showing a sidewall structure formed in an embodiment of the present application is shown;

[0030] Figure 2d A schematic diagram showing the removal of auxiliary structures in an embodiment of the present application is shown;

[0031] Figure 2e A schematic diagram showing the formation of a fin-shaped structure in a semiconductor substrate in accordance with the present application is shown;

[0032] Figure 2f A schematic diagram showing the implementation of the present application to remove the side wall structure;

[0033] Figure 2g A schematic diagram showing the implementation of the present application to form a first dielectric layer;

[0034] Figure 2h A schematic diagram showing the implementation of etching back the first dielectric layer in the present application is shown;

[0035] Figure 2i A schematic diagram showing the implementation of the present application to remove the first hard mask layer on the top of the fin-shaped structure;

[0036] Figure 2j A schematic diagram showing the implementation of the present application to form a third hard mask layer;

[0037] Figure 2k A schematic diagram showing the implementation of removing the first dielectric layer in the present application is shown;

[0038] Figure 2l A schematic diagram showing the formation of a well region at the bottom of a fin-shaped structure in accordance with the present application is shown;

[0039] Figure 2m A schematic diagram showing the implementation of the present application to remove the third hard mask layer on the upper portion of the fin-shaped structure;

[0040] Figure 2n A schematic diagram showing the STI structure formed by the present application is shown;

[0041] Figure 2o A schematic diagram showing the formation of a trench in an STI structure according to the present application;

[0042] Figure 2p A schematic diagram showing the formation of an air gap in the present application is shown;

[0043] Figure 2qA schematic diagram showing the implementation of the present application to form a gate dielectric layer and a gate conductor layer;

[0044] Figure 2r A schematic diagram showing the implementation of the present application to form a gate stack structure and a source region and a drain region;

[0045] Figure 2s A schematic diagram showing the implementation of the present application to form a dielectric layer and to form an air gap in the dielectric layer. DETAILED DESCRIPTION

[0046] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0047] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0048] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0049] Unless otherwise specified below, the various parts of the semiconductor device can be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials that can conduct electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer can be made of SiO2 or a material with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. In addition, the gate dielectric layer can be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for the gate dielectric layer.

[0050] This application may be presented in a variety of forms, some examples of which are described below.

[0051] Figure 1a Schematic diagram of a Fin FET device provided in an embodiment of the present application is shown. Figure 1b Shows Figure 1a Cross-sectional view along AA direction, Figure 1c Shows Figure 1a Schematic diagram omitting the dielectric layer, Figure 1d Shows Figure 1c Cross-sectional view along the AA direction.

[0052] like Figure 1a to Figure 1d As shown, the Fin FET device includes a semiconductor substrate 101 , a fin-shaped structure, an STI (Shallow Trench Isolation) structure 108 , a gate stack structure and a dielectric layer 115 .

[0053] The fin-shaped structure is located on the semiconductor substrate 101 and is disposed in a first direction (eg Figure 1a to Figure 1d In this embodiment, the semiconductor substrate 101 is etched to form a fin structure on the semiconductor substrate 101, that is, the semiconductor substrate 101 and the fin structure are made of the same material, and the semiconductor substrate 101 and the fin structure can be selected from any one of a semiconductor layer, a doped well region, a doped epitaxial semiconductor layer or a combination thereof.

[0054] The lower part of the fin structure is doped to form a well region 107, and a dielectric layer is filled between adjacent well regions 107 to form an STI structure 108, that is, adjacent well regions 107 are isolated by the STI structure 108. The gate stack structure is in a second direction (eg, Figure 1a to Figure 1d The gate stack structure extends across the upper part of the fin-shaped structure and contacts the sidewalls and the top of the upper part of the fin-shaped structure respectively. The upper part of the fin-shaped structure surrounded by the gate stack structure forms the channel region 113 of the device, and the upper part of the fin-shaped structure on both sides of the channel region 113 is doped to form a source region 111 and a drain region 112. The doping type of the source region 111 and the drain region 112 is opposite to the doping type of the well region 107. For example, for an N-type MOSFET, the well region 107 is P-type doped, and the source region 111 and the drain region 112 are N-type doped; for a P-type MOSFET, the well region 107 is N-type doped, and the source region 111 and the drain region 112 are P-type doped. The gate stack structure includes a gate dielectric 109 and a gate conductor 110, and the gate dielectric 109 separates the gate conductor 110 from the fin-shaped structure. The lower surface of the gate stack structure contacts the STI structure 108 . Specifically, the gate dielectric 109 on the lower surface of the gate stack structure contacts the STI structure 108 .

[0055] Furthermore, an air gap 108a is formed in the STI structure 108. In this embodiment, the fin-shaped structure is Figure 1a to Figure 1d The air gap 108a extends in a second direction (eg, Figure 1a to Figure 1d However, it should be noted that the air gap 108a is only located in the STI structure 108 and is not located in the fin structure, but is separated by the fin structure. Figure 1b shown.

[0056] The dielectric layer 115 covers the surface of the gate stack structure (specifically covers the surface of the gate conductor 110), covers the surface of the fin structure, fills between adjacent gate stack structures, and fills between adjacent fin structures. Further, an air gap 115a is formed in the dielectric layer 115. The air gap 115a can be set to one or more, and the air gap 115a is located between adjacent gate conductors 110. Figure 1b In the illustrated embodiment, the air gap 115a is located in the second direction (eg Figure 1a to Figure 1d In the X-axis direction) between the gate conductors 110, although Figure 1b It is not shown in the figure, but it is worth noting that the air gap 115a can also be arranged in the first direction (for example Figure 1a to Figure 1d Between the gate conductors 110 arranged in the Y-axis direction.

[0057] See also Figure 1b and Figure 1d The gate dielectric 109, the STI structure 108, and the air gap 108a in the STI structure 108 constitute the first isolation dielectric between the gate conductor 110 and the semiconductor substrate 101, and the first parasitic capacitor C1 is formed between the gate conductor 110, the gate first isolation dielectric, and the semiconductor substrate 101. In this embodiment, the air gap 108a is formed in the STI structure 108 to reduce the overall dielectric constant of the first isolation dielectric, thereby reducing the first parasitic capacitor C1. The dielectric layer 115 and the air gap 115a in the dielectric layer 115 constitute the second isolation dielectric between adjacent gate conductors 110, and the adjacent gate conductors 110 and the second isolation dielectric between the gate conductors 110 constitute the second parasitic capacitor C2. In this embodiment, the air gap 115a is formed in the dielectric layer 115 to reduce the overall dielectric constant of the second isolation dielectric, thereby reducing the second parasitic capacitor C2. The reduction of the first parasitic capacitor C1 and the second parasitic capacitor C2 helps to solve the problem of resistance-capacitance delay (RC delay) of Fin FET devices.

[0058] Furthermore, the portion of the gate stack structure located on the surface of the STI structure 108 is opposite to the air gap 108a in the STI structure 108. In one embodiment, the fin structure extends along a first direction by a length L, the air gap 108a has a width W1 in the first direction, the gate stack structure has a width W2 in the first direction, and W2≦W1≦L / 3.

[0059] In the embodiment of the present application, by arranging the gate stack structure opposite to the air gap in the STI structure and setting the size of the air gap, the lateral size of the air gap is reduced while the first parasitic capacitance is reduced as much as possible to prevent the size of the air gap from being too large and affecting the firmness and stability of the Fin FET device.

[0060] Corresponding to the Fin FET device provided in the above embodiment, the present application also provides a method for manufacturing the Fin FET device, the manufacturing method comprising:

[0061] Step S10: forming a fin-shaped structure in a semiconductor substrate, wherein the fin-shaped structure extends in a first direction;

[0062] Step S20: forming a hard mask layer on the upper portion of the fin-shaped structure, and doping the lower portion of the fin-shaped structure through the hard mask layer to form a well region;

[0063] Step S30: forming an STI structure between the fin-shaped structures;

[0064] Step S40: forming an air gap in the STI structure;

[0065] Step S50: forming a gate stack structure and a source region and a drain region;

[0066] The air gap and the gate stack structure extend in a second direction intersecting the first direction, and a portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

[0067] Figure 2a to Figure 2s Schematic diagram of each step of an exemplary method for manufacturing a FinFET device provided in an embodiment of the present application. Figure 2a to Figure 2r The manufacturing method of the FinFET device provided in the embodiment of the present application is described in detail.

[0068] like Figure 2a to Figure 2f As shown, in step S10 , a fin-shaped structure 101 a is formed in a semiconductor substrate 101 , wherein the fin-shaped structure 101 a extends in a first direction.

[0069] See also Figure 2a, a first hard mask layer 102 is formed on a semiconductor substrate 101, and an auxiliary structure 103 is formed on the first hard mask layer 102. Specifically, a first hard mask layer 102 is formed on the semiconductor substrate 101, and the first hard mask layer 102 covers the surface of the semiconductor substrate 101. In this embodiment, the semiconductor substrate 101 is single crystal silicon or silicon on insulator (SOI), and the first hard mask layer 102 is a nitride layer (for example, a silicon nitride layer). Next, an auxiliary layer is formed on the first hard mask layer 102, a patterned photoresist is formed on the auxiliary layer by a photolithography process, and the auxiliary layer is etched through the patterned photoresist to form an auxiliary structure 103. Among them, the auxiliary structure 103 is used to define the position of the sidewall structure 104a formed subsequently, so as to finally define the position of the fin-shaped structure 101a. In this embodiment, the material of the auxiliary structure 103 is, for example, polysilicon.

[0070] See also Figure 2b , forming a second hard mask layer 104. Specifically, the second hard mask layer 104 is formed by a deposition process, and the second hard mask layer 104 conformally covers the surface of the first hard mask layer 102 and the top surface and sidewalls of the auxiliary structure 103. In this embodiment, the second hard mask layer 104 is, for example, an oxide layer.

[0071] See also Figure 2c , forming a sidewall structure 104a. Specifically, the second hard mask layer 104 is etched by an etching process, wherein the second hard mask layer 104 on the surface of the first hard mask layer 102 and the second hard mask layer 104 on the top surface of the auxiliary structure 103 are removed, while the second hard mask layer 104 on the sidewall of the auxiliary structure 103 is retained to form a sidewall structure 104a. In this embodiment, for example, the second hard mask layer 104 is etched by a dry etching process. During the dry etching process, the first hard mask layer 102 serves as a protective layer of the semiconductor substrate 101 to prevent over-etching from damaging the surface of the semiconductor substrate 101.

[0072] See also Figure 2d After forming the spacer structure 104a, the auxiliary structure 103 is removed.

[0073] See also Figure 2e , the first hard mask layer 102 and the semiconductor substrate 101 are etched through the spacer structure 104a to form a fin structure 101a in the semiconductor substrate 101. The fin structure 101a includes an upper portion 101a-1 and a lower portion 101a-2, the upper portion 101a-1 is used to form a source region, a drain region, and a channel region between the source region and the drain region of the device; the lower portion 101a-2 is used to form a well region of the device. Further, the fin structure 101a extends in a first direction, for example, Figure 2e The Y-axis direction.

[0074] See also Figure 2f, remove the sidewall structure 104a.

[0075] Furthermore, if Figures 2g to 2m As shown, in step S20, a hard mask layer is formed on the upper portion of the fin-shaped structure 101a, and the lower portion of the fin-shaped structure 101a is doped through the hard mask layer to form a well region 107;

[0076] See also Figure 2g , forming a first dielectric layer 105, the first dielectric layer 105 fills the gaps between the fin-shaped structures 101 a and covers the top of the first hard mask layer 102, and then, a CMP (Chemical Mechanical Planarization) process is used to remove the first dielectric layer 105 on the top of the first hard mask layer 102, and make the top of the first dielectric layer 105 flush with the top of the first hard mask layer 102.

[0077] See also Figure 2h , the first dielectric layer 105 is etched back to remove the first dielectric layer 105 between the upper part 101a-1 of the fin-shaped structure 101a, while the first dielectric layer 105 between the lower part 101a-2 of the fin-shaped structure 101a is retained. In this step, for example, dry etching is used to etch back the first dielectric layer 105, wherein the first hard mask layer 102 serves as a protective layer of the fin-shaped structure 101a to prevent the etch-back process from damaging the fin-shaped structure 101a.

[0078] See also Figure 2i , the first hard mask layer 102 on the top of the fin structure 101 a is removed.

[0079] See also Figure 2j , a third hard mask layer 106 is formed on the top and sidewalls of the upper portion 101a-1 of the fin-shaped structure 101a. Specifically, the third hard mask layer 106 is formed, and the third hard mask layer 106 conformally covers the surface of the first dielectric layer 105 and the top and sidewalls of the exposed fin-shaped structure 101a (i.e., the top and sidewalls of the upper portion 101a-1 of the fin-shaped structure 101a), and then the third hard mask layer 106 on the surface of the first dielectric layer 105 is selectively removed, and the remaining third hard mask layer 106 covers the top and sidewalls of the upper portion 101a-1 of the fin-shaped structure 101a.

[0080] See also Figure 2k , the first dielectric layer 105 is removed to expose the surface of the semiconductor substrate 101 and the sidewall of the lower portion 101 a - 2 of the fin structure 101 a .

[0081] See also Figure 2l, ion implantation is performed on the lower portion 101a-2 of the fin-shaped structure 101a through the third hard mask layer 106 to form a well region 107 in the lower portion 101a-2 of the fin-shaped structure 101a. Further, ion implantation is performed on the exposed surface of the semiconductor substrate 101 at the same time, and the well region 107 is also formed on the surface of the semiconductor substrate 101 and extends from the surface of the semiconductor substrate 101 to a certain depth inward. It is worth noting that for different types of MOS devices, such as PMOS devices and NMOS devices, the doping type of the well region 107 is different, and the doping type of the well region 107 can be set according to the type of MOS device to be formed. For example Figure 2l The doping types of the well regions 107 of the two fin structures 101 a shown may be the same or different.

[0082] See also Figure 2m , the third hard mask layer 106 of the upper portion 101 a - 1 of the fin-shaped structure 101 a is removed to expose the top and sidewalls of the upper portion 101 a - 1 of the fin-shaped structure 101 a.

[0083] Further, see Figure 2n In step S30 , an STI structure 108 is formed between the fin structures 101 a .

[0084] In this step, a second dielectric layer is formed, the second dielectric layer fills the gaps between the fin-shaped structures 101a, and covers the top of the fin-shaped structure 101a. Then, the second dielectric layer on the top of the fin-shaped structure 101a is removed by a CMP process, and the top of the second dielectric layer is flush with the top of the fin-shaped structure 101a. Then, the second dielectric layer is etched back to remove the second dielectric layer between the upper portions 101a-1 of the fin-shaped structure 101a, while the second dielectric layer between the lower portions 101a-2 of the fin-shaped structure 101a is retained. The second dielectric layer between the lower portions 101a-2 of the fin-shaped structure 101a forms an STI structure 108, and the STI structure 108 is located between the lower portions 101a-2 of the adjacent fin-shaped structures 101a, exposing the upper portion 101a-1 of the fin-shaped structure 101a.

[0085] Further, see Figure 2o and Figure 2p In step S40, an air gap 108a is formed in the STI structure.

[0086] See also Figure 2o , a trench 108 a - 1 is formed in the STI structure 108 .

[0087] In this step, for example, a patterned mask layer is formed on the surface of the semiconductor structure formed above, and the surface of the STI structure 108 is etched through the patterned mask layer to form a groove 108a-1 extending from the surface of the STI structure 108 to the inside thereof, wherein, on the surface of the STI structure 108, the groove 108a-1 extends in a second direction intersecting with the first direction, and the second direction is, for example, Figure 2o Furthermore, the trench 108a-1 is interrupted by the fin-shaped structure 101a extending in the first direction.

[0088] like Figure 2p As shown, a third dielectric layer is quickly deposited on the top of the trench 108a-1 to quickly seal the trench 108a-1. After the third dielectric layer is deposited, the top of the trench 108a-1 is covered by the third dielectric layer, and the trench 108a-1 forms an air gap 108a whose top is blocked by the third dielectric layer.

[0089] See also Figure 2q to Figure 2r In step S50, a gate stack structure and a source region and a drain region are formed.

[0090] See also Figure 2q , a gate dielectric layer 109a and a conductor layer 110a are sequentially formed on the semiconductor structure. The gate dielectric layer 109a conformally covers the surface of the semiconductor structure, and the conductor layer 110a covers the surface of the gate dielectric layer 109a.

[0091] See also Figure 2r , the conductor layer 110a is etched to form a gate conductor 110, and the gate dielectric layer 109a is further etched to form a gate dielectric 109, and the gate dielectric 109 is located between the gate conductor 110 and the fin structure 101a and between the gate conductor 110 and the STI structure 108. The gate dielectric 109 and the gate conductor 110 constitute a gate stack structure.

[0092] Furthermore, the gate stack structure on the STI structure 108 is opposite to the air gap 108a in the STI structure 108. The air gap 108a has a width W1 in the first direction, the fin structure 101a extends over a length L in the first direction, the gate stack structure has a width W2 in the first direction, and W2≦W1≦L / 3.

[0093] Next, ion implantation is performed on the fin structure 101 a to form a source region 111 and a drain region 112 in the fin structure 101 a .

[0094] See also Figure 2s , a dielectric layer 115 is formed, and an air gap 115 a is formed in the dielectric layer 115 .

[0095] Specifically, for example, the dielectric layer 115 is formed by a deposition process, and the dielectric layer 115 is planarized by a CMP process. Then, a trench is formed in the dielectric layer 115, and the dielectric layer is quickly filled on the top of the trench so that the trench is quickly sealed to form an air gap 115a in the dielectric layer 115.

[0096] The air gaps 115 a are located between the gate conductors 110 arranged in the first direction and / or between the gate conductors 110 arranged in the second direction.

[0097] The unexpected technical effects of this application are:

[0098] The embodiment of the present application forms an air gap in the STI structure to reduce the overall dielectric constant of the first isolation medium, thereby reducing the first parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem.

[0099] In a preferred embodiment, by aligning the gate stack structure with the air gap in the STI structure and setting the size of the air gap, the lateral size of the air gap is reduced while the first parasitic capacitance is reduced as much as possible to prevent the size of the air gap from being too large and affecting the firmness and stability of the Fin FET device.

[0100] In a preferred embodiment, the air gap extends in a second direction intersecting the first direction, but the air gap is only located in the STI structure and not in the fin structure, but is separated by the fin structure to prevent the air gap from affecting the fin structure and the well region formed by the fin structure, thereby affecting the conductive performance of the Fin FET device.

[0101] In a preferred embodiment, an air gap is formed in the dielectric layer to reduce the dielectric constant of the entire second isolation dielectric, thereby reducing the second parasitic capacitance, thereby effectively solving the resistance-capacitance delay (RC delay) problem of the FinFET device.

[0102] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A Fin FET device, characterized in that: include: Semiconductor substrate; A fin-shaped structure located on a semiconductor substrate, wherein the fin-shaped structure extends in a first direction; A well region located at a lower portion of the fin-shaped structure; The STI structure is located on the semiconductor substrate and between adjacent well regions; a gate stack structure extending in a second direction intersecting the first direction, the gate stack structure spanning an upper portion of the fin-shaped structure and contacting a sidewall and a top of the upper portion of the fin-shaped structure respectively; and The source region and the drain region are located on the upper part of the fin-shaped structure and on both sides of the gate stack structure; The STI structure has an air gap therein, the air gap extends in a second direction intersecting the first direction, and a portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap in the STI structure.

2. The FinFET device according to claim 1, characterized in that: The air gaps extending in the second direction are interrupted by the fin-shaped structures extending in the first direction.

3. The FinFET device according to claim 1, characterized in that: The gate dielectric layer, the STI structure and the air gap in the STI structure constitute a first isolation dielectric between the gate conductor and the substrate; The gate conductor, the first isolation medium and the substrate constitute a first parasitic capacitor.

4. The FinFET device according to claim 1, wherein: The fin structure extends for a length L in the first direction, the air gap has a width W1 in the first direction, the gate stack structure has a width W2 in the first direction, and W2≦W1≦L / 3.

5. The FinFET device according to claim 1, wherein: Also included is a dielectric layer, the dielectric layer being located between adjacent gate conductors; An air gap is formed in the dielectric layer, and the air gap of the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

6. The FinFET device according to claim 5, characterized in that: The dielectric layer and the air gap in the dielectric layer constitute a second isolation dielectric, and the adjacent gate conductor and the second isolation dielectric constitute a second parasitic capacitor.

7. A method for manufacturing a FinFET device, characterized in that: include: forming a fin-shaped structure in a semiconductor substrate, wherein the fin-shaped structure extends in a first direction; Forming a hard mask layer on the upper portion of the fin-shaped structure, and doping the lower portion of the fin-shaped structure through the hard mask layer to form a well region; Forming an STI structure on a semiconductor substrate, wherein the STI structure is located between adjacent fin-shaped structures and exposes an upper portion of the fin-shaped structure; forming an air gap in the STI structure; forming a gate stack structure and a source region and a drain region, wherein the gate stack structure extends in a second direction intersecting the first direction, the gate stack structure spans the upper portion of the fin-shaped structure and contacts the sidewall and the top of the upper portion of the fin-shaped structure respectively, and the source region and the drain region are located on the upper portion of the fin-shaped structure and on both sides of the gate stack structure; The air gap extends in a second direction intersecting the first direction, and a portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

8. The manufacturing method according to claim 7, characterized in that: Methods for forming air gaps in STI structures include: forming a trench in the STI structure, wherein the trench extends from a surface of the STI structure toward an interior thereof, the trench extending in a second direction intersecting the first direction and being interrupted by a fin-shaped structure extending in the first direction; A dielectric layer is quickly filled on the top of the trench to quickly seal the trench and form an air gap.

9. The manufacturing method according to claim 7, characterized in that: Also includes: forming a dielectric layer between adjacent gate conductors; The CMP process is used to flatten the surface of the dielectric layer; forming a groove in the dielectric layer extending from a surface of the dielectric layer to an interior thereof; as well as A dielectric layer is quickly filled on the top of the trench to quickly seal the trench and form an air gap.

10. The manufacturing method according to claim 9, characterized in that: The air gaps of the dielectric layer are located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

Images