Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, an epitaxial layer located on one side surface of the substrate, and a cell structure comprising a plurality of active regions and a gate. The plurality of active regions are arranged at intervals in the epitaxial layer. Each active region comprises an adjacent injection region and a base region, and a source region located in the base region. The source region is in contact with the injection region. The side surface of the active region close to another active region is the side surface of the base region. The gate comprises a common part and a plurality of split gates. The common part and the plurality of split gates are located on the side of the epitaxial layer away from the substrate. The plurality of split gates surround the common part and are connected to the common part. The orthographic projection of one split gate on the epitaxial layer covers a part of the surface of one base region away from the substrate. The doping type of the base region and the injection region is a first doping type. The doping type of the source region, the epitaxial layer and the substrate is a second doping type. The application solves the problem of poor reliability of the planar split gate type semiconductor structure in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Silicon carbide (SiC) as a third-generation semiconductor material, compared with the first generation of silicon material, in the band gap, breakdown field, thermal conductivity, etc. have a significant improvement, can meet the market demand for power devices to the greatest extent, high temperature, high voltage, high frequency characteristics. Gate oxide (Gox) reliability and performance as a barrier to large-scale application of silicon carbide MOSFET, cause the attention of scholars at home and abroad.

[0003] In order to improve the reliability of gate oxide and the switching speed of the device, researchers have proposed a planar split gate type SiC MOSFET, as shown in Figure 1 and Figure 2 The structure includes: substrate 10', epitaxial layer 11', gate 12', injection area 13' and base area 14', source area 15' and gate oxide layer 17', in which Gate Poly (poly-silicon gate) is split into two strips, the end is directly connected to Gate Bus (gate bus), and the two Gate Polys are separated, and the cell design (active area injection) is also a strip (see Figure 2 ). However, with the development of the application market, the size requirement of the cell pitch is getting smaller and smaller, which leads to the continuous compression of the width of Gate Poly. The too narrow Gate poly makes the process more difficult, and the narrower the Gate poly, the higher the risk of fracture, and also weakens the turn-off ability of the gate. As shown in the structure design of Figure 2 , as long as one position fails, it will lead to the turn-off failure of the whole gate, causing serious electric field imbalance problem, resulting in poor reliability of the device. SUMMARY

[0004] The main purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, to at least solve the problem of poor reliability of the planar split gate type semiconductor structure in the prior art.

[0005] In order to achieve the above object, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on one side surface of the substrate; a cell structure comprising a plurality of active regions and a gate, the plurality of active regions are arranged in the epitaxial layer, the active region comprises an adjacent injection region and a base region, and a source region located in the base region, the source region is in contact with the injection region, the side surface of the active region close to another active region is the side surface of the base region, the gate comprises a common part and a plurality of split gates, the common part and the plurality of split gates are located on the side of the epitaxial layer away from the substrate, the plurality of split gates surround the common part and are connected to the common part, the projection of one split gate on the epitaxial layer covers part of the surface of one base region away from the substrate, the doping type of the base region and the injection region is a first doping type, and the doping type of the source region, the epitaxial layer and the substrate is a second doping type.

[0006] Optionally, two split gates correspond to one base region, the projection of one of the two split gates on the epitaxial layer covers part of the surface of the base region away from the substrate, and the projection of the other of the two split gates on the epitaxial layer covers the remaining part of the surface of the base region away from the substrate.

[0007] Optionally, the cell structure further comprises: a JFET region located in the epitaxial layer, the JFET region is located between any two adjacent base regions and contacts each base region respectively, and the projection of the split gate on the epitaxial layer covers part of the surface of the base region away from the substrate, part of the surface of the JFET region away from the substrate and part of the surface of the source region away from the substrate.

[0008] Optionally, the cell structure further comprises: a gate oxide layer located between the gate and the epitaxial layer, the gate oxide layer is located on the surface of the JFET region away from the substrate.

[0009] Optionally, the semiconductor structure further comprises: a dielectric layer located on the surface of the gate away from the epitaxial layer, on the sidewall of the gate and on the surface of the gate oxide layer away from the epitaxial layer; a source metal layer located on the surface of the injection region away from the substrate, on part of the surface of the source region away from the substrate, on the surface of the dielectric layer away from the epitaxial layer and on the sidewall of the dielectric layer; and a drain metal layer located on the surface of the substrate away from the epitaxial layer.

[0010] Optionally, the cell structure is a square cell.

[0011] According to another aspect of the present application, a method for manufacturing the semiconductor structure is provided, comprising: providing a substrate; forming an initial epitaxial layer on one side surface of the substrate; forming a plurality of active regions in at least the initial epitaxial layer, the remaining initial epitaxial layer forming an epitaxial layer, the plurality of active regions being arranged in the epitaxial layer, the active region comprising an adjacent injection region and a base region, and a source region in the base region, the source region being in contact with the injection region, the active region being adjacent to a side surface of another active region, the base region and the injection region being of a first doping type, the source region, the epitaxial layer and the substrate being of a second doping type; forming a gate on a side of the epitaxial layer away from the substrate, the gate comprising a common part and a plurality of split gates, the common part and the plurality of split gates being on the side of the epitaxial layer away from the substrate, the plurality of split gates surrounding the common part and being connected to the common part, a split gate covering a part of a surface of the base region away from the substrate in a projection of the epitaxial layer.

[0012] Optionally, forming a plurality of active regions in at least the initial epitaxial layer comprises: forming a plurality of the active regions in the initial epitaxial layer; stacking a first mask and a second mask on a side of the initial epitaxial layer away from the substrate, and forming a first barrier layer on a surface of the initial epitaxial layer away from the substrate by using a double-layer mask technology, the first barrier layer leaving the initial epitaxial layer exposed between any two adjacent base regions, the first mask being a mask used in a process of forming the base region, and the second mask being a mask used in a process of forming the gate; performing ion implantation on the initial epitaxial layer on which the active regions are formed, with the first barrier layer as a mask, to form a JFET region in the initial epitaxial layer, the initial epitaxial layer on which the JFET region is formed forming the epitaxial layer, a projection of the split gate covering a part of a surface of the base region away from the substrate, a part of a surface of the JFET region away from the substrate, and a part of a surface of the source region away from the substrate; and removing the first barrier layer.

[0013] Optionally, the forming of the plurality of active regions in the initial epitaxial layer comprises: disposing the first mask on a side of the initial epitaxial layer away from the substrate, and forming a second barrier layer on a surface of the initial epitaxial layer away from the substrate by using the first mask, the second barrier layer exposing part of the surface of the initial epitaxial layer; performing ion implantation on the initial epitaxial layer by using the second barrier layer as a mask to obtain a plurality of initial base regions arranged at intervals; performing ion implantation on part of an area of the initial base region away from an adjacent initial base region to form the injection region in the initial base region; performing ion implantation on the initial base region to form the source region adjacent to the injection region in the initial base region, and the remaining initial base region forms the base region; and removing the second barrier layer.

[0014] Optionally, after the first barrier layer is removed, before the gate is formed on the side of the epitaxial layer away from the substrate, the method further comprises: annealing the structure in which the JFET region is formed; and forming a gate oxide layer on part of the surface of the epitaxial layer away from the substrate, the gate oxide layer being located on the surface of the JFET region away from the substrate.

[0015] By using the technical solution of the present application, the mesh-shaped gate structure composed of split gates and a common part is adopted, when a certain split gate is broken, the other split gates can still be connected to the gate bus through the common part, so that the control signal of the gate can be received, and the problem of complete failure of the entire gate does not occur, which avoids the problems of cracking and degradation of effective shutdown capability caused by the size reduction of the split gate, in other words, the present application can greatly overcome the difficulty that the cell pitch cannot be further reduced due to the limitation of the minimum process line width of the gate in the existing planar split gate type technology; at the same time, the present application can also retain the low impedance and high switching speed performance of the planar split gate type semiconductor structure, and ensure the reliability and good device performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0016] The drawings accompanying the specification of the present application form a part thereof, serve to provide further understanding of the present application, and together with the specification explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A cross-sectional structure schematic diagram of a planar split gate type MOSFET in the prior art is shown;

[0018] Figure 2 A top view schematic diagram of a planar split gate type MOSFET in the prior art is shown; Figure 1

[0019] Figure 3 ​A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application is shown;

[0020] Figure 4 It shows Figure 3 A top view schematic diagram of a semiconductor structure;

[0021] Figure 5 It shows Figure 3 Another top view of a semiconductor structure;

[0022] Figure 6 A cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application is shown;

[0023] Figure 7 A schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application is shown;

[0024] Figure 8 A cross-sectional view of the structure obtained after forming an initial epitaxial layer on a substrate according to an embodiment of this application is shown;

[0025] Figure 9 A cross-sectional view of the structure obtained after forming an active region in an initial epitaxial layer according to an embodiment of this application is shown.

[0026] Figure 10 It shows Figure 9 A top-down view;

[0027] Figure 11 A cross-sectional view of the structure obtained after forming a first barrier layer on an initial epitaxial layer according to an embodiment of this application is shown.

[0028] Figure 12 It shows Figure 11 A top-down view;

[0029] Figure 13 A cross-sectional view of the structure obtained after forming the JFET region according to an embodiment of this application is shown;

[0030] Figure 14 It shows Figure 13 A top-down view;

[0031] Figure 15 A cross-sectional view of the structure obtained after forming an initial gate according to an embodiment of this application is shown;

[0032] Figure 16 It shows Figure 15 A top-down view;

[0033] Figure 17A cross-sectional view of a structure after forming a gate electrode is shown according to an embodiment of the present application;

[0034] Figure 18 A cross-sectional view of a structure after forming an initial dielectric layer is shown according to an embodiment of the present application;

[0035] Figure 19 A top view of the structure is shown according to an embodiment of the present application; Figure 18

[0036] Figure 20 A cross-sectional view of a structure after forming a dielectric layer is shown according to an embodiment of the present application;

[0037] Figure 21 A top view of the structure is shown according to an embodiment of the present application; Figure 20

[0038] Figure 22 A cross-sectional view of another semiconductor structure is shown according to an embodiment of the present application.

[0039] In the above drawings, the following reference signs are used:

[0040] 10, substrate; 11, epitaxial layer; 12, gate electrode; 121, common part; 122, split gate; 13, implantation region; 14, base region; 15, source region; 16, JFET region; 17, gate oxide layer; 18, dielectric layer; 19, source metal layer; 20, drain metal layer; 21, initial epitaxial layer; 22, first barrier layer; 23, initial gate oxide layer; 24, initial gate electrode; 25, initial dielectric layer. DETAILED DESCRIPTION

[0041] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0042] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should belong to the scope of protection of the present application.

[0043] ​​It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0044] As introduced in the background, there is a problem of poor reliability of the planar split gate type semiconductor structure in the prior art. To solve the above technical problem, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application.

[0046] Embodiments of the present application provide a semiconductor structure, as shown in Figure 3 and Figure 4 , or as shown in Figure 3 and Figure 5 , the semiconductor structure comprises:

[0047] a substrate 10;

[0048] an epitaxial layer 11 located on one side surface of the substrate 10;

[0049] a cell structure comprising a plurality of active regions and a gate 12, a plurality of the active regions are arranged in the epitaxial layer 11, the active region comprises an adjacent injection region 13 and a base region 14, and a source region 15 located in the base region 14, the source region 15 is in contact with the injection region 13, the side surface of the active region close to another active region is the side surface of the base region 14, the gate 12 comprises a common part 121 and a plurality of split gates 122, the common part 121 and a plurality of the split gates 122 are located on the side of the epitaxial layer 11 away from the substrate 10, a plurality of the split gates 122 surround the common part 121 and are connected with the common part 121, the orthogonal projection of one split gate 122 on the epitaxial layer 11 covers a part of the surface of one base region 14 away from the substrate 10, the doping type of the base region 14 and the injection region 13 is a first doping type, and the doping type of the source region 15, the epitaxial layer 11 and the substrate 10 is a second doping type.

[0050] Specifically, the side surface of the source region 15 is in contact with the side surface of the injection region 13. The side surface of the base region 14 away from the side surface of the injection region 13 is the side surface of the active region to which the base region 14 belongs, and the side surfaces of two adjacent active regions are opposite to each other. The common part 121 is located in the middle of the plurality of split gates 122 and serves to connect any two split gates 122. There are a plurality of base regions 14 in the cell structure, and there are a plurality of split gates 122. The correspondence between the base region 14 and the split gate 122 can be that the projection of the split gate 122 can correspondingly cover the surface of the base region 14 away from the substrate 10; the correspondence between the base region 14 and the split gate 122 can also be that the projections of a plurality of split gates 122 cover the surface of one base region 14 away from the substrate 10, for example, the projections of two split gates 122 correspondingly cover the surface of one base region 14; the correspondence between the base region 14 and the split gate 122 can also be that part of the surface of the base region 14 away from the substrate 10 is covered by the projection of the split gate 122, and part of the surface of the base region 14 away from the substrate 10 is not covered by the projection of the split gate 122.

[0051] Through the embodiment, a plurality of spaced active regions are arranged in the epitaxial layer, the active region includes an injection region, a base region and a source region located in the base region, the epitaxial layer is provided with a gate on the side away from the substrate, the gate includes a common part and a plurality of split gates, the plurality of split gates surround the common part and are connected to the common part, forming a mesh-shaped gate structure, and the projection of one split gate on the epitaxial layer covers part of the surface of one base region. The mesh-shaped gate structure formed by the split gate and the common part in the application can still connect other split gates to the gate bus through the common part when a certain split gate is broken, so that the split gate can receive the control signal of the gate, and the problem of complete failure of the entire gate does not occur. In other words, the application can greatly overcome the difficulty that the cell pitch cannot be further reduced due to the limitation of the minimum process line width of the gate in the existing planar split gate type technology. At the same time, the application can also retain the low impedance and high switching speed performance of the planar split gate type semiconductor structure, and ensure the reliability and good device performance of the semiconductor structure.

[0052] It should be noted that, Figure 3 is a sectional view of the semiconductor structure obtained along the dashed line AA' in Figure 4 and Figure 5 .

[0053] At least part of the ends of the plurality of split gates are connected to the gate bus. Since the common part connects all the split gates, all the split gates can be connected to the gate bus.

[0054] The width of the common part 121 in a predetermined direction is greater than the width of the split gate 122 in the predetermined direction, and the predetermined direction is perpendicular to the extension direction of the split gate 122.

[0055] The person skilled in the art can select any suitable material as the substrate material of the present application according to the actual device requirements, such as a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, an SOI substrate, or a GOI substrate, etc. Similarly, the person skilled in the art can select any suitable material as the epitaxial layer material of the present application according to the actual device requirements, such as silicon, germanium silicon, silicon carbide, silicon nitride, or gallium nitride, etc. The thickness of the epitaxial layer can be 7-14 μm, and the doping concentration of the epitaxial layer can be 1e 14 ~1e 18 cm -3 .

[0056] Exemplarily, the base region is a square injection region, and the doping concentration of the base region can be 1e 14 ~1e 17 cm -3 . The injection region is a square injection region, and the doping concentration of the injection region can be 1e 16 ~1e 19 cm -3 . The source region is a square injection region, and the doping concentration of the source region can be 1e 16 ~1e 19 cm -3 . The longitudinal and lateral spacing of the injection region and the base region can be flexibly adjusted according to the actual load requirements.

[0057] In some embodiments, the materials of the substrate and the epitaxial layer are both silicon carbide (SiC). The semiconductor structure is a planar gate type SiC MOSFET device. The material of the gate can be polysilicon or other semiconductor materials. The material of the split gate and the common part is the same.

[0058] Exemplarily, the thickness of the gate is 0.3-0.6 μm.

[0059] In actual applications, the cell shape of the cell structure can be square, circular, hexagonal, and 8-shaped, etc. In the semiconductor structure of the present application, the cell structure can be multiple. The layout of multiple cell structures can be a field-shaped layout, a pin-shaped layout, and a honeycomb-shaped layout, etc. The spacing of adjacent cells can be adjusted according to the actual load requirements, and has great flexibility.

[0060] In exemplary embodiments of the present application, as shown in Figure 4 and Figure 5 , the cell structure is a square cell. As shown inFigure 4 and Figure 5 As shown, the source region 15 at least partially surrounds the outer periphery of the injection region 13.

[0061] In this application, the cell injection adopts a square structure design. By adjusting the spacing between cells, the load capacity of the device can be adjusted, which provides great flexibility in application.

[0062] This application adopts a design combining square cell and split gate structure, with the split gate surrounding the square cell. This structure retains the low impedance and high switching speed characteristics of planar split gate SiC MOSFET to the greatest extent, while further solving the problem of poor gate reliability caused by the smaller cell pitch and narrower gate.

[0063] Among some alternative solutions, such as Figure 4 As shown, two split gates 122 correspond to one base region 14. The orthographic projection of one of the two split gates 122 onto the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10, while the orthographic projection of the other split gate 122 onto the epitaxial layer 11 covers the remaining portion of the surface of the base region 14 away from the substrate 10. In this embodiment, both split gates are connected to a common portion. When one split gate malfunctions, the gate control signal can be received through the other split gate, preventing the complete failure of the gates corresponding to the channel of that base region, thus further ensuring good reliability of the semiconductor structure.

[0064] In some alternative embodiments, the cell structure further includes: a gate oxide layer 17 located on the surface of the epitaxial layer 11 away from the substrate 10, at least a portion of the surface of the base region 14 away from the substrate 10, and a portion of the surface of the source region 15 away from the substrate 10, wherein the gate 12 is located on at least a portion of the surface of the gate oxide layer 17 away from the epitaxial layer 11. That is, the gate oxide layer 17 exposes at most the surface of the implantation region 13 away from the substrate 10, a portion of the surface of the base region 14 away from the substrate 10, and a portion of the surface of the source region 15 away from the substrate 10, for example, such as... Figure 4 As shown, the gate oxide layer 17 exposes only the surface of the implantation region 13 away from the substrate 10 and the portion of the surface of the source region 15 away from the substrate 10. For example, as... Figure 5 As shown, the gate oxide layer 17 exposes the surface of the implantation region 13 away from the substrate 10, the portion of the source region 15 away from the substrate 10, and the portion of the base region 14 away from the substrate 10.

[0065] According to some other optional embodiments of this application, such as Figure 3 to Figure 5As shown, the cell structure further comprises: a JFET region 16 located in the epitaxial layer 11, the JFET region 16 being located between any two adjacent base regions 14 and contacting each base region 14 respectively, and the split gate 122 covering the part of the surface of the base region 14, the part of the surface of the JFET region 16 and the part of the surface of the source region 15 away from the substrate 10 in the orthogonal projection of the epitaxial layer 11. In this embodiment, by arranging the JFET region between the adjacent base regions, the resistance of the JFET region can be effectively reduced, thereby optimizing the on-resistance of the semiconductor structure.

[0066] In specific applications, the JFET region 16 and the epitaxial layer 11 can have the same or different doping types, and the doping concentration of the JFET region 16 can be greater than, less than or equal to the doping concentration of the epitaxial layer 11.

[0067] Specifically, the part of the base region 14 between the source region 15 and the JFET region 16 away from the substrate forms a channel, and the length of the channel is 0.2-0.8 μm. The doping concentration of the JFET region 16 can be 7.5e 12 ~1.5e 12 cm -3 .

[0068] As shown in Figure 4 and Figure 5 , the gate 12 presents a "net-like" type trace, the split gate 122 between the two lateral source regions 15 (located above the JFET region 16) is separated, the pitch of the split gate 122 is less than the width of the JFET region 16, and the total length of the width of the two split gates 122 plus the pitch therebetween should not be less than the pitch between the left and right source regions 15. The split gate 122 between the two longitudinal source regions 15 is separated, the pitch of the split gate 122 is less than the width of the JFET region 16, and the total length of the width of the two split gates 122 plus the pitch therebetween should not be less than the pitch between the upper and lower source regions 15. The thickness of the split gate 122 is adjusted by the longitudinal height between the two implantation regions 13 and the base region 14.

[0069] Optionally, as shown in Figure 3 to Figure 5As shown, the cell structure further comprises: a gate oxide layer 17 located between the gate 12 and the epitaxial layer 11, the gate oxide layer 17 is located on the surface of the JFET region 16 away from the substrate 10. The gate oxide layer separates the gate from the active region, preventing current from flowing directly from the gate to the active region, ensuring the normal operation of the semiconductor structure; the gate oxide layer and the gate and the active region form a capacitor structure, when the gate voltage changes, the capacitor will store charge, this capacitor effect makes the semiconductor structure has faster response speed, helps to improve the performance of the semiconductor structure; another important role of the gate oxide layer is to control the conduction channel of the semiconductor structure through the electric field, when a sufficient voltage is applied to the gate, a conduction channel will be formed under the gate oxide layer, allowing current to flow from the source to the drain, by adjusting the gate voltage, the conductivity of the channel can be controlled, thereby realizing the switch control of the semiconductor structure.

[0070] In a specific embodiment, the thickness of the gate oxide layer is 300-800 angstroms.

[0071] The material of the gate oxide layer includes but is not limited to: silicon oxide, high-K dielectric layer, silicon nitride, and aluminum oxide, etc.

[0072] As shown in Figure 3 to Figure 5 The orthographic projection of the gate 12 on the epitaxial layer 11 is located in the orthographic projection of the gate oxide layer 17 on the epitaxial layer 11, that is, the gate oxide layer 17 is also located on at least part of the surface of the base region 14 away from the substrate 10 and part of the surface of the source region 15 away from the substrate 10.

[0073] The thickness of the gate oxide layer located on the surface of the JFET region 16 away from the substrate 10 can be greater than the thickness of the gate oxide layer at other positions, which can further increase the reliability of the gate oxide layer.

[0074] Optionally, as shown in Figure 6 The semiconductor structure further comprises: a dielectric layer 18 located on the surface of the gate 12 away from the epitaxial layer 11, on the sidewall of the gate 12, and on the surface of the gate oxide layer 17 away from the epitaxial layer 11; a source metal layer 19 located on the surface of the implantation region 13 away from the substrate 10, on part of the surface of the source region 15 away from the substrate 10, on the surface of the dielectric layer 18 away from the epitaxial layer 11, and on the sidewall of the dielectric layer 18; a drain metal layer 20 located on the surface of the substrate 10 away from the epitaxial layer 11.

[0075] In the embodiment, the medium layer functions to isolate the gate and the source metal layer, and also functions to protect the gate, the gate oxide layer and the active region; the source metal layer is in contact with the source region and the injection region respectively to form an ohmic contact, so as to reduce the contact resistance of the semiconductor structure, reduce the power loss of the semiconductor structure and improve the efficiency of the semiconductor structure.

[0076] Specifically, the thickness of the medium layer can be 0.7-1.4 μm. The material of the medium layer includes but is not limited to SIOF, TEOS, MSQ, BPSG and other low dielectric constant materials or a combination thereof. In the present application, a combination of BPSG and TEOSD is used as the material of the medium layer.

[0077] The material of the source metal layer and the drain metal layer is independently selected from one or more of titanium, nickel, silver, aluminum, copper, palladium and gold and the like. The thickness of the source metal layer can be 3-6 μm. The thickness of the drain metal layer can be 1-3 μm.

[0078] The semiconductor structure of the present application can be a silicon carbide MOSFET power device, in particular a planar silicon carbide MOSFET power device.

[0079] Figure 7 is a flow chart of the manufacturing method of the semiconductor structure according to the embodiment of the present application. As shown in Figure 7 , the method comprises the following steps:

[0080] Step S201, as shown in Figure 8 , a substrate 10 is provided;

[0081] Step S202, an initial epitaxial layer 21 is formed on one side surface of the substrate 10 to obtain a structure as shown in Figure 8

[0082] Step S203, as shown in Figure 13 and Figure 14 , a plurality of active regions are formed in the initial epitaxial layer 21, the remaining initial epitaxial layer 21 forms an epitaxial layer 11, and the plurality of active regions are arranged in the epitaxial layer 11, the active region comprises an injection region 13 and a base region 14 adjacent to each other and a source region 15 in the base region 14, the side surface of the active region close to another active region is the side surface of the base region 14, the base region 14 and the injection region 13 are of a first doping type, and the source region 15, the epitaxial layer 11 and the substrate 10 are of a second doping type;

[0083] ​Specifically, the side of the source region 15 contacts the side of the injection region 13. The side of the base region 14 away from the injection region 13 serves as the side of its corresponding active region, and the sides of two adjacent active regions face each other.

[0084] Step S204, as follows Figure 17 As shown, a gate 12 is formed on the side of the epitaxial layer 11 away from the substrate 10, and the orthographic projection of the gate on the epitaxial layer is shown in the figure. Figure 4 or Figure 5 As shown, the gate 12 includes a common portion 121 and a plurality of split gates 122. The common portion 121 and the plurality of split gates 122 are located on the side of the epitaxial layer 11 away from the substrate 10. The plurality of split gates 122 surround the common portion 121 and are all connected to the common portion 121. The orthographic projection of one of the split gates 122 on the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10.

[0085] Specifically, the common portion 121 is located in the middle of the plurality of split gates 122, serving to connect any two of the split gates 122. There are multiple base regions 14 and multiple split gates 122 in the cell structure. The correspondence between the base regions 14 and the split gates 122 can be as follows: the orthographic projection of each split gate 122 can cover the surface of the base region 14 away from the substrate 10 in a one-to-one correspondence; the correspondence between the base regions 14 and the split gates 122 can also be as follows: the orthographic projections of multiple split gates 122 cover the surface of one base region 14 away from the substrate 10, for example, the orthographic projections of two split gates 122 correspondingly cover the surface of one base region 14; the correspondence between the base regions 14 and the split gates 122 can also be as follows: the portion of the base region 14 away from the substrate 10 is covered by the orthographic projection of the split gates 122, while the portion of the base region 14 away from the substrate 10 is not covered by the orthographic projection of the split gates 122.

[0086] Through the embodiment, a substrate is provided first, then an initial epitaxial layer is formed on one side surface of the substrate, and a plurality of spaced active regions are formed in the initial epitaxial layer, the initial epitaxial layer with the active regions forms an epitaxial layer, the active regions include an adjacent injection region, a base region and a source region located in the base region, and a gate is formed on a side of the epitaxial layer away from the substrate, the gate includes a common part and a plurality of split gates, the plurality of split gates surround the common part and are connected with the common part, forming a mesh-shaped gate structure, and a projection of one split gate on the epitaxial layer covers one base region away from the part of the surface. The mesh-shaped gate structure formed by the split gates and the common part in the application, when a certain split gate breaks, other split gates can still be connected to the gate bus through the common part, thereby receiving the control signal of the gate, and the problem of complete failure of the entire gate does not occur, which avoids the problems of cracking and effective shutdown capability degradation caused by the size reduction of the split gate, in other words, the application can greatly overcome the difficulty that the cell pitch cannot be further reduced due to the limitation of the minimum process line width of the gate in the existing planar split gate type technology; at the same time, the application can also retain the low impedance and high switching speed performance of the planar split gate type semiconductor structure, ensuring the reliability and good device performance of the semiconductor structure.

[0087] In an alternative, at least the initial epitaxial layer is formed with a plurality of active regions, including: as shown in Figure 8 、 Figure 9 and Figure 10 , a plurality of active regions are formed in the initial epitaxial layer 21; as shown in Figure 9 、 Figure 10 、 Figure 11 and Figure 12 , a first mask and a second mask are stacked on a side of the initial epitaxial layer 21 away from the substrate 10, and a double-layer mask technology is used to form a first barrier layer 22 on the surface of the initial epitaxial layer 21 away from the substrate 10, the first barrier layer 22 exposes the initial epitaxial layer 21 between any two adjacent base regions 14, the first mask is a mask used in the process of forming the base region 14, and the second mask is a mask used in the process of forming the gate 12; as shown in Figure 11 、 Figure 12 、 Figure 13 and Figure 14As shown, the initial epitaxial layer 21 in which the active region is formed is subjected to ion implantation with the first barrier layer 22 as a mask to form a JFET region 16 in the initial epitaxial layer 21, and the initial epitaxial layer 21 in which the JFET region 16 is formed forms the epitaxial layer 11, and the split gate 122 covers the part of the surface of the base region 14, the part of the surface of the JFET region 16 and the part of the surface of the source region 15 away from the substrate 10 in the orthogonal projection of the epitaxial layer 11; and the first barrier layer 22 is removed.

[0088] In the embodiment, the mask of the gate and the mask of the base region are reused, the precise ion implantation of the JFET region is achieved through the double-layer mask technology, the resistance of the JFET region can be effectively reduced without affecting the carrier concentration of other regions, thereby optimizing the on-resistance of the device and reducing the power consumption of the device; and the above effects can be achieved without increasing additional masks, thereby saving the cost of the manufacturing process.

[0089] In the process of forming the first barrier layer, a first sub-barrier layer can be formed above the base region through the first mask, and a second sub-barrier layer can be formed above the gate region through a second mask, the first sub-barrier layer and the second sub-barrier layer constitute the first barrier layer, and the injection window left by the first barrier layer forms the window of the JFET region. The total thickness of the first barrier layer is between 2.5 and 5 μm.

[0090] In addition, a multi-gradient implantation is adopted in the process of ion implantation to form the JFET region.

[0091] In an optional embodiment, a plurality of active regions are formed in the initial epitaxial layer, including: disposing the first mask on the side of the initial epitaxial layer away from the substrate, and forming a second barrier layer on the surface of the initial epitaxial layer away from the substrate by using the first mask, so that part of the surface of the initial epitaxial layer is exposed; and performing ion implantation on the initial epitaxial layer with the second barrier layer as a mask to obtain a plurality of initial base regions arranged at intervals; performing ion implantation on part of the region of the initial base region away from the adjacent initial base region to form the injection region in the initial base region; performing ion implantation on the initial base region to form the source region adjacent to the injection region in the initial base region, and the remaining initial base region forms the base region, and the source region is on the side of the injection region close to the adjacent active region; and removing the second barrier layer. The first mask can be used to achieve precise ion implantation of the initial base region, and ensure the position accuracy of the initial base region. Then, the ion implantation is performed on the initial base region to obtain the injection region and the source region, and the remaining initial base region forms the base region.

[0092] Specifically, the process of forming the implantation region and the process of forming the source region can be achieved by forming a blocking layer through a mask.

[0093] According to some embodiments of the present application, after the first blocking layer is removed, before the gate is formed on the side of the epitaxial layer away from the substrate, the method further comprises: annealing the structure formed with the JFET region; and forming a gate oxide layer on the surface of the epitaxial layer away from the substrate, the gate oxide layer being located on the surface of the JFET region away from the substrate. In the embodiments, through high-temperature annealing, the implanted ions can be activated and the lattice damage in the ion implantation process can be repaired. By forming the gate oxide layer, the gate is separated from the active region, preventing the current from directly flowing from the gate to the active region, and ensuring the normal operation of the semiconductor structure; the gate oxide layer forms a capacitor structure with the gate and the active region, when the gate voltage changes, the capacitor stores charges, and the capacitor effect makes the semiconductor structure have a faster response speed, which helps to improve the performance of the semiconductor structure; another important role of the gate oxide layer is to control the conduction channel of the semiconductor structure through the electric field, when a sufficient voltage is applied to the gate, a conduction channel is formed under the gate oxide layer, allowing the current to flow from the source to the drain, and by adjusting the gate voltage, the conductivity of the channel can be controlled, thereby realizing the switching control of the semiconductor structure.

[0094] Specifically, the annealing temperature can be controlled between 1700℃ and 1800℃, and the annealing time can be controlled between 30min and 60min.

[0095] In some embodiments, the gate oxide layer can be formed by thermal oxidation of the epitaxial layer, or can be formed by deposition.

[0096] In addition, after the gate oxide layer is formed on the surface of the epitaxial layer away from the substrate, the method further comprises: annealing the structure formed with the gate oxide layer in a nitrogen-containing atmosphere, the annealing temperature being between 1000℃ and 1100℃, and the annealing time being between 30min and 60min. The nitrogen-containing atmosphere helps to reduce the interface state defects between the epitaxial layer and the gate oxide layer.

[0097] After the gate is formed on the side of the epitaxial layer away from the substrate, the method further comprises: forming an initial dielectric layer on the exposed surface of the gate, the exposed surface of the gate oxide layer, and the exposed surface of the active region away from the substrate by deposition; etching the initial dielectric layer so that the surface of the implantation region away from the substrate and part of the surface of the source region away from the substrate are exposed, and the remaining initial dielectric layer forms a dielectric layer; and Figure 20 、 Figure 21 and Figure 22As shown, metal deposition is performed on the exposed surface of the dielectric layer 18, the surface of the injection region 13 away from the substrate 10, and part of the surface of the source region 15 away from the substrate 10 to form a source metal layer 19; and metal deposition is performed on the surface of the substrate 10 away from the epitaxial layer 11 to form a drain metal layer 20.

[0098] Specifically, the gate oxide layer and the dielectric layer can be formed synchronously or in steps. In one embodiment, as shown in Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 and Figure 22 As shown, first, an initial gate oxide layer 23 is formed on the surface of the active region away from the substrate 10 and on the surface of the JFET region 16 away from the substrate 10; the second mask is used to form an initial gate electrode 24 on the surface of the initial gate oxide layer 23 away from the epitaxial layer 11; part of the initial gate electrode 24 is removed to obtain the gate electrode 12; the initial dielectric layer 25 is formed on the exposed surface of the gate electrode 12 and on the exposed surface of the initial gate oxide layer 23; part of the initial gate oxide layer 23 and the initial dielectric layer 25 are removed so that the surface of the injection region 13 away from the substrate 10 and part of the surface of the source region 15 away from the substrate 10 are exposed, and the remaining initial dielectric layer 25 forms the dielectric layer 18, and the remaining initial gate oxide layer 23 forms the gate oxide layer 17.

[0099] In one exemplary embodiment, the first doping type is P-type, and the second doping type is N-type. The injected N-type carriers are mainly elements of group V, such as N, P, As, etc., and the injected P-type carriers are mainly elements of group III, such as B, Al, In, etc. The injection of N-type carriers and P-type carriers can be one-time or multiple-time injection, and the energy and dose of each injection can be the same or different.

[0100] It is also necessary to note that the terms "comprising", "containing" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or apparatus that comprises a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0101] From the above description, it can be seen that the embodiments described in the present application achieve the following technical effects:

[0102] 1) In the semiconductor structure of this application, multiple spaced active regions are provided in the epitaxial layer. The active regions include adjacent implantation regions, base regions, and source regions located in the base regions. A gate is provided on the side of the epitaxial layer away from the substrate. The gate includes a common portion and multiple split gates. The multiple split gates surround the common portion and are all connected to the common portion, forming a mesh-like gate structure. The orthogonal projection of one split gate on the epitaxial layer covers a portion of the base region away from the aforementioned surface. This application uses a mesh-like gate structure composed of split gates and a common portion. When one split gate breaks, other split gates can still be connected to the gate bus through the common portion, thereby receiving the gate control signal. The problem of the entire gate failing will not occur. This avoids the problems of cracking and degradation of effective turn-off capability caused by the size reduction of split gates. In other words, this application can greatly overcome the dilemma that the cell pitch cannot be further reduced due to the minimum process linewidth limitation of the gate in the existing planar split gate technology. At the same time, this application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0103] 2) In the semiconductor structure fabrication method of this application, a substrate is first provided, and then an initial epitaxial layer is formed on one side surface of the substrate. Multiple spaced active regions are formed in the initial epitaxial layer. The initial epitaxial layer with active regions forms an epitaxial layer. The active regions include adjacent implantation regions, base regions, and source regions located in the base regions. A gate is formed on the side of the epitaxial layer away from the substrate. The gate includes a common portion and multiple split gates. The multiple split gates surround the common portion and are all connected to the common portion, forming a mesh-type gate structure. The orthogonal projection of a split gate on the epitaxial layer covers a portion of the base region away from the aforementioned surface. This application employs a mesh gate structure composed of split gates and a common section. When one split gate breaks, the other split gates can still be connected to the gate bus through the common section, thereby receiving the gate control signal. This avoids the problem of the entire gate failing, thus preventing cracking and degradation of effective turn-off capability caused by the reduction in the size of the split gate. In other words, this application can greatly overcome the predicament of existing planar split gate technology, which is limited by the minimum process linewidth of the gate, preventing further reduction in cell pitch. At the same time, this application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0104] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an epitaxial layer on a side surface of the substrate; a cell structure comprising a plurality of active regions and a gate, the plurality of active regions being spaced apart in the epitaxial layer, each of the active regions comprising an injection region and a base region abutting each other, and a source region in the base region, the source region being in contact with the injection region, a side surface of each of the active regions being a side surface of the base region, the gate comprising a common part and a plurality of split gates, the common part and the plurality of split gates being on a side of the epitaxial layer away from the substrate, the plurality of split gates surrounding the common part and being connected to the common part, a projection of one of the split gates on the epitaxial layer covering a part of a surface of one of the base regions away from the substrate, the base region and the injection region being of a first doping type, the source region, the epitaxial layer and the substrate being of a second doping type.

2. The semiconductor structure of claim 1, wherein, Two of the split gates correspond to one of the base regions, a projection of one of the two split gates on the epitaxial layer covering a part of a surface of the base region away from the substrate, a projection of the other of the two split gates on the epitaxial layer covering a remaining part of a surface of the base region away from the substrate.

3. The semiconductor structure of claim 1, wherein, The cell structure further comprises: a JFET region in the epitaxial layer, the JFET region being between any two adjacent base regions and in contact with each of the base regions, a projection of the split gate on the epitaxial layer covering a part of a surface of the base region away from the substrate, a part of a surface of the JFET region away from the substrate and a part of a surface of the source region away from the substrate.

4. The semiconductor structure of claim 3, wherein, The cell structure further comprises: a gate oxide layer between the gate and the epitaxial layer, the gate oxide layer being on a surface of the JFET region away from the substrate.

5. The semiconductor structure of claim 4, wherein, The semiconductor structure further comprises: a dielectric layer on a surface of the gate away from the epitaxial layer, on a sidewall of the gate and on a surface of the gate oxide layer away from the epitaxial layer; a source metal layer on a surface of the injection region away from the substrate, on a part of a surface of the source region away from the substrate, on a surface of the dielectric layer away from the epitaxial layer and on a sidewall of the dielectric layer; a drain metal layer on a surface of the substrate away from the epitaxial layer.

6. The semiconductor structure of any one of claims 1 to 5, wherein, The cell structure is a square cell.

7. A method of fabricating the semiconductor structure of any one of claims 1 to 6, wherein The semiconductor structure comprises: providing a substrate; forming an initial epitaxial layer on a side surface of the substrate; forming a plurality of active regions in at least the initial epitaxial layer, a remaining part of the initial epitaxial layer forming an epitaxial layer, the plurality of active regions being spaced apart in the epitaxial layer, each of the active regions comprising an injection region and a base region abutting each other, and a source region in the base region, the source region being in contact with the injection region, a side surface of each of the active regions being a side surface of the base region, the base region and the injection region being of a first doping type, the source region, the epitaxial layer and the substrate being of a second doping type; A gate is formed on a side of the epitaxial layer away from the substrate, the gate comprising a common part and a plurality of split gates, the common part and the plurality of split gates being located on the side of the epitaxial layer away from the substrate, the plurality of split gates surrounding the common part and being connected to the common part, a projection of one of the split gates on the epitaxial layer covering a part of a surface of the base region away from the substrate.

8. The method of claim 7, wherein, The method further comprises forming a plurality of active regions in the initial epitaxial layer, comprising: The method further comprises forming a plurality of active regions in the initial epitaxial layer, comprising: A first mask and a second mask are stacked on a side of the initial epitaxial layer away from the substrate, and a double-layer mask technique is used to form a first barrier layer on a surface of the initial epitaxial layer away from the substrate, the first barrier layer exposing the initial epitaxial layer between any two adjacent base regions, the first mask being a mask used in a process of forming the base regions, and the second mask being a mask used in a process of forming the gate; The initial epitaxial layer on which the active regions are formed is subjected to ion implantation with the first barrier layer as a mask, so as to form a JFET region in the initial epitaxial layer, the initial epitaxial layer on which the JFET region is formed forming the epitaxial layer, a projection of the split gate on the epitaxial layer covering a part of a surface of the base region away from the substrate, a part of a surface of the JFET region away from the substrate, and a part of a surface of the source region away from the substrate; The first barrier layer is removed.

9. The method of claim 8, wherein, The method further comprises forming a plurality of active regions in the initial epitaxial layer, comprising: The first mask is arranged on a side of the initial epitaxial layer away from the substrate, and a second barrier layer is formed on a surface of the initial epitaxial layer away from the substrate by using the first mask, the second barrier layer exposing a part of a surface of the initial epitaxial layer; The initial epitaxial layer is subjected to ion implantation with the second barrier layer as a mask, so as to obtain a plurality of initial base regions arranged at intervals; A part of an area of the initial base region away from an adjacent initial base region is subjected to ion implantation, so as to form the implantation region in the initial base region; The initial base region is subjected to ion implantation, so as to form the source region adjacent to the implantation region in the initial base region, the remaining initial base region forming the base region, the source region being located on a side of the implantation region close to an adjacent active region; The second barrier layer is removed.

10. The method of claim 8, wherein, After the first barrier layer is removed, before the gate is formed on a side of the epitaxial layer away from the substrate, the method further comprises: The structure on which the JFET region is formed is subjected to an annealing treatment; A gate oxide layer is formed on a part of a surface of the epitaxial layer away from the substrate, the gate oxide layer being located on a surface of the JFET region away from the substrate.

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