Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a manufacturing method thereof, wherein the device comprises: a body region, adjacent to the sidewall of the trench gate; an epitaxial layer, at least a portion of the epitaxial layer is located between the body region and the second surface, and adjacent to the trench gate and the body region, wherein the trench comprises a first trench extending from the first surface of the semiconductor layer to the second surface and a second trench located at the bottom of the first trench and connected to the first trench, the cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewall of the second trench is adjacent to the body region. The semiconductor device and the manufacturing method thereof of the present application increase the length of the channel by forming a second trench with a circular or elliptical cross-sectional shape at the bottom of the first trench and making the second trench at least partially adjacent to the body region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a trench gate structure and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices mainly include planar diffused MOS transistors (LDMOS) and trench MOS transistors (Trench MOS). Because trench MOS transistors use vertical channels, the number of devices per unit area can be greater than that of planar diffused MOS transistors, so their current density can be greatly improved. In order to reduce the on-resistance of the device, the method of increasing the channel length can be adopted.

[0003] However, the trench gate structure requires a larger trench depth-to-width ratio in order to increase the channel length. However, it is difficult to increase the depth-to-width ratio in the trench structure in the prior art, and local electric field concentration is easily generated at the corners of the trench bottom that have not been specially treated, affecting device reliability. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, by forming a second trench with a circular or elliptical cross-sectional shape at the bottom of the first trench, and making the second trench at least partially adjacent to the body region, thereby increasing the length of the channel.

[0005] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface relative to each other, the trench gate is located in a trench, the semiconductor layer comprises: a body region, adjacent to the sidewalls of the trench gate; an epitaxial layer, at least a portion of the epitaxial layer is located between the body region and the second surface, and adjacent to the trench gate and the body region, wherein the trench comprises a first trench extending from the first surface to the second surface of the semiconductor layer and a second trench located at the bottom of the first trench and connected to the first trench, the cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewalls of the second trench are adjacent to the body region.

[0006] Optionally, a bottom of the second trench is located in the epitaxial layer.

[0007] Optionally, the cross-sectional shape of the first trench is rectangular, and along the width direction of the trench gate, the lateral dimension of the first trench is less than or equal to the lateral dimension of the second trench.

[0008] Optionally, the trench gate includes: a gate dielectric layer located in the trench and adjacent to the sidewall of the trench; a gate conductor located in the trench, and the gate dielectric layer isolates the gate conductor from the semiconductor layer, wherein the thickness of the gate dielectric layer in the first trench and the second trench is consistent.

[0009] Optionally, the semiconductor layer also includes: a source region adjacent to the side wall of the trench gate, the source region extending from the first surface toward the body region and adjacent to a portion of the upper surface of the body region; a body contact region adjacent to the side wall of the source region, extending from the first surface toward the body region and adjacent to a portion of the upper surface of the body region.

[0010] Optionally, the semiconductor layer also includes: a source region adjacent to the side wall of the trench gate, the source region extending from the first surface toward the body region and adjacent to a portion of the upper surface of the body region; a third trench extending from the first surface to the second surface of the semiconductor layer, located on the side of the source region away from the trench gate, adjacent to the side wall of the source region; a body contact region adjacent to the bottom of the third trench and the body region, and located between the bottom of the third trench and the second surface of the semiconductor layer.

[0011] Optionally, the source region and the epitaxial layer are of a first conductivity type, the body region and the body contact region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0012] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a body region and a source region in a semiconductor layer, the semiconductor layer comprising a first surface and a second surface opposite to each other, the body region and the source region being located on a side of the semiconductor layer close to the first surface; forming a mask layer on the semiconductor layer and forming a first trench in the semiconductor layer via the mask layer; forming a second trench in the semiconductor layer via the bottom of the first trench, wherein the cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewalls of the second trench are adjacent to the body region.

[0013] Optionally, in the step of forming a second trench in the semiconductor layer through the bottom of the first trench, the bottom of the second trench exposes the semiconductor layer below the body region.

[0014] Optionally, between the steps of forming a mask layer on the semiconductor layer and forming a first trench in the semiconductor layer via the mask layer and forming a second trench in the semiconductor layer via the bottom of the first trench, the method further includes: forming a barrier layer on the sidewall of the first trench.

[0015] Optionally, the step of forming a barrier layer on the sidewall of the first trench includes: forming a barrier layer on the upper surfaces of the first trench and the mask layer; and removing the barrier layer on the upper surface of the mask layer and the barrier layer at the bottom of the first trench.

[0016] Optionally, after the step of forming a second trench in the semiconductor layer via the bottom of the first trench, the method further includes: trimming the shape of the first trench to expand the lateral dimension of the bottom of the first trench.

[0017] Optionally, after the step of trimming the shape of the first trench, the method further includes: forming a gate dielectric layer with uniform thickness in the first trench and the second trench; forming a gate conductor in the first trench and the second trench, wherein the gate dielectric layer isolates the gate conductor and the semiconductor layer.

[0018] Optionally, the step of forming the body region and the source region in the semiconductor layer includes: forming a third trench in the semiconductor layer; and forming the body region and the source region in the semiconductor layer by an ion implantation process.

[0019] The above technical solution has the following beneficial effects:

[0020] The semiconductor device and the manufacturing method thereof provided by the present application include a first trench and a second trench connected to each other in the semiconductor device. The second trench is located at the bottom of the first trench and is circular. The upper arc-shaped sidewall of the second trench is adjacent to the body region, and the lower arc-shaped sidewall is adjacent to the epitaxial layer. Therefore, when the device is turned on, compared with the vertical trench gate sidewall, the channel formed along the trench gate sidewall in the present application will increase the length of the channel due to the arc-shaped part, thereby reducing the on-resistance of the device and the field effect per unit length, and reducing the leakage current of the device, thereby improving the reliability of the device.

[0021] Furthermore, in the semiconductor device, the spherical second trench can increase the length of the channel without increasing the width of the trench gate. Therefore, compared with semiconductor devices with straight channels of the same length, the semiconductor device of the present application can accommodate more cellular structures per unit area, thereby achieving lower on-resistance, reducing chip size, and increasing the number of chips produced by a wafer.

[0022] Furthermore, in the semiconductor device, in a cross-section along the width direction of the trench gate, the sidewall and bottom of the second trench form a circular or elliptical portion, so that the bottom of the trench gate has no corners, thereby making the distribution of the electric field more dispersed and uniform, avoiding the problem of local electric field concentration at the bottom of the trench gate, and effectively eliminating the possibility of the gate dielectric layer being broken down by the electric field.

[0023] Furthermore, in the semiconductor device, the thickness of the gate dielectric layer is consistent in the first trench and the second trench, which can make the current path in the device smoother, thereby reducing the electric field concentration problem at the connection between the first trench and the second trench; in addition, the thickness of the gate dielectric layer is consistent, and the threshold voltage and leakage current in the device are more stable, thereby improving the reliability of the device.

[0024] The semiconductor device and the manufacturing method thereof provided by the present application, in the manufacturing method, firstly form a first inverted trapezoidal groove, then form a barrier layer on the side wall in the first groove, form a second groove with a circular or elliptical cross-sectional shape in the semiconductor layer at the bottom of the first groove, and then partially trim the side wall of the first groove, so that the lateral dimension of the bottom of the first groove is basically consistent with the lateral dimension of the top. After the trimming, the angle of the corner at the connection with the second groove becomes larger, which reduces the problem of electric field concentration at the corner at the connection between the first groove and the second groove, and also facilitates the formation of a gate dielectric layer with uniform thickness in subsequent steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0026] Figure 1 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present application is shown;

[0027] Figure 2 A schematic cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present application is shown;

[0028] Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present application is shown;

[0029] Figure 4a to Figure 4g A schematic cross-sectional view of each stage in a method for manufacturing a semiconductor device according to a first embodiment of the present application is shown;

[0030] Figure 5 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a second embodiment of the present application is shown;

[0031] Figure 6 A schematic cross-sectional structure diagram of a semiconductor device according to a second embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0033] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0034] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0035] Many specific details of the present application are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to make the present application more clearly understood. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.

[0036] Figure 1 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present application is shown; Figure 2 FIG. 1 shows a schematic cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present application. Specifically, Figure 2 For example, along Figure 1 The screenshot is obtained by taking a screenshot in the direction indicated by the dotted line AA. Figure 1 Only part of the structure is shown.

[0037] like Figure 1 and Figure 2 As shown, the semiconductor device of the present application includes a semiconductor layer 100, a plurality of trench gates 150, an interlayer dielectric layer 170, a first conductive layer 181, and a second conductive layer 182. The semiconductor layer 100 has a first surface and a second surface opposite to each other, the first conductive layer 181 is located on the first surface, and the second conductive layer 182 is located on the second surface. The semiconductor layer 100 includes a plurality of trenches, which extend from the first surface to the second surface into the semiconductor layer 100.

[0038] The semiconductor layer is, for example, a SiC, GaN, Ga2O3, Al2O3 substrate or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of the present application are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer as needed, such as other wide bandgap semiconductor materials.

[0039] In the present application, the semiconductor layer 100 includes, for example, a substrate 110, an epitaxial layer 120, a body region 131, a source region 140, and a body contact region 132. Specifically, the epitaxial layer 120 is located above the substrate 110, a trench extends from a first surface to a second surface of the semiconductor layer 100 into the epitaxial layer 120, and a plurality of trench gates 150 are located in corresponding trenches in the semiconductor layer 100. The source region 140 is located on both sides of the trench gate 150 and extends from the first surface to the second surface of the semiconductor layer 100, and the source region 140 is adjacent to the sidewall of the trench gate 150; the body region 131 is adjacent to the lower surface of the source region 140 and the sidewall of the trench gate 150, and at least part of the epitaxial layer 120 is located between the body region 131 and the second surface of the semiconductor layer 100; the body contact region 132 is located on the side of the source region 140 away from the trench gate 150, and the sidewall of the body contact region 132 is adjacent to the source region 140, and the lower surface is adjacent to the upper surface of the body region 131. Optionally, the depth of the lower surface of the body contact region 132 extending from the first surface to the second surface of the semiconductor layer 100 can be the same as the depth of the source region 140 extending from the first surface to the second surface of the semiconductor layer 100, or it can be different. Figure 1 and Figure 2 An embodiment is shown in which the depth at which the lower surface of the body contact region 132 extends from the first surface to the second surface of the semiconductor layer 100 is greater than the depth at which the source region 140 extends from the first surface to the second surface of the semiconductor layer 100 .

[0040] The trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench, and the gate conductor 152 is located in the trench. The gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, and is used to separate the semiconductor layer 100 from the gate conductor 152. The width direction of the trench gate 150 is a first direction, such as the X-axis direction, the length direction is a second direction, such as the Y-axis direction, and the depth direction is a third direction, such as the Z-axis direction. Optionally, the first direction, the second direction, and the third direction are perpendicular to each other.

[0041] In this embodiment, the grooves include a first groove 104 and a second groove 106 connected to each other. The second groove 106 is located at the bottom of the first groove 104. Figure 2The shape in the cross-section shown is circular or elliptical, so the bottom shape of the trench gate 150 formed along the trench matches the shape of the second trench 106, which is also circular or elliptical. Among them, at least part of the sidewall of the second trench 106 is adjacent to the body region 131, specifically, the upper part of the sidewall of the second trench 106 is adjacent to the body region 131, and the lower part of the sidewall or the bottom is located in the epitaxial layer 120. Along the width direction of the trench gate, the lateral size of the second trench 106 is greater than or equal to the lateral size of the first trench 104. The interlayer dielectric layer 170 is located on the first surface of the semiconductor layer 100 and covers the upper surface of the trench gate 150. The first conductive layer 181 serves as a source, covers the first surface of the semiconductor layer 100 and the interlayer dielectric layer 170, and the first conductive layer 181 is adjacent to at least part of the upper surface of the source region 140. The substrate 110 serves as a drain region, the second conductive layer 182 serves as a drain electrode, and the second conductive layer 182 covers the second surface of the semiconductor layer 100 , that is, the lower surface of the substrate 110 .

[0042] In this embodiment, along the first direction, a plurality of trench gates 150 are arranged at intervals, and the body region 131 and the source region 140 are located between adjacent trench gates 150 .

[0043] In this embodiment, the source region 140, the epitaxial layer 120 and the substrate 110 are of the first conductivity type, the body region 131 and the body contact region 132 are of the second conductivity type, and the doping concentration of the body contact region 132 is greater than the doping concentration of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of the P type and the N type, and the second conductivity type is the other of the P type and the N type.

[0044] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is set on the second surface 102 of the semiconductor layer, and the conductivity type of the drain contact region is set to the first conductivity type or the second conductivity type. However, the embodiment of the present application is not limited to this, and those skilled in the art can perform other settings on the conductivity type of each region in the semiconductor layer as needed to use the semiconductor device as a MOSFET or an IGBT.

[0045] In this embodiment, when the device is turned on, the body region 131 and the part adjacent to the side wall of the trench gate 150 are inverted to form a channel, and carriers flow in from the first conductive layer 181, then flow to the epitaxial layer 120 through the source region 140 and the channel, and finally flow out from the second conductive layer 182. In the present application, since the trench includes the first trench 104 and the second trench 106, and the body region 131 is adjacent to the side wall of part of the second trench 106, at least a part of the trench is an arc along the side wall of the second trench 106. Compared with a straight trench of the same depth, the channel length of the semiconductor device with a partially arcuate trench side wall of the present application is increased; and compared with a semiconductor device with a straight trench of the same length, the trench depth of the semiconductor device of the present application can be reduced, and then the width can also be reduced under the same aspect ratio, and more cell structures can be accommodated under a unit area, thereby achieving lower on-resistance, reducing chip size, and increasing the number of chips produced by a wafer.

[0046] Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present application is shown; Figure 4a to Figure 4g The cross-sectional schematic diagrams of various stages in the method for manufacturing a semiconductor device according to the first embodiment of the present application are shown. Figure 1 to Figure 4g The manufacturing method of the semiconductor device of the present application is described in detail.

[0047] Step S201: forming an epitaxial layer on a substrate by using an epitaxial process, and sequentially forming a body region, a source region and a body contact region in the epitaxial layer by using an ion implantation process.

[0048] In this step, an epitaxial layer 120 is formed on the substrate 110 by an epitaxial process, and the thickness of the epitaxial layer 120 is greater than the thickness of the substrate 110. Since the epitaxial layer 120 is formed by the epitaxial process, the epitaxial layer 120 has the same lattice orientation as the substrate 110.

[0049] The epitaxial layer 120 and the substrate 110 form a semiconductor layer 100 .

[0050] Furthermore, an ion implantation process is used to sequentially form a body region 131, a source region 140 and a body contact region 132 in the epitaxial layer 120, as shown in FIG. Figure 4a The source region 140 and the body contact region 132 have different doping types and therefore cannot be formed at the same time, while the body contact region 132 and the body region 131 have the same doping type, but the doping concentration of the body contact region 132 is greater than that of the body region 131 .

[0051] Step S202: forming a mask layer on the first surface of the semiconductor layer.

[0052] In this step, a hard mask 101 is first formed on the first surface of the semiconductor layer 100, and then a photoresist layer 102 is formed on the hard mask 101. Then, the photoresist layer 102 is patterned by an exposure and development process to form a mask layer. In this embodiment, the hard mask 101 and the photoresist layer 102 serve as a mask layer together. The photoresist layer 102 has a groove 103, and the groove 103 is located in the photoresist layer 102 corresponding to the epitaxial layer 120 between the adjacent body contact regions 132, for forming a groove, such as Figure 4a shown.

[0053] The material of the hard mask 101 is, for example, silicon oxide.

[0054] Step S203: forming a first trench in the semiconductor layer through the mask layer.

[0055] In this step, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation and the like, is used to form a first trench 104 in the semiconductor layer 100 via a mask layer. Figure 4b shown.

[0056] The first trench 104 penetrates the source region 140 and the body region 131 and extends to near the bottom of the body region 131 . It can be in the epitaxial layer 120 below the body region 131 or in the body region 131 close to the epitaxial layer 120 . The portion of the first trench 104 located in the semiconductor layer 100 is located between adjacent body contact regions 132 .

[0057] In this step, the first trench 104 formed is, for example, in an inverted trapezoidal shape.

[0058] Furthermore, the photoresist layer 102 is removed, and only the patterned hard mask 101 is retained as a mask layer.

[0059] Step S204: forming a barrier layer on the sidewalls of the first trench.

[0060] In this step, a barrier layer 105 is first deposited on the upper surface of the mask layer and the sidewalls and bottom of the first trench 104 by a deposition process such as physical vapor deposition or chemical vapor deposition. Figure 4c shown.

[0061] The portion of the barrier layer 105 located in the first trench 104 covers the sidewall and the bottom of the first trench 104 , so that the lateral dimension of the first trench 104 is reduced.

[0062] Further, the barrier layer 105 on the surface of the mask layer and the barrier layer 105 at the bottom of the first trench 104 are removed, so that the remaining barrier layer 105 only covers the sidewall of the first trench 104 and exposes the bottom of the first trench 104, as shown in FIG. Figure 4d shown.

[0063] In this embodiment, the material of the barrier layer 105 is, for example, silicon nitride. The barrier layer 105 serves as an isolation layer in the subsequent etching process to prevent the semiconductor layer 100 on the sidewall of the trench from being etched again.

[0064] Step S205: forming a second trench at the bottom of the first trench.

[0065] In this step, an etching process, such as wet etching or vapor etching, is used to etch the semiconductor layer 100 at the bottom of the first trench 104 to form a second trench 106 with a circular or elliptical cross-sectional shape, such as Figure 4e shown.

[0066] Since wet etching or vapor etching is adopted, the etching rates in all directions during the etching process are similar, thereby forming a circular or elliptical second trench 106. In addition, in the process of etching to form the second trench 106, since the etching starts from the bottom of the first trench 104, despite the existence of the barrier layer 105, the semiconductor layer 100 on both sides of the bottom of the first trench 104 will also be partially etched during the etching process.

[0067] In addition, since the bottom of the first trench 104 is located near the area where the body region 131 and the epitaxial layer 120 are adjacent, at least a portion of the side walls of the formed second trench 106 are adjacent to the body region 131. Specifically, the second trench 106 spans the body region 131 and the epitaxial layer 120, that is, the upper half of the second trench 106 is located in the body region 131, and the lower half is located in the epitaxial layer 120, and the bottom of the second trench 106 exposes the epitaxial layer 120 below the body region.

[0068] Step S206: removing the barrier layer and trimming the shape of the first trench.

[0069] In this step, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation and the like, is used to trim the shape of the first trench 104 through the mask layer, specifically, to widen the lateral dimension of the lower portion of the first trench 104 so that the cross-sectional shape of the first trench 104 is similar to a rectangle, such as Figure 4f and Figure 4g shown.

[0070] Among them, trimming the shape of the first groove 104 can increase the corner size at the junction of the bottom of the first groove 104 and the second groove 106, thereby reducing the electric field concentration problem at the corner, making the current path of the device smoother and improving the stability of the device.

[0071] Furthermore, by trimming the shape of the first trench 104 and increasing the lateral dimension of the bottom of the first trench 104 , the opening at the connection between the second trench 106 and the first trench 104 can be enlarged, thereby facilitating the subsequent formation of the trench gate 150 in the second trench 106 .

[0072] Step S207: forming trench gates in the first trench and the second trench, and forming an interlayer dielectric layer, a first conductive layer, and a second conductive layer.

[0073] In this step, the mask layer is removed, and then a gate dielectric layer 151 and a gate conductor 152 are sequentially formed in the first trench 104 and the second trench 106, and an interlayer dielectric layer 170, a first conductive layer 181 and a second conductive layer 182 are formed on the semiconductor layer 100. Figure 2 shown.

[0074] Among them, in the step of forming the trench gate, since the aforementioned step expands the lateral dimension of the bottom of the first trench 104, the gate dielectric layer 151 and the gate conductor 152 can also be formed relatively easily in the second trench 106. At the same time, the thickness of the gate dielectric layer 151 in the first trench 104 and the second trench 106 is basically the same, thereby improving the reliability of the device.

[0075] The interlayer dielectric layer 170 and the first conductive layer 181 are formed on the first surface of the semiconductor layer 100 , and the second conductive layer 182 is formed on the second surface of the semiconductor layer 100 . The interlayer dielectric layer 170 isolates the first conductive layer 181 and the trench gate 150 .

[0076] Figure 5 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a second embodiment of the present application is shown; Figure 6 A schematic cross-sectional structure diagram of a semiconductor device according to a second embodiment of the present application is shown. Figure 6 For example, along Figure 5 The screenshot is obtained in the direction shown by the dotted line BB.

[0077] Compared with the first embodiment, the difference is that the semiconductor device of the second embodiment is a double-trench semiconductor device, and the similarities will not be described here again, and reference may be made to the relevant description in the first embodiment.

[0078] refer to Figure 5 and Figure 6In the double-trench semiconductor device, the semiconductor device between adjacent trench gates 150 also has a third trench 191, and the depth of the third trench 191 extending from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the source region 140 extending from the first surface to the second surface of the semiconductor layer 100, and the sidewall of the third trench 191 is at least partially adjacent to the sidewall of the source region 140.

[0079] A body contact region 132 is formed in the semiconductor layer 100 below the third trench 191 , and an upper surface of the body contact region 132 is adjacent to at least a portion of a bottom surface of the third trench 191 .

[0080] Further, refer to Figure 6 , the first conductive layer 181 fills the third trench 191 , so that the first conductive layer 181 includes a portion (a) located on the first surface of the semiconductor layer 100 and a portion (b) located in the third trench 191 .

[0081] In addition, in order to better adjust the electric field distribution at the bottom of the trench gate, the depth of the body region 131 extending from the first surface to the second surface of the semiconductor layer 100 at the portion away from the trench gate 150 may be increased.

[0082] Specifically, in a double-trench semiconductor device, the depth at which the upper surface of the body contact region 132 extends from the first surface to the second surface of the semiconductor layer 100 is greater than the depth at which the lower surface of the source region 140 extends from the first surface to the second surface of the semiconductor layer 100, and the source region 140 and the body contact region 132 are no longer adjacent to each other; the depth at which the lower surface of the body region 131 extends from the first surface to the second surface of the semiconductor layer 100 is inconsistent, wherein the depth at which the lower surface of the body region 131 near the trench gate 150 extends from the first surface to the second surface of the semiconductor layer 100 is less than the depth at which the lower surface of the body region 131 far from the trench gate 150 extends from the first surface to the second surface of the semiconductor layer 100.

[0083] Furthermore, when manufacturing the double-trench semiconductor device, for example, based on the aforementioned single-trench semiconductor device manufacturing method, the etching of the third trench 191 is completed first, and then ion implantation is performed on the semiconductor layer 100 to form the source region 140, the body region 131 and the body contact region 132 and subsequent steps.

[0084] The semiconductor device and the manufacturing method thereof provided by the present application include a first trench and a second trench connected to each other in the semiconductor device. The second trench is located at the bottom of the first trench and is circular. The upper arc-shaped sidewall of the second trench is adjacent to the body region, and the lower arc-shaped sidewall is adjacent to the epitaxial layer. Therefore, when the device is turned on, compared with the vertical trench gate sidewall, the channel formed along the trench gate sidewall in the present application will increase the length of the channel due to the arc-shaped part, thereby reducing the on-resistance of the device and the field effect per unit length, and reducing the leakage current of the device, thereby improving the reliability of the device.

[0085] Furthermore, in the semiconductor device, the spherical second trench can increase the length of the channel without increasing the width of the trench gate. Therefore, compared with semiconductor devices with straight channels of the same length, the semiconductor device of the present application can accommodate more cellular structures per unit area, thereby achieving lower on-resistance, reducing chip size, and increasing the number of chips produced by a wafer.

[0086] Furthermore, in the semiconductor device, in a cross-section along the width direction of the trench gate, the sidewall and bottom of the second trench form a circular or elliptical portion, so that the bottom of the trench gate has no corners, thereby making the distribution of the electric field more dispersed and uniform, avoiding the problem of local electric field concentration at the bottom of the trench gate, and effectively eliminating the possibility of the gate dielectric layer being broken down by the electric field.

[0087] Furthermore, in the semiconductor device, the thickness of the gate dielectric layer is consistent in the first trench and the second trench, which can make the current path in the device smoother, thereby reducing the electric field concentration problem at the connection between the first trench and the second trench; in addition, the thickness of the gate dielectric layer is consistent, and the threshold voltage and leakage current in the device are more stable, thereby improving the reliability of the device.

[0088] The semiconductor device and the manufacturing method thereof provided by the present application, in the manufacturing method, firstly form a first inverted trapezoidal groove, then form a barrier layer on the side wall in the first groove, form a second groove with a circular or elliptical cross-sectional shape in the semiconductor layer at the bottom of the first groove, and then partially trim the side wall of the first groove, so that the lateral dimension of the bottom of the first groove is basically consistent with the lateral dimension of the top. After the trimming, the angle of the corner at the connection with the second groove becomes larger, which reduces the problem of electric field concentration at the corner at the connection between the first groove and the second groove, and also facilitates the formation of a gate dielectric layer with uniform thickness in subsequent steps.

[0089] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present application. The scope of the present application is limited by the attached claims and their equivalents. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A semiconductor device, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, the trench gate is located in a trench, and the semiconductor layer comprises: a body region adjacent to a sidewall of the trench gate; an epitaxial layer, at least a portion of the epitaxial layer is located between the body region and the second surface and is adjacent to the trench gate and the body region, The groove includes a first groove extending from the first surface to the second surface of the semiconductor layer and a second groove located at the bottom of the first groove and connected to the first groove. The cross-sectional shape of the second groove is circular or elliptical, and at least part of the sidewall of the second groove is adjacent to the body region.

2. The semiconductor device according to claim 1, wherein At least a portion of the second trench is located in the epitaxial layer.

3. The semiconductor device according to claim 2, wherein: The cross-sectional shape of the first groove is rectangular.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Along the width direction of the trench gate, a lateral dimension of the first trench is smaller than or equal to a lateral dimension of the second trench.

5. The semiconductor device according to claim 4, wherein: The trench gate comprises: a gate dielectric layer, located in the trench and adjacent to a sidewall of the trench; a gate conductor located in the trench, wherein the gate dielectric layer isolates the gate conductor from the semiconductor layer, The gate dielectric layer in the first trench and the second trench has the same thickness.

6. The semiconductor device according to claim 2, wherein: The semiconductor layer further comprises: A source region, adjacent to a sidewall of the trench gate, the source region extending from the first surface toward the body region and adjacent to a portion of an upper surface of the body region; The body contact region is adjacent to the sidewall of the source region, extends from the first surface toward the body region, and is adjacent to a portion of the upper surface of the body region.

7. The semiconductor device according to claim 2, wherein: The semiconductor layer further comprises: A source region, adjacent to a sidewall of the trench gate, the source region extending from the first surface toward the body region and adjacent to a portion of an upper surface of the body region; A third trench, extending from the first surface to the second surface of the semiconductor layer, is located on a side of the source region away from the trench gate and is adjacent to a sidewall of the source region; A body contact region is adjacent to the bottom of the third trench and the body region and is located between the bottom of the third trench and the second surface of the semiconductor layer.

8. The semiconductor device according to claim 6 or 7, wherein: The source region and the epitaxial layer are of a first conductivity type, the body region and the body contact region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

9. A method for manufacturing a semiconductor device, comprising: forming a body region and a source region in a semiconductor layer, wherein the semiconductor layer comprises a first surface and a second surface opposite to each other, and the body region and the source region are located on a side of the semiconductor layer close to the first surface; forming a mask layer on the semiconductor layer and forming a first trench in the semiconductor layer via the mask layer; forming a second trench in the semiconductor layer through a bottom of the first trench, The cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewall of the second trench is adjacent to the body region.

10. The manufacturing method according to claim 9, wherein: In the step of forming a second trench in the semiconductor layer through the bottom of the first trench, the bottom of the second trench exposes the semiconductor layer below the body region.

11. The manufacturing method according to claim 9 or 10, wherein: Between the steps of forming a mask layer on the semiconductor layer and forming a first trench in the semiconductor layer via the mask layer and forming a second trench in the semiconductor layer via the bottom of the first trench, the method further includes: A barrier layer is formed on the sidewalls of the first trench.

12. The manufacturing method according to claim 11, wherein: The step of forming a barrier layer on the sidewall of the first trench comprises: forming a barrier layer on the first trench and an upper surface of the mask layer; The barrier layer on the upper surface of the mask layer and the barrier layer at the bottom of the first trench are removed.

13. The manufacturing method according to claim 9, wherein: After the step of forming a second trench in the semiconductor layer through the bottom of the first trench, the method further comprises: The shape of the first groove is trimmed to expand the lateral dimension of the bottom of the first groove.

14. The manufacturing method according to claim 13, wherein: After the step of trimming the shape of the first groove, the method further includes: forming a gate dielectric layer with uniform thickness in the first trench and the second trench; A gate conductor is formed in the first trench and the second trench, and the gate dielectric layer isolates the gate conductor from the semiconductor layer.

15. The manufacturing method according to claim 9, wherein: The steps of forming a body region and a source region in a semiconductor layer include: forming a third trench in the semiconductor layer; A body region and a source region are formed in the semiconductor layer through an ion implantation process.

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