Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a substrate, a device groove is arranged in the substrate; a field oxide layer is arranged on the groove wall of the device groove, the field oxide layer has a step structure, and the width of the step structure decreases along the direction away from the first surface of the substrate, wherein the first surface is the surface of the substrate forming the device groove; a drift region is arranged in the substrate, the drift region is connected to the field oxide layer, and the drift region is wrapped outside the field oxide layer, wherein the width of the drift region decreases along the direction away from the first surface of the substrate, and the ion doping concentration of the drift region decreases; and a polysilicon layer is filled in the device groove, and the polysilicon layer is connected to the field oxide layer. The present invention provides a semiconductor device and a method for manufacturing the same, which can effectively improve the device's withstand voltage performance, reduce the device size, reduce the device's on-resistance, and bidirectionally optimize the relationship between the device's withstand voltage capability and on-resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process integrates transistors, CMOS and DMOS devices on the same chip, realizing the integration of devices with different performances on the same chip. The BCD process combines the advantages of high transconductance and strong load driving capability of bipolar devices, high integration and low power consumption of CMOS, and DMOS working in switching mode with extremely low power consumption. With market demand and industrial development, high-voltage DMOS devices have higher requirements for low on-resistance and high breakdown voltage.

[0003] In laterally diffused metal oxide semiconductors, improving the voltage resistance of the device will sacrifice the device area, and the high breakdown voltage and low on-resistance of the semiconductor device cannot be achieved at the same time. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can effectively improve the voltage resistance of the device, reduce the device size, reduce the on-resistance of the device, and bidirectionally optimize the relationship between the voltage resistance and on-resistance of the device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a semiconductor device, comprising: A substrate, wherein a device trench is provided in the substrate; A field oxide layer is disposed on a groove wall of the device groove, the field oxide layer has a stepped structure, and a width of the stepped structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate forming the device groove; a drift region, disposed in the substrate, the drift region connected to the field oxide layer and wrapped outside the field oxide layer, wherein a width of the drift region decreases along a direction away from the first surface of the substrate, and an ion doping concentration of the drift region decreases; and A polysilicon layer is filled in the device trench, and the polysilicon layer is connected to the field oxide layer.

[0006] In an embodiment of the present invention, surfaces of the field oxide layer, the drift region, the substrate and the polysilicon layer are flush.

[0007] In one embodiment of the present invention, along a direction perpendicular to the surface of the substrate, the dielectric constant of the field oxide layer changes in a step-like manner.

[0008] In one embodiment of the present invention, the semiconductor device includes a plurality of shallow trench isolation structures, the shallow trench isolation structures are arranged in the substrate, and the plurality of shallow trench isolation structures separate a plurality of active regions in the substrate, wherein the drift region is arranged in the active region.

[0009] In one embodiment of the present invention, the semiconductor device comprises: A first type deep well region is disposed in the substrate, wherein the first type deep well region and the drift region are doped with the same ion type; and A second type of deep well region is arranged in the substrate, the second type of deep well region is arranged on the first type of deep well region and connected to the first type of deep well region, wherein the drift region is arranged on the second type of deep well region and connected to the second type of deep well region, wherein the doping ion types of the second type of deep well region and the drift region are different.

[0010] In one embodiment of the present invention, the semiconductor device includes a body region, the body region is arranged in the second type deep well region, the body region is connected to the drift region, and the body region and the second type deep well region are doped with the same ion type.

[0011] In one embodiment of the present invention, the device trench passes through the body region and the first type deep well region and extends to below the first type deep well region, and the polysilicon layer extends along a direction perpendicular to the first surface and toward the second surface of the substrate, wherein the first surface and the second surface are parallel, wherein one end of the polysilicon layer is flush with the first surface, and the other end of the polysilicon layer extends to below the first type deep well region.

[0012] In one embodiment of the present invention, the semiconductor device comprises: a first well region, disposed in the substrate, the first well region being located in the active region outside the drift region, and the first well region being connected to the second-type deep well region; and The second well region is arranged in the substrate, the second well region is located in the active region outside the first well region, and the second well region is connected to the first type deep well region.

[0013] In one embodiment of the present invention, the polysilicon layer has a symmetry plane, the semiconductor device is a symmetrical structure, and the semiconductor device is symmetrical about the symmetry plane, wherein the drift region is symmetrical about the symmetry plane, and the field oxide layer is symmetrical about the symmetry plane.

[0014] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate; Stepwise forming a device trench in the substrate, while gradually forming the device trench, forming a field oxide layer on the trench wall of the device trench, wherein the field oxide layer has a step structure, and the width of the step structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate on which the device trench is formed; While gradually forming the device trenches, gradually forming a plurality of doped regions in the substrate; After the annealing treatment, the plurality of doped regions form a drift region, wherein the drift region is connected to the field oxide layer and the drift region is wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; and The device trench is filled to form a polysilicon layer, wherein the polysilicon layer is connected to the field oxide layer.

[0015] In one embodiment of the present invention, the step of gradually forming the device trench, the field oxide layer and the drift region comprises: forming a current dielectric layer on the exposed surface of the substrate and the surface of the previous dielectric layer; Etching the current dielectric layer and the substrate to form a current transition trench, wherein when forming the current transition trench, the current dielectric layer located on the side trench wall of the previous transition trench is retained; Implanting ions into the substrate to form a doped region; Among them, a plurality of doped regions are connected to form the drift region, and a plurality of the current dielectric layers on the side walls of the transition trenches are connected to form the field oxide layer.

[0016] As described above, the present invention provides a semiconductor device and a method for manufacturing the same, and the unexpected technical effect is that: the present invention provides a field oxide layer with a stepped structure, and is matched with a drift region with a concentration gradient, wherein the concentration gradient of the drift region decreases while the width of the region also decreases, and the cross-sectional area of ​​the field oxide layer also decreases, thereby effectively improving the voltage resistance of the semiconductor device while the area of ​​the semiconductor device remains unchanged. Moreover, the present invention can reduce the size of the device and reduce the on-resistance of the device while ensuring the longitudinal voltage resistance of the device, which can not only optimize the voltage resistance of the device, but also reduce the on-resistance of the device, and bidirectionally optimize the relationship between the voltage resistance and on-resistance of the device. Moreover, according to the method for manufacturing the semiconductor structure provided by the present invention, while forming the concentration gradient of the drift region, a field oxide layer with a stepped structure is formed, the process is mature, the molding yield of the semiconductor device can be improved, and the process controllability is high, which can effectively reduce device defects.

[0017] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of the structure of forming the first type of deep well region and the second type of deep well region in one embodiment of the present invention.

[0020] Figure 2 FIG. 1 is a schematic diagram of a structure for forming a shallow trench isolation structure in an embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the structure of forming an interlayer dielectric layer and a hard mask layer in one embodiment of the present invention.

[0022] Figure 4 FIG. 1 is a schematic diagram of a structure for forming a process trench in an embodiment of the present invention.

[0023] Figure 5 FIG. 4 is a schematic diagram of a structure for forming a first dielectric layer in one embodiment of the present invention.

[0024] Figure 6 It is a schematic diagram of the structure of forming the first section of the groove in one embodiment of the present invention.

[0025] Figure 7 FIG. 4 is a schematic diagram of a structure for forming a second dielectric layer in one embodiment of the present invention.

[0026] Figure 8 It is a schematic diagram of the structure of forming the second section of the groove in one embodiment of the present invention.

[0027] Fig. 9 FIG. 4 is a schematic diagram of a structure for forming a third dielectric layer in one embodiment of the present invention.

[0028] Fig.10 It is a schematic diagram of the structure of forming the third section of the groove in one embodiment of the present invention.

[0029] Fig.11 FIG. 4 is a schematic diagram of a structure for forming a fourth dielectric layer in one embodiment of the present invention.

[0030] Fig.12 FIG. 4 is a schematic diagram of a structure for forming a fourth groove in an embodiment of the present invention.

[0031] Fig.13 FIG. 4 is a schematic diagram of a structure for forming a fifth dielectric layer in one embodiment of the present invention.

[0032] Fig.14FIG. 4 is a schematic diagram of a structure for forming a fifth groove in an embodiment of the present invention.

[0033] Fig.15 It is a schematic diagram of a structure for forming a reserved gate oxide layer in one embodiment of the present invention.

[0034] Fig.16 It is a schematic diagram of the structure of etching and removing the reserved gate oxide layer in one embodiment of the present invention.

[0035] Fig.17 FIG. 1 is a schematic diagram of a structure for forming a gate oxide layer in one embodiment of the present invention.

[0036] Fig.18 FIG. 4 is a schematic diagram of a structure for forming a drift region in one embodiment of the present invention.

[0037] Fig.19 FIG. 4 is a schematic diagram of a structure for forming a polysilicon layer in one embodiment of the present invention.

[0038] Fig. 20 FIG. 4 is a schematic diagram of a semiconductor structure in one embodiment of the present invention.

[0039] Fig.21 FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor device in one embodiment of the present invention.

[0040] Fig. 22 FIG. 4 is a schematic diagram of the layout structure of a semiconductor device from a top view according to an embodiment of the present invention.

[0041] Fig.23 FIG. 4 is a schematic diagram of an electrode structure of a semiconductor device in one embodiment of the present invention.

[0042] In the figure: 100, substrate; 101, first type deep well region; 102, second type deep well region; 103, shallow trench isolation structure; 104, first doped region; 105, second doped region; 106, third doped region; 107, fourth doped region; 108, body region; 109, first well region; 110, second well region; 111, electrode doped region; 112, base doped region; 113, silicide layer; 201, interlayer dielectric layer; 202, hard mask layer; 203, first dielectric layer; 204, process trench; 2 041, first transition trench; 2042, second transition trench; 2043, third transition trench; 2044, fourth transition trench; 2045, fifth transition trench; 205, second dielectric layer; 206, third dielectric layer; 207, fourth dielectric layer; 208, fifth dielectric layer; 209, reserved gate oxide layer; 210, gate oxide layer; 211, polysilicon layer; 300, photoresist layer; 400, contact electrode; 10, drift region; 20, field oxide layer; S, source; B, base; D, drain; G, gate. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] See also Figure 1 As shown, the present invention provides a method for manufacturing a semiconductor device, first providing a substrate 100, forming a first type of deep well region 101 in the substrate 100, and then forming a second type of deep well region 102 in the substrate 100. The substrate 100 is, for example, a silicon substrate for forming a semiconductor device. The substrate 100 may include a substrate and a silicon layer disposed above the substrate, and the substrate is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and the silicon layer is formed above the substrate. In this embodiment, the substrate 100 is, for example, a P-type semiconductor. Pentavalent ions, such as phosphorus ions, are injected into the substrate 100 to form the first type of deep well region 101. Then, trivalent ions, such as boron ions, are injected into the substrate 100 to form the second type of deep well region 102. In this embodiment, the second type of deep well region 102 is located above the first type of deep well region 101 and is connected to the first type of deep well region 101. It should be noted that the first type deep well region 101 and the second type deep well region 102 are both deep well structures. The first type deep well region 101 and the second type deep well region 102 are located in the substrate 100. The present invention does not limit the depth of the first type deep well region 101 and the second type deep well region 102 in the substrate 100.

[0045] See also Figures 1 to 3As shown, in one embodiment of the present invention, a plurality of shallow trench isolation structures 103 are formed in the substrate 100, an interlayer dielectric layer 201 is formed on the substrate 100, and a hard mask layer 202 is formed on the interlayer dielectric layer 201. The process for forming the shallow trench isolation structure 103 is a shallow trench isolation process (STI). The plurality of shallow trench isolation structures 103 separate a plurality of active regions in the substrate 100. In this embodiment, the active region above the second type deep well region 102 is a process region. The plurality of shallow trench isolation structures 103 are distributed on both sides of the process region, and the shallow trench isolation structures 103 located on both sides of the process region are symmetrically distributed about a symmetric plane of the second type deep well region 102. In this embodiment, the process for forming the interlayer dielectric layer 201 and the hard mask layer 202 is chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The interlayer dielectric layer 201 is silicon oxide, and the hard mask layer 202 is silicon nitride. The present invention does not limit the thickness of the interlayer dielectric layer 201 and the hard mask layer 202.

[0046] See also Figures 1 to 4 As shown, in one embodiment of the present invention, the hard mask layer 202 and the interlayer dielectric layer 201 are etched to form a process groove 204. In this embodiment, a photoresist material is first coated on the hard mask layer 202, and then the photoresist material is patterned by exposure and development to form a photoresist layer 300. Using the photoresist layer 300 as a mask, a portion of the hard mask layer 202 and a portion of the interlayer dielectric layer 201 are removed by dry etching to form a process groove 204. In this embodiment, the process groove 204 is located on the process area. After the etching is completed, the photoresist layer 300 can be directly washed away. Then, using the hard mask layer 202 and the interlayer dielectric layer 201 as masks, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a first doped region 104. In this embodiment, the first doped region 104 is located in the process area, wherein the depth of the first doped region 104 in the substrate 100 can be greater than the depth of the shallow trench isolation structure 103 in the substrate 100. In this embodiment, in the step of forming the first doping region 104, the ion injection direction is tilted. The present invention does not limit the tilt angle. After the ion injection, the width W2 of the first doping region 104 is greater than the cross-sectional width W1 of the process trench 204. Figure 4 shown.

[0047] See also Figures 4 to 6As shown, in one embodiment of the present invention, after forming the first doping region 104, a first dielectric layer 203 is formed on the hard mask layer 202 and in the process trench 204. Then, the first dielectric layer 203 and a portion of the substrate 100 are etched to form a first transition trench 2041. Then, using the hard mask layer 202 and the interlayer dielectric layer 201 as masks, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a second doping region 105. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the groove wall of the process trench 204 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the first dielectric layer 203, wherein the groove wall of the process trench 204 includes a portion of the sidewall of the hard mask layer 202, a portion of the sidewall of the interlayer dielectric layer 201, and an exposed surface of the substrate 100. Then, the first dielectric layer 203 on the surface of the hard mask layer 202 and a portion of the first dielectric layer 203 on the substrate 100 are removed by etching, and then the substrate 100 is etched to deepen the process trench 204 and form a first transition trench 2041. The etching step is dry etching and can be performed in multiple steps.

[0048] See also Figures 4 to 6 As shown, in one embodiment of the present invention, the process of forming the first transition groove 2041 is described as the first etching step of the substrate 100. The first etching depth of the substrate 100 is equal to the implantation depth of the first doping region 104. In this embodiment, the second doping region 105 is connected to the first doping region 104, and the ion concentration of the second doping region 105 is lower than the ion concentration of the first doping region 104. In this embodiment, the width W3 of the second doping region 105 is less than the width W2 of the first doping region 104, and the width W3 of the second doping region 105 is less than the cross-sectional length of the process groove 204. The first doping region 104 is symmetrical about the symmetric plane of the second type deep well region 102, and the second doping region 105 is symmetrical about the symmetric plane of the second type deep well region 102. In this embodiment, the first doping region 104 covers the second doping region 105.

[0049] See also Figures 4 to 6As shown, in one embodiment of the present invention, in the etching step of the hard mask layer 202, the interlayer dielectric layer 201 and the substrate 100, part of the first dielectric layer 203 on the substrate 100 will not be completely removed. Specifically, the dielectric material located on the side wall of the process trench 204 will not be removed with the etching, but will be retained on the side wall of the process trench 204. Therefore, in the ion implantation process of forming the second doping region 105, the first dielectric layer 203 will also serve as a mask for ion implantation to help form the second doping region 105. In this embodiment, in the ion implantation process of forming the second doping region 105, the ion injection direction is vertical implantation, so that a width difference is formed between the second doping region 105 and the first doping region 104, thereby forming a stepped shape of the doping region, and the second doping region 105 and the first doping region 104 can still maintain the same symmetry plane. It should be noted that, in this embodiment, the bottom surface of the first transition trench 2041 is the surface of the second doping region 105 , and the side walls of the first transition trench 2041 include the exposed surface of the first dielectric layer 203 and the exposed side walls of the first doping region 104 .

[0050] See also Figures 6 to 8 As shown, in one embodiment of the present invention, after forming the second doping region 105, a second dielectric layer 205 is formed on the surface of the hard mask layer 202 and on the groove wall of the first transition groove 2041. Then, the second dielectric layer 205 and the substrate 100 are etched to form a second transition groove 2042. Then, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a third doping region 106. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and on the groove wall of the first transition groove 2041 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the second dielectric layer 205. The groove wall of the first transition groove 2041 includes the exposed surface of the first dielectric layer 203 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the second dielectric layer 205. Then, the second dielectric layer 205 on the surface of the hard mask layer 202 and a portion of the second dielectric layer 205 on the substrate 100 are removed by etching, and then the substrate 100 is etched to deepen the first transition trench 2041 and form a second transition trench 2042. The etching step is dry etching and can be performed in multiple steps.

[0051] See also Figures 6 to 8As shown, in one embodiment of the present invention, the process of forming the second transition groove 2042 is described as a second etching step of the substrate 100. The second etching depth of the substrate 100 is equal to the implantation depth of the second doping region 105. In this embodiment, the third doping region 106 is connected to the second doping region 105, and the ion concentration of the third doping region 106 is lower than the ion concentration of the second doping region 105. In this embodiment, the width W4 of the third doping region 106 is less than the width W3 of the second doping region 105, wherein the second doping region 105 covers the third doping region 106. In this embodiment, the third doping region 106 is symmetrical about the symmetry plane of the second type deep well region 102. In the step of forming the second transition groove 2042, specifically, the dielectric material located on the side wall of the first transition groove 2041 will not be removed with etching, but will be retained on the side wall of the first transition groove 2041. Therefore, in the ion implantation process of forming the third doping region 106, the second dielectric layer 205 will also serve as a mask for ion implantation to help form the third doping region 106. In this embodiment, in the ion implantation process for forming the third doping region 106, the ion injection direction is vertical implantation, and the second dielectric layer 205 covers a portion of the surface of the second doping region 105. Therefore, after the ion implantation, a width difference is formed between the second doping region 105 and the third doping region 106, thereby forming a step shape between the third doping region 106 and the second doping region 105. The third doping region 106, the second doping region 105 and the first doping region 104 have the same symmetry plane.

[0052] See also Figures 8 to 10 As shown, in one embodiment of the present invention, after forming the third doping region 106, a third dielectric layer 206 is formed on the surface of the hard mask layer 202 and on the groove wall of the second transition groove 2042. Then, the third dielectric layer 206 and the substrate 100 are etched to form a third transition groove 2043. Then, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a fourth doping region 107. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and on the groove wall of the second transition groove 2042 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the third dielectric layer 206. The groove wall of the second transition groove 2042 includes the exposed surface of the second dielectric layer 205 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the third dielectric layer 206. Then, the third dielectric layer 206 on the hard mask layer 202 and a portion of the third dielectric layer 206 on the substrate 100 are removed by etching, and then the substrate 100 is etched to deepen the second transition trench 2042 and form a third transition trench 2043. The etching step is dry etching and can be performed in multiple steps.

[0053] See also Figures 8 to 10As shown, in one embodiment of the present invention, the process of forming the third transition groove 2043 is described as the third etching step of the substrate 100. The third etching depth of the substrate 100 is equal to the implantation depth of the third doping region 106. In this embodiment, the fourth doping region 107 is connected to the third doping region 106, and the ion concentration of the fourth doping region 107 is lower than the ion concentration of the third doping region 106. In this embodiment, the width W5 of the fourth doping region 107 is less than the width W4 of the third doping region 106, wherein the third doping region 106 covers the fourth doping region 107. In this embodiment, the fourth doping region 107 is symmetrical about the symmetry plane of the second type deep well region 102. In the step of forming the third transition groove 2043, specifically, the dielectric material located on the side wall of the second transition groove 2042 will not be removed with etching, but will be retained on the side wall of the second transition groove 2042. Therefore, in the ion implantation process for forming the fourth doping region 107, the third dielectric layer 206 will also serve as a mask for ion implantation to help form the fourth doping region 107. In the present embodiment, in the ion implantation process for forming the fourth doping region 107, the ion injection direction is vertical implantation, and the third dielectric layer 206 covers part of the surface of the third doping region 106. Therefore, after the ion implantation, a width difference is formed between the third doping region 106 and the fourth doping region 107, thereby forming a step shape between the fourth doping region 107 and the third doping region 106. Among them, the fourth doping region 107, the third doping region 106, the second doping region 105 and the first doping region 104 have the same symmetry plane. In the present embodiment, the fourth doping region 107 is connected to the second type deep well region 102, and specifically, the fourth doping region 107 is connected to two second type deep well regions 102.

[0054] See also Figures 10 to 12 As shown, in one embodiment of the present invention, after forming the fourth doping region 107, a fourth dielectric layer 207 is formed on the surface of the hard mask layer 202 and on the wall of the third transition groove 2043. Then, the fourth dielectric layer 207 and the substrate 100 are etched to form a fourth transition groove 2044. Then, trivalent ions, such as boron ions, are implanted into the substrate 100 to form a body region 108. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and on the wall of the third transition groove 2043 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the fourth dielectric layer 207. The wall of the third transition groove 2043 includes the exposed surface of the third dielectric layer 206 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the fourth dielectric layer 207. Then, the fourth dielectric layer 207 on the hard mask layer 202 and a portion of the fourth dielectric layer 207 on the substrate 100 are removed by etching, and then the substrate 100 is etched to deepen the third transition trench 2043 and form a fourth transition trench 2044. The etching step is dry etching and can be performed in multiple steps.

[0055] See also Figures 10 to 12 As shown, in one embodiment of the present invention, the process of forming the fourth transition trench 2044 is described as the fourth etching step of the substrate 100. The fourth etching depth of the substrate 100 is equal to the implantation depth of the fourth doping region 107. In this embodiment, the body region 108 is connected to the fourth doping region 107, and the body region 108 is connected to the first type deep well region 101, and the body region 108 is connected to the second type deep well region 102. The body region 108 is arranged between two second type deep well regions 102. In this embodiment, the width W6 of the body region 108 is less than the width W5 of the fourth doping region 107, and the fourth doping region 107 covers the body region 108. In this embodiment, the body region 108 is symmetrical about the symmetry plane of the second type deep well region 102. In the step of forming the fourth transition trench 2044, specifically, the dielectric material located on the side wall of the third transition trench 2043 will not be removed with etching, but will be retained on the side wall of the third transition trench 2043. Therefore, in the ion implantation process for forming the body region 108, the fourth dielectric layer 207 will also serve as a mask for ion implantation to help form the body region 108. In this embodiment, in the ion implantation process for forming the body region 108, the ion implantation direction is vertical implantation, and the fourth dielectric layer 207 covers a portion of the surface of the fourth doping region 107. Therefore, after the ion implantation, a width difference is formed between the fourth doping region 107 and the body region 108, thereby forming a step shape between the body region 108 and the fourth doping region 107. Among them, the body region 108, the fourth doping region 107, the third doping region 106, the second doping region 105 and the first doping region 104 have the same symmetry plane.

[0056] See also Figure 12 to Figure 14 As shown, in one embodiment of the present invention, after the body region 108 is formed, a fifth dielectric layer 208 is formed on the surface of the hard mask layer 202 and on the groove wall of the fourth transition groove 2044. Then, the fifth dielectric layer 208 and the substrate 100 are etched to form a fifth transition groove 2045. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and on the groove wall of the fourth transition groove 2044 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the fifth dielectric layer 208. The groove wall of the fourth transition groove 2044 includes the exposed surface of the fourth dielectric layer 207 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the fifth dielectric layer 208. Then, the fifth dielectric layer 208 located on the hard mask layer 202 and a portion of the fifth dielectric layer 208 located on the substrate 100 are etched away, and then the substrate 100 is etched, thereby deepening the fourth transition groove 2044 to form the fifth transition groove 2045. The etching step is dry etching and can be performed in multiple steps.

[0057] See also Figure 12 to Figure 14 As shown, in one embodiment of the present invention, the process of forming the fifth transition groove 2045 is described as the fifth etching step of the substrate 100. The fifth etching depth of the substrate 100 is greater than the ion implantation depth of the body region 108 and the first type deep well region 101. The fifth transition groove 2045 passes through the first type deep well region 101 and extends to the bottom of the first type deep well region 101. In this embodiment, the width W6 of the body region 108 is greater than the width W7 of the fifth transition groove 2045. In the step of forming the fifth transition groove 2045, specifically, the dielectric material located on the side wall of the fourth transition groove 2044 will not be removed with the etching, but will be retained on the side wall of the fourth transition groove 2044.

[0058] See also Figures 14 to 16 As shown, in one embodiment of the present invention, after forming the fifth transition trench 2045, a reserved gate oxide layer 209 is formed on the hard mask layer 202 and the groove wall of the fifth transition trench 2045. Then, the reserved gate oxide layer 209 is etched, and only a portion of the reserved gate oxide layer 209 located at the bottom of the fifth transition trench 2045 is retained. In this embodiment, silicon oxide can be deposited on the surface of the hard mask layer 202 and the groove wall of the third transition trench 2043 by chemical vapor deposition or plasma enhanced chemical vapor deposition, so as to form the reserved gate oxide layer 209. It should be noted that the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207 and the fifth dielectric layer 208 form a stacked structure, and when the reserved gate oxide layer 209 is deposited to form the reserved gate oxide layer 209, the reserved gate oxide layer 209 also covers the stacked structure. Then, the reserved gate oxide layer 209 on the hard mask layer 202 , the reserved gate oxide layer 209 on the stacked structure, and the reserved gate oxide layer 209 on the side walls of the fifth transition trench 2045 are etched by dry etching.

[0059] See also Figures 16 to 19As shown, in one embodiment of the present invention, a gate oxide layer 210 is formed on the hard mask layer 202 and on the groove wall of the fifth transition groove 2045. In this embodiment, silicon dioxide is deposited on the hard mask layer 202 and on the groove wall of the fifth transition groove 2045 by chemical vapor deposition or plasma enhanced chemical vapor deposition or rapid thermal oxidation, thereby forming a gate oxide layer 210. The formed gate oxide layer 210 covers the reserved gate oxide layer 209. After removing the reserved gate oxide layer 209, the newly grown gate oxide layer 210 has better uniformity and better thickness consistency. The part of the reserved gate oxide layer 209 left at the bottom of the fifth transition groove 2045 can avoid the occurrence of voids in the deep groove long film. After the gate oxide layer 210 is formed, the semiconductor device is annealed to diffuse the doping ions of the first doping region 104, the second doping region 105, the third doping region 106 and the fourth doping region 107, and the doping regions originally distributed in a gradient manner can be distributed in a gradual manner to form a drift region 10. In this embodiment, the ion concentration of the drift region 10 decreases along the direction close to the first type deep well region 101, and the width of the drift region 10 decreases along the direction close to the first type deep well region 101. Among them, the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 are made of the same material, so with the annealing and time, the oxides deposited at different times can merge with each other to form a more complete whole, that is, to form a field oxide layer 20.

[0060] See also Figures 18 to 20As shown, in one embodiment of the present invention, a polysilicon layer 211 is then formed on the gate oxide layer 210, and the fifth transition trench 2045 is filled. In this embodiment, polysilicon is deposited on the gate oxide layer 210 by chemical vapor deposition or plasma enhanced chemical vapor deposition, the fifth transition trench 2045 is filled, and a polysilicon film structure is formed on the gate oxide layer 210 on the hard mask layer 202. With annealing and time, the oxides deposited at different times can merge with each other to form a more complete whole, that is, to form a field oxide layer 20. Among them, the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 can be materials with different dielectric constants. In this embodiment, the dielectric constants of the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 are stepped, and can be specifically stepped down. Since the depths of the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 increase in sequence, the dielectric constant of the field oxide layer 20 in the finally formed field oxide layer 20 changes in a step-like manner along the direction perpendicular to the surface of the substrate 100. Specifically, in the direction away from the first surface of the substrate 100, the dielectric constant of the field oxide layer 20 may decrease in a step-like manner. In this embodiment, after the polysilicon layer 211 is formed, the hard mask layer 202 and the interlayer dielectric layer 201 are removed to expose the surface of the substrate 100, and the surface of the polysilicon layer 211 is made flush with the surface of the substrate 100. In this embodiment, the polysilicon layer 211 located above the hard mask layer 202, the gate oxide layer 210 located above the hard mask layer 202, the hard mask layer 202, and the interlayer dielectric layer 201 are polished and removed in sequence by chemical mechanical polishing (CMP). While the hard mask layer 202 and the interlayer dielectric layer 201 are removed by chemical mechanical polishing, the field oxide layer 20 located above the substrate 100 is also removed by synchronous polishing, and the polysilicon layer 211 located in the fifth transition trench 2045 and above the substrate 100 is also removed by synchronous polishing. The polishing stop layer of the chemical mechanical polishing is the surface of the substrate 100. After the polishing is completed, the surfaces of the substrate 100, the shallow trench isolation structure 103, the field oxide layer 20 and the polysilicon layer 211 are flush, as shown in FIG. Fig. 20 After the grinding is completed, the surface of the drift region 10 is also exposed.

[0061] See also Fig. 20As shown, in one embodiment of the present invention, the present invention provides a semiconductor structure, the semiconductor structure includes a substrate 100, a field oxide layer 20, a drift region 10 and a polysilicon layer 211. A device groove is provided in the substrate 100, and the groove wall of the device groove is embodied as the groove wall of the substrate 100 that accommodates the field oxide layer 20. The device groove is not formed at one time, but is gradually formed along with the process of forming the field oxide layer 20. In this embodiment, the field oxide layer 20 is provided on the groove wall of the device groove, the field oxide layer 20 has a stepped structure, and the stepped structure width of the field oxide layer 20 decreases along the direction away from the first surface of the substrate 100. The substrate 100 has a first surface and a second surface, the first surface is a surface for forming the fifth transition groove 2045, and the first surface is away from the first type of deep well region 101, and the second surface is close to the first type of deep well region 101. In the present embodiment, the drift region 10 is disposed in the substrate 100, the drift region 10 is connected to the field oxide layer 20, and the drift region 10 is wrapped outside the field oxide layer 20, wherein the width of the drift region 10 decreases along the direction away from the first surface of the substrate 100, and the ion doping concentration of the drift region 10 decreases. In the present embodiment, the polysilicon layer 211 is filled in the device trench, and the polysilicon layer 211 is connected to the field oxide layer 20. Specifically, the polysilicon layer 211 is filled in the fifth transition trench 2045.

[0062] See also Figure 20 to Figure 22As shown, in one embodiment of the present invention, based on the semiconductor structure provided by the present invention, a semiconductor device is further formed. After forming the polysilicon layer 211, a first well region 109 and a second well region 110 are formed in the substrate 100. In this embodiment, trivalent ions, such as boron ions, are injected into the substrate 100 to form the first well region 109. Pentavalent ions, such as phosphorus ions, are injected into the substrate 100 to form the second well region 110. In this embodiment, the first well region 109 extends along a direction perpendicular to the first surface of the substrate 100 and extends to the surface of the second type of deep well region 102. The second well region 110 extends along a direction perpendicular to the first surface of the substrate 100 and extends to the surface of the first type of deep well region 101. Then, an electrode doping region 111 is formed in the second well region 110 and in the drift region 10. In this embodiment, pentavalent ions, such as phosphorus ions, are injected into the second well region 110 and the drift region 10 to form the electrode doping region 111. A base doping region 112 is formed in the first well region 109. In this embodiment, trivalent ions, such as boron ions, are injected into the first well region 109 to form a base doping region 112. In this embodiment, the depth of the electrode doping region 111 in the substrate 100 is less than the depth of the shallow trench isolation structure 103 in the substrate 100. In this embodiment, the cross-sectional area of ​​the first type deep well region 101 and the semiconductor device are equal, the second type deep well region 102 is rectangular, the body region 108 is arranged in the second type deep well region 102, and the body region 108 is a rectangular shape distributed at the same center as the second type deep well region 102. In this embodiment, the first well region 109 and the second well region 110 are distributed in a U-shaped shape, wherein the polysilicon layer 211 is rectangular, and specifically can be a square, and the center of the polysilicon layer 211 is the symmetry center of the semiconductor device.

[0063] See also Figure 21 to Figure 23As shown, in one embodiment of the present invention, a silicide layer 113 is then formed in the electrode doping region 111 and the base doping region 112, as well as in the polysilicon layer 211. In this embodiment, a metal can be deposited on the substrate 100 by physical vapor deposition (PVD), such as depositing metal materials such as cobalt, titanium and nickel, to form a metal layer. Then, the metal layer is annealed to react the silicon substrate and the metal to form a silicide layer 113. In this embodiment, the silicide layer 113 is formed on the upper part of the electrode doping region 111 and the base doping region 112. After the silicide layer 113 is formed, a contact electrode 400 is formed on the silicide layer 113, thereby forming an electrical connection structure of the semiconductor device. In this embodiment, the contact electrode 400 is a contact plug (CT). In this embodiment, the contact electrode 400 connected to the silicide layer 113 on the polysilicon layer 211 is a gate G. The contact electrode 400 connected to the silicide layer 113 in the second well region 110 is the source S. The contact electrode 400 connected to the silicide layer 113 in the first well region 109 is the base B. The contact electrode 400 connected to the silicide layer 113 in the drift region 10 is the drain D. In this embodiment, the drain D is located between the base B and the gate G, and the base B is located between the drain D and the source S. The present invention does not limit the specific use of the semiconductor device, and the contact electrode 400 can be called according to the integrated circuit design.

[0064] The present invention provides a semiconductor device and a method for manufacturing the same, and the unexpected technical effect is that: the present invention provides a field oxide layer with a stepped structure, and is matched with a drift region with a concentration gradient, wherein the concentration gradient of the drift region decreases while the width of the region also decreases, and the cross-sectional area of ​​the field oxide layer also decreases, thereby effectively improving the voltage resistance of the semiconductor device while the area of ​​the semiconductor device remains unchanged. Moreover, the present invention can reduce the size of the device and reduce the on-resistance of the device while ensuring the longitudinal voltage resistance of the device, which can not only optimize the voltage resistance of the device, but also reduce the on-resistance of the device, and bidirectionally optimize the relationship between the voltage resistance and on-resistance of the device. Moreover, according to the method for manufacturing the semiconductor structure provided by the present invention, while forming the concentration gradient of the drift region, a field oxide layer with a stepped structure is formed, the process is mature, the molding yield of the semiconductor device can be improved, and the process controllability is high, which can effectively reduce device defects.

[0065] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein a device trench is provided in the substrate; A field oxide layer is disposed on a groove wall of the device groove, the field oxide layer has a stepped structure, and a width of the stepped structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate forming the device groove; A drift region is disposed in the substrate, the drift region is connected to the field oxide layer, and the drift region is wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; as well as A polysilicon layer is filled in the device trench, and the polysilicon layer is connected to the field oxide layer.

2. A semiconductor device according to claim 1, characterized in that: Surfaces of the field oxide layer, the drift region, the substrate, and the polysilicon layer are flush.

3. A semiconductor device according to claim 1, characterized in that: Along the direction perpendicular to the surface of the substrate, the dielectric constant of the field oxide layer changes in a step-like manner.

4. A semiconductor device according to claim 1, characterized in that: The semiconductor device comprises a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are arranged in the substrate, and the plurality of shallow trench isolation structures separate a plurality of active regions in the substrate, wherein the drift region is arranged in the active region.

5. A semiconductor device according to claim 4, characterized in that: The semiconductor device comprises: A first type deep well region is disposed in the substrate, wherein the first type deep well region and the drift region are doped with the same ion type; and A second type of deep well region is arranged in the substrate, the second type of deep well region is arranged on the first type of deep well region and connected to the first type of deep well region, wherein the drift region is arranged on the second type of deep well region and connected to the second type of deep well region, wherein the doping ion types of the second type of deep well region and the drift region are different.

6. A semiconductor device according to claim 5, characterized in that: The semiconductor device comprises a body region, wherein the body region is arranged in the second-type deep well region and connected to the drift region, wherein the body region and the second-type deep well region are doped with the same ion type.

7. A semiconductor device according to claim 6, characterized in that: The device trench passes through the body region and the first type deep well region and extends to below the first type deep well region, and the polysilicon layer extends along a direction perpendicular to the first surface and toward the second surface of the substrate, wherein the first surface and the second surface are parallel, wherein one end of the polysilicon layer is flush with the first surface, and the other end of the polysilicon layer extends to below the first type deep well region.

8. A semiconductor device according to claim 5, characterized in that: The semiconductor device comprises: a first well region, disposed in the substrate, the first well region being located in the active region outside the drift region, and the first well region being connected to the second-type deep well region; and The second well region is arranged in the substrate, the second well region is located in the active region outside the first well region, and the second well region is connected to the first type deep well region.

9. A semiconductor device according to claim 1, characterized in that: The polysilicon layer has a symmetry plane, the semiconductor device is a symmetrical structure, and the semiconductor device is symmetrical about the symmetry plane, wherein the drift region is symmetrical about the symmetry plane, and the field oxide layer is symmetrical about the symmetry plane.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: providing a substrate; Stepwise forming a device trench in the substrate, while gradually forming the device trench, forming a field oxide layer on the trench wall of the device trench, wherein the field oxide layer has a step structure, and the width of the step structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate on which the device trench is formed; While gradually forming the device trenches, gradually forming a plurality of doped regions in the substrate; After the annealing treatment, the plurality of doped regions form a drift region, wherein the drift region is connected to the field oxide layer and the drift region is wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; and The device trench is filled to form a polysilicon layer, wherein the polysilicon layer is connected to the field oxide layer.

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