High-mobility and high-reliability oxide transistor and preparation method thereof

Abstract

The invention belongs to the field of integrated circuits and display, and provides a high-mobility and high-reliability oxide transistor and a preparation method thereof. The heterojunction structure active layer is formed by two oxide semiconductor materials with different work functions, and the transport mechanism of the heterojunction structure active layer is as follows: electrons are injected from the active layer with a relatively small work function to the active layer with a relatively large work function by selecting reasonable material types and deposition conditions; therefore, the transport current of carriers at the interface of the gate dielectric and the active layer is increased. Defects in the active layer are effectively reduced through high-temperature annealing, and the reliability of the oxide transistor is improved. After high-temperature annealing, the work functions of the two oxide semiconductor materials in the heterojunction structure are both increased, and electrons are maintained to be injected from the active layer with the smaller work function to the active layer with the larger work function, so that the mobility of the device is not degraded. According to the invention, the technical bottleneck of mutual exclusion of the mobility and reliability of the oxide transistor is solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits and displays, and in particular to a high-mobility and high-reliability oxide transistor and a preparation method thereof. Background Art

[0002] Oxide transistors have the advantages of low off-state current, high mobility, high consistency, and compatibility with silicon-based processes, and are increasingly attracting attention in the field of integrated circuits and displays. In order to further explore the application potential of oxide transistors, researchers have improved the electrical performance of oxide transistors, especially the field effect mobility, by developing new materials, new processes, and new structures. However, there is an exclusive relationship between the mobility and reliability of oxide transistors. Improving mobility will lead to reliability degradation. The main mechanism is as follows: The active layer of the oxide transistor is an oxide semiconductor thin film material. The oxygen vacancy content of the active layer can be increased by adjusting the film composition and process conditions. The carrier (electron) concentration of the active layer is positively correlated with the oxygen vacancy content. Increasing the carrier concentration can improve the mobility of the oxide transistor, so the increase or decrease of oxygen vacancies is beneficial to improving the mobility characteristics of the oxide transistor. However, under conditions such as polarization and temperature increase, the electrons in the oxygen vacancies transition to become free electrons and participate in current transport, which will cause the threshold voltage of the oxide transistor to drift, manifested as reliability degradation.

[0003] Currently, the mutually exclusive problems of mobility and reliability have become the main technical bottleneck limiting the widespread application of oxide transistors, and solving this problem is very important. Summary of the invention

[0004] In view of the above problems, the present invention provides a high-mobility and high-reliability oxide transistor and a preparation method thereof. Two oxide semiconductor materials with different work functions are used to form an active layer, the active layer is a heterojunction structure active layer, and the oxide transistor is a heterojunction structure oxide transistor. The present invention selects reasonable material types and deposition conditions so that the heterojunction structure active layer has the following transport mechanism: electrons are injected from the active layer with a smaller work function to the active layer with a larger work function, thereby increasing the transport current of carriers at the interface between the gate dielectric and the active layer. On the basis of using a heterojunction structure active layer, the present invention effectively reduces defects in the active layer, including oxygen vacancies and interface defects, through high-temperature annealing, to achieve the improvement of the reliability of the oxide transistor. It should be noted that after high-temperature annealing, the work functions of the two oxide semiconductor materials in the heterojunction structure are both increased, and the transport behavior of electrons being injected from the active layer with a smaller work function to the active layer with a larger work function is maintained, so that the device mobility does not degrade. Therefore, the technical solution proposed by the present invention solves the mutually exclusive technical bottlenecks of the mobility and reliability of oxide transistors.

[0005] A high-mobility and high-reliability oxide transistor, the oxide transistor is a bottom-gate structure oxide transistor, comprising a substrate, a gate electrode, a gate dielectric, an active layer and a source-drain electrode; the gate electrode is located on the substrate, the gate dielectric is located on the gate electrode, the active layer is located on the gate dielectric, and the source-drain electrode is located on the active layer; the active layer is an oxide heterojunction structure active layer, comprising an upper active layer and a lower active layer, the upper active layer and the lower active layer are two oxide semiconductor materials with different work functions, and the work function of the lower active layer is greater than the work function of the upper active layer.

[0006] A high-mobility and high-reliability oxide transistor, the oxide transistor is a top-gate structure oxide transistor, comprising a substrate, a gate electrode, a gate dielectric, an active layer and a source-drain electrode; the source-drain electrode is located on the substrate, the active layer is located on the source-drain electrode, the gate dielectric is located on the active layer, and the gate electrode is located on the gate dielectric; the active layer is an oxide heterojunction structure active layer, comprising an upper active layer and a lower active layer, the upper active layer and the lower active layer are two oxide semiconductor materials with different work functions, and the work function of the lower active layer is smaller than the work function of the upper active layer.

[0007] Furthermore, the oxide semiconductor is a semiconductor film of zinc oxide, gallium oxide, indium oxide, tin oxide, or a semiconductor film doped with zinc oxide, gallium oxide, indium oxide, or tin oxide. The thickness of the lower and upper active layer films is 1-300 nanometers.

[0008] Furthermore, for semiconductor films doped with zinc oxide, doped with gallium oxide, doped with indium oxide, and doped with tin oxide, the doping elements are one or more combinations of metal elements such as hafnium, tungsten, aluminum, molybdenum, titanium, non-metal elements such as silicon, carbon, phosphorus, or rare earth elements such as lanthanum and erbium, wherein the content (mass fraction) of the doping elements is 0.1%-50%.

[0009] Furthermore, the gate electrode is a combination of one or more metals such as aluminum, titanium, molybdenum, etc., or a combination of one or more transparent conductive films such as indium tin oxide, aluminum zinc oxide, etc., or a combination of metal and transparent conductive film, and the thickness of the gate electrode is 3-1000 nanometers.

[0010] Furthermore, the gate dielectric layer is one or a combination of silicon oxide, aluminum oxide, hafnium oxide, and titanium oxide, and the thickness of the gate dielectric layer is 3-1000 nanometers.

[0011] Furthermore, the source and drain electrodes are a combination of one or more metals such as aluminum, titanium, molybdenum, etc., or a combination of one or more transparent conductive films such as indium tin oxide, aluminum zinc oxide, etc., or a combination of metal and transparent conductive film, and the thickness of the source and drain electrodes is 3-1000 nanometers.

[0012] At the same time, the present invention provides a method for preparing an oxide transistor with high mobility and high reliability, including the preparation of a bottom-gate structure oxide transistor and the preparation of a top-gate structure oxide transistor. The preparation steps of the bottom-gate structure oxide transistor are as follows:

[0013] (1) pre-cleaning the substrate;

[0014] (2) depositing a gate electrode film on the substrate surface and forming a gate electrode structure by photolithography and etching processes;

[0015] (3) depositing a gate dielectric film on the gate electrode and forming a gate dielectric structure by photolithography and etching processes;

[0016] (4) depositing an active layer thin film on the gate dielectric layer, and forming an active layer structure by photolithography and etching processes;

[0017] (5) depositing a source-drain electrode film on the active layer, and forming a source-drain electrode structure by photolithography and etching processes;

[0018] (6) The device is treated by annealing process.

[0019] The steps for preparing a top-gate oxide transistor are as follows:

[0020] (1) Pre-cleaning the substrate;

[0021] (2) depositing a source-drain electrode thin film on the substrate surface, and forming a source-drain electrode structure by photolithography and etching processes;

[0022] (3) depositing an active layer thin film on the source and drain electrodes, and forming an active layer structure by photolithography and etching processes;

[0023] (4) depositing a gate dielectric film on the active layer and forming a gate dielectric structure by photolithography and etching processes;

[0024] (5) depositing a gate electrode film on the gate dielectric and forming a gate electrode structure by photolithography and etching processes;

[0025] (6) The device is treated by annealing process.

[0026] Furthermore, the annealing method used in the annealing process is a combination of one or more of tubular furnace annealing, rapid thermal annealing, and hot plate annealing. The annealing atmosphere is a combination of one or more of oxygen, air, argon, vacuum, nitrogen, etc., the annealing temperature is 300-1000 degrees Celsius, and the annealing time is 0.01-100 hours.

[0027] Advantages of the present invention:

[0028] First, the present invention proposes a method for preparing an oxide transistor, which combines a heterojunction structure oxide semiconductor active layer with high-temperature annealing to achieve directional regulation of the energy band of the oxide semiconductor film at the material level, and maintains the injection of electrons from the active layer with a smaller work function to the active layer with a larger work function on the basis of reducing oxygen vacancies in the film, thereby significantly improving the reliability of the device while maintaining the mobility from being significantly degraded, thereby achieving the purpose of breaking through the mutually exclusive technical bottleneck of mobility and reliability. The oxide transistor prepared by the present invention has excellent electrical properties and reliability, and can break through the mutually exclusive bottleneck between the mobility and reliability of oxide transistors, which will promote my country's integrated circuit and display industries to occupy the high ground of oxide transistor and circuit technology. Secondly, the present invention is based on traditional oxide semiconductor materials and oxide transistor preparation technology, with a simple process, convenient preparation, and a low threshold for the application and promotion of related technologies. Finally, the relevant technology of the present invention has been experimentally verified, and the mobility of the developed oxide transistor exceeds 80cm 2 V -1 s -1 , the threshold voltage drift under the polarized bias (NBIS) condition is -0.6V ( Figure 4 ). BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the structure of a high-mobility and high-reliability oxide transistor device with a bottom-gate structure.

[0030] Figure 2 Schematic diagram of the structure of a high-mobility and high-reliability oxide transistor device with a top-gate structure.

[0031] Figure 3 Schematic diagram of the active layer of the heterojunction structure.

[0032] Figure 4 The electrical performance of the high-mobility and high-reliability oxide transistor prepared by the present invention, wherein (a) is the oxide transistor polarized light bias voltage (NBIS) reliability, and (b) is the oxide transistor field effect mobility versus gate electrode voltage curve.

[0033] 1—substrate; 2—gate electrode; 3—gate dielectric; 4—upper active layer; 5—lower active layer; 6—source-drain electrode; 7—lower active layer in the heterojunction structure active layer; 8—upper active layer in the heterojunction structure active layer. DETAILED DESCRIPTION

[0034] The present invention is further described below by examples in conjunction with the accompanying drawings of the specification. It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the attached claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0035] The high-mobility and high-reliability oxide transistor proposed in the present invention includes a substrate, a gate electrode, a gate dielectric, an active layer, and a source-drain electrode. The oxide transistor includes two device types, namely, a bottom-gate oxide transistor and a top-gate oxide transistor. For a bottom-gate oxide transistor, such as Figure 1 As shown, the oxide transistor is prepared on a substrate 1 such as silicon, glass or polyimide (PI), a gate electrode 2 is located on the substrate 1, a gate dielectric 3 is located on the gate electrode 2, an oxide heterojunction active layer, namely an upper active layer 4 and a lower active layer 5 are located on the gate dielectric 3, and a source-drain electrode 6 is located on the oxide heterojunction active layer. For a top-gate oxide transistor, as shown in FIG. Figure 2 As shown, the oxide transistor is prepared on a substrate 1 such as silicon, glass or polyimide (PI), source and drain electrodes 6 are located on the substrate, active layers 4 and 5 are located on the source and drain electrodes 6, gate dielectric 3 is located on the active layer, and gate electrode 2 is located on the gate dielectric 3. After the device is prepared, it is treated by a high temperature annealing process.

[0036] Taking the bottom-gate oxide transistor as an example, the device uses a heterojunction structure active layer, such as Figure 3 As shown, the lower active layer 7 is an indium oxide film doped with gallium, that is, an indium gallium oxygen film, and the upper active layer 8 is an indium oxide film doped with gallium and zinc, that is, an indium gallium zinc oxygen film. The process parameters are adjusted so that the work function of the lower active layer film needs to be greater than the work function of the upper active layer. The specific preparation steps of the heterojunction structure active layer are as follows:

[0037] (1) Depositing a lower layer of indium gallium oxygen thin film using a magnetron sputtering process, completing the startup steps of the sputtering equipment, opening the sputtering chamber, and fixing the substrate on the sputtering equipment tray;

[0038] (2) Close the reaction chamber, turn on the mechanical pump and molecular pump, and pre-pump the back gas pressure of the sputtering equipment chamber to 1×10 -4 -5×10 -4 Pa;

[0039] (3) When the back gas pressure reaches the required value, introduce argon and oxygen into the sputtering equipment chamber, adjust the pressure control valve, and set the chamber pressure to 1 Pa;

[0040] (4) Turn on the tray rotation button and set the speed to 10 rpm;

[0041] (5) Turn on the RF power supply and pre-sputter for 2 minutes. The sputtering target used in the magnetron sputtering process is a ceramic target, and the sputtering temperature is room temperature;

[0042] (6) Turn the magnetron sputtering target baffle and sputter for 10 minutes;

[0043] (7) After the deposition of the lower layer of InGaO thin film is completed, turn off the RF power supply, remove the substrate and complete the shutdown step;

[0044] (8) depositing an upper layer of InGaZnO thin film by magnetron sputtering, and repeating steps (1) to (7); or depositing an upper layer of InGaZnO thin film by atomic layer deposition, completing the startup step of the atomic layer deposition equipment, opening the reaction chamber, and fixing the substrate in the reaction chamber of the atomic layer deposition equipment. If the upper layer of InGaZnO thin film is deposited by atomic layer deposition, then continuing with subsequent steps (9) to (12);

[0045] (9) Pumping the back bottom gas pressure of the atomic layer deposition equipment reaction chamber to 20 Pa;

[0046] (10) When the back pressure reaches the required value, nitrogen is introduced into the reaction chamber and the reaction temperature is set to 120 degrees Celsius;

[0047] (11) The reaction sources are introduced into the reaction chamber in sequence to start depositing the upper InGaZnO film.

[0048] (12) After the deposition of the upper InGaZnO film is completed, the substrate is removed and the shutdown step is completed.

[0049] Based on the above-mentioned heterojunction structure active layer, the specific preparation process of the high-mobility and high-reliability oxide transistor proposed by the present invention is as follows:

[0050] (1) The substrate was ultrasonically cleaned in acetone, ethanol, and deionized water for 5 minutes.

[0051] (2) depositing an indium tin oxide thin film on a glass substrate as a gate electrode of an oxide transistor by a magnetron sputtering process, the film thickness is 100 nanometers, and the specific sputtering process conditions are as follows: the atmosphere is argon gas, the gas flow rate is 90, the chamber pressure is 1 Pa, and the temperature is room temperature;

[0052] (3) The indium tin oxide gate electrode pattern is defined by photolithography and a wet etching process is used to form the indium tin oxide gate electrode structure.

[0053] (4) Atomic layer deposition (ALD) was used to deposit aluminum oxide film as the gate dielectric of the oxide transistor. The film thickness was 7 nanometers. The specific ALD process conditions were as follows: the reaction sources were trimethylaluminum and deionized water, the reaction temperature was 120 degrees Celsius, and the number of reaction cycles was 69.

[0054] (5) The aluminum oxide gate dielectric pattern is defined by photolithography and a wet etching process is used to form the aluminum oxide gate dielectric structure.

[0055] (6) A magnetron sputtering process and an atomic layer deposition process are used to deposit a heterojunction structure active layer. The specific deposition process is as described above, wherein the thickness of the lower active layer is 6 nanometers, and the thickness of the upper active layer is 20 nanometers.

[0056] (7) The active layer pattern is defined by photolithography and wet etching.

[0057] (8) using a magnetron sputtering process to deposit an indium tin oxide thin film as the source and drain electrodes of the oxide transistor, the film thickness is 100 nanometers, and the specific sputtering process conditions are as follows: the atmosphere is argon gas, the gas flow rate is 90, the chamber pressure is 1 Pa, and the temperature is room temperature;

[0058] (9) defining the indium tin oxygen source and drain electrode pattern by using a photolithography process, and forming the indium tin oxygen source and drain electrode structure by using a wet etching process;

[0059] (10) The prepared oxide transistor is treated using a tube furnace, with an annealing temperature of 500 degrees Celsius, an annealing time of 0.5 hours, and an annealing atmosphere of oxygen.

[0060] The experimental results show that the mobility of the oxide transistor prepared by the method of the present invention exceeds 80 cm 2 V -1 s -1 , the threshold voltage drift under the polarized bias (NBIS) condition is -0.6V, such as Figure 4 shown.

[0061] Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A high-mobility and high-reliability oxide transistor, characterized in that: The oxide transistor is a bottom-gate structure oxide transistor, comprising a substrate, a gate electrode, a gate dielectric, an active layer and a source-drain electrode; The gate electrode is located on the substrate, the gate dielectric is located on the gate electrode, the active layer is located on the gate dielectric, and the source and drain electrodes are located on the active layer; The active layer is an oxide heterojunction structure active layer, including an upper active layer and a lower active layer. The upper active layer and the lower active layer are two oxide semiconductor materials with different work functions, and the work function of the lower active layer is greater than that of the upper active layer.

2. A high-mobility and high-reliability oxide transistor, characterized in that: The oxide transistor is a top-gate structure oxide transistor, comprising a substrate, a gate electrode, a gate dielectric, an active layer and a source-drain electrode; The source and drain electrodes are located on the substrate, the active layer is located on the source and drain electrodes, the gate dielectric is located on the active layer, and the gate electrode is located on the gate dielectric; The active layer is an oxide heterojunction structure active layer, including an upper active layer and a lower active layer. The upper active layer and the lower active layer are two oxide semiconductor materials with different work functions, and the work function of the lower active layer is smaller than that of the upper active layer.

3. The high-mobility and high-reliability oxide transistor according to claim 1 or 2, characterized in that: The oxide semiconductor material is a semiconductor film of zinc oxide, gallium oxide, indium oxide, tin oxide, or a semiconductor film doped with zinc oxide, gallium oxide, indium oxide, or tin oxide. The thickness of the lower active layer and the upper active layer are both 1-300 nanometers.

4. The high-mobility and high-reliability oxide transistor according to claim 3, characterized in that: In the semiconductor film doped with zinc oxide, gallium oxide, indium oxide, or tin oxide, the doping elements are one or a combination of hafnium, tungsten, aluminum, molybdenum, titanium, silicon, carbon, phosphorus, lanthanum, and erbium, and the mass fraction of the doping elements is 0.1%-50%.

5. The high-mobility and high-reliability oxide transistor according to claim 1 or 2, characterized in that: The gate electrode is a combination of one or more of aluminum, titanium, and molybdenum, or a combination of one or more of transparent conductive films such as indium tin oxide and aluminum zinc oxide, or a combination of metal and transparent conductive film, and the thickness of the gate electrode is 3-1000 nanometers.

6. The high-mobility and high-reliability oxide transistor according to claim 1 or 2, characterized in that: The gate dielectric layer is one or a combination of silicon oxide, aluminum oxide, hafnium oxide, and titanium oxide, and the thickness of the gate dielectric layer is 3-1000 nanometers.

7. The high-mobility and high-reliability oxide transistor according to claim 1 or 2, characterized in that: The source-drain electrode is a combination of one or more of aluminum, titanium, and molybdenum, or a combination of one or more of transparent conductive films such as indium tin oxide and aluminum zinc oxide, or a combination of metal and transparent conductive film, and the thickness of the source-drain electrode is 3-1000 nanometers.

8. A method for preparing a high-mobility and high-reliability oxide transistor according to claim 1, characterized in that: The following steps are involved: (1) pre-cleaning the substrate; (2) depositing a gate electrode film on the substrate surface and forming a gate electrode structure by photolithography and etching processes; (3) depositing a gate dielectric film on the gate electrode and forming a gate dielectric structure by photolithography and etching processes; (4) depositing an active layer thin film on the gate dielectric layer, and forming an active layer structure by photolithography and etching processes; (5) depositing a source-drain electrode film on the active layer, and forming a source-drain electrode structure by photolithography and etching processes; (6) The device obtained in step (5) is treated by an annealing process.

9. A method for preparing a high-mobility and high-reliability oxide transistor according to claim 2, characterized in that: The following steps are involved: (1) pre-cleaning the substrate; (2) depositing a source-drain electrode thin film on the substrate surface, and forming a source-drain electrode structure by photolithography and etching processes; (3) depositing an active layer thin film on the source and drain electrodes, and forming an active layer structure by photolithography and etching processes; (4) depositing a gate dielectric film on the active layer and forming a gate dielectric structure by photolithography and etching processes; (5) depositing a gate electrode film on the gate dielectric and forming a gate electrode structure by photolithography and etching processes; (6) The device obtained in step (5) is treated by an annealing process.

10. The preparation method according to claim 8 or 9, characterized in that: The annealing method of the annealing process is a combination of one or more of tubular furnace annealing, rapid thermal annealing, and hot plate annealing; the annealing atmosphere is a combination of one or more of oxygen, air, argon, vacuum, nitrogen and the like; the annealing temperature is 300-1000 degrees Celsius, and the annealing time is 0.01-100 hours.

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