Oxide thin film transistor, display panel and display device

Abstract

The invention discloses an oxide thin film transistor, a display panel and a display device. The oxide thin film transistor comprises a substrate and a semiconductor layer which are arranged in a stacked mode. The semiconductor layer comprises a first region, and a second region and a third region which are positioned on two opposite sides of the first region, and the second region and the third region both comprise doped ions; the semiconductor layer further comprises barrier structures, the barrier structures are used for blocking doping ions of the second area and the third area, the barrier structures are arranged on the first edge and the second edge of the first area, the first edge is the edge where the first area is connected with the second area, and the second edge is the edge where the first area is connected with the third area. The barrier structure at least penetrates through the semiconductor layer in the thickness direction of the semiconductor layer. The oxide thin film transistor can reduce diffusion of ions into the first region of the semiconductor layer in a conductive process, thereby reducing deterioration of the thin film transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of thin film transistors, and in particular to an oxide thin film transistor, a display panel and a display device. Background Art

[0002] Oxide thin-film transistors have become the first choice for large-size, high-resolution, low-power, and narrow-border display panels due to their advantages such as high electron mobility, low off-state current, and simple preparation process.

[0003] However, the dopant injected into the semiconductor layer will diffuse during the conduction process, and the ions in the dopant will diffuse into the channel in the semiconductor layer, which may deteriorate the driving stability of the thin film transistor and further affect the yield of the display panel. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides an oxide thin film transistor, which can reduce the diffusion of ions into the first region of the semiconductor layer during the conduction process, thereby reducing the degradation of the thin film transistor.

[0005] The present invention also aims to provide a display panel having the above oxide thin film transistor.

[0006] The present invention also aims to provide a display device having the above display panel.

[0007] An oxide thin film transistor according to an embodiment of the first aspect of the present invention includes a substrate and a semiconductor layer stacked in layers; The semiconductor layer includes a first region, and a second region and a third region located on opposite sides of the first region, wherein the second region and the third region both include doping ions; The semiconductor layer also includes a blocking structure, which is used to block the doped ions in the second region and the third region. The blocking structure is arranged at a first edge and a second edge of the first region, the first edge is an edge where the first region is connected to the second region, and the second edge is an edge where the first region is connected to the third region. Along the thickness direction of the semiconductor layer, the blocking structure at least penetrates the semiconductor layer.

[0008] According to some embodiments of the present invention, the present invention further includes a gate stacked on a side of the semiconductor layer facing away from the substrate, wherein a projection of the gate on the semiconductor layer covers the first region.

[0009] According to some embodiments of the present invention, the barrier structure includes a first barrier structure provided at the first edge and a second barrier structure provided at the second edge; Along a first direction, the length of the first barrier structure, the length of the second barrier structure, and the length of the semiconductor layer are all the same, and the first direction is a direction perpendicular to the second region to the third region. According to some embodiments of the present invention, the barrier structure includes a first barrier structure provided at the first edge and a second barrier structure provided at the second edge; Along a first direction, at least one of a length of the first barrier structure and a length of the second barrier structure is smaller than a length of the semiconductor layer, and the first direction is a direction perpendicular to the second region to the third region. According to some embodiments of the present invention, at least one of the first barrier structure and the second barrier structure is a strip barrier structure, and in the first direction, at least one end of the strip barrier structure is spaced a certain distance from an edge of the semiconductor layer. According to some embodiments of the present invention, at least one of the first barrier structure and the second barrier structure includes a plurality of barrier portions, and the plurality of barrier portions are spaced apart along the first direction. According to some embodiments of the present invention, one of the first barrier structure and the second barrier structure is a strip barrier structure, and the other includes a plurality of barrier portions, and the plurality of barrier portions are spaced apart along the first direction. According to some embodiments of the present invention, an insulating layer is further included and stacked between the semiconductor layer and the gate, and the barrier structure at least penetrates the semiconductor layer and the insulating layer. According to some embodiments of the present invention, the material of the barrier structure is the same as that of the gate. According to some embodiments of the present invention, a wiring layer is further included on a side of the gate facing away from the substrate, and the barrier structure at least penetrates from a side of the semiconductor layer facing the substrate to a side of the wiring layer facing away from the substrate. According to some embodiments of the present invention, the material of the barrier structure is the same as the material of the routing layer. In the present application, an oxide thin film transistor is provided, wherein a barrier structure is provided at a first edge of a first region connected to the second region and a second edge connected to the third region, so that doped ions provided in the second region and the third region are not easily diffused to the first region during the conduction process, the doped ions in the second region and the third region enable the second region and the third region to be conductive, and the electrical conduction state of the first region is stably controlled by the gate. The barrier structure at least penetrates the semiconductor layer in the thickness direction of the semiconductor layer, so that in the thickness direction of the semiconductor layer, doped ions are not easily diffused from the second region and the third region to the first region, and the first region is not easily conductive through doped ions at any position in the thickness direction of the semiconductor layer, and the electrical conduction state of the first region can be stably controlled by the gate.

[0010] A display panel according to an embodiment of the second aspect of the present invention comprises the oxide thin film transistor in the above embodiment.

[0011] The display panel according to the embodiment of the present invention improves the control stability of the display panel by adopting the oxide thin film transistor in the above embodiment.

[0012] A display device according to an embodiment of the third aspect of the present invention includes the display panel in the above embodiment.

[0013] According to the display device of the embodiment of the present invention, the control stability of the display device is improved by adopting the display panel in the above embodiment.

[0014] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of diffusion of doping ions in a semiconductor layer into a first region in the prior art; Figure 2 is a top view of an embodiment of an oxide thin film transistor according to an embodiment of the present application; Figure 3 is a cross-sectional view of an embodiment of an oxide thin film transistor according to an embodiment of the present application; Figure 4 is a top view of another embodiment of an oxide thin film transistor according to an embodiment of the present application; Figure 5 is a top view of another embodiment of an oxide thin film transistor according to an embodiment of the present application; Figure 6 is a top view of another embodiment of the oxide thin film transistor according to the embodiment of the present application; Figure 7is a cross-sectional view of another embodiment of an oxide thin film transistor according to an embodiment of the present application; Figure 8 is a cross-sectional view of another embodiment of the oxide thin film transistor according to the embodiment of the present application.

[0016] Reference numerals: Oxide thin film transistor 100, Substrate 10, Semiconductor layer 20, first region 21, first edge 21a, second edge 21b, second region 22, third region 23, doping ions 24, barrier structure 25, first barrier structure 251, second barrier structure 252, barrier portion 253, The gate 30 , the insulating layer 40 , the wiring layer 50 , the protection layer 60 , and the buffer layer 70 . DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0018] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific processes and examples of materials, but those of ordinary skill in the art can be aware of the applicability of other processes and / or the use of other materials.

[0019] Thin Film Transistor (TFT) is a special transistor, which is characterized by the use of thin-layer technology to deposit semiconductor materials and other materials on a substrate to form a transistor. Thin film transistor technology is mainly used in the field of liquid crystal display (LCD) and is one of the core components of modern display technology. In the display panel of the LCD, each pixel is equipped with a thin film transistor, which controls the arrangement of liquid crystal molecules by adjusting the current passing through the pixel, thereby changing the amount of light transmitted by the pixel to achieve grayscale or color changes. This active control mechanism enables the liquid crystal display area to provide high resolution, high contrast, fast response time and good color reproduction, making it the preferred display technology for televisions, computer monitors, mobile phone screens and other portable electronic devices.

[0020] The basic structure of thin film transistors and the functions of each structure are as follows: Substrate: Thin-film transistors can be built on different types of substrates, such as glass (for LCD screens) or flexible materials (such as plastic, for bendable display technology). The choice of substrate affects the performance and application scenarios of the display; Gate Electrode: Located on the top layer, when voltage is applied to the gate, an electric field is generated through the gate insulating layer; Gate Insulator: prevents current from flowing directly from the gate to the source and drain, while allowing the electric field to act on the semiconductor layer; Semiconductor Layer: Usually composed of amorphous silicon (a-Si), microcrystalline silicon (poly-Si) or oxide materials (such as IGZO), responsible for transmitting the electric field effect generated by the gate and controlling the conductivity state of the channel area; Source Electrode and Drain Electrode: These two electrodes define the inflow and outflow channels of current and are in contact with the semiconductor layer; Protection layer (ILD) and contact holes: The protection layer covers the semiconductor layer and leaves contact holes so that the source and drain electrodes can be connected to the pixel electrodes on the upper layer.

[0021] The working principle of thin film transistors is based on the electric field effect. The specific process is as follows: Non-conducting state: When no voltage is applied, the channel of the semiconductor layer is not conductive, no current flows between the source and drain, the pixel is in the off state, and light is not transparent; On state: When a positive voltage is applied to the gate, the electric field penetrates the gate insulating layer, changes the charge distribution in the area below the semiconductor layer, and forms a conductive channel, allowing current to flow between the source and drain. The magnitude of this current depends on the gate voltage, so the current intensity passing through the pixel can be accurately controlled, and then the brightness and darkness of the pixel can be controlled to display the image.

[0022] In the prior art, it is usually necessary to perform ion doping on the semiconductor layer so that both sides of the channel region of the semiconductor layer can conduct electricity. Figure 1 However, the dopant ions injected into the semiconductor layer will diffuse during the conduction process. The ions in the dopant diffuse into the channel in the semiconductor layer, so that when no voltage is applied to the gate, the channel area may also be conductive, which may cause the driving stability of the thin film transistor to deteriorate, thereby affecting the yield of the display panel.

[0023] Based on this, the present invention proposes an oxide thin film transistor 100 , which can reduce the diffusion of ions into the first region 21 of the semiconductor layer 20 during the conduction process, thereby reducing the degradation of the thin film transistor.

[0024] Figure 2-Figure 8 FIG. 1 is a schematic diagram of the structure of an oxide thin film transistor 100 according to an embodiment of the present invention. Figure 2 and Figure 3 The oxide thin film transistor 100 includes a substrate 10 and a semiconductor layer 20 which are stacked; wherein the substrate 10 is used for support, and the substrate 10 can be glass or a flexible material (for example, plastic, etc.). The semiconductor layer 20 is used to transmit an electric field effect to control the conductivity state of the first region 21. The semiconductor layer 20 can be crystalline silicon (a-Si), microcrystalline silicon (poly-Si) or an oxide material (such as IGZO), etc.

[0025] Reference Figure 2 and Figure 3 The semiconductor layer 20 includes a first region 21, which is a channel region in the semiconductor layer 20. A second region 22 and a third region 23 are located on opposite sides of the first region 21, and the source and the drain are respectively arranged in the second region 22 and the third region 23. The first region 21 separates the second region 22 and the third region 23. Both the second region 22 and the third region 23 include doping ions 24, so that the second region 22 and the third region 23 can conduct electricity.

[0026] Reference Figure 2 and Figure 3 The semiconductor layer 20 further includes a blocking structure 25, which is used to block the doping ions 24 in the second region 22 and the third region 23. The blocking structure 25 is provided at the first edge 21a and the second edge 21b of the first region 21, wherein the first edge 21a is the edge where the first region 21 and the second region 22 meet, and the second edge 21b is the edge where the first region 21 and the third region 23 meet. In this way, the first region 21 becomes a blocking region, and the ions doped in the second region 22 and the third region 23 are not easily diffused to the first region 21 during the conduction process, thereby avoiding the degradation of the thin film transistor caused by the conduction of the first region 21, so that the electrical conduction state of the first region 21 can be stably controlled by the gate 30.

[0027] Reference Figure 3 , along the thickness direction of the semiconductor layer 20, the barrier structure 25 at least penetrates the semiconductor layer 20. In this way, in the thickness direction of the semiconductor layer 20, the doping ions 24 are not easy to diffuse from the second region 22 and the third region 23 to the first region 21, so that the electrical conduction state of the first region 21 can be stably controlled by the gate 30.

[0028] Therefore, refer to Figure 2 and Figure 3 According to the oxide thin film transistor 100 of the present invention, by providing a barrier structure 25 at the first edge 21a of the first region 21 connected to the second region 22 and the second edge 21b connected to the third region 23, the doping ions 24 provided in the second region 22 and the third region 23 are not easily diffused to the first region 21 during the conduction process, the doping ions 24 in the second region 22 and the third region 23 enable the second region 22 and the third region 23 to be conductive, and the electrical conduction state of the first region 21 is stably controlled by the gate 30. The barrier structure 25 at least penetrates the semiconductor layer 20 in the thickness direction of the semiconductor layer 20, so that in the thickness direction of the semiconductor layer 20, the doping ions 24 are not easily diffused from the second region 22 and the third region 23 to the first region 21, and the first region 21 is not easily conductive through the doping ions 24 at any position in the thickness direction of the semiconductor layer 20, and the electrical conduction state of the first region 21 can be stably controlled by the gate 30.

[0029] It is understandable that the barrier structure 25 is conductive, so that under the action of the electric field, the electrons in the first region 21 can pass through the barrier structure 25 and conduct the first region 21. The barrier structure 25 can be made of a conductive material, such as metal.

[0030] In some embodiments of the present invention, reference Figure 3 The oxide thin film transistor 100 further includes a gate 30 stacked on a side of the semiconductor layer 20 facing away from the substrate 10 , and a projection of the gate 30 on the semiconductor layer 20 covers the first region 21 .

[0031] By setting the gate 30, when a positive voltage is applied to the gate 30, the generated electric field can change the charge distribution of the first region 21 of the semiconductor layer 20, forming a conductive channel, and the current can flow from the second region 22 to the third region 23 via the first region 21. The projection of the gate 30 on the semiconductor layer 20 covers the first region 21, so that the gate 30 can block the doping ions 24 in other layers above it from diffusing into the semiconductor layer 20.

[0032] In some embodiments, the projection of the gate 30 on the semiconductor layer 20 may overlap with the first region 21 ; or, the projection area of ​​the gate 30 on the semiconductor layer 20 is larger than the area of ​​the first region 21 , and the first region 21 falls within the projection of the gate 30 on the semiconductor layer 20 .

[0033] The present application is not limited to this. In other embodiments, the projection of the gate 30 on the semiconductor layer 20 can fall into the first region 21. At this time, the two side edges of the projection of the gate 30 on the semiconductor layer 20 along the direction from the second region 22 to the third region 23 are spaced apart from the first edge 21a and the second edge 21b by a first spacing and a second spacing, respectively, and the sum of the first spacing and the second spacing is less than half of the distance between the first edge 21a and the second edge 21b.

[0034] In some embodiments of the present invention, reference Figure 4 The barrier structure 25 includes a first barrier structure 251 disposed at the first edge 21a and a second barrier structure 252 disposed at the second edge 21b; along the first direction, the length of the first barrier structure 251, the length of the second barrier structure 252 and the length of the semiconductor layer 20 are all the same, and the first direction is perpendicular to the direction from the second region 22 to the third region 23.

[0035] By setting the length of the first barrier structure 251, the length of the second barrier structure 252 and the length of the semiconductor layer 20 to be the same in the direction perpendicular to the second region 22 to the third region 23, the doped ions 24 cannot diffuse from the second region 22 and the third region 23 to the first region 21 at the first edge 21a and the second edge 21b of the first region 21.

[0036] Specifically, the shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 may be the same or different. Preferably, the shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 are set to be the same for easy processing. The shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 can be set to a straight line, a curve, a broken line, an irregular shape, etc. The first barrier structure 251 and the second barrier structure 252 can be extended along the first direction, or they can be extended at a certain angle to the first direction. For example, they can be at an angle of 3°, 8°, 10°, 15°, 30°, 45°, etc. to the first direction.

[0037] In some embodiments of the present invention, reference Figure 2 and Figure 5 The barrier structure 25 includes a first barrier structure 251 disposed at the first edge 21a and a second barrier structure 252 disposed at the second edge 21b; along the first direction, at least one of the length of the first barrier structure 251 and the length of the second barrier structure 252 is less than the length of the semiconductor layer 20, and the first direction is perpendicular to the direction from the second region 22 to the third region 23.

[0038] By setting at least one of the length of the first barrier structure 251 and the length of the second barrier structure 252 to be smaller than the length of the semiconductor layer 20 in a direction perpendicular to the direction from the second region 22 to the third region 23, the doped ions 24 cannot diffuse in large quantities from the second region 22 and the third region 23 to the first region 21 at the first edge 21a and the second edge 21b of the first region 21.

[0039] Specifically, along the first direction, one of the length of the first barrier structure 251 and the length of the second barrier structure 252 is smaller than the length of the semiconductor layer 20 , or both are smaller than the length of the semiconductor layer 20 .

[0040] Specifically, the shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 may be the same or different. Preferably, the shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 are set to be the same for easy processing. The shape structure of the first barrier structure 251 and the shape structure of the second barrier structure 252 can be set to a straight line, a curve, a broken line, an irregular shape, etc. The first barrier structure 251 and the second barrier structure 252 can be extended along the first direction, or they can be extended at a certain angle to the first direction. For example, they can be at an angle of 3°, 8°, 10°, 15°, 30°, 45°, etc. to the first direction.

[0041] In some embodiments of the present invention, reference Figure 2 At least one of the first barrier structure 251 and the second barrier structure 252 is a strip barrier structure, and in the first direction, at least one end of the strip barrier structure is spaced a certain distance from the edge of the semiconductor layer 20 .

[0042] By setting at least one of the first barrier structure 251 and the second barrier structure 252 as a strip barrier structure, and in the first direction, at least one end of the strip barrier structure has a certain distance from the edge of the semiconductor layer 20, so that the length of at least one of the first barrier structure 251 and the second barrier structure 252 in the first direction is less than the length of the semiconductor layer 20.

[0043] Specifically, one of the first barrier structure 251 and the second barrier structure 252 may be a strip barrier structure. For example, the first barrier structure 251 is a strip barrier structure, and in the first direction, one end of the first barrier structure 251 is spaced from the edge of the semiconductor layer 20 close to the end, or both ends are spaced from the edges of both sides of the semiconductor layer 20 along the first direction; or, the second barrier structure 252 is a strip structure, and in the first direction, one end of the second barrier structure 252 is spaced from the edge of the semiconductor layer 20 close to the end, or both ends are spaced from the edges of both sides of the semiconductor layer 20 along the first direction. The first barrier structure 251 and the second barrier structure 252 may both be strip barrier structures, and one end of each of them is spaced from the edge of the semiconductor layer 20 close to the end, or both ends are spaced from the edges of both sides of the semiconductor layer 20 along the first direction, etc.

[0044] In some embodiments, the length of the first barrier structure 251 and the second barrier structure 252 along the first direction may be greater than half of the length of the first region 21 along the first direction, may be equal to half of the length of the first region 21 along the first direction, or may be less than half of the length of the first region 21 along the first direction. Preferably, the length of the first barrier structure 251 and the second barrier structure 252 along the first direction is greater than half of the length of the first region 21 along the first direction. Further, the first barrier structure 251 and the second barrier structure 252 are symmetrically arranged and have the same length along the first direction, and both ends of the first barrier structure 251 and the second barrier structure 252 have the same spacing from the two side edges of the semiconductor layer 20 along the first direction.

[0045] In some embodiments of the present invention, reference Figure 5 At least one of the first barrier structure 251 and the second barrier structure 252 includes a plurality of barrier portions 253 , and the plurality of barrier portions 253 are spaced apart along the first direction.

[0046] By configuring at least one of the first and second barrier structures 251 and 252 to include a plurality of barrier portions 253 spaced apart along the first direction, a length of at least one of the first and second barrier structures 251 and 252 in the first direction is smaller than a length of the semiconductor layer 20 .

[0047] Specifically, one of the first barrier structure 251 and the second barrier structure 252 may include a plurality of barrier portions 253 spaced apart along the first direction. For example, the first barrier structure 251 includes a plurality of barrier portions 253 spaced apart along the first direction; or, the second barrier structure 252 includes a plurality of barrier portions 253 spaced apart along the first direction; or, the first barrier structure 251 and the second barrier structure 252 each include a plurality of barrier portions 253 spaced apart along the first direction.

[0048] In some embodiments, the total length of the plurality of barrier portions 253 of the first barrier structure 251 and the total length of the plurality of barrier portions 253 of the second barrier structure 252 along the first direction may be the same or different. Preferably, the total length of the plurality of barrier portions 253 of the first barrier structure 251 and the total length of the plurality of barrier portions 253 of the second barrier structure 252 along the first direction are the same. The barrier shape lengths of the barrier portions 253 of the first barrier structure 251 and the second barrier structure 252 may be the same or different. Preferably, the barrier shape lengths of the barrier portions 253 of the first barrier structure 251 and the second barrier structure 252 are the same. For example, they may be circular, rectangular, etc. The spacings between the plurality of barrier portions 253 of the first barrier structure 251 may be the same or different. Preferably, the spacings between the plurality of barrier portions 253 of the first barrier structure 251 are set to be the same. The spacings between the plurality of barrier portions 253 of the second barrier structure 252 may be the same or different. Preferably, the spacing between the plurality of barrier portions 253 of the second barrier structure 252 is set to be the same. The spacing between the plurality of barrier portions 253 of the first barrier structure 251 and the spacing between the plurality of barrier portions 253 of the second barrier structure 252 may be the same or different. Preferably, the spacing between the plurality of barrier portions 253 of the first barrier structure 251 and the spacing between the plurality of barrier portions 253 of the second barrier structure 252 are the same.

[0049] The total length of the multiple barrier portions 253 of the first barrier structure 251 and the total length of the multiple barrier portions 253 of the second barrier structure 252 along the first direction may be greater than half of the length of the first region 21 along the first direction, may be equal to half of the length of the first region 21 along the first direction, or may be less than half of the length of the first region 21 along the first direction. Preferably, the total length of the multiple barrier portions 253 of the first barrier structure 251 and the total length of the multiple barrier portions 253 of the second barrier structure 252 along the first direction are greater than half of the length of the first region 21 along the first direction.

[0050] In some embodiments of the present invention, reference Figure 6One of the first barrier structure 251 and the second barrier structure 252 is a strip barrier structure, and the other includes a plurality of barrier portions 253, and the plurality of barrier portions 253 are spaced apart along the first direction.

[0051] By setting one of the first barrier structure 251 and the second barrier structure 252 as a strip barrier structure and the other as a plurality of barrier portions 253 spaced apart along the first direction, at least one of the first barrier structure 251 and the second barrier structure 252 has a length in the first direction that is less than the length of the semiconductor layer 20.

[0052] Specifically, the length of the strip-shaped barrier structure along the first direction may be the same as the length of the semiconductor layer 20 along the first direction, or may be less than the length of the semiconductor layer 20 along the first direction. When the length of the strip-shaped barrier structure along the first direction is less than the length of the semiconductor layer 20 along the first direction, at least one of the two ends of the strip-shaped barrier structure along the first direction may have a certain interval with the edge of the semiconductor layer 20 along the first direction. The shapes and lengths of the plurality of barrier portions 253 spaced apart along the first direction may be the same or different. Preferably, the shapes and lengths of the plurality of barrier portions 253 spaced apart along the first direction are the same. The spacings between the plurality of barrier portions 253 may be the same or different. Preferably, the spacings between the plurality of barrier portions 253 are the same.

[0053] In some embodiments of the present invention, reference Figure 7 The oxide thin film transistor 100 further includes an insulating layer 40 stacked between the semiconductor layer 20 and the gate 30 , and the barrier structure 25 at least penetrates the semiconductor layer 20 and the insulating layer 40 .

[0054] By providing the insulating layer 40, current is prevented from flowing directly from the gate 30 to the second region 22 and the third region 23 of the semiconductor layer 20, while allowing the electric field to act on the semiconductor layer 20. The barrier structure 25 at least penetrates the semiconductor layer 20 and the insulating layer 40 to prevent the doping ions 24 from diffusing along the insulating layer 40 to the first region 21 of the semiconductor layer 20.

[0055] Specifically, the length of the barrier structure 25 along the thickness direction of the semiconductor layer 20 may be the same as the sum of the lengths of the semiconductor layer 20 and the insulating layer 40 along the thickness direction of the semiconductor layer 20 , or may be greater than the sum of the lengths of the semiconductor layer 20 and the insulating layer 40 along the thickness direction of the semiconductor layer 20 .

[0056] In some embodiments of the present invention, the material of the barrier structure 25 is the same as the material of the gate 30 .

[0057] By setting the material of the barrier structure 25 to be the same as that of the gate 30 , the barrier structure 25 is made conductive and current can pass through.

[0058] Specifically, the actual production process includes the following steps: a) preparing a semiconductor layer 20 on a substrate 10, and etching a first hole and a second hole at a first edge 21a and a second edge 21b of the semiconductor layer 20, respectively; b) preparing an insulating layer 40 on a side of the semiconductor layer 20 away from the substrate 10, and etching a third hole and a fourth hole at positions corresponding to the first hole and the second hole, wherein the third hole includes the first hole, and the fourth hole includes the second hole; c) preparing a gate 30 on a side of the insulating layer 40 away from the semiconductor layer 20, and patterning it, at which time, the third hole and the fourth hole are filled with gate 30 material.

[0059] In some embodiments of the present invention, reference Figure 8 The oxide thin film transistor 100 further includes a wiring layer 50 disposed on a side of the gate 30 facing away from the substrate 10 , and the barrier structure 25 at least penetrates from a side of the semiconductor layer 20 facing the substrate 10 to a side of the wiring layer 50 facing away from the substrate 10 .

[0060] By penetrating the barrier structure 25 at least from the side of the semiconductor layer 20 facing the substrate 10 to the side of the wiring layer 50 facing away from the substrate 10 , the doping ions 24 are prevented from diffusing along the wiring layer 50 to the first region 21 of the semiconductor layer 20 .

[0061] Specifically, the length of the barrier structure 25 along the thickness direction of the semiconductor layer 20 may be the same as the sum of the lengths along the thickness direction of the semiconductor layer 20 from the side of the semiconductor layer 20 facing the substrate 10 to the side of the wiring layer 50 facing away from the substrate 10, or may be greater than the sum of the lengths along the thickness direction of the semiconductor layer 20 from the side of the semiconductor layer 20 facing the substrate 10 to the side of the wiring layer 50 facing away from the substrate 10.

[0062] In some embodiments, the oxide thin film transistor 100 further includes a protection layer 60 (ILD). The protection layer 60 is located on a side of the insulating layer 40 facing away from the semiconductor layer 20 and covers the gate 30 .

[0063] In some embodiments, the oxide thin film transistor 100 further includes a buffer layer 70 disposed between the semiconductor and the substrate 10 .

[0064] In some embodiments of the present invention, the material of the barrier structure 25 is the same as the material of the routing layer 50 .

[0065] By setting the material of the barrier structure 25 to be the same as that of the wiring layer 50 , the barrier structure 25 is made conductive and current can pass through.

[0066] Specifically, the actual production process includes the following steps: a) preparing a semiconductor layer 20 on a substrate 10, and etching a first hole and a second hole at a first edge 21a and a second edge 21b of the semiconductor layer 20, respectively; b) preparing an insulating layer 40, a gate 30 and a protective layer 60 in sequence on a side of the semiconductor layer 20 away from the substrate 10, and etching a fifth hole and a sixth hole at positions corresponding to the first hole and the second hole, wherein the fifth hole includes the first hole and the sixth hole includes the second hole; c) preparing a wiring layer 50 on a side of the protective layer 60 away from the semiconductor layer 20, and patterning it, at which time, the fifth hole and the sixth hole are filled with wiring layer 50 material.

[0067] The display panel according to the second aspect of the present invention comprises the oxide thin film transistor 100 in the above embodiment.

[0068] The display panel according to the embodiment of the present invention improves the stability of the display panel control by adopting the oxide thin film transistor 100 in the above embodiment.

[0069] It is understandable that the display surface has all the features and advantages of the above-mentioned oxide thin film transistor 100, which will not be elaborated here.

[0070] A display device according to an embodiment of the third aspect of the present invention includes the display panel in the above embodiment.

[0071] According to the display device of the embodiment of the present invention, the control stability of the display device is improved by adopting the display panel in the above embodiment.

[0072] It is understandable that the display device has all the features and advantages of the above-mentioned display panel, which will not be elaborated here.

[0073] The display device is a product with an image display function. For example, the display device may be any of: a mobile phone, a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, etc. The display device may also be a microdisplay or a product containing a microdisplay. The product containing a microdisplay may be any of a smart watch, a smart bracelet, a helmet display, a stereo display mirror, and an AR device (such as AR glasses), a VR device (such as VR glasses), etc. For example, a microdisplay may be a display with a display size ranging from about 0.2 inches to about 2.5 inches, but is not limited thereto. It can be understood that the microdisplay may also be a display with a smaller display size, such as a display size less than or equal to 0.2 inches.

[0074] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0075] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0076] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or means that the first feature is lower in level than the second feature.

[0077] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0078] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An oxide thin film transistor, characterized in that: comprising a substrate and a semiconductor layer arranged in a stacked manner; The semiconductor layer includes a first region, and a second region and a third region located on opposite sides of the first region, wherein the second region and the third region both include doping ions; The semiconductor layer also includes a blocking structure, which is used to block the doped ions in the second region and the third region. The blocking structure is arranged at a first edge and a second edge of the first region, the first edge is an edge where the first region is connected to the second region, and the second edge is an edge where the first region is connected to the third region. Along the thickness direction of the semiconductor layer, the blocking structure at least penetrates the semiconductor layer.

2. The oxide thin film transistor according to claim 1, characterized in that: It also includes a gate stacked on a side of the semiconductor layer away from the substrate, wherein a projection of the gate on the semiconductor layer covers the first region.

3. The oxide thin film transistor according to claim 1, characterized in that: The barrier structure comprises a first barrier structure disposed at the first edge and a second barrier structure disposed at the second edge; Along a first direction, the length of the first barrier structure, the length of the second barrier structure, and the length of the semiconductor layer are all the same, and the first direction is a direction perpendicular to the second region to the third region.

4. The oxide thin film transistor according to claim 1, characterized in that: The barrier structure comprises a first barrier structure disposed at the first edge and a second barrier structure disposed at the second edge; Along a first direction, at least one of a length of the first barrier structure and a length of the second barrier structure is smaller than a length of the semiconductor layer, and the first direction is a direction perpendicular to the second region to the third region.

5. The oxide thin film transistor according to claim 4, characterized in that: At least one of the first barrier structure and the second barrier structure is a strip barrier structure, and in the first direction, at least one end of the strip barrier structure is spaced a certain distance from an edge of the semiconductor layer.

6. The oxide thin film transistor according to claim 4, characterized in that: At least one of the first barrier structure and the second barrier structure includes a plurality of barrier portions, and the plurality of barrier portions are spaced apart along the first direction.

7. The oxide thin film transistor according to claim 4, characterized in that: One of the first barrier structure and the second barrier structure is a strip barrier structure, and the other includes a plurality of barrier portions, and the plurality of barrier portions are arranged at intervals along the first direction.

8. The oxide thin film transistor according to any one of claims 2 to 7, characterized in that: It also includes an insulating layer stacked between the semiconductor layer and the gate, and the barrier structure at least penetrates the semiconductor layer and the insulating layer.

9. The oxide thin film transistor according to claim 8, characterized in that: The material of the barrier structure is the same as that of the gate.

10. The oxide thin film transistor according to any one of claims 2 to 7, characterized in that: It also includes a wiring layer arranged on a side of the gate away from the substrate, and the barrier structure at least penetrates from a side of the semiconductor layer toward the substrate to a side of the wiring layer away from the substrate.

11. The oxide thin film transistor according to claim 10, characterized in that: The material of the barrier structure is the same as that of the routing layer.

12. A display panel, characterized in that: An oxide thin film transistor comprising any one of claims 1-11.

13. A display device, characterized in that: Includes the display panel as claimed in claim 12.

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