A semiconductor power device and a method for manufacturing the same

Abstract

The present application provides a semiconductor power device and a manufacturing method thereof, wherein the semiconductor power device includes a substrate, a first conductive type drift layer and an electric field modulation structure, wherein the first conductive type drift layer is located on the substrate. The first conductive type drift layer has a second conductive type doped region in the surface layer away from the substrate. The electric field modulation structure is located in the first conductive type drift layer, and the electric field modulation structure provides at least one electric field modulation surface, which is used to disperse the electric field at the corner of the second conductive type doped region close to the substrate side. The semiconductor power device has an electric field modulation structure that provides an electric field modulation surface, which can avoid the occurrence of local electric field concentration problems in the first conductive type drift layer and improve the breakdown voltage of the device. The manufacturing method is simple in process and low in cost.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices and relates to a semiconductor power device and a method for manufacturing the same. Background Art

[0002] As one of the power devices, power diodes are usually used in semiconductor switching devices. Traditional power diodes include Schottky diodes and PiN diodes. Schottky diodes have fast switching speeds, but large reverse leakage and limited withstand voltage performance. PiN diodes have good reverse blocking characteristics, but slow switching speeds.

[0003] See also Figure 1 , Figure 1 A cross-sectional schematic diagram of a hybrid PiN / Schottky diode (Merged PiN Schottky, MPS for short) is shown. The MPS diode includes a cathode metal 101, a substrate 102, an N-type drift layer 103 and an anode metal 104 stacked in sequence from bottom to top. A P-type grid 105 is formed in the N-type drift layer 103. The P-type grid 105 and the N-type drift layer 103 form a PN junction. The anode metal 104 contacts the Schottky portion of the N-type drift layer 103 located between adjacent PN junctions to form a Schottky junction, and an n-type conductive channel is formed between adjacent PN junctions. When reverse blocking, the PN junction depletion region shields the Schottky junction, avoiding the Schottky junction from generating large reverse leakage. When forward conducting, the presence of the PN junction introduces a charge storage effect, reducing the on-state voltage drop, but because the Schottky junction does not inject carriers, the n-type drift layer 103 stores less charge than the PiN diode, ensuring the switching speed of the device. Therefore, the MPS diode combines the advantages of Schottky diodes and PiN diodes, has the characteristics of fast switching and low on-state voltage drop, and meets the demand for high-performance power diodes in the power electronics field.

[0004] However, although the device structure of the MPS diode can provide effective electric field shielding protection for the Schottky junction, avoiding the premature breakdown problem caused by the barrier lowering effect of the Schottky junction, the strong electric field concentration phenomenon that is prone to occur at the bottom corner of the p-type grid structure may still cause premature breakdown of the device, thereby affecting the device's working performance. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor power device and a method for manufacturing the same, so as to solve the problem of local electric field concentration in semiconductor power devices in the prior art causing premature breakdown of the device.

[0006] To achieve the above objectives and other related objectives, in a first aspect, a semiconductor power device is provided, comprising:

[0007] substrate;

[0008] A first conductive type drift layer is located on the substrate, wherein a second conductive type doping region is provided in a surface layer of the first conductive type drift layer away from the substrate;

[0009] The electric field modulation structure is located in the first conductive type drift layer, and the electric field modulation structure provides at least one electric field modulation surface, and the electric field modulation surface is used to disperse the electric field at the corner of the second conductive type doped region close to the substrate side.

[0010] Optionally, the electric field modulation structure includes at least two dielectric layers, and the dielectric constants of two adjacent dielectric layers are different, so that the electric field modulation surface is formed based on the contact interface of the two adjacent dielectric layers.

[0011] Optionally, the dielectric constant of the dielectric layer is in the range of 3 to 30, and the material of the dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, boron nitride and zirconium oxide.

[0012] Optionally, along a direction perpendicular to the substrate to the first conductive type drift layer, a width of the dielectric layer ranges from 1 μm to 3 μm.

[0013] Optionally, in the electric field modulation structure:

[0014] The electric field modulation surface farthest from the substrate is located between the second conductive type doping region and the substrate;

[0015] The distance between the electric field modulation surface closest to the substrate and the substrate is not greater than half the thickness of the first conductive type drift layer.

[0016] Optionally, the electric field modulation structure further includes a groove, and along the direction from the substrate to the first conductive type drift layer, the groove at least partially penetrates the second conductive type doped region, and all the dielectric layers in the same electric field modulation structure are stacked in the groove.

[0017] Optionally, a surface of the electric field modulation structure away from the second conductivity type doping region is connected to the substrate.

[0018] Optionally, a surface of the electric field modulation structure away from the substrate is flush with a surface of the first conductive type drift layer away from the substrate.

[0019] Optionally, the surface layer of the first conductive type drift layer away from the substrate has multiple second conductive type doped regions, and the multiple second conductive type doped regions are arranged at intervals; the semiconductor power device also includes a first metal layer, the first metal layer is in ohmic contact with the second conductive type doped region, and the first metal layer is in Schottky contact with a portion of the first conductive type drift layer located between two adjacent second conductive type doped regions, the second conductive type doped region, the first conductive type drift layer and the substrate constitute a PiN diode, the first metal layer and the portion of the first conductive type drift layer located between two adjacent second conductive type doped regions constitute a Schottky diode, and the PiN diode and the Schottky diode constitute an MPS diode.

[0020] In a second aspect, a method for manufacturing a semiconductor power device is provided, wherein the method is used to manufacture the semiconductor power device as described above, and the method comprises the following steps:

[0021] providing a substrate;

[0022] forming a first conductive type drift layer on the substrate, wherein a second conductive type doped region is formed in a surface layer of the first conductive type drift layer away from the substrate;

[0023] An electric field modulation structure is formed in the first conductive type drift layer, wherein the electric field modulation structure provides at least one electric field modulation surface for dispersing the electric field at a corner of the second conductive type doped region close to the substrate.

[0024] As described above, the semiconductor power device of the present application has an electric field modulation structure located in the first conductive type drift layer, and the electric field modulation structure provides at least one electric field modulation surface, through which the electric field at the corner of the second conductive type doped region close to the substrate side is dispersed, thereby avoiding the occurrence of the problem of local electric field concentration in the first conductive type drift layer and improving the breakdown voltage of the device. The manufacturing method of the semiconductor power device of the present application has a simple process and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the cross-sectional structure of an MPS diode in the related art.

[0026] Figure 2 It is a schematic diagram of the cross-sectional structure of an MPS diode with a stepped shielding ring in the related art.

[0027] Figure 3 This is a schematic diagram of the first cross-sectional structure of a semiconductor power device provided in an embodiment of the present application.

[0028] Figure 4 yes Figure 1 A-A' Figure 3 Schematic diagram of the comparison of the electric field distribution curves at BB'.

[0029] Figure 5 This is a schematic diagram of the second cross-sectional structure of the semiconductor power device provided in an embodiment of the present application.

[0030] Figure 6 This is a schematic diagram of the third cross-sectional structure of the semiconductor power device provided in the embodiment of the present application.

[0031] Figure 7 This is a schematic diagram of the fourth cross-sectional structure of the semiconductor power device provided in the embodiment of the present application.

[0032] Figure 8 It is a flowchart of the steps of the method for manufacturing a semiconductor power device provided in an embodiment of the present application.

[0033] Fig. 9 It is a schematic diagram of the structure obtained after forming a second conductive type doping region in the method for manufacturing a semiconductor power device provided in an embodiment of the present application.

[0034] Fig.10 It is a schematic diagram of the structure obtained after forming a groove in the method for manufacturing a semiconductor power device provided in an embodiment of the present application.

[0035] Fig.11 It is a schematic diagram of the structure obtained after an electric field modulation structure is formed in the method for manufacturing a semiconductor power device provided in an embodiment of the present application.

[0036] Description of reference numerals:

[0037] 101, 201-cathode metal, 102, 202-substrate, 103, 203-N-type drift layer, 104-anode metal, 204a-Schottky contact anode metal, 204b-ohmic contact anode metal, 105, 205-P-type grid, 206-step shielding ring;

[0038] 10 - substrate, 20 - first conductivity type drift layer, 30 - second conductivity type doped region, 40 - electric field modulation structure, 401 - contact interface, 41 - dielectric layer, 42 - trench, 50 - first metal layer, 60 - second metal layer, S1 to S3 - steps. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present application clearer, the implementation mode of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0040] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0041] At present, in order to solve the technical problems mentioned in the background technology, please refer to Figure 2 , Figure 2 A schematic diagram of the cross-sectional structure of an MPS diode with a step shielding ring is shown. The MPS diode with a step shielding ring includes a cathode metal 201, a substrate 202, an N-type drift layer 203, a Schottky contact anode metal 204a and an ohmic contact anode metal 204b stacked in sequence from bottom to top. Among them, a P-type grid 205 and a P-type step shielding ring 206 are formed in the N-type drift layer 203. The doping concentration of the step shielding ring 206 is less than the doping concentration of the P-type grid 205. In the MPS with a step shielding ring, by introducing a lightly doped P-type step shielding ring 206 under the P-type grid 205, the depletion effect of the T-shaped step shielding ring 206 further moves the depletion region to the N-type drift layer 203, thereby effectively alleviating the strong electric field concentration at the corner at the bottom of the heavily doped p-grid structure, forming an electric field shielding protection effect thereon. At the same time, the T-shaped morphology of the step shielding ring 206 can simultaneously generate lateral and longitudinal depletion regions when reverse biased, and the coupling of the depletion regions will strengthen the charge coupling effect, making the two-dimensional electric field distribution uniform. However, in the process of preparing the T-shaped step shielding ring 206, it is necessary to etch the grooves of the T-shaped steps step by step and then re-epitaxially grow to obtain the step shielding ring 206, which is complex and costly.

[0042] Therefore, although the above technical solution can improve the problem of premature device breakdown caused by strong electric field concentration at the bottom corner of the P-type grid, the process and cost factors restrict the promotion and application of this method to a certain extent.

[0043] The semiconductor power device provided in the embodiment of the present application introduces an electric field modulation structure in the device structure, and the electric field modulation structure provides at least one electric field modulation surface, which is used to disperse the electric field at the corner of the second conductive type doped region close to the substrate side, thereby avoiding the occurrence of the local electric field concentration problem in the first conductive type drift layer, and improving the breakdown voltage of the device. The embodiment of the semiconductor power device of the present application is introduced below.

[0044] See also Figure 3 , Figure 3 The first cross-sectional structure schematic diagram of the semiconductor power device is shown. The semiconductor power device of the embodiment of the present application includes a substrate 10, a first conductive type drift layer 20 and an electric field modulation structure 40. It should be noted that the embodiment of the present application is illustrated by an example having two cell structures. In actual application, the structure of the semiconductor power device of the embodiment of the present application is not limited to that shown in the accompanying drawings.

[0045] Specifically, the first conductivity type is located on the substrate 10. The first conductivity type drift layer 20 has a second conductivity type doped region 30 in the surface layer away from the substrate 10. The electric field modulation structure 40 is located in the first conductivity type drift layer 20. The electric field modulation structure 40 provides at least one electric field modulation surface, which is used to disperse the electric field at the corner of the second conductivity type doped region 30 close to the substrate 10.

[0046] In the embodiment of the present application, a new electric field peak is introduced into the first conductive type drift layer 20 through the electric field modulation surface provided by the electric field modulation structure 40, and the electric field at the corner of the second conductive type doping region 30 close to the substrate 10 is dispersed through the new electric field peak, thereby alleviating the problem of strong electric field concentration at the corner of the second conductive type doping region 30 close to the substrate 10, avoiding the occurrence of the problem of local electric field concentration in the first conductive type drift layer 20, and improving the breakdown voltage of the device. In addition, through the structural design of the electric field modulation structure 40 extending into the second conductive type doping region 30, the electric field modulation structure 40 can disperse the electric field concentrated at all corners of the second conductive type doping region 30 close to the substrate 10. If the electric field modulation structure 40 is located on one side of the second conductive type doping region 30 in the direction perpendicular to the substrate 10 to the first conductive type drift layer 20, the electric field modulation structure 40 can only disperse the electric field concentrated at a part of the corners of the second conductive type doping region 30 close to the substrate 10, and the improvement of the breakdown voltage performance of the device is limited.

[0047] In an optional embodiment, if Figure 3 As shown, the electric field modulation structure 40 includes at least two dielectric layers, and the dielectric constants of the two adjacent dielectric layers are different, so that an electric field modulation surface is formed based on a contact interface 401 between the two adjacent dielectric layers.

[0048] In the embodiment of the present application, during the operation of the semiconductor power device, due to the existence of an external electric field (taking the semiconductor power device as a power diode as an example, the external electric field refers to the electric field generated by the voltage applied to the power diode through the anode and cathode of the power diode), the position of the ions in the dielectric layer 41 will change and generate polarized charges on the surface of the dielectric layer 41 (the generated polarized charges include polarized positive charges and polarized negative charges). The polarized charges will move under the action of the external electric field and generate a new electric field, and the new electric field causes the original electric field in the dielectric layer 41 to change. When the electric field modulation structure 40 includes at least two dielectric layers and the dielectric constants of the two adjacent dielectric layers are different, for example, the two adjacent dielectric layers are the first dielectric layer and the second dielectric layer. Based on Gauss's theorem, it can be seen that the electric flux passing through a closed surface is proportional to the amount of charge enclosed by the closed surface, and there is in, is the boundary surface of the closed volume, the closed volume can be any closed body containing (part of) the contact interface at the contact interface between the first dielectric layer and the second dielectric layer, D is the electric displacement (related to the electric field strength E), dS is the area of ​​the contact interface contained in the closed body (for example, if the closed body is a cylinder, dS is equal to the bottom area of ​​the cylinder), and q0 is the total amount of free charge in the closed surface. When the total amount of charge in the first dielectric layer or the second dielectric layer is substantially zero (that is, there is no net charge inside the first dielectric layer or the second dielectric layer, the electric field E inside the first dielectric layer or the second dielectric layer has nothing to do with the free charge, but only with the polarization of the first dielectric layer or the second dielectric layer), at this time, the electric displacement D inside the first dielectric layer or the second dielectric layer and the electric field E satisfy D=ε r ε0E, where ε r is the relative dielectric constant of the first dielectric layer or the second dielectric layer, and ε0 is the dielectric constant of vacuum. At the contact interface between the first dielectric layer and the second dielectric layer, the normal component of the electric displacement D is continuous (that is, at the contact interface between the first dielectric layer and the second dielectric layer, the normal component of the electric displacement D is equal), and there exists ε 1n E 1n =ε 2n E 2n , where ε 1n is the relative dielectric constant of the first dielectric layer, ε 2n is the relative dielectric constant of the second dielectric layer, E 1n is the normal component of the electric field of the first dielectric layer on the contact interface, E 2nis the normal component of the electric field of the second dielectric layer at the contact interface. Since the dielectric constant of the first dielectric layer is different from that of the second dielectric layer, the electric field lines will be redistributed at the contact interface between the two, causing a sudden change in the electric field intensity at the contact interface 401 between the two, generating a new electric field peak, thereby changing the electric field distribution in the semiconductor power device.

[0049] In the semiconductor power device in the embodiment of the present application, due to the presence of the electric field modulation structure 40 in the first conductive type drift layer 20, when the electric field modulation structure 40 includes at least two dielectric layers and the dielectric constants of the two adjacent dielectric layers are different, the electric field lines will be redistributed at the contact interface of any two adjacent dielectric layers due to the difference in dielectric constants. The redistribution of the electric field lines causes a sudden change in the electric field intensity at the contact interface to form a new electric field peak, thereby alleviating the electric field concentration at the corner of the second conductive type doped region 30 close to the substrate 10, improving the electric field distribution inside the first conductive type drift layer 20, making the device electric field distribution more uniform, and improving the breakdown voltage of the device, avoiding the occurrence of premature breakdown of the device, and ensuring the working performance of the device.

[0050] See also Figure 4 , Figure 4 Shows Figure 1 A-A' Figure 3 Comparison diagram of the electric field distribution curve at B-B' in Fig. Figure 4 It can be seen that along Figure 1 The electric field strength at each position distributed at A-A' in the figure increases first and then decreases as the distance between each position and the side of the N-type drift layer 103 away from the substrate 102 increases. The electric field strength peak in the electric field distribution curve corresponds to the bottom corner of the P-type grid 105 (the corner close to the substrate 102), that is, there is an electric field concentration phenomenon at the bottom corner of the P-type grid 105. Figure 3 The electric field strength at each position distributed at BB' in the middle shows a trend of alternating increase and decrease as the distance between each position and a surface of the first conductive type drift layer 20 away from the substrate 10 increases, so that multiple electric field strength peaks appear in the electric field distribution curve. The number of electric field strength peaks is related to the number of electric field modulation surfaces provided by the electric field modulation structure (for example, Figure 3 The electric field modulation structure shown in FIG. 4 provides two electric field modulation surfaces. In addition to the electric field peak at the corner of the second conductive type doping region 30 close to the substrate 10, the electric field distribution curve also includes the electric field peak introduced by the two electric field modulation surfaces. The electric field modulation surface provided by the electric field modulation structure 40 disperses the electric field at the corner of the second conductive type doping region 30 close to the substrate 10, so that compared with FIG. Figure 1 For the structure shown, Figure 3 The electric field peak at the corner of the second conductive type doping region 30 facing the substrate 10 in the structure shown is reduced, thereby avoiding the occurrence of the local electric field concentration problem in the first conductive type drift layer 20. It should be noted that Figure 4 The "drift layer" at the horizontal axis refers to Figure 1 The N-type drift layer 203 and Figure 3 The first conductivity type drift layer 20 in the embodiment of the present invention.

[0051] For an alternative embodiment, see Figure 3 , Figure 5 and Figure 6 ,in, Figure 5 shows a second cross-sectional structure schematic diagram of the semiconductor power device, Figure 6 The third cross-sectional structure schematic diagram of the semiconductor power device is shown. The number of dielectric layers 41 in the electric field modulation structure 40 is two layers ( Figure 5 As shown), three layers ( Figure 3 shown) or more than three layers ( Figure 6 As shown). The number of dielectric layers 41 in the semiconductor power device is selected based on the actual application scenario and breakdown voltage performance requirements of the semiconductor power device. In the case where the semiconductor power device includes more than two dielectric layers 41, the dielectric constant of each dielectric layer 41 is different, or the dielectric layers 41 with different dielectric constants are alternately stacked. For example, when the electric field modulation structure 40 includes three dielectric layers 41, the three dielectric layers 41 have different dielectric constants, or the dielectric constants of the two dielectric layers on both sides of the middle dielectric layer 41 are the same.

[0052] In an optional embodiment, the electric field modulation structure 40 further includes a groove 42, and in the direction from the substrate 10 to the first conductive type drift layer 20, the groove 42 at least partially penetrates the second conductive type doping region 30, and all the dielectric layers 41 in the same electric field modulation structure 40 are stacked in the groove 42 (that is, the electric field modulation structure 40 is filled in the groove 41, that is, the electric field modulation structure 40 at least partially extends into the second conductive type doping region 30). Further, in the direction from the substrate 10 to the first conductive type drift layer 20, the groove 42 partially penetrates the second conductive type doping region 30, which includes two situations: the groove 42 only penetrates a part of the second conductive type doping region 30, and the groove 42 completely penetrates the second conductive type doping region 30. In one embodiment, in the above two situations, the groove 42 is centered relative to the second conductive type doping region 30, and in the direction perpendicular to the substrate 10 to the first conductive type drift layer 20, the center line of the groove 42 coincides with the center line of the second conductive type doping region 30, so that the electric field modulation structure 40 located in the groove 42 can improve the electric field concentration phenomenon at each corner of the second conductive type doping region 30 close to the first conductive type drift layer 20.

[0053] In one embodiment, see Figure 7 , Figure 7 4 shows a schematic diagram of a fourth cross-sectional structure of the semiconductor power device. The groove 42 only penetrates a portion of the second conductive type doping region 30. In this case, the side of the electric field modulation structure 40 away from the substrate 10 is located in the region of the second conductive type doping region 30. In another embodiment, as Figure 3 As shown, the groove 42 completely penetrates the second conductive type doping region 30, and at this time, the side of the electric field modulation structure 40 away from the substrate 10 is flush with the side of the first conductive type drift layer 20 away from the substrate 10. In the above two cases, since the distance between the side of the electric field modulation structure 40 away from the substrate 10 and the substrate 10 is greater than the distance between the side of the second conductive type doping region 30 close to the substrate 10 and the substrate 10, the electric field modulation structure 40 can alleviate the electric field concentration problem at the side of the second conductive type doping region 30 facing the substrate 10. Therefore, when applied, the specific structure of the groove 42 and the electric field modulation structure 40 can be selected based on actual needs.

[0054] In the embodiment of the present application, the electric field modulation structure 40 includes a groove 42 and at least two dielectric layers stacked in the groove 42. The electric field modulation structure 40 can be obtained by step-depositing the dielectric layer 41 after one groove etching. Compared with the solution of using a step shielding ring to improve the breakdown performance of the device, at least one photolithography and etching process is saved, which saves process costs and reduces process difficulty to improve product yield.

[0055] In an optional embodiment, the electric field modulation structure 40 is connected to the substrate 10 at a side away from the second conductive type doping region 30. In the case where the electric field modulation structure 40 includes a groove 42, the electric field modulation structure 40 filled in the groove 42 is directly connected to the substrate 10, thereby avoiding the problem of premature breakdown of the device caused by the groove bottom of the groove 42 being located in the first conductive type drift layer 20 and generating a new electric field concentration at a side of the groove 42 close to the substrate 10 and a corner of the side of the groove 41 close to the substrate 10, thereby further ensuring the breakdown performance of the device.

[0056] In an optional embodiment, the first conductive type drift layer 20 has a plurality of second conductive type doped regions 30 in the surface layer away from the substrate 10, and the plurality of second conductive type doped regions 30 are arranged at intervals. The semiconductor power device also includes a first metal layer 50, the first metal layer 50 is in ohmic contact with the second conductive type doped region 30, and the first metal layer 50 is in Schottky contact with a portion of the first conductive type drift layer 20 located between two adjacent second conductive type doped regions 30. The second conductive type doped region 30, the first conductive type drift layer 20 and the substrate 10 constitute a PiN diode, the first metal layer 50 and the portion of the first conductive type drift layer 20 located between two adjacent second conductive type doped regions 30 constitute a Schottky diode, and the PiN diode and the Schottky diode constitute an MPS diode. That is, the semiconductor power device provided in the embodiment of the present application includes an MPS power diode, and the first metal layer 50 serves as the anode metal of the MPS power diode. Of course, the semiconductor power device in the embodiment of the present application may also be other device types that need to improve the withstand voltage capability.

[0057] In an optional embodiment, when there are multiple second conductive type doping regions 30, the number of electric field modulation structures 40 is also multiple. When the side of the electric field modulation structure 40 away from the substrate 10 is flush with the side of the first conductive type drift layer 20 away from the substrate 10 and the side of the electric field modulation structure 40 close to the substrate 10 is connected to the substrate 10, the multiple electric field modulation structures 40 are arranged in the first conductive type drift layer 20 in a direction perpendicular to the substrate 10 and pointing to the first conductive type drift layer 20 (referring to the horizontal direction) to separate the first conductive type drift layer 20 into multiple first conductive type drift regions. Figure 3 In the cross-sectional view shown, the first conductive type drift region located between two adjacent electric field modulation structures 40 and the portion of the second conductive type doped region 30 located in the first conductive type drift region together constitute a cellular structure, that is, the electric field modulation structure 40 is located between two adjacent cellular structures.

[0058] In an optional embodiment, the dielectric constant of the dielectric layer 41 is in the range of 3 to 30 (including the end values), for example, the dielectric constant of the dielectric layer 41 may be 6, 10, 15 or 20. The material of the dielectric layer 41 includes silicon oxide (SiO2), silicon nitride (SiN X , x>0), aluminum oxide (Al2O3), hafnium oxide (H f O2), boron nitride (h-BN, hexagonal boron nitride) and zirconium oxide (ZrO2), for example, the electric field modulation structure 40 includes a single dielectric layer 41 having only one dielectric material, and / or the electric field modulation structure 40 includes a composite dielectric layer 41 mixed with two or more dielectric materials.

[0059] In an optional embodiment, the width of the dielectric layer 41 in a direction perpendicular to the substrate 10 and pointing toward the first conductive type drift layer 20 is ( Figure 3 The width of the dielectric layer 41 in the direction perpendicular to the substrate 10 pointing to the first conductive type drift layer 20 may be 1.5 μm, 1.8 μm, 2.2 μm or 2.8 μm. The widths of different dielectric layers 41 in the direction perpendicular to the substrate 10 pointing to the first conductive type drift layer 20 may be the same or different to realize a specific electric field modulation structure 40.

[0060] In the embodiment of the present application, in order to take into account the application of the device and the effect of improving the breakdown performance, the width range of the above-mentioned dielectric layer 41 in the direction perpendicular to the substrate 10 pointing to the first conductive type drift layer 20 is verified and summarized. Among them, when the width of the dielectric layer 41 in the direction perpendicular to the substrate 10 pointing to the first conductive type drift layer 20 is greater than 3μm, the setting of the electric field modulation structure 40 will occupy more device area, which is not conducive to the miniaturization of the device. When the width of the dielectric layer 41 in the direction perpendicular to the substrate 10 pointing to the first conductive type drift layer 20 is less than 1μm, the contact interface 401 of the adjacent dielectric layer 41 is small in area, which is not conducive to the introduction of electric field spikes that effectively disperse the electric field strength, and the improvement of the breakdown performance of the device is limited. The thickness of the dielectric layer 41 in the direction of the substrate 10 pointing to the first conductive type drift layer 20 is designed based on the thickness of the first conductive type drift layer 20 in this direction, the material of the dielectric layer 41 and the withstand voltage performance requirements of the semiconductor power device, and is not specifically limited here.

[0061] In an optional embodiment, in the electric field modulation structure 40, the electric field modulation surface farthest from the substrate 10 is located between the second conductive type doping region 30 and the substrate 10. The distance between the electric field modulation surface closest to the substrate 10 and the substrate 10 ( Figure 3 d) is not greater than the thickness of the first conductive type drift layer 20 ( Figure 3The electric field modulation surface farthest from the substrate 10 is located between the second conductive type doping region 30 and the substrate 10, which can generate an electric field peak in the portion of the first conductive type drift layer 20 located on the side of the second conductive type doping region 30 close to the substrate 10, thereby effectively dispersing the electric field intensity concentrated at the corner of the second conductive type doping region 30 close to the substrate 10. The distance between the electric field modulation surface closest to the substrate 10 and the substrate 10 is not greater than half of the thickness of the first conductive type drift layer 20, that is, in the area of ​​the first conductive type drift layer 20 relatively close to the substrate 10, a new electric field peak is introduced through the electric field modulation surface, and the electric field intensity is dispersed, so that the electric field peak is distributed inside the first conductive type drift layer 20, thereby effectively improving the breakdown voltage of the device, so that the device may only break down under higher voltage conditions, and the voltage resistance of the device is improved.

[0062] In an optional embodiment, the semiconductor power device further includes a second metal layer 60, and the second metal layer 60 is located on a side of the substrate 10 away from the first conductive type drift layer 20. The second metal layer 60 serves as a cathode metal of the MPS power diode.

[0063] In an optional embodiment, the material of the substrate 10 includes at least one of silicon, silicon carbide, gallium nitride, gallium arsenide and gallium oxide, for example, the substrate 10 is a gallium nitride substrate. In an optional embodiment, the substrate 10 is of a first conductivity type, and the doping concentration of the substrate 10 is greater than the doping concentration of the first conductivity type drift layer 20. Optionally, the first conductivity type is N-type, and correspondingly, the second conductivity type is P-type, that is, the semiconductor power device in the embodiment of the present application includes an N+ substrate, an N-drift layer and a P-type doping region (i.e., a P-type grid). It should be noted that "N+" and "N-" here are only used to compare the N-type element doping concentration of the substrate 10 and the first conductivity type drift layer 20, and the doping concentration range of the substrate 10 and the first conductivity type drift layer 20 is selected based on actual needs.

[0064] The semiconductor power device in the embodiment of the present application has an electric field modulation structure located in the first conductive type drift layer, and the electric field modulation structure provides at least one electric field modulation surface. The electric field at the corner of the second conductive type doped region close to the substrate side is dispersed through the electric field modulation surface, thereby avoiding the occurrence of local electric field concentration problems in the first conductive type drift layer and improving the breakdown voltage of the device.

[0065] The present application also provides a method for manufacturing a semiconductor power device. The method can be used for the above-mentioned semiconductor power device. Fig. 9 , Fig. 9 A flowchart of the steps of the method for manufacturing the semiconductor power device is shown, and the method comprises the following steps:

[0066] S1: providing a substrate;

[0067] S2: forming a first conductive type drift layer on the substrate, wherein a second conductive type doped region is formed in a surface layer of the first conductive type drift layer away from the substrate;

[0068] S3: forming an electric field modulation structure in the first conductivity type drift layer, the electric field modulation structure providing at least one electric field modulation surface, the electric field modulation surface being used to disperse the electric field at a corner of the second conductivity type doped region close to the substrate side.

[0069] First, see Fig.10 , perform step S1, provide a substrate 10. For example, the substrate 10 is a gallium nitride substrate.

[0070] Please see again Fig.11 , performing step S2 to form a first conductive type drift layer 20 on the substrate 10 , wherein a second conductive type doped region 30 is formed in a surface layer of the first conductive type drift layer 20 away from the substrate 10 .

[0071] In an optional embodiment, step S2 includes the following steps: epitaxially growing a first conductive type drift layer 20 on a side surface of the substrate 10; forming an implantation mask layer ( Fig.11 (not shown) on the side of the first conductive type drift layer 20 away from the substrate 10; patterning the implantation mask layer to form an ion implantation window ( Fig.11 Based on the ion implantation window, a second conductive type doping region 30 is formed in the surface layer of the first conductive type drift layer 20 away from the substrate 10. For example, the material of the etching mask layer includes at least one of silicon nitride and silicon oxide. The method of patterning the implantation mask layer includes photolithography etching.

[0072] Next, see Figure 3 , perform step S3 to form an electric field modulation structure 40 in the first conductive type drift layer 20, the electric field modulation structure 40 provides at least one electric field modulation surface, and the electric field modulation surface is used to disperse the electric field at the corner of the second conductive type doped region 30 close to the substrate 10.

[0073] In an optional embodiment, the electric field modulation structure 40 includes at least two dielectric layers, and the dielectric constants of two adjacent dielectric layers are different, so that an electric field modulation surface is formed based on a contact interface 401 between the two adjacent dielectric layers.

[0074] In an optional embodiment, the electric field modulation structure 40 further includes a groove 42, and the at least two dielectric layers are stacked in the groove 42. Fig.11 and Figure 3 ,in, Fig.11FIG. 4 is a schematic cross-sectional view of a structure obtained after a trench 42 is formed in the first conductive type drift layer 20. In one embodiment, forming the electric field modulation structure 40 in the first conductive type drift layer 20 includes the following steps:

[0075] like Fig.11 As shown, a trench 42 is formed in the first conductive type drift layer 20 , and along the direction from the substrate 10 to the first conductive type drift layer 20 , the trench 42 at least partially penetrates the second conductive type doped region 30 .

[0076] In one embodiment, when the trench 42 penetrates the second conductive type doping region 30, forming the trench 42 in the first conductive type drift layer 20 includes the following steps: forming an etching mask layer ( Fig.11 (not shown) on the side of the first conductive type drift layer 20 away from the substrate 10; patterning the etching mask layer to form an etching window ( Fig.11 The etching window reveals at least a portion of the second conductive type doped region 30; based on the etching window, the second conductive type doped region 30 and the first conductive type drift layer 20 are etched to obtain a groove 42. For example, the material of the etching mask layer includes at least one of silicon nitride and silicon oxide. The method of patterning the etching mask layer includes photolithography. For another example, the method of etching the second conductive type doped region 30 and the first conductive type drift layer 20 includes at least one of dry etching and laser etching.

[0077] like Fig.11 As shown, at least two dielectric layers are deposited on the first conductive type drift layer 20, and at least two dielectric layers are also filled in the groove 42. The method of depositing at least two dielectric layers includes at least one of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition and atomic layer deposition. The deposition method of each dielectric layer 41 can be the same or different. In one embodiment, the dielectric layer 41 is deposited step by step to form a laminated dielectric layer ( Fig.11 Not shown), and then the laminated dielectric layer ( Fig.11 The portion of the substrate (not shown) outside the trench 42 is etched to obtain the at least two dielectric layers.

[0078] In the optional embodiment, please refer to Figure 3 The manufacturing method further includes the step of forming a first metal layer 50. The step of forming the first metal layer 50 is performed after forming the electric field modulation structure 40. The first metal layer 50 is in ohmic contact with the second conductive type doping region 30, and the first metal layer 50 is in Schottky contact with a portion of the first conductive type drift layer 20 located between two adjacent second conductive type doping regions 30. In an optional embodiment, please refer to Figure 3The manufacturing method further includes the step of forming a second metal layer 60, and the second metal layer 60 is located on a side of the substrate 10 away from the first conductive type drift layer 20. The step of forming the second metal layer 60 can be performed after forming the electric field modulation structure 40, or before providing a substrate 10, and the substrate 10 is grown based on one side of the second metal layer 60.

[0079] The method for manufacturing the semiconductor power device according to the embodiment of the present application has a simple process and low cost.

[0080] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A semiconductor power device, characterized in that: include: substrate; A first conductive type drift layer is located on the substrate, wherein a second conductive type doping region is provided in a surface layer of the first conductive type drift layer away from the substrate; The electric field modulation structure is located in the first conductive type drift layer, and the electric field modulation structure provides at least one electric field modulation surface, and the electric field modulation surface is used to disperse the electric field at the corner of the second conductive type doped region close to the substrate side.

2. The semiconductor power device according to claim 1, characterized in that: The electric field modulation structure includes at least two dielectric layers, and the dielectric constants of two adjacent dielectric layers are different, so that the electric field modulation surface is formed based on the contact interface of the two adjacent dielectric layers.

3. The semiconductor power device according to claim 2, characterized in that: The dielectric constant of the dielectric layer is in the range of 3 to 30, and the material of the dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, boron nitride and zirconium oxide.

4. The semiconductor power device according to claim 2, characterized in that: In a direction perpendicular to the substrate to the first conductive type drift layer, the width of the dielectric layer ranges from 1 μm to 3 μm.

5. The semiconductor power device according to claim 2, characterized in that: In the electric field modulation structure: The electric field modulation surface farthest from the substrate is located between the second conductive type doping region and the substrate; The distance between the electric field modulation surface closest to the substrate and the substrate is not greater than half the thickness of the first conductive type drift layer.

6. The semiconductor power device according to claim 2, characterized in that: The electric field modulation structure further includes a groove, and along the direction from the substrate to the first conductive type drift layer, the groove at least partially penetrates the second conductive type doped region, and all the dielectric layers in the same electric field modulation structure are stacked in the groove.

7. The semiconductor power device according to claim 6, characterized in that: A side of the electric field modulation structure away from the second conductive type doping region is connected to the substrate.

8. The semiconductor power device according to claim 6 or 7, characterized in that: A surface of the electric field modulation structure away from the substrate is flush with a surface of the first conductive type drift layer away from the substrate.

9. The semiconductor power device according to claim 1, characterized in that: The surface layer of the first conductive type drift layer away from the substrate has multiple second conductive type doped regions, and the multiple second conductive type doped regions are arranged at intervals; the semiconductor power device also includes a first metal layer, the first metal layer is in ohmic contact with the second conductive type doped region, and the first metal layer is in Schottky contact with a portion of the first conductive type drift layer located between two adjacent second conductive type doped regions, the second conductive type doped region, the first conductive type drift layer and the substrate constitute a PiN diode, the first metal layer and the portion of the first conductive type drift layer located between two adjacent second conductive type doped regions constitute a Schottky diode, and the PiN diode and the Schottky diode constitute an MPS diode.

10. A method for manufacturing a semiconductor power device, characterized in that: The manufacturing method is used to manufacture the semiconductor power device according to any one of claims 1 to 9, and the manufacturing method comprises the following steps: providing a substrate; forming a first conductive type drift layer on the substrate, wherein a second conductive type doped region is formed in a surface layer of the first conductive type drift layer away from the substrate; An electric field modulation structure is formed in the first conductive type drift layer, wherein the electric field modulation structure provides at least one electric field modulation surface for dispersing the electric field at a corner of the second conductive type doped region close to the substrate.

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