Semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device may include: a first gate structure including stacked first selection lines, each first selection line including a first cell region and a first pad region adjacent in a first direction; a second gate structure including stacked second selection lines, each second selection line including a second cell region and a second pad region adjacent in the first direction; first contact plugs extending through the first pad regions and connected to the first selection lines, respectively; and second contact plugs extending through the second pad regions and respectively connected to the second selection lines, and the first pad regions may have a width greater than a width of the first cell regions in a second direction intersecting the first direction, and the second pad regions may have a width greater than a width of the second cell regions in a second direction intersecting the first direction. And the second pad region may have a width greater than a width of the first pad region.

Description

Technical Field

[0001] The present disclosure relates generally to an electronic device, and more particularly, to a semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a two-dimensional semiconductor device in which a memory cell is formed in a single layer on a substrate has reached a limit, a three-dimensional (3-D) semiconductor device in which memory cells are stacked in multiple layers above a substrate has been proposed. Currently, extensive research work is being conducted for developing a 3-D semiconductor device with improved operational reliability and for improving its manufacturing method. Summary of the invention

[0003] According to an embodiment disclosed in the present invention, a semiconductor device may include: a first gate structure, the first gate structure includes stacked first selection lines, each first selection line includes a first unit region and a first pad region adjacent to each other in a first direction; a second gate structure, the second gate structure includes stacked second selection lines, each second selection line includes a second unit region and a second pad region adjacent to each other in the first direction; a first contact plug, the first contact plug extends through the first pad region and is respectively connected to the first selection line; and a second contact plug extends through the second pad region and is respectively connected to the second selection line, and in a second direction intersecting the first direction, the first pad region may have a width greater than a width of the first unit region, and the second pad region may have a width greater than a width of the first pad region.

[0004] According to one embodiment disclosed in the present invention, a semiconductor device may include: a gate line; a first selection line, which is stacked on the gate line; a dummy selection line, which is stacked on the gate line; an isolation structure, which is arranged between the first selection line and the dummy selection line and extends to the topmost gate line among the gate lines; a first contact plug, which extends into the first selection line at different depths and is respectively connected to the first selection line; a third contact plug, which extends through the dummy selection line and is respectively connected to the gate lines; and a fourth contact plug, which extends through the first selection line and is connected to the topmost gate line. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A and Figure 1B is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0006] Figure 2A and Figure 2B is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0007] FIG. 3A to FIG. 3C is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0008] Figure 4 is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0009] Figure 5A and Figure 5B is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 6 is a circuit diagram showing a cell array structure of a semiconductor device according to one embodiment disclosed in the present invention. DETAILED DESCRIPTION

[0011] One embodiment of the present disclosure provides a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same.

[0012] The integration degree of a semiconductor device can be increased by stacking memory cells in three dimensions. In addition, a semiconductor device having a stable structure and improved reliability can also be provided.

[0013] Hereinafter, embodiments according to the technical spirit disclosed in the present invention are described with reference to the accompanying drawings.

[0014] Figure 1A and Figure 1B is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0015] Reference Figure 1A, the semiconductor device may include a first selection line SL1 and a second selection line SL2. The first selection line SL1 may extend in a first direction I, and may include a protrusion protruding in a second direction II. The second selection line SL2 may extend in the first direction I, and may include a recess. The protrusion of the first selection line SL1 may be disposed in the recess of the second selection line SL2. The first selection line SL1 and the second selection line SL2 may be arranged in a form in which the protrusion and the recess are engaged. The second selection line SL2 may surround the protrusion of the first selection line SL1. The first selection line SL1 and the second selection line SL2 may be disposed at substantially the same height in a third direction III. Here, the first direction I and the second direction II may intersect each other. In some embodiments, the first direction I and the second direction II may intersect at a right angle. The third direction III may be a direction orthogonal to a plane defined by the first direction I and the second direction II.

[0016] The first selection line SL1 may be a source selection line or a drain selection line. The first selection line SL1 may include a first cell region CR1 and a first pad region PD1. The first cell region CR1 and the first pad region PD1 may be adjacent in the first direction I. The first cell region CR1 and the first pad region PD1 may contact each other in the first direction I. In the second direction II, the first cell region CR1 may have a first width W1C, and the first pad region PD1 may have a first width W1P. In the second direction II, the width W1P of the first pad region PD1 may be greater than the width W1C of the first cell region CR1. The first cell region CR1 and the first pad region PD1 may each have a substantially rectangular prism shape, and may be formed adjacent to each other to form the first selection line SL1 to have an L shape.

[0017] The second selection line SL2 may be a source selection line or a drain selection line. The second selection line SL2 may include a second unit region CR2 and a second pad region PD2. The second unit region CR2 and the second pad region PD2 may be connected to each other through a connection region CN. In the second direction II, the second unit region CR2 may have a second width W2C, and the second pad region PD2 may have a second width W2P. In the second direction II, the width W2P of the second pad region PD2 may be greater than the width W2C of the second unit region CR2. The width W2P of the second pad region PD2 may be greater than the width W1P of the first pad region PD1.

[0018] The second selection line SL2 may further include a connection region CN connecting the second cell region CR2 with the second pad region PD2. The connection region CN may extend along the sidewall of the first pad region in the first direction I. In the second direction II, the connection region CN may have a width smaller than that of the second cell region CR2 and the second pad region PD2.

[0019] The first pad region PD1 may protrude toward the connection region CN between the second unit region CR2 and the second pad region PD2. In the second direction II, the width of the connection region CN may be less than the width W2C of the second unit region. A rectangular receiving region may be defined between the second unit region CR2 and the second pad region PD2, and the first pad region PD1 may protrude into the rectangular receiving region. Therefore, the more the width of the connection region CN is reduced, the more the first pad region PD1 may protrude into the rectangular receiving region.

[0020] The first cell region CR1 and the second cell region CR2 may be regions where a memory string is disposed. The first pad region PD1 and the second pad region PD2 may be regions where a contact plug for transmitting a bias (e.g., a bias voltage or a bias current, typically a bias voltage) to a selection line is disposed. The first cell region CR1 and the second cell region CR2 may be adjacent in the second direction II. The first pad region PD1 and the connection region CN may be adjacent in the second direction II.

[0021] The first pad region PD1 and the second pad region PD2 may be adjacent in the first direction I. The first pad region PD1 may be disposed between the first unit region CR1 and the second pad region PD2 and between the second unit region CR2 and the second pad region PD2. Therefore, in the second direction II, the width of the second pad region PD2 may be greater than the width obtained by adding the width of the first unit region CR1 to the width of the second unit region CR2.

[0022] Reference Figure 1B , the semiconductor device may include a first gate structure GST1 and a second gate structure GST2. The first gate structure GST1 may include stacked first selection lines SL1_1 to SL1_n. The second gate structure GST2 may include stacked second selection lines SL2_1 to SL2_n, where n is an integer equal to or greater than 1.

[0023] The semiconductor device may further include at least one of a third gate structure GST3 and a dummy gate structure DGST. The third gate structure GST3 may include stacked gate lines GL. The gate lines GL may be word lines WL or dummy gate lines DGL. The dummy gate structure DGST may include stacked dummy selection lines DMSL1 to DMSLn.

[0024] Among the gate lines GL included in the third gate structure GST3, at least one uppermost gate line GL may be a dummy gate line DGL. The dummy gate line DGL may have a shape similar to that of at least one of the first selection lines SL1_1 to SL1_n, the second selection lines SL2_1 to SL2_n, and the gate line GL. The dummy gate line DGL may be disposed between the gate line GL and the first selection lines SL1_1 to SL1_n, between the gate line GL and the second selection lines SL2_1 to SL2_n, and between the gate line GL and the dummy selection lines DMSL1 to DMSLn.

[0025] The first selection lines SL1_1 to SL1_n and the second selection lines SL2_1 to SL2_n may be stacked on the gate lines GL. The dummy selection lines DMSL1 to DMSLn may be stacked on the gate lines GL. The dummy selection lines DMSL1 to DMSLn may be adjacent to the second selection lines SL2_1 to SL2_n in the first direction I. The second pad region PD2 may be disposed between the dummy selection lines DMSL1 to DMSLn and the first pad region PD1 and between the connection region CN and the dummy selection lines DMSL1 to DMSLn. In the second direction II, the dummy selection lines DMSL1 to DMSLn may have substantially the same width as the second pad region PD2.

[0026] According to the above structure, the first pad region PD1 may have a width greater than that of the first cell region CR1, and the second pad region PD2 may have a width greater than that of the second cell region CR2. By selectively increasing the widths of the first pad region PD1 and the second pad region PD2, areas where contact plugs connected to the first selection lines SL1_1 to SL1_n and the second selection lines SL2_1 to SL2_n are to be formed may be ensured.

[0027] Figure 2A and Figure 2B 1 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0028] Reference Figure 2A , the semiconductor device may include at least one of a first gate structure GST1, a second gate structure GST2, and a dummy gate structure DGST. The first gate structure GST1 and the second gate structure GST2 may be alternately arranged along the second direction II. The first gate structure GST1 and the second gate structure GST2 may be adjacent to the dummy gate structure DGST in the first direction I.

[0029] The first gate structure GST1 may include a stacked first selection line SL1. The first selection line SL1 may include a first cell region CR1 and a first pad region PD1. A channel structure CH and a dummy channel structure DCH may be provided in the first cell region CR1. The first contact plug CT1 may be provided in the first pad region PD1. The number of the first contact plugs CT1 may be equal to or greater than the number of the first selection lines SL1. The insulating spacer SPC may surround the sidewall of the first contact plug CT1. The first contact plug CT1 may have a width (or diameter) greater than a width (or diameter) of the channel structure CH. The first support member SP1 may be provided around the first contact plug CT1.

[0030] The second gate structure GST2 may include a stacked second selection line SL2. The second selection line SL2 may include a second cell region CR2 and a second pad region PD2. The channel structure CH and the dummy channel structure DCH may be disposed in the second cell region CR2. The second contact plug CT2 may be disposed in the second pad region PD2. The number of the second contact plugs CT2 may be equal to or greater than the number of the second selection lines SL2. The insulating spacer SPC may surround the sidewall of the second contact plug CT2. The second contact plug CT2 may have a width greater than the width of the channel structure CH. The first support member SP1 may be disposed around the second contact plug CT2.

[0031] The dummy gate structure DGST may include a stacked dummy selection line DMSL. The first support member SP1 and the third contact plug CT3 may be disposed in the dummy gate structure DGST. The insulating spacer SPC may surround the sidewall of the third contact plug CT3. The third contact plug CT3 may have a width greater than the width of the channel structure CH. The second support member SP2 may be disposed around the third contact plug CT3. In some embodiments, the second support member SP2 may be arranged along the periphery of a circular shape, an elliptical shape, a polygonal shape, or a similar shape surrounding the third contact plug CT3. The first support member SP1 may be disposed around the second support member SP2. The second support member SP2 may have a width narrower than the width of the first support member SP1.

[0032] The first gate structure GST1, the second gate structure GST2, and the dummy gate structure DGS may be isolated by an isolation structure ISS. The isolation structure ISS may include at least one of a first line portion L1, a second line portion L2, and a third line portion L3. The first line portion L1 may extend between the first gate structure GST1 and the second gate structure GST2. In some embodiments, the first line portion L1 may extend between the first gate structure GST1 and the second gate structure GST2 adjacent in the second direction II.

[0033] The first line portion L1 may include a straight line portion LP and a bent portion BP. The straight line portion LP may extend in the first direction I between the first cell region CR1 and the second cell region CR2. The bent portion BP may extend between the first pad region PD1 and the second pad region PD2. In some embodiments, the bent portion BP may include a first portion P1 extending between the second cell region CR2 and the first pad region PD1, a second portion P2 extending between the first pad region PD1 and the connection region CN, and a third portion P3 extending between the first pad region PD1 and the second pad region PD2. Each of these portions may have a straight line shape, and a bending point may be set between each of these portions.

[0034] The second line portion L2 may extend in the second direction II. The second gate structure GST2 and the dummy gate structure DGST may be separated from each other by the second line portion L2. The third line portion L3 may extend in the first direction I. The first gate structure GST1 and the second gate structure GST2 adjacent in the second direction II may be separated from each other by the third line portion L3.

[0035] Reference Figure 2B , the semiconductor device may further include a third gate structure GST3. The third gate structure GST3 may be disposed above or below the first gate structure GST1, the second gate structure GST2, and the dummy gate structure DGST. In some embodiments, the first gate structure GST1, the second gate structure GST2, and the dummy gate structure DGST may be disposed on the third gate structure GST3. The first unit region CR1 and the second unit region CR2 may be disposed on the third unit region CR3. The first pad region PD1, the connection region CN, and the second pad region PD2 may be disposed on the connection region CNR. The dummy gate structure DGST may be disposed on the third pad region PD3.

[0036] The third gate structure GST3 may include a stacked word line WL. The word line WL may include a third cell region CR3, a connection region CNR, and a third pad region PD3. The connection region CNR may connect the third cell region CR3 and the third pad region PD3. In the second direction II, the third cell region CR3, the connection region CNR, and the third pad region PD3 may have substantially the same width.

[0037] The channel structure CH and the dummy channel structure DCH may be disposed in the third cell region CR3. The first support member SP1 may be disposed in the connection region CNR and the third pad region PD3. The third contact plug CT3 and the second support member SP2 may be disposed in the third pad region PD3. The insulating spacer SPC may surround the sidewall of the third contact plug CT3. The second support member SP2 may be disposed around the third contact plug CT3. The first support member SP1 may be disposed around the second support member SP2.

[0038] For reference, in the present embodiment, a case is described where the memory block MB includes three first gate structures GST1, three second gate structures GST2, and one third gate structure GST3, but the number of the first gate structures GST1 and the second gate structures GST2 included in the memory block MB may be changed. Similarly, the number of the channel structures CH included in the memory block MB may be changed. In addition, the number of the first line portions L1 and the third line portions L3 included in the isolation structure ISS may be changed.

[0039] According to the above structure, the first pad region PD1 may have a width greater than that of the first cell region CR1. The second pad region PD2 may have a width greater than that of the second cell region CR2. Therefore, the first contact plug CT1 and the second contact plug CT2 may have a width greater than that of the channel structure CH.

[0040] FIG. 3A to FIG. 3C 1 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0041] Reference Figure 3A , the semiconductor device may include at least one of a first gate structure GST1 , a second gate structure GST2 , a third gate structure GST3 , a first channel structure CH1 , a second channel structure CH2 , and an isolation structure ISS.

[0042] The first gate structure GST1 may include alternately stacked first conductive layers 31 and insulating layers 35. The first conductive layer 31 may be a first selection line SL1, a drain selection line, or a source selection line. The first conductive layer 31 may include polysilicon, tungsten, molybdenum, or the like.

[0043] The second gate structure GST2 may include alternately stacked second conductive layers 32 and insulating layers 35. The second conductive layer 32 may be a second selection line SL2, a drain selection line, or a source selection line. The second conductive layer 32 may include polysilicon, tungsten, molybdenum, or the like.

[0044] The third gate structure GST3 may include alternately stacked third conductive layers 33 and insulating layers 35. The third conductive layers 33 may be word lines WL or dummy gate lines DGL. In some embodiments, at least one uppermost conductive layer may be a dummy gate line DGL, and the remaining third conductive layers 33 may be word lines WL. The third conductive layer 33 may include polysilicon, tungsten, molybdenum, etc.

[0045] The first channel structure CH1 may extend through the first gate structure GST1 and the third gate structure GST3. The first channel structure CH1 may extend through the first cell region CR1 and the third cell region CR3. The first channel structure CH1 may include at least one of a first channel layer 36A, a first memory layer 37A, and a first insulating core 38A. The first memory layer 37A may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The first channel structure CH1 may have a first width Wch1.

[0046] The second channel structure CH2 may extend through the second gate structure GST2 and the third gate structure GST3. The second channel structure CH2 may extend through the second cell region CR2 and the third cell region CR3. The second channel structure CH2 may include at least one of a second channel layer 36B, a second memory layer 37B, and a second insulating core 38B. The second memory layer 37B may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The second channel structure CH2 may have a second width Wch2. The first width Wch1 and the second width Wch2 may be the same or substantially the same.

[0047] The first channel structure CH1 may be adjacent to the second channel structure CH2 in the second direction II. The isolation structure ISS may be disposed between the first channel structure CH1 and the second channel structure CH2. The first line portion L1 of the isolation structure ISS may be disposed between the first gate structure GST1 and the second gate structure GST2, and may isolate the first gate structure GST1 and the second gate structure GST2 from each other. The isolation structure ISS may be disposed on the third gate structure GST3. A via 39 may be connected to the first channel structure CH1 and the second channel structure CH2.

[0048] Reference Figure 3B , the semiconductor device may include at least one of a first gate structure GST1 , a second gate structure GST2 , a third gate structure GST3 , a first contact plug CT1 , a second contact plug CT2 , an insulating spacer SPC, and an isolation structure ISS.

[0049] The first contact plug CT1 may extend through the first gate structure GST1. The first contact plugs CT1 may extend at different depths within the first pad region PD1 and may be electrically connected to the first conductive layer 31 in a one-to-one correspondence, respectively. The first contact plug CT1 may have a first width WC1, which may be greater than at least one of a first width Wch1 of the first channel structure CH1 and a second width Wch2 of the second channel structure CH2.

[0050] The second contact plug CT2 may extend through the second gate structure GST2. The second contact plug CT2 may extend at different depths within the second pad region PD2. The second contact plugs CT2 may be electrically connected to the second conductive layer 32 in a one-to-one correspondence, respectively. The second contact plug CT2 may have a second width WC2. The second width WC2 may be greater than at least one of the first width Wch1 of the first channel structure CH1 and the second width Wch2 of the second channel structure CH2.

[0051] The first contact plug CT1 and the second contact plug CT2 may be adjacent in the first direction I, wherein an isolation structure ISS is disposed between the first contact plug CT1 and the second contact plug CT2. A third line portion L3 of the isolation structure ISS may be disposed between the first gate structure GST1 and the second gate structure GST2, and may isolate the first gate structure GST1 and the second gate structure GST2 from each other. The isolation structure ISS may be disposed on the third gate structure GST3.

[0052] Reference Figure 3C , the semiconductor device may include at least one of a first gate structure GST1 , a second gate structure GST2 , a third gate structure GST3 , a dummy gate structure DGST, a third contact plug CT3 , an insulating spacer SPC, and an isolation structure ISS.

[0053] The dummy gate structure DGST may include a fourth conductive layer 34 and an insulating layer 35 alternately stacked in the third direction III. The fourth conductive layer 34 may be a dummy selection line DMSL. The fourth conductive layer 34 may include polysilicon, tungsten, molybdenum, etc. The first gate structure GST1, the second gate structure GST2, and the dummy gate structure DGST may be disposed on the third gate structure GST3.

[0054] The third contact plug CT3 may extend through the dummy gate structure DGST and the third gate structure GST3. The third contact plug CT3 may pass through the dummy gate structure DGST and extend at different depths within the third pad region PD3. The third contact plugs CT3 may be electrically connected to the third conductive layer 33, respectively. The third contact plug CT3 may have a third width WC3, and the third width WC3 may be greater than at least one of the first width Wch1 of the first channel structure CH1 and the second width Wch2 of the second channel structure CH2.

[0055] The third contact plug CT3 and the second contact plug CT2 may be adjacent in the first direction I, wherein an isolation structure ISS is disposed between the third contact plug CT3 and the second contact plug CT2. A second line portion L2 of the isolation structure ISS may be disposed between the dummy gate structure DGST and the second gate structure GST2, and may isolate the dummy gate structure DGST and the second gate structure GST2 from each other. The isolation structure ISS may be disposed on the third gate structure GST3.

[0056] According to the above structure, the first to third gate structures GST1 to GST3 may not be patterned in a stepped shape, and the first to third contact plugs CT1 to CT3 may be connected to the first to third conductive layers 31 to 33. Since the first to third contact plugs CT1 to CT3 extend through the first to third gate structures GST1 to GST3, the first to third contact plugs CT1 to CT3 may be formed with a width greater than that of the first channel structure CH1 and the second channel structure CH2. In addition, since the first and second pad regions PD1 and PD2 have a width greater than that of the first and second cell regions CR1 and CR2, the first to third contact plugs CT1 to CT3 having relatively large widths may be connected to the first to third conductive layers 31 to 33, respectively.

[0057] Figure 4 1 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0058] Reference Figure 4 The semiconductor device may include at least one of a first gate structure GST1, a second gate structure GST2, a dummy gate structure DGST, a first support member SP1, a second support member SP2, a first contact plug CT1, a second contact plug CT2, a third contact plug CT3, an insulating spacer SPC, and an isolation structure ISS.

[0059] The isolation structure ISS may include a first line portion L1, a second line portion L2, and a third line portion L3. The second line portion L2 may extend in the second direction II, and the third line portion L3 may extend in the first direction I. The first line portion L1 may be disposed between the third line portions L3 adjacent in the second direction II, and may be connected to the third line portion L3 between the first contact plug CT1 and the second contact plug CT2.

[0060] The first line portion L1 may include a straight line portion LP and a bent portion BP. The straight line portion LP may extend in the first direction I, and the first cell region CR1 and the second cell region CR2 may be separated by the straight line portion LP. The bent portion BP may extend in a shape surrounding the first contact plug CT1, and a first pad region PD1 having a width greater than that of the first cell region CR1 may be defined by the bent portion BP.

[0061] The shape of the bent portion BP may be changed according to the layout. In some embodiments, the bent portion BP may include a first portion BP1, a second portion BP2, and a third portion BP3. The first portion BP1 may extend in the second direction II or in an oblique direction, the second portion BP2 may extend in the first direction I, and the third portion BP3 may extend in the second direction II or in an oblique direction. Here, the second direction II may intersect the first direction I at a right angle. The oblique direction may intersect the first direction I and the second direction II, and may intersect the second direction II at an angle θ. The angle θ may be an acute angle. Here, the shape of the bent portion BP may be changed according to the distance between the third line portions L3 adjacent in the second direction II, the distance between the first contact plug CT1 and the second contact plug CT2, etc.

[0062] Meanwhile, the shape of the isolation structure ISS may be changed in various ways. In some embodiments, the isolation structure ISS may have a Figure 2B and Figure 2B Described shapes and references Figure 4 The shapes described are combined into shapes.

[0063] According to the above structure, the first pad region PD1 and the second pad region PD2 may have a width greater than the width of the first cell region CR1 and the second cell region CR2, and the second pad region PD2 may have a width greater than the width of the first pad region PD1. Therefore, the area where the first contact plug CT1 and the second contact plug CT2 are to be disposed can be ensured.

[0064] Figure 5A and Figure 5B is a diagram showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0065] Reference Figure 5A and Figure 5B The semiconductor device may include a first selection line SL1, a second selection line SL2, a dummy selection line DMSL, a gate line GL, an insulating layer 55, a first contact plug CT1, a second contact plug CT2, a third contact plug CT3, and at least one of isolation structures ISS_A and ISS_B.

[0066] The gate lines GL and the insulating layers 55 may be alternately stacked. The gate lines GL may be word lines, selection lines, dummy gate lines, etc. In some embodiments, at least one uppermost gate line GL may be a dummy word line.

[0067] At least one of the first selection line SL1 and the second selection line SL2 may be stacked on the gate line GL. The first selection line SL1 and the insulating layer 55 may be alternately stacked. The second selection line SL2 and the insulating layer 55 may be alternately stacked. The first selection line SL1 and the second selection line SL2 may be source selection lines or drain selection lines.

[0068] The dummy selection line DMSL may be stacked on the gate line GL. The dummy selection line DMSL and the insulating layer 55 may be alternately stacked. The dummy selection line DMSL may be a dummy source selection line or a dummy drain selection line.

[0069] The first contact plugs CT1 may each extend at a different depth and be connected to different first selection lines SL1 among the first selection lines SL1. The first contact plugs CT1 may pass through one or more first selection lines SL1, except for the first contact plugs CT1 connected to the uppermost first selection line SL1. The second contact plugs CT2 may each extend to a different depth and be connected to different second selection lines SL2 among the second selection lines SL2. The second contact plugs CT2 may pass through one or more second selection lines SL2, except for the second contact plugs CT2 connected to the uppermost second selection line SL2. The third contact plugs CT3 may extend to different depths and pass through the dummy selection line DMSL to be connected to different gate lines among the gate lines GL. The first contact plugs CT1 and the second contact plugs CT2 may be disposed on one side of the isolation structures ISS_A and ISS_B. The third contact plugs CT3 may be disposed on the other side of the isolation structures ISS_A and ISS_B.

[0070] The semiconductor device may further include at least one of a fourth contact plug CT4 and a fifth contact plug CT5. The fourth contact plug CT4 may extend through the first selection line SL1 and may be connected to the uppermost gate line U_GL. The fifth contact plug CT5 may extend through the second selection line SL2 and may be connected to the uppermost gate line U_GL. The fourth contact plug CT4 and the fifth contact plug CT5 may be disposed on one side of the isolation structures ISS_A and ISS_B. The fourth contact plug CT4 and the fifth contact plug CT5 may have the same or substantially the same height as at least one of the third contact plugs CT3, and the third to fifth contact plugs CT3 to CT5 having the same or substantially the same height may be connected to the same gate line GL.

[0071] It may be considered that the fourth contact plug CT4 and the fifth contact plug CT5 are formed by cutting the gate line GL according to the uneven depth of the isolation structures ISS_A and ISS_B. During the manufacturing process, due to process limitations, the isolation structures ISS_A and ISS_B may be formed at different depths. Figure 5A The isolation structure ISS_A may isolate the first and second selection lines SL1 and SL2 from the dummy selection line DMSL and may be disposed on the gate line GL. Figure 5B , the isolation structure ISS_B may extend into the uppermost gate line GL and may pass through the uppermost gate line GL. Therefore, the uppermost gate line U_GL may be isolated by the isolation structure ISS_B. The isolated uppermost gate lines U_GL may be insulated from each other. In this case, the bias transmitted through the third contact plug CT3 may be transmitted only to the uppermost gate line U_GL disposed on the other side of the isolation structure ISS_B, and not to the uppermost gate line U_GL disposed on one side of the isolation structure ISS_B.

[0072] Therefore, considering the depth variation of the isolation structures ISS_A and ISS_B, the semiconductor device may further include at least one of a fourth contact plug CT4 and a fifth contact plug CT5. The fourth contact plug may extend through the first selection line SL1 and may be connected to the uppermost gate line U_GL. The fifth contact plug CT5 may extend through the second selection line SL2 and may be connected to the uppermost gate line U_GL. In some embodiments, at least one fourth contact plug CT4 may be connected to at least one uppermost gate line GL. The fourth contact plug CT4 and the fifth contact plug CT5 may transfer bias to the uppermost gate line U_GL on one side of the isolation structures ISS_A and ISS_B. The third contact plug CT3 may transfer bias to the uppermost gate line U_GL on the other side of the isolation structures ISS_A and ISS_B.

[0073] According to the above structure, considering the depth variation of the isolation structures ISS_A and ISS_B, the semiconductor device may further include at least one of the fourth contact plug CT4 and the fifth contact plug CT5. Therefore, even if the uppermost gate line U_GL is cut by the isolation structure ISS_B, the bias may be transmitted to the uppermost gate line U_GL through the fourth contact plug CT4 and the fifth contact plug CT5.

[0074] Figure 6 is a circuit diagram showing a cell array structure of a semiconductor device according to one embodiment disclosed in the present invention.

[0075] Reference Figure 6 , the cell array may include a plurality of memory strings MS. The plurality of memory strings MS may be connected between a bit line BL and a source line Source. Each memory string MS may include at least one drain select transistor DST, a plurality of memory cells MC, and at least one source select transistor SST. Each of the memory strings MS may further include at least one dummy memory cell connected between the drain select transistor DST and the memory cell MC and / or connected between the source select transistor SST and the memory cell MC.

[0076] The gate electrode of the memory cell MC is connected to the word line WL. The word line voltage (programming voltage, pass voltage, read voltage, etc.) required for the drive transistor may be applied to each of the word lines WL. The gate electrode of the drain select transistor DST may be connected to the drain select lines DSL1 to DSL6. The gate electrode of the source select transistor SST may be connected to the source select lines SSL1 and SSL2.

[0077] According to the above structure, the cell array may include a plurality of memory blocks, each of which may include a plurality of pages. The memory block may be a unit for performing an erase operation, and the page may be a unit for performing a program operation or a read operation.

[0078] The memory strings MS connected to the same bit line BL may be connected to different drain selection lines DSL0 to DSL6, respectively. The drain selection lines DSL0 to DSL6 may be connected to the same bit line BL as described above. Figures 1A to 5B The described isolation structures ISS, ISS_A, and ISS_B are electrically isolated. Therefore, the drain selection lines DSL0 to DSL6 may be driven respectively, and a program operation or a read operation may be performed in units of pages.

[0079] Although the embodiments according to the technical scope of the present disclosure have been described with reference to the accompanying drawings, this is only for the purpose of describing the embodiments of the concept disclosed in the present disclosure, and the present disclosure is not limited to the above embodiments. Within the scope of the present disclosure described in the claims, technicians in the field of the present disclosure can make various forms of substitutions, modifications and changes to the embodiments, which also belong to the scope of the present disclosure.

[0080] CROSS-REFERENCE TO RELATED APPLICATIONS

[0081] This application claims priority to Korean Patent Application No. 10-2023-0131563, filed on October 4, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first gate structure, the first gate structure comprising stacked first selection lines, each of the first selection lines comprising a first unit region and a first pad region adjacent to each other in a first direction; a second gate structure, the second gate structure comprising stacked second selection lines, each second selection line comprising a second unit region and a second pad region adjacent in the first direction; first contact plugs extending through the first pad region and connected to the first selection lines, respectively; as well as second contact plugs extending through the second pad region and connected to the second selection lines, respectively, Wherein, in a second direction intersecting the first direction, the first pad region has a width greater than a width of the first unit region, and the second pad region has a width greater than a width of the first pad region.

2. The semiconductor device according to claim 1, wherein The first pad region is disposed between the first cell region and the second pad region.

3. The semiconductor device according to claim 2, wherein: The first pad region protrudes between the second cell region and the second pad region.

4. The semiconductor device according to claim 1, wherein The first pad region and the second pad region are adjacent to each other in the first direction.

5. The semiconductor device according to claim 1, in, The second gate structure includes a connection region connecting the second cell region with the second pad region, and Wherein, the first pad area protrudes toward the connection area.

6. The semiconductor device according to claim 5, in, The first pad region protrudes into the second gate structure, and The second unit region, the connection region and the second pad region surround the first pad region.

7. The semiconductor device according to claim 1, further comprising: An isolation structure extends between the first gate structure and the second gate structure.

8. The semiconductor device according to claim 1, further comprising: a dummy gate structure, the dummy gate structure comprising stacked dummy selection lines; as well as An isolation structure electrically isolates the first gate structure, the second gate structure, and the dummy gate structure from each other.

9. The semiconductor device according to claim 8, wherein: The isolation structure comprises: a first line portion extending between the first gate structure and the second gate structure and including a bent portion; and A second line portion extends between the second gate structure and the dummy gate structure.

10. The semiconductor device according to claim 9, wherein The first line portion comprises: a straight line portion extending between the first unit region and the second unit region; and A bent portion extends between the first pad region and the second pad region.

11. The semiconductor device according to claim 8, further comprising: a third gate structure, the third gate structure comprising stacked gate lines, The first gate structure, the second gate structure, the dummy gate structure and the isolation structure are arranged on the third gate structure.

12. The semiconductor device according to claim 11, further comprising: Third contact plugs extend through the dummy gate structure and the third gate structure and are connected to the gate lines, respectively.

13. The semiconductor device according to claim 12, further comprising: A fourth contact plug extends through the first gate structure, wherein the fourth contact plug is connected to an uppermost gate line.

14. The semiconductor device according to claim 13, wherein: The uppermost gate line is a dummy word line.

15. The semiconductor device according to claim 13, further comprising: A fifth contact plug extends through the second gate structure, wherein the fifth contact plug is connected to the uppermost gate line.

16. The semiconductor device according to claim 1, further comprising: a first support member extending through the first pad region and disposed around the first contact plug; as well as A second support member extends through the second pad region and is disposed around the second contact plug.

17. The semiconductor device according to claim 1, further comprising: Insulating spacers surround sidewalls of the first contact plug and sidewalls of the second contact plug, respectively.

18. A semiconductor device, comprising: Gate lines; a first selection line, the first selection line being stacked on the gate line; A dummy selection line, the dummy selection line being stacked on the gate line; an isolation structure, the isolation structure being disposed between the first selection line and the dummy selection line and extending to an uppermost gate line among the gate lines; first contact plugs extending into the first selection lines at different depths and connected to the first selection lines, respectively; third contact plugs extending through the dummy selection lines and connected to the gate lines, respectively; as well as A fourth contact plug extends through the first selection line and is connected to the uppermost gate line.

19. The semiconductor device according to claim 18, further comprising: a second selection line, the second selection line being stacked on the gate line; as well as Second contact plugs extend into the second selection lines at different depths and are respectively connected to the second selection lines.

20. The semiconductor device according to claim 19, wherein Each of the first selection lines includes a first unit region and a first pad region adjacent to each other in a first direction, the first pad region having a width greater than a width of the first unit region in a second direction intersecting the first direction, and Each of the second selection lines includes a second pad region having a width greater than a width of the first pad region in the second direction.

21. The semiconductor device according to claim 19, further comprising: A fifth contact plug extends through the second selection line and is connected to the uppermost gate line.

22. The semiconductor device according to claim 18, wherein The uppermost gate line is a dummy gate line.

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