Removal of defective dies on donor wafers for selective layer transfer

Abstract

In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) features on a first substrate. The method further includes dispensing droplets into a subset of a plurality of regions of a second substrate, where the regions of the second substrate are defined by hydrophobic lines patterned to match a layout of IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate (e.g., via capillary force) is bonded to the droplets on the second substrate, and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of the IC components is separated from the first substrate and remains on the second substrate.

Description

Background Art

[0001] During semiconductor manufacturing, layers are transferred from one substrate to another using layer transfer techniques, typically on a wafer-level scale. These techniques require the entire layer to be transferred intact, whether or not the entire layer is needed. As a result, any unwanted portions of the transferred layer must be etched away after the transfer, which increases cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A -I shows an exemplary process flow for selective layer transfer using selective release technology.

[0003] Figure 2A -I shows an exemplary process flow for selective layer transfer using blanket laser exposure.

[0004] Figure 3A -I shows an exemplary process flow for selective layer transfer from a separate donor substrate.

[0005] Figure 4A -C shows an exemplary process flow for selective layer transfer from multiple donor substrates.

[0006] Figure 5A -F shows an exemplary process flow for forming an integrated circuit package using selective transfer of a passive interposer.

[0007] Fig. 6A -B shows an example of selective layer transfer between wafers.

[0008] Figure 7 A flow chart for performing a selective layer transfer is shown.

[0009] Figure 8 A generalized schematic diagram of a selective die removal process according to embodiments herein is shown.

[0010] Fig. 9 A more detailed schematic diagram of a selective die removal process according to embodiments herein is shown.

[0011] Fig.10 Another schematic diagram of a selective die removal process according to embodiments herein is shown.

[0012] Fig.11 A graph is shown showing the capillary stress ("pull-down" stress) on the die versus die / chip size for an exemplary 200 μm drop height.

[0013] Fig.12A graph is shown showing the pull-down stress on the die for different drop heights relative to the contact angle with the die.

[0014] Fig.13 A graph 1300 is shown showing release height relative to drop volume.

[0015] Fig.14 is a top view of a wafer and die that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0016] Fig.15 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0017] Fig.16A -D is a perspective view of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors.

[0018] Fig.17 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0019] Fig.18 is a block diagram of an exemplary electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0020] Selective layer transfer

[0021] During semiconductor manufacturing, layers are transferred from one substrate to another using layer transfer techniques, typically at a wafer-level scale. Layer transfer is useful for a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material manufacturing, III-V semiconductors above complementary metal oxide semiconductors (CMOS), and traditional CMOS applications such as metal-insulator-metal (MIM) devices and thin device and / or interconnect layer transfers. However, current layer transfer techniques are limited to entire layer transfers, which may affect cost and performance when the entire layer is not required. For example, blanket layer transfer techniques, such as ion cutting and laser lift-off layer transfers, require the entire layer to be transferred intact. As a result, any unwanted areas of the transferred layer must be etched away after the transfer, which leads to increased cost and process complexity.

[0022] Alternatively, a pick-and-place technique can be used to transfer a specific die or chiplet. For example, a chiplet generally refers to an integrated circuit (IC) that contains a clear subset of functions, which is designed to be combined with other chiplets to form a single IC package. In order to transfer a chiplet (e.g., for MIM chiplet integration in a system on a chip (SoC)), a chiplet device is manufactured on a donor substrate (e.g., a wafer or panel), the donor substrate is separated into multiple chiplets, and then the chiplets are attached one by one to a receiver substrate (e.g., a SoC wafer or package) using a pick-and-place machine. Since additional processing is required to separate the wafer and attach the corresponding chiplet dies one by one, this greatly increases the cost. For example, chiplets are typically manufactured on thicker substrates so that they can be handled without damage during the separation and attachment steps, and after the attachment step, additional processing is performed to thin the chiplets and / or remove the carrier substrate, which further increases the cost and process complexity. Specifically, cores are typically fabricated on substrates over 700 micrometers (μm) thick to provide structural and mechanical stability during fabrication, and after the separation / attachment steps, they can be thinned to approximately 20-100 μm by grinding the backside. However, grinding often results in breakage along the edges of the core die. Furthermore, thinning cores over 20 μm without creating defects can be challenging. Similarly, cores are typically separated with die areas on the millimeter scale, as for cores less than 1 millimeter (mm) the thickness of the die is often limited. 2 With the chip, pick and place assembly becomes very challenging.

[0023] Integrated circuits can also be manufactured monolithically, where all IC components and interconnects are fabricated sequentially on the same underlying substrate or wafer. However, monolithic ICs have various limitations, including design restrictions due to incompatible processes, lack of flexibility, and low yields.

[0024] Therefore, the present disclosure provides a selective layer transfer technology for selectively transferring portions of layers between substrates, and also provides devices and systems formed using the technology. For example, the technology enables the transfer of selected areas of a donor substrate to a receptor substrate, which enables the donor substrate to be reused multiple times, while also solving the above-mentioned limitations on blanket layer transfer and pick-and-place technology. Specifically, the scheme uses a selective release technology on a donor substrate (e.g., a wafer, panel, or die), combined with a patterned bonding template on a receptor substrate (e.g., a wafer, panel, or die), so that a selected area of ​​a layer on the donor substrate can be transferred to the receptor substrate. For the purposes of this disclosure, a layer may refer to one or more layers formed above a substrate, such as an individual layer of material or a stack of layers that together form an IC component (e.g., a die, interconnect, bridge, capacitor, and / or other semiconductor device) layer. A layer may also include stacked wafers, such as wafer-to-wafer bonded and stacked logic and / or memory wafers. For example, a donor wafer may include a layer of IC components (e.g., an IC die), and a selective layer transfer may be used to selectively and simultaneously transfer a specific subset of those IC components to a receptor substrate.

[0025] The scheme provides various advantages. For example, the scheme enables the transfer of selected areas of the donor wafer rather than the entire layer, which enables the donor wafer to be reused for multiple products, thereby amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) across multiple wafers. This scheme also eliminates the need to etch away excess areas, which is necessary for the transfer of the entire layer (as a result, the selectively transferred areas may not have a tilted edge from the etching, or may have a reverse tilt due to etching for separation before the transfer, unlike the areas that are etched after the entire layer transfer).

[0026] Additionally, layers of IC components may be selectively transferred at any level of granularity including entire IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, and the like.

[0027] This approach also enables areas of ultra-thin layers to be selectively transferred without greater handling and yield loss due to the handling challenges of core pick and place methods (e.g., separation, attaching each core individually, post-attachment thinning of the core). This helps to reduce the Z height of the product (e.g., for form factor, thermal and / or power transfer reasons) as well as the overall process complexity. For example, very thin IC dies or cores can be formed on any substrate and selectively transferred directly from the substrate. As a result, selectively transferring the die not only eliminates the need for post-attachment thinning, but also enables the die to be much thinner than a die that is separated, pick-and-place attached, and then thinned. In some cases, for example, the approach can enable the transfer of dies with thicknesses ranging from 100 nanometers (nm) to 5μm or more. In addition, since post-attachment thinning is not required, the selectively transferred die can have no or minimal crushing at the die edge because grinding is not performed, unlike the core that is thinned after attachment.

[0028] Similarly, this approach supports the selective transfer of very small areas on a donor substrate, such as very small dies or core particles, which are extremely difficult to do using pick-and-place techniques. In some cases, for example, the approach can enable transfer of areas less than 1 mm 2 The die (or other IC component) is, for example, 100 μm 2 (10x10μm), 10,000μm 2 (100x100μm), 810,000μm 2 (900 x 900 μm), etc. (there is no limitation on the maximum size of the area that can be selectively transferred).

[0029] This scheme also supports the selective transfer of tube cores with non-standard shapes and designs that are difficult to handle using pick-and-place machines, such as tube cores with atypical, arbitrary, irregular or non-convex shapes (e.g., L-shape, U-shape, shapes with sharp angles), tube cores with high aspect ratios (e.g., aspect ratios of 8:1 or higher), tube cores with holes, etc.

[0030] Furthermore, this scheme has extremely low topography and supports high surface cleanliness and planarization (eg, using chemical mechanical polishing (CMP) processes), which makes it compatible with hybrid bonding and fusion bonding processes. Additional advantages are described throughout this disclosure and will be apparent from the following description.

[0031] Thus, this approach enables the manufacture of complex IC packages and products by selectively transferring specific components (e.g., active circuits such as IC dies, passive circuits), rather than incorporating specific components using traditional processes such as: (i) full-layer transfer, etching away excess areas; (ii) pick-and-place assembly of individual IC components; and / or (iii) monolithic IC manufacturing.

[0032] Figure 1A -I shows an exemplary process flow for selective layer transfer using a selective release technique. In the illustrated example, a layer of integrated circuit (IC) components is selectively transferred from a donor substrate 100 to an acceptor substrate 110, as further described below.

[0033] exist Figure 1A In the process of transfer, a release layer 102 is formed over a carrier substrate, which is referred to as a donor substrate 100. The release layer 102 is a layer used for temporary bonding and peeling of a layer 104 to be selectively transferred. In some embodiments, the release layer 102 may include one or more layers and / or materials capable of providing adhesion to the donor substrate 100 and / or absorbing energy from a laser (e.g., a laser beam), such as a lossy dielectric and / or thin metal layer that provides adhesion and absorbs / reflects infrared (IR) light, an organic polymer layer (e.g., polyimide) that provides adhesion and absorbs visible or ultraviolet (UV) light, and / or a patterned dielectric layer with an anchor to provide residual adhesion (e.g., after IR laser ablation of a metal layer).

[0034] The layer 104 to be selectively transferred is formed over the release layer 102 of the donor substrate 100, for example, by directly manufacturing the layer 104 or blanket transferring the layer 104. The selective transfer layer 104 may include one or more material layers, such as a single layer of material or a stack of layers that together form an IC component (e.g., a complete IC die, core grain, interconnect, bridge, capacitor, transistor, and / or other semiconductor device) layer. In some embodiments, for example, the selective transfer layer 104 may be a prefabricated semiconductor wafer containing unseparated integrated circuit (IC) dies that is blanket transferred to the release layer 102 on the donor wafer 100.

[0035] exist Figure 1B In the process, the selective transfer layer 104 is cut over the donor substrate 100 - without cutting through the donor substrate 100 - to partially separate the IC components 106 in the layer 104, using techniques such as etching, reactive ion etching (RIE), plasma cutting, mechanical sawing, etc. In some embodiments, the release layer 102 can also be separated (e.g., cut or etched) together with the transfer layer 104.

[0036] exist Figure 1CIn the embodiment of the present invention, a release layer 112 is optionally formed over another carrier substrate, which is referred to as an acceptor substrate 110. For example, if the selectively transferred IC component 106 will subsequently be peeled off from the acceptor substrate 110 after transfer, the release layer 112 can be formed over the acceptor substrate 110. Otherwise, if the selectively transferred IC component 106 will remain on the acceptor substrate 110 after transfer, the release layer 112 on the acceptor substrate 110 can be omitted.

[0037] Next, a bonding template 114 is formed on a surface of the acceptor substrate 110 (e.g., over the release layer 112, if included). The bonding template 114 includes a pattern of bonding features or adhesion areas 114 that enable selective transfer of specific areas of the donor substrate 100 to the acceptor substrate 110. For example, the locations of the bonding features 114 on the acceptor substrate 110 correspond to the areas or IC components 106 on the donor substrate 100 that are to be transferred to the acceptor substrate 110.

[0038] In some embodiments, for example, bonding features 114 may include "island" or "mesa" structures that are similar in size to the target area to be transferred from donor substrate 100. For example, each island or mesa structure 114 may be an elevated structure on the surface of acceptor substrate 110 that occupies an area (e.g., shape / surface area) similar to the corresponding IC component 106 on donor substrate 100. In other embodiments, mesas 114 may be replaced by surface treatments by photolithography or additive manufacturing that enhance adhesion in the target area of ​​acceptor substrate 110 (e.g., the area showing mesas 114) and prevent adhesion in other areas, including but not limited to surface topography changes, use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, and the like.

[0039] In various embodiments, these bonding features 114 may be made of a dielectric material, a conductive material (e.g., a metal), or both, depending on whether an electrical connection is required between the bonded IC component 106 and the receptor substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or they may be dielectric structures with electrical contacts (e.g., hybrid bond pads) passing through them if an electrical connection is required across the bonding interface.

[0040] exist Figure 1D In the process, the donor substrate 100 and the acceptor substrate 110 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 106 on the donor 100 are aligned with the corresponding bonding features 114 on the acceptor 110 .

[0041] exist Figure 1E, the donor substrate 100 and the acceptor substrate 110 are partially bonded together. For example, an area of ​​the acceptor substrate 110 having a raised surface feature or "mesa" 114 is bonded to a corresponding area of ​​the donor substrate 100 having a target IC component 106, while other areas of the donor substrate 100 and the acceptor substrate 110 remain unbonded. In some embodiments, for example, this is controlled by the height of the bonding protrusions 114 to prevent undesired contact between areas that are not transferred. As previously mentioned, this can also be controlled by surface treatment of different areas to achieve good adhesion in the target area (e.g., where the mesa 114 is shown) and prevent or reduce adhesion in other areas.

[0042] exist Figure 1F In the present invention, the IC components 106 bonded to the receptor 110 are selectively peeled from the donor 100 using a selective release technique, such as IR peeling, selective visible or ultraviolet (UV) laser exposure, etc. For example, a laser, such as an IR or UV laser, can be used to selectively remove or ablate those areas 103 of the release layer 102 where the IC components 106 are bonded to the donor 100, thus forming gaps or pores 103 in the release layer 102 and causing those IC components 106 to be released from the donor 100.

[0043] exist Figure 1G In the embodiment of the present invention, the donor substrate 100 and the acceptor substrate 110 are mechanically separated from each other. At this point, the IC components 106 that were selectively bonded to the acceptor 110 (e.g., via the bonding structure 114) and peeled from the donor 100 remain on the acceptor 110 and are separated from the donor 100. All other IC components 106 that are not bonded to the acceptor 110 remain on the donor 100.

[0044] exist Figure 1H , the receptor substrate 110 is now ready for continued processing, such as dielectric fill 116 around the transferred IC component 106, planarization, selective transfer or pick-and-place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment of a structural substrate, stripping of the receptor substrate (e.g., via an optional receptor release layer 112), and / or any other processing required to complete the product (e.g., an IC package).

[0045] exist Fig.11 The donor substrate 100 is then reused to transfer the remaining IC components 106 (e.g., the remaining areas of the selectively transferred layer 104) to a new acceptor substrate 110'. The donor substrate 100 may continue to be reused in this manner until all IC components 106, or the entire layer 104, have been selectively transferred to any number of acceptor substrates 110.

[0046] It should be understood that the illustrated process flow for selective layer transfer is given as an example only, and many other process variations are possible. For example, the donor substrate 100 and the acceptor substrate 110 can be wafers, panels, IC packages, cores, dies, or any combination thereof (e.g., for transfer from wafer to panel, core to wafer, etc.). In addition, each substrate 100, 110 can be made of various materials, including but not limited to inorganic materials (e.g., silicon, silicon on insulator (SOI), quartz, glass, and / or III-V materials), organic materials (e.g., IR or UV transparent epoxy resin), etc.

[0047] The materials used in the release layers 102, 112 may vary depending on the type of release or stripping technique used. For example, for infrared (IR) laser stripping, the release layers 102, 112 may include one or more materials that can absorb and / or reflect infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser stripping, the release layers 102, 112 may include one or more materials that can absorb UV light (e.g., a wide range of organic polymers, including but not limited to polyimide). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric materials (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al 2 O 3 ), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 )), which can be used to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer 102, 112 are weakened, removed and / or ablated by the laser.

[0048] The number of layers 104 on the donor substrate 100 , the arrangement / structure of the layers 104 , the materials in each layer 104 , and the types of IC components 106 formed in those layers 104 may vary.

[0049] The adhesion regions or bonding features 114 on the receptor substrate 110 may be formed using any suitable surface treatment or other technique to control the adhesion level in different areas, including but not limited to surface topography changes (e.g., terraces, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc. In addition, the bonding features or adhesion regions 114 on the receptor substrate 110 may vary in size, shape, height, topography, pattern, and material. For example, inorganic dielectrics (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON) and / or silicon carbonitride (SiCN)), organic dielectrics (e.g., photoresists and adhesives), conductive materials (e.g., metals), and combinations thereof to form the bonding feature 114.

[0050] The donor substrate 100 and the acceptor substrate 110 may be (partially) bonded using any suitable bonding technique, including but not limited to hybrid bonding, fusion bonding, and adhesive bonding. The donor substrate 100 and the acceptor substrate 110 may be peeled or released using any suitable peeling technique, including but not limited to IR and UV laser peeling. In addition, there may be additional cleaning steps to reuse the donor substrate 100 before or after each selective layer transfer to the acceptor substrate 110.

[0051] In addition, in some embodiments, additional bonding and / or alignment features can be included at the wafer level and / or the die level (e.g., on the donor die, donor wafer, acceptor wafer, and / or final product). For example, the donor wafer and / or acceptor wafer can include ridges or cross structures to facilitate bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and / or through the center of the wafer, or multiple orthogonal ridges forming a cross-like pattern. Alignment features for wafers, small dies, and / or arrays of dies can also be included to facilitate bonding with proper alignment. In addition, multiple dies can be connected by small (e.g., dielectric) bridges to help them bond together and transfer together. For example, if some of the dies connected by the bridge are successfully bonded to the acceptor, the bridge can also help other bonding. Therefore, these inter-die bridges can exist on the donor before transfer, and exist on the acceptor and final product after transfer.

[0052] Additionally, in some cases, the stripping process may result in some unique damage or delamination near the die edge and / or backside that does not affect process performance but may indicate that such a solution is being used.

[0053] Figure 2A-I shows an exemplary process flow for selective layer transfer using blanket laser exposure. In the illustrated example, a layer 204 of integrated circuit (IC) components 206 is selectively transferred from a donor substrate 200 to an acceptor substrate 210. However, prior to the transfer, the entire release layer 202 on the donor 200 is mechanically weakened (e.g., using IR laser, visible light laser, UV laser, chemical etching and / or thermal techniques), which can also be referred to as partial release. In this way, after the target IC components 206 on the donor 200 are bonded to the acceptor 210, they can be completely released from the donor 200 by mechanically separating the donor 200 from the acceptor 210. In some cases, with Figure 1A This can result in a simplified and faster bonding / stripping process compared to the bonding / selective release / stripping process of the present invention. Alternatively, rather than using blanket laser exposure, the respective materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the bond to the donor 200 is weaker than the bond to the receptor 210 that is subsequently formed.

[0054] exist Figure 2A In the embodiment of the present invention, a release layer 202 is formed over a donor substrate 200. A layer 204 to be selectively transferred is formed over the release layer 202, for example, by directly manufacturing the layer 204 or blanket transferring the layer 204. In some embodiments, the selectively transferred layer 204 can be a layer of IC components (e.g., IC die, core particles, interconnects, bridges, capacitors, transistors, and / or other semiconductor devices).

[0055] exist Figure 2B In the embodiment of the present invention, the selective transfer layer 204 is cut over the donor substrate 200 - without cutting through the source substrate 200 - to partially separate the IC components 206 in the layer 204.

[0056] exist Figure 2C In the embodiment of the present invention, a blanket laser exposure is performed on the donor release layer 202 to weaken the entire release layer 202 before transfer. In some embodiments, for example, the blanket laser exposure can be performed using laser (e.g., IR or UV laser exposure), chemical and / or thermal techniques. In this way, the weakened release layer 202 has a lower bonding energy, which causes the IC components bonded to the layer 202 to be partially released.

[0057] exist Figure 2D In the embodiment, a release layer 212 is optionally formed over the acceptor substrate 210. For example, if the selectively transferred IC component 206 is to be subsequently peeled off from the acceptor substrate 210 after transfer, the release layer 212 may be formed over the acceptor 210; otherwise, the release layer 212 on the acceptor 210 may be omitted.

[0058] Next, a bonding template 214 is formed on the surface of the acceptor substrate 210 (e.g., over the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or adhesion areas 214, such as mesas, that enable selective transfer of specific areas of the donor substrate 200 to the acceptor substrate 210. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the acceptor substrate 210 (e.g., to form adhesion and non-adhesion areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc.

[0059] exist Figure 2E In the process, the donor substrate 200 and the acceptor substrate 210 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 206 on the donor 200 are aligned with the corresponding bonding features 214 on the acceptor 210 .

[0060] exist Figure 2F In FIG. 4 , a donor substrate 200 and an acceptor substrate 210 are partially bonded together, wherein a region of the donor 200 having a target IC component 206 is bonded to a region of the acceptor 210 having a bonding mesa 214 .

[0061] exist Figure 2G , the donor substrate 200 and the acceptor substrate 210 are mechanically separated from each other. At this point, the IC components 206 that are selectively bonded to the acceptor 210 (e.g., via the bonding mesas 214) remain on the acceptor 210 and are peeled / separated from the donor 200 due to the blanket weakening of the donor release layer 202. All other IC components 206 that are not bonded to the acceptor 210 remain on the donor 200.

[0062] Alternatively, in some embodiments, instead of (or in addition to) executing Figure 2C By performing blanket laser exposure in the embodiment of the present invention, the respective materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the bond of the target IC component 206 to the receptor 210 will be stronger than the bond to the donor 200. In this way, when the donor 200 and the receptor 210 are mechanically separated, the target IC component 206 will be peeled off the donor 200 and remain on the receptor 210 due to the difference in bonding strength.

[0063] exist Figure 2H, the receptor substrate 210 is ready for continued processing, such as dielectric fill 216 around the transferred IC component 206, planarization, selective transfer or pick-and-place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment of a structural substrate, stripping of the receptor substrate (e.g., via an optional receptor release layer 212), and / or any other processing required to complete a product (e.g., an IC package).

[0064] exist Fig.2I The donor substrate 200 is then reused to transfer the remaining IC components 206 (e.g., the remaining areas of the selectively transferred layer 204) to a new acceptor substrate 210'. The donor substrate 200 may continue to be reused in this manner until all IC components 206, or the entire layer 204, have been selectively transferred to any number of acceptor substrates 210.

[0065] Figure 2A -The elements marked with reference numerals in I may be similar to Figure 1A Furthermore, it should be understood that the illustrated process flow for selective layer transfer is given as an example only, and many other process variations are possible, including but not limited to those described throughout this disclosure.

[0066] Figure 3A -I shows an exemplary process flow for selective layer transfer from a separated donor substrate 300. In some cases, for example, if the percentage of integrated circuit (IC) components 306 transferred for each selective layer transfer is small, it may be easier and more cost-effective to cut the donor substrate 300 and transfer from separated donor dies 301 that contain a smaller subset of IC components 306 from the original donor substrate 300. Therefore, in the illustrated example, the donor substrate 300 having the layer 304 of IC components 306 is cut, and the resulting layer of IC components 306 located on the separated donor die 301 is selectively transferred to an acceptor substrate 310. In this way, the transfer is performed at the donor die level rather than the wafer or panel level.

[0067] exist Figure 3A In the embodiment of the present invention, a release layer 302 is formed over a donor substrate 300. A layer 304 to be selectively transferred is formed over the release layer 302, for example, by directly fabricating the layer 304 or blanket transferring the layer 304. In some embodiments, the selectively transferred layer 304 may be a layer of an IC component (e.g., an IC die, a chip, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor devices).

[0068] exist Figure 3BIn the embodiment, the selective transfer layer 304 is cut over the donor substrate 300 - without cutting through the donor substrate 300, to partially separate the IC components 306 in the layer 304. In some embodiments, the release layer 302 can also be separated (eg, cut or etched) together with the transfer layer 306.

[0069] exist Figure 3C , the donor substrate 300 is cut into separate donor dies 301, each of which contains a subset of IC components 306 from the original donor substrate 300. For example, each donor die 301 may include one or more IC components 306 from a layer 304 on the original donor substrate 300.

[0070] exist Figure 3D In the process, blanket laser exposure (as shown) or selective laser release is performed on the donor release layer 302 (e.g., using IR / UV laser exposure or thermal techniques) to weaken the entire release layer 302 before transfer, thereby partially releasing the IC component 306 from the donor die 301.

[0071] exist Figure 3E , a release layer 312 is optionally formed on the acceptor substrate 310 (e.g., if the selectively transferred IC component 306 is subsequently peeled from the acceptor substrate 310 after transfer). Next, a bonding template 314 is formed on the surface of the acceptor substrate 310 (e.g., above the release layer 312, if included). The bonding template 314 includes a pattern of bonding features or adhesion areas 314, such as mesas, which enable specific areas of the donor die 301 to be selectively transferred to the acceptor substrate 310. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the acceptor substrate 310 (e.g., to form adhesion and non-adhesion areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc.

[0072] exist Figure 3F In the embodiment, one of the donor dies 301 is picked up using a bond head 320 and placed face down on an acceptor substrate 310 such that a target IC component 306 on the donor die 301 is aligned with a corresponding bonding mesa 314 on the acceptor substrate 310. The donor die 301 and the acceptor substrate 310 are then partially bonded together (e.g., die-to-wafer bonding) such that the target IC component 306 is bonded to the acceptor bonding mesa 314.

[0073] exist Figure 3GIn the embodiment of the present invention, the bonding head 320 lifts the donor die 301 from the acceptor substrate 310 and mechanically separates it from the acceptor substrate. At this point, the IC components 306 that are selectively bonded to the acceptor 310 (e.g., via the bonding mesas 314) remain on the acceptor 310 and are peeled / separated (e.g., die-to-wafer peel) from the donor die 301 due to the blanket weakening of the donor release layer 302. All other IC components 306 that are not bonded to the acceptor substrate 310 remain on the donor die 301.

[0074] Alternatively, in some embodiments, instead of (or in addition to) executing Figure 3D Blanket laser exposure in can selectively release (e.g., as combined with Figure 1F Alternatively, the donor release layer 302 and the acceptor bonding template 314 may be formed using materials having different bonding strengths so that the bond between the target IC component 306 and the acceptor substrate 310 will be stronger than that between the target IC component 306 and the donor die 301.

[0075] exist Figure 3H and Fig. 3I In the embodiment, the bonding head 320 steps and repeats. For example, the bonding head 320 moves to a new position and repeats Figure 3F and Figure 3G The process is performed to selectively transfer another set of IC components 306 from the donor die 301 to other areas of the acceptor substrate 310.

[0076] The process may be repeated in this manner until all IC components 306 on the donor die 301 have been transferred. At this point, the bond head 320 may pick up another donor die 301 and continue transferring IC components 306 from the new donor die 301 to the same or a different receptor substrate 310.

[0077] After all transfers to receptor substrate 310 are completed, receptor 310 can be ready for continued processing, such as dielectric fill around the transferred IC components 306, planarization, selective transfer or pick-and-place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, stripping of the receptor substrate (e.g., via an optional receptor release layer 312), and / or any other processing required to complete a product (e.g., an IC package).

[0078] Figure 3A -The elements marked with reference numerals in I may be similar to Figure 1A Furthermore, it should be understood that the illustrated process flow for selective layer transfer is given as an example only, and many other process variations are possible, including but not limited to those described throughout this disclosure.

[0079] Figure 4A -C shows an exemplary process flow for selective layer transfer from multiple donor substrates. In the illustrated example, integrated circuit (IC) components 414, 434 from multiple donor substrates 410, 430 are selectively transferred to an acceptor substrate 450 using intermediate carrier substrates 420, 440. In some embodiments, the respective donors 410, 430 may have different types of IC components 414, 434, such as different types of IC dies or core particles. In this way, selective layer transfer can be used to transfer multiple types of IC components, such as different types of dies or core particles, to the same acceptor substrate 450. Although the illustrated example depicts selective transfer from two types of donor substrates 410, 430 (e.g., having two types of IC components 414, 434), any number of donor substrates having any type of IC dies or other components are possible (including different die sizes).

[0080] exist Figure 4A In the process, a layer of IC components 414 is selectively transferred from a first donor substrate 410 to an intermediate carrier substrate 420 (e.g., using any of the selective transfer flows described throughout the disclosure). For example, a release layer 412 is formed over the donor substrate 410. The layer 414 to be selectively transferred is then formed over the release layer 412 (e.g., by directly manufacturing the layer 414 or blanket transferring the layer 414 from a wafer to the donor carrier 410), and the layer 414 is cut into partially separated IC components 414. Additionally, a release layer 422 is formed over the intermediate carrier / acceptor substrate 420, and a bonding template 424 is formed on a surface of the intermediate carrier / acceptor substrate 420 (e.g., over the release layer 422). The donor 410 and the intermediate carrier 420 are then partially bonded together (e.g., the target IC component 414 on the donor 410 is bonded to a bonding feature or bonding area 424 on the intermediate carrier 420). The donor 410 and intermediate carrier 420 are then peeled and separated from each other using any of the techniques described throughout this disclosure (eg, selective release, blanket laser exposure, etc.). As a result, the target IC components 414 are peeled / separated from the donor 410 and remain on the intermediate carrier 420.

[0081] exist Figure 4BIn the process, another layer of IC components 434 is selectively transferred from a second donor substrate 430 to another intermediate carrier substrate 440 (e.g., using any of the selective transfer processes described throughout the disclosure). For example, a release layer 432 is formed over the donor substrate 430. The layer 434 to be selectively transferred is then formed over the release layer 432 (e.g., by directly manufacturing the layer 434 or blanket transferring the layer 434 from a wafer to the donor carrier 430), and the layer 434 is cut into partially separated IC components 434. In addition, a release layer 442 is formed over the intermediate carrier / receiver substrate 440, and a bonding template 444 is formed on a surface of the intermediate carrier 440 (e.g., over the release layer 442). The donor 430 and the intermediate carrier 440 are then partially bonded together (e.g., the target IC component 434 on the donor 430 is bonded to a bonding feature or bonding area 444 on the intermediate carrier 440). The donor 430 and the intermediate carrier 440 are then peeled and separated from each other using any of the techniques described throughout this disclosure (eg, selective release, blanket laser exposure, etc.). As a result, the target IC components 434 are peeled / separated from the donor 430 and remain on the intermediate carrier 440.

[0082] exist Figure 4C , the IC components 414, 434 on the two intermediate carriers 420, 440 are selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout the disclosure). For example, a release layer 452 is optionally formed on the acceptor substrate 450 (e.g., if the selectively transferred IC components 414, 434 are to be subsequently peeled off from the acceptor substrate 450 after transfer). A bonding layer 454 (e.g., having bonding areas / bonding features) is then formed on the surface of the acceptor 450 (e.g., above the release layer 452, if included). Next, the IC component 414 on the first intermediate carrier 420 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout the disclosure). Finally, the IC component 434 on the second intermediate carrier 440 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout the disclosure).

[0083] Additional processing may then be performed on the receptor substrate 450, such as cleaning steps (e.g., removing remaining bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selective transfer or pick-and-place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, stripping the receptor substrate (e.g., via an optional receptor release layer 452), and / or any other processing required to complete a product (e.g., an IC package).

[0084] It should be understood that the illustrated process flow for selective layer transfer is given by way of example only and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0085] Figure 5A -F shows an exemplary process flow for forming an integrated circuit (IC) package 500 using a selectively transferred passive interposer 506. Selective transfer can be used for a variety of applications, including the transfer of active components (e.g., IC die, transistors, diodes) and passive components (e.g., interconnects, metal-insulator-metal (MIM) cores, resistors, capacitors, inductors, transformers). In the illustrated example, the process flow is used to form an IC package 500 using a selectively transferred low-cost passive interposer 506. For example, an interposer 506 with a high-density die-to-die (D2D) link 508 is created on a donor wafer 502 and then selectively transferred to a recipient wafer 512, which enables the same donor wafer 502 to be reused multiple times and the cost of the interconnect device is amortized between multiple recipient wafers 512. In some embodiments, other components of the IC package 500, such as IC die 518a-b, may also be selectively transferred. Selective transfer can also be used for other applications, including but not limited to transfer of photonic / optical components for radio frequency (RF) and high power devices, local transfer of III-V semiconductors.

[0086] exist Figure 5A In the embodiment of the present invention, a repeating D2D interconnect pattern 506 is created on a release layer 504 of a donor substrate 502, and the resulting D2D interconnects are partially separated (eg, cut but not through the donor substrate 502). The D2D interconnects 506 include high density interconnect links 508 separated by dielectric layers 510.

[0087] exist Figure 5B In the embodiment, a transfer template 516 for selective transfer is created on a release layer 514 of an acceptor / carrier substrate 512. The transfer template 516 includes dielectric bonding protrusions 516, referred to as mesas, on the surface of the acceptor substrate 512. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the acceptor substrate 512 (e.g., to form adherent and non-adhesive areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc. In addition, in various embodiments, any number of build layers may be formed on the acceptor substrate 512 prior to forming the templated connection base or mesas 516 for selective transfer.

[0088] The bonding mesa 516 is used to selectively transfer the D2D interconnect 506 from the donor 502 to the receptor 512 (e.g., using any selective transfer described throughout this disclosure). For example, the donor 502 and the receptor 512 are aligned face-to-face, stacked, and then partially bonded together such that one of the D2D interconnects 506 on the donor 502 is bonded to the bonding mesa 516 on the receptor 512.

[0089] exist Figure 5C In the embodiment, the D2D interconnect 506 bonded to the acceptor mesa 516 is peeled off and / or released from the donor release layer 504 using any of the techniques described herein (e.g., selective release, blanket laser exposure, forming bonds with strength differences), and the donor 502 and the acceptor 512 are mechanically separated. As a result, the transferred D2D interconnect 506 is separated from the donor 502 and remains on the acceptor 512.

[0090] exist Figure 5D In the process, additional processing is performed to form the remaining interconnects, including dielectric (e.g., oxide) fill 510 and planarization, patterning / metallization of interconnect 508 (e.g., forming through dielectric vias (TDVs) 508, top metal contacts 508, such as hybrid bonding pads, dielectric layer 510), etc.

[0091] It is noted that since the D2D interposer 506 is selectively transferred and the surrounding dielectric layer 510 is fabricated directly on the receptor 512, there is a gap 511 between the transferred D2D interposer 506 and the surrounding layer 510, as shown in FIG. Figure 5D In general, such gaps or transitions can exist around any type of selectively transferred feature because they are not formed simultaneously with the surrounding layers.

[0092] exist Figure 5E In the embodiment, multiple IC dies 518a-b are attached to the top metal pad 508 (e.g., via hybrid bonding), the area around the dies 518a-b is filled with a dielectric material 510 (e.g., oxide) and planarized, and a structural substrate 520 (e.g., a structural silicon wafer) is attached.

[0093] Dies 518a-b may be attached using standard assembly techniques, such as pick and place, or using the selective transfer techniques described herein (eg, similar to the transferred D2D interconnect 506).

[0094] If pick-and-place assembly is used to attach the dies 518a-b, they are typically formed on a thick substrate for handling purposes and then thinned after attachment.

[0095] However, if the die 518a-b are selectively transferred, they can be formed on an extremely thin substrate and transferred directly from the substrate. As a result, selectively transferring the die 518a-b not only eliminates the need for post-attachment thinning, but also enables the die 518a-b to be much thinner than a die that is pick-and-place attached and subsequently thinned. In addition, if the die 518a-b are selectively transferred, there can be a gap 511 between the die 518a-b and the portion of the layer 510 surrounding the die 518a-b, similar to the gap 511 shown around the transferred D2D interconnect 506, as described above. In addition, because the die 518a-b are selectively transferred, they can be different types of die, formed on separate pieces of substrate material (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of the IC device 500.

[0096] exist Fig. 5F In the process, receptor 512 is peeled off from release layer 514 and released (eg, using any of the techniques described herein, such as IR or UV laser ablation).

[0097] At this point, IC package 500 may be finished, or additional processing may be performed. For example, if processing is performed at the wafer or panel level, the resulting IC package 500 on structural substrate 520 may be separated.

[0098] Fig. 6A -B shows an example of selective layer transfer between a donor wafer 600 and an acceptor wafer 610. Specifically, Fig. 6A 6 shows wafers 600, 610 before transfer, and Figure 6B Wafers 600, 610 after transfer are shown. In the illustrated example, a discontinuous region of the donor wafer 600 is selectively transferred to a discontinuous portion on the acceptor wafer 610. However, in other embodiments, the target region on the donor 600 and the destination region on the acceptor 610 may be partially or completely contiguous.

[0099] like Fig. 6AAs shown, before transfer, the donor wafer 600 includes a layer of integrated circuit (IC) components 602 (e.g., dies, core particles, interconnects, capacitors, transistors, etc.), which can be partially separated (e.g., cut down but not through the lower wafer 600). The acceptor wafer 610 includes an adhesion area 612 (also called a bonding template) patterned at discrete locations on the surface, which is where the target IC components 602 from the donor 600 will be transferred. In some embodiments, for example, the adhesion area 612 can be a raised structure or protrusion (referred to as a "mesa") patterned on the surface of the acceptor 610. In addition, in some embodiments, the adhesion area 612 on the acceptor 610 can have a similar footprint as the target IC component 602 on the donor 600. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the receptor substrate 610 (e.g., to form selectively transferred adhesion and non-adhesion areas), including but not limited to surface topography changes (e.g., terraces, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc.

[0100] like Figure 6B As shown, after transfer, the target IC components 602 have been transferred from the donor wafer 600 to the acceptor wafer 610. As a result, the donor wafer 600 includes a blank area 603 where the transferred IC components 602 are located, while the acceptor wafer 610 includes the transferred IC components 602 at the location of the patterned adhesion area 612. Specifically, the individual IC components 602 from the donor wafer 600 are now bonded to the individual adhesion areas 612 on the acceptor wafer 610.

[0101] Although the illustrated example depicts selective transfer between two wafers, selective transfer may be performed between panels or other substrates of any shape or size, including substrates having non-matching shapes and sizes.

[0102] Figure 7A flowchart 700 for performing a selective layer transfer is shown. It should be understood that the illustrated process flow is merely an exemplary method for performing a selective layer transfer in accordance with the present disclosure. In addition, the steps of the illustrated process flow may be performed using any suitable semiconductor manufacturing technology. For example, any suitable deposition technology, such as chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) and / or physical vapor deposition (PVD), may be used to perform film deposition, such as depositing a layer, filling portions of a layer (e.g., removed portions), and filling via openings. In addition, any suitable technology, such as lithography-based patterning / masking and / or etching, may be used to perform patterning and removal, such as interconnect patterning, forming via openings, and shaping.

[0103] The flow chart begins at block 702 by receiving a first substrate having an integrated circuit (IC) component layer, which may be referred to as a donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer over the base substrate, and a (partially separated) IC component layer over the release layer.

[0104] In some embodiments, a donor substrate can be formed by receiving a base substrate, forming a release layer over the base substrate, forming a layer of IC components over the release layer (e.g., by fabricating or transferring the layer of IC components over the release layer), and partially separating the layer of IC components (e.g., by cutting through the layer of IC components without cutting through the base substrate).

[0105] In various embodiments, the layer of IC components may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuits or components.

[0106] The base substrate may be made of one or more materials including elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H), and / or Group III-V elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including but not limited to silicon (Si), silicon dioxide (SiO2 or SiO 2 ), silicon on insulator (SOI), quartz, glass, III-V materials (e.g., gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxies / resins (e.g., IR or UV transparent epoxies).

[0107] Depending on the type of release or stripping technique used, the release layer can include one or more layers of varying materials. For example, for IR laser stripping, the release layer can include one or more layers of materials that can absorb and / or reflect infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser stripping, the release layer can include one or more layers of materials that can absorb ultraviolet (UV) electromagnetic radiation (e.g., organic polymers such as polyimide). In some embodiments, the release layer can additionally or alternatively include one or more layers of dielectric materials to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer are weakened, removed, and / or ablated by the laser (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al 2 O 3 ), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 )). Therefore, in some embodiments, the release layer can be made of one or more materials, including elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H) and carbon (C), including but not limited to any of the materials mentioned above.

[0108] The flow chart then proceeds to block 704 to receive a second substrate having one or more adhesion areas, which may be referred to as an acceptor substrate. In some embodiments, the acceptor substrate may include a base substrate having one or more adhesion areas patterned on a surface, such as a layer of raised bonding structures or "mesas" above the base substrate. The acceptor substrate may also optionally include a release layer above the base substrate (e.g., to enable the base substrate to be subsequently peeled off after transfer) and / or one or more additional build-up layers and / or IC components.

[0109] In some embodiments, the acceptor substrate can be formed by receiving a base substrate, forming a release layer over the base substrate, optionally forming additional build-up layers and / or IC components over the base substrate (e.g., over the optional release layer, if included), and forming adhesion areas (e.g., bonding structures) on the surface of the acceptor substrate (e.g., over the aforementioned layers, if included). In some embodiments, the base substrate and the optional release layer of the acceptor substrate can be made of any of the materials mentioned above for the release layers of the base substrate and the donor, respectively.

[0110] In some embodiments, the adhesion area may include a mesa structure that occupies an area similar to that of the corresponding IC component to be transferred from the donor (although in some cases, the mesa may be slightly larger or smaller than the IC component to accommodate alignment and manufacturing tolerances). Depending on the type of bonding and / or whether electrical connection is required across the bonding interface for the next bonded IC component, the mesa structure may be made of a variety of materials (e.g., dielectric materials, metals, or both). For example, the mesa structure may include a blanket dielectric structure without conductive contacts (e.g., for dielectric-to-dielectric bonding), a dielectric structure with conductive contacts (e.g., for mixed dielectric and metal bonding), and / or the conductive contacts themselves (e.g., for metal-to-metal bonding). Thus, in some embodiments, the mesa structure may be made of one or more materials including elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including but not limited to inorganic dielectrics (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and / or silicon carbonitride (SiCN)), organic dielectrics (e.g., photoresists and adhesives) and / or conductive materials (e.g., metals and alloys (e.g., any of the aforementioned metal elements and / or compounds / alloys thereof)).

[0111] However, in various embodiments, any suitable technique may be used to control adhesion levels on different regions of the acceptor substrate. For example, various surface treatments (e.g., photolithographic or additively manufactured) may be used to enhance and / or reduce adhesion in selected regions of the acceptor substrate, including but not limited to modifying the surface topography (e.g., elevated vs. recessed regions, smooth vs. rough regions), using materials with high and / or low adhesion (e.g., forming layers with adhesive and / or non-adhesive materials in selected regions), using treatments with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques (e.g., plasma or wet activation), among other examples.

[0112] For example, the surface topography of the receptor substrate can be modified (e.g., using techniques such as deposition, lithography, etching, roughening, etc.) to form regions with different adhesion levels, such as elevated (e.g., adhesion) and recessed (e.g., non-adhesion) regions, smooth (e.g., adhesion) and rough (e.g., non-adhesion) regions, etc.

[0113] As another example, the surface of the receptor substrate can be patterned with materials having high and / or low adhesion in selected areas. For example, a layer patterned with different areas of adhesive and non-adhesive materials can be formed on the receptor substrate. In some embodiments, the adhesive material can include: silicon dioxide (SiO 2 ) or silicon carbonitride (SiCN) to facilitate strong oxide fusion bonding; silicon carbide (SiC) to provide 2 or SiCN; and / or metal to form an electrical connection. In addition, in some embodiments, the non-adhesive material may include silicon nitride (Si 3 N 4 ) to form a weak bond or no bond.

[0114] As another example, treatment with a hydrophobic material and / or a self-assembled monolayer (SAM) can be used to enhance and / or reduce adhesion in selected areas of a receptor substrate (e.g., treatment with a SAM to create a monolayer with high and / or low adhesion in selected areas). In some embodiments, the hydrophobic material can include a SAM material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecylphosphonic acid), a phosphoric acid (e.g., octadecyl or perfluoroalkanephosphonic acid), or an alkanoic acid (e.g., heptanoic acid). However, non-SAM-based materials or membranes can also be used. In some embodiments, the hydrophobic material can include a polymer film, such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C 4 F 8 In other embodiments, other hydrophobic materials may be used.

[0115] As another example, surface activation techniques may be used to enhance and / or reduce adhesion in selected areas of the receptor substrate, including but not limited to plasma or wet activation.

[0116] The flow chart then proceeds to block 706 to partially bond the donor substrate to the acceptor substrate (e.g., face-to-face) such that one or more target IC components on the donor substrate are selectively bonded to one or more adhesion regions on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including but not limited to hybrid bonding, fusion bonding, and / or adhesive bonding.

[0117] The flow chart then proceeds to block 708 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. In this way, when the donor substrate and the acceptor substrate are separated, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0118] In some embodiments, the donor substrate and the acceptor substrate can be peeled / separated from each other by at least partially releasing the target IC component from the release layer of the donor substrate and then mechanically separating the donor substrate and the acceptor substrate. For example, in some embodiments, the target IC components can be completely released from the donor substrate by selectively peeling them from the donor release layer using a laser (e.g., an IR or UV laser), or the target IC components can be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After the target IC component is completely or partially released from the donor, the donor substrate and the acceptor substrate are mechanically separated, and after separation, the target IC component remains bonded to the acceptor and is no longer located on the donor.

[0119] Alternatively, or in addition, the donor release layer and receptor bonding structure can be formed using corresponding materials having different bonding strengths so that the target IC component is more strongly bonded to the receptor than to the donor, resulting in the target IC component being peeled off the donor and remaining on the receptor when the donor and receptor are mechanically separated.

[0120] The flowchart then proceeds to box 710 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick-and-place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, stripping off a receptor base substrate (e.g., via an optional receptor release layer), and / or any other processing required to complete the product (e.g., an IC package, device, system, etc.).

[0121] The finished product may include a variety of components and circuits (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memories), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, optical fibers), and / or radio frequency (RF) or high voltage components (e.g., high voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW) / bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, III-V devices / chiplets, passive RF devices (e.g., interconnects, antennas, and inductors)).

[0122] Furthermore, in some embodiments, the resulting IC package or product can be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0123] At this point, the flow chart can be completed. However, in some embodiments, the flow chart can restart and / or can repeat certain frames. For example, in some embodiments, the flow chart can restart at frame 702 to continue to perform selective transfer.

[0124] Removing defective die from donor wafer

[0125] In some cases, after fabrication, there may be one or more defective layer regions or defective dies on a donor wafer. Before the donor wafer can be used in a selective transfer process, the defective regions / dies may be removed, for example, to prevent them from being incorporated into a device / package. One way to remove defective regions / dies is to use a pick-and-place process, by which a tool can selectively remove known bad regions / dies. However, as die sizes become smaller, this type of process becomes slower and at some point becomes infeasible. This process is also not feasible for extremely thin dies or layers, for high aspect ratio dies, and for other shaped dies that cannot be handled by pick-and-place processing. Another possible way to remove these dies is to fabricate a custom repair wafer with a mesa structure morphology that matches the defects of the donor wafer, and then use a selective transfer process to remove the defects. However, such a process requires a custom repair wafer based on known defects, and the repair wafer cannot be manufactured before the defects are known (requiring additional processing time and expense) or the repair wafer must be manufactured for every known combination of defects (which is not feasible).

[0126] Thus, embodiments of the present disclosure provide a technique in which a reusable repair wafer can be used to remove defects from a donor wafer for use in a selective transfer process. The reusable repair wafer can be patterned with features that match the pattern of IC components on the donor wafer. The patterned features can be hydrophobic marks similar to those used in microfluidic self-assembly, and can contain droplets of liquid (e.g., water) placed inside the repair wafer area defined by the features. The droplets can then be placed on the repair wafer at locations that match the defects of the donor wafer, and after the adhesion of the die to the donor wafer has been weakened by, for example, laser exposure of an absorptive release layer, a selective transfer process can be used to remove the defects using capillary forces between the droplets and the defective area / die. The repair wafer can then be cleaned (i.e., bad dies and droplets are removed from it) and can be reused in a subsequent repair process to remove the defective area / die of a second donor wafer, i.e., using a droplet pattern that matches the defects of the second donor wafer.

[0127] This technique can provide one or more advantages. For example, as previously mentioned, this technique allows the use of a repair wafer that can be used and reused several times without any customization (other than matching the donor wafer pattern). Therefore, only one repair wafer needs to be manufactured for each donor wafer design, which can be manufactured after the process design is completed and can be ready as part of the process tool operation. In addition, there is no need to wait for the repair wafer to complete the entire transfer process because one repair wafer can be reused. In this way, processing costs can be significantly reduced.

[0128] Furthermore, with the embodiments herein, layers of any size, shape, or thickness can be selectively removed from a donor wafer. Thus, dies that cannot be removed by a pick-and-place process (e.g., because they are too small or too thin) can be removed by the embodiments herein. Furthermore, the embodiments herein can provide a faster process for removing defects, because liquid dispensing for each bad die location can be much faster than removing each bad die one by one from the donor wafer.

[0129] Figure 8 A generalized schematic diagram of a selective die removal process according to an embodiment of the present invention is shown. In the illustrated example, there is a donor wafer 800 having a number of defective die 802 (indicated by cross-hatching on the wafer). In addition, there is a repair wafer 810 that includes a pattern of hydrophobic features 811 that match the die pattern of the donor wafer 800. The areas between the hydrophobic features 811 of the repair wafer 810 are coated with a hydrophilic material, or can be a hydrophilic inorganic dielectric surface. These two features together can promote droplets to be retained within the area defined by the hydrophobic features 811, such as Figure 8 shown.

[0130] The hydrophobic features 811 may be formed on the repair wafer 810 using a chemical coating deposited on the wafer. In some embodiments, the hydrophobic material may be a self-assembled monolayer (SAM) material including alkyl and fluoroalkylene silanes (e.g., ODS (octadecylsilane), FDTS (perfluorodecyltrichlorosilane)), thiols (e.g., hexadecanethiol), phosphoric acids (e.g., octadecyl and perfluoroalkanephosphoric acids), alkanoic acids (e.g., heptanoic acid), or the hydrophobic material may be a non-SAM thin polymer film including siloxanes (e.g., PDMS (polydimethylsiloxane) and its derivatives, HMDSO (hexamethyldisiloxane)), silazanes (HMDS (hexamethyldisiloxane)), polyolefins (e.g., polypropylene), and fluorinated polymers (e.g., PTFE (polytetrafluoroethylene), PFPE (perfluoropolymer), PFDA (ammonium perfluorodecanoate), C 4 F 8 (octafluorocyclobutane or perfluorocyclobutane), plasma polymerized films, etc. These features can also include physical structuring of the surface to help confine the droplets to hydrophilic areas, such as roughening or grooves etched into the substrate. The hydrophilic areas can be formed by a blanket inorganic dielectric film on the substrate, which can then be patterned by forming hydrophobic features around locations that will match the die pattern on the donor wafer. The hydrophobic features can be pattern coated or deposited using a semi-additive manufacturing (SAM) process. The inorganic dielectric layer surface (e.g., SiO2) can be cleaned prior to the donor wafer repair process. 2 or Si 3 N 4 ) to reduce the water contact angle (WCA). In some embodiments, plasma treatment can be used to activate the hydrophilic surface to further reduce the WCA.

[0131] As previously described, to remove the defective die 802, a droplet may be placed onto the repair wafer at the same relative position as the corresponding defective die on the donor wafer 800. For example, for the defective die 802A of the donor wafer 800, a droplet 812A is placed on an area of ​​the repair wafer 810 corresponding to the position of the defective die 802A. Similarly, for the defective die 802B of the donor wafer 800, a droplet 812B is placed on an area of ​​the repair wafer 810 corresponding to the position of the defective die 802B. Since the area of ​​the repair wafer 810 is constrained using a hydrophobic material, the material may contain the droplet within the corresponding area as shown.

[0132] The defective die 802 may then be removed from the donor wafer 800 using a selective transfer process. That is, the donor wafer 800 may be contacted with a water droplet (or other liquid droplet) on the repair wafer 810 in the same or similar manner as described above, and the liquid droplet 812 may be able to wet the hydrophilic defective die 802 and remove the die 802 (partially released from the donor wafer 800 but still weakly adhesively bonded) via capillary forces as the donor wafer 800 is separated from the repair wafer as shown.

[0133] Fig. 9 A more detailed schematic diagram of a selective die removal process according to embodiments herein is shown. As shown, there is a repair wafer 910 that includes a pattern of hydrophobic lines 911. The pattern of lines 911 matches the die pattern of the donor wafer 900. Droplets 914A, 914B are added to selected areas of the repair wafer 910 at locations corresponding to defective die 902 of the donor wafer 900 (i.e., die 902D and 902F in the illustrated example).

[0134] The wafers are brought close together so that the die 902D, 902F contact the droplets 914A, 914B (and are not pressed too close together to avoid the droplets flowing outside the hydrophobic barrier), and the droplets 914A, 914B remove the die 902D, 902F via capillary forces. That is, the capillary forces pull the die up from the donor wafer. The capillary forces may act when contacting the die, and may pull the die from the donor wafer before the donor wafer is removed from the repair wafer, and the capillary forces keep the die 902D, 902F bonded to the repair wafer 910, as shown, while they are peeled from the adhesive layer of the donor wafer. The donor wafer 900 can then be used in a selective transfer process using an acceptor wafer 920 as described above, and the repair wafer 910 can be cleaned and reused. In some cases, for example, the repair wafer 910 may be rinsed and / or wiped with water or other solvents to remove the droplets 914 and the die 902, and may be cleaned and dried before being reused in another repair process for another donor wafer. In some embodiments, the surface of the hydrophilic dielectric layer may be roughened by an etching process to prevent the die from bonding to the repair wafer if the water droplets evaporate or are otherwise removed from the surface before the defective die is removed.

[0135] Fig.10 Another schematic diagram of a selective die removal process according to an embodiment of the present invention is shown. Specifically, Fig.10 Shows Fig. 91003 , but using a die 1002 that has hydrophobic features patterned on the outer surface in a manner similar to the hydrophobic features of the repair wafer 1010 , and in some cases, may also include a hydrophilic coating in the areas on the die surface between the hydrophobic features 1003 . In the case of thicker dies, e.g., greater than 5 μm thick, the hydrophobic features 1003 may not be needed because the edges of the die 1002 can be used to confine the liquid. However, for the removal of very thin dies, e.g., 5 μm thick or less, this may not be true, and the hydrophobic features 1003 can allow the liquid to be contained to the die surface when the die is removed. These features 1003 can be retained when the die is transferred to the recipient wafer 1020 , as shown, and can therefore be detected in an integrated circuit device incorporating the die 1002 .

[0136] To ensure that defective dies are removed in the repair process described herein, it is critical that the capillary forces pulling the defective dies away from the donor wafer are stronger than the residual adhesion forces holding the dies to the donor wafer.An analytical model is described below to illustrate the feasibility of the embodiments herein and the defined implementation conditions.

[0137] Fig.11 A graph 1100 is shown which illustrates the capillary stress ("pull-down" stress) on the die relative to the die / chip size for an exemplary 200 μm drop height. Fig.11 An exemplary residual adhesion stress 1110 is also shown for comparison. Each trace 1102-1108 shows the pull-down stress for a different contact angle (θ) relative to the die, where trace 1102 represents θ=0°, trace 1104 represents θ=30°, trace 1106 represents θ=60°, and trace 1108 represents θ=90°. As shown, the pull-down stress increases as the die size decreases, but at lower contact angles, it approaches a constant value within the range of die sizes represented by the shaded area, which obtains the highest stress. This is because the stress from the Laplace vacuum pressure in the droplet dominates for this size range at low contact angles. In this size range, the maximum stress is approximately the 0.6 mN / mm shown for a 200 μm drop height. 2 This result can be achieved using a contact angle of 30° or less and is sufficient to remove dies where residual adhesion (shown by trace 1110) has been demonstrated using infrared laser lift-off processing.

[0138] Fig.12A graph 1200 is shown showing the pull-down stress on the die for different drop heights relative to the contact angle with the die. As shown, higher pull-down stresses can be achieved by reducing the dispensed drop height / drop volume to remove the die with higher residual adhesion. The reduced drop height reduces its meniscus radius, which results in a lower vacuum level Laplace pressure in the drop. As shown, a drop volume of 2 μL or less may be sufficient to remove the die and is well within standard dispensing capabilities (such that the drop size can be controlled to sub-μL volumes).

[0139] Fig.13 Graph 1300 is shown, which shows the release height relative to the drop volume. In the case of lower drop volumes, the wafers must be brought closer together. However, as Fig.13 As shown, the release height of a 2 μL droplet for an exemplary 3.8 mm x 8.2 mm rectangular die is approximately 65 μm, which is much larger than the typical total thickness variation (TTV) value of the donor wafer.

[0140] Exemplary Embodiments

[0141] Fig.14 1400 and dies 1402 that may be included in any of the embodiments disclosed herein. Wafer 1400 may be made of semiconductor material and may include one or more dies 1402 having integrated circuit structures formed on a surface of wafer 1400. Individual dies 1402 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, wafer 1400 may undergo a separation process in which the dies 1402 are separated from one another to provide discrete "chips" of the integrated circuit product. Die 1402 may be any die disclosed herein. Die 1402 may include one or more transistors (e.g., transistors discussed below). Fig.15 Some of the transistors 1540 of the transistors 1540), supporting circuit systems that transmit electrical signals to the transistors, passive components (e.g., signal traces, transistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1400 or die 1402 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or XOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 1402. For example, a memory array formed by multiple memory devices may be combined with a processor unit (e.g., a processor unit) configured to store information in the memory devices or execute instructions stored in the memory devices. Fig.18 The processor unit 1802) or other logic is formed on the same die 1402. Various components of the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly techniques, in which some dies are attached to a wafer 1400 that includes other dies, which are then separated.

[0142] Fig.15 1402 ( Fig.14 ) among. The integrated circuit device 1500 can be formed on a die substrate 1502 (eg, Fig.14 1400) and may be included in a die (e.g., Fig.14 The die substrate 1502 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 1502 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) infrastructure. In some embodiments, the die substrate 1502 may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1502. Although several examples of materials that may form the die substrate 1502 are described herein, any material that may serve as the basis for the integrated circuit device 1500 may be used. The die substrate 1502 may be a separate die (e.g., Fig.14 of a die 1402) or a wafer (e.g., Fig.14 portion of wafer 1400).

[0143] The integrated circuit device 1500 may include one or more device layers 1504 disposed on a die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1502. The transistor 1540 may include, for example, one or more source and / or drain (S / D) regions 1520, a gate 1522 to control the flow of current between the S / D regions 1520, and one or more S / D contacts 1524 to transmit electrical signals to and from the S / D regions 1520. The transistor 1540 may include additional features not shown for clarity, such as device isolation regions and gate contacts, etc. The transistor 1540 is not limited to Fig.15The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and gate-wrap-around or all-wrap-around transistors such as nanoribbon transistors, nanosheet transistors, or nanowire transistors.

[0144] Fig.16A -D is a simplified perspective view of exemplary planar transistors, FinFET transistors, gate-all-around transistors, and stacked gate-all-around transistors that may be included in any of the embodiments disclosed herein (eg, in any of the dies). Figures 16A-16D The transistor is shown formed on a substrate 1616 having a surface 1608. Isolation regions 1614 isolate the source and drain regions of the transistor from other transistors and from a bulk region 1618 of the substrate 1616.

[0145] Fig.16A is a perspective view of an exemplary planar transistor 1600 including a gate 1602 that controls current flow between a source region 1604 and a drain region 1606. Transistor 1600 is planar because source region 1604 and drain region 1606 are planar relative to substrate surface 1608.

[0146] Fig. 16B is a perspective view of an exemplary FinFET transistor 1620 including a gate 1622 that controls current flow between a source region 1624 and a drain region 1626. Transistor 1620 is non-planar because source region 1624 and drain region 1626 include a "fin" that extends upward from substrate surface 1628. Because gate 1622 encompasses three sides of the semiconductor fin extending from source region 1624 to drain region 1626, transistor 1620 can be considered a tri-gate transistor. Fig. 16B One S / D fin is shown extending through the gate 1622 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0147] Fig. 16C is a perspective view of a gate all around (GAA) transistor 1640 including a gate 1642 that controls current flow between a source region 1644 and a drain region 1646. The transistor 1640 is non-planar because the source region 1644 and the drain region 1646 are elevated from the substrate surface 1628.

[0148] Fig.16D16 is a perspective view of a GAA transistor 1660 including a gate 1662 that controls current flow between multiple elevated source regions 1664 and multiple elevated drain regions 1666. Transistor 1660 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions arranged one on top of another. Transistors 1640 and 1660 are considered to be gate-all-around transistors because the gate covers all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 1648 and 1668 of transistors 1640 and 1660, respectively), transistors 1640 and 1660 may be alternatively referred to as nanowire, nanosheet, or nanoribbon transistors.

[0149] refer to Fig.15 , transistor 1540 may include a gate 1522 formed of at least two layers, namely a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material.

[0150] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0151] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal according to whether the transistor 1540 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0152] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0153] In some embodiments, when viewed from a cross-sectional view of transistor 1540 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1502 and two sidewall portions substantially perpendicular to the top surface of die substrate 1502. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1502 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1502. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0154] In some embodiments, a pair of sidewall spacers may be formed to opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0155] The S / D region 1520 may be formed within the die substrate 1502 and adjacent to the gate 1522 of each transistor 1540. For example, the S / D region 1520 may be formed using an implantation / diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1502 to form the S / D region 1520. The ion implantation process may be followed by an annealing process that activates the dopant and further diffuses it into the die substrate 1502. In the latter process, the die substrate 1502 may first be etched to form a recess at the location of the S / D region 1520. Thereafter, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D region 1520. In some embodiments, the S / D region 1520 may be made of a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or III-V materials or alloys, may be used to form S / D region 1520. In other embodiments, S / D region 1520 may be formed using one or more layers of metals and / or metal alloys.

[0156] By providing one or more interconnect layers (in Fig.15 The interconnect layers 1506-1510 (illustrated as interconnect layers 1506-1510) transmit electrical signals (e.g., power signals and / or input / output (I / O) signals) to / from devices (e.g., transistors 1540) of the device layer 1504. For example, the conductive features (e.g., gates 1522 and S / D contacts 1524) of the device layer 1504 can be electrically coupled to the interconnect structures 1528 of the interconnect layers 1506-1510 (also referred to as build-up layers in some cases). The one or more interconnect layers 1506-1510 can form a metallization stack (also referred to as an "ILD stack") 1519 of the integrated circuit device 1500.

[0157] The interconnect structure 1528 may be arranged within the interconnect layers 1506-1510 to transmit electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to Fig.15 The specific configuration of interconnect structure 1528 is depicted. Fig.15 A specific number of interconnect layers 1506 - 1510 are shown in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0158] In some embodiments, the interconnect structure 1528 may include a line 1528a and / or a via 1528b filled with a conductive material such as a metal. The line 1528a may be arranged to transmit an electrical signal in a direction substantially parallel to a plane of a surface of the die substrate 1502 on which the device layer 1504 is formed. For example, the line 1528a may be arranged to transmit an electrical signal in a direction substantially parallel to a plane of a surface of the die substrate 1502 on which the device layer 1504 is formed. Fig.15 The vias 1528b may be arranged to transmit electrical signals in a direction in and out of the page and / or across the page from the perspective of the device layer 1504. The vias 1528b may be arranged to transmit electrical signals in a direction substantially perpendicular to a plane of a surface of a die substrate 1502 on which the device layer 1504 is formed. In some embodiments, the vias 1528b may electrically couple together wires 1528a of different interconnect layers 1506-1510.

[0159] The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between interconnect structures 1528, such as Fig.15 1506-1510. In some embodiments, the dielectric material 1526 disposed between the interconnect structures 1528 in different layers of the interconnect layers 1506-1510 may have different compositions; in other embodiments, the composition of the dielectric material 1526 may be the same between different interconnect layers 1506-1510. The device layer 1504 may also include a dielectric material 1526 disposed between the transistor 1540 and the bottom layer of the metallization stack. The dielectric material 1526 included in the device layer 1504 may have a different composition than the dielectric material 1526 included in the interconnect layers 1506-1510; in other embodiments, the composition of the dielectric material 1526 in the device layer 1504 may be the same as the composition of the dielectric material 1526 included in any of the interconnect layers 1506-1510.

[0160] A first interconnect layer 1506 (referred to as Metal 1 or "M1") can be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 can include lines 1528a and / or vias 1528b, as shown. The lines 1528a of the first interconnect layer 1506 can be coupled to contacts (e.g., S / D contacts 1524) of the device layer 1504. The vias 1528b of the first interconnect layer 1506 can be coupled to the lines 1528a of the second interconnect layer 1508.

[0161] The second interconnect layer 1508 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include vias 1528b to couple the lines 1528a of the second interconnect layer 1508 and the lines 1528a of the third interconnect layer 1510. Although the lines 1528a and the vias 1528b are structurally outlined with lines within each interconnect layer for clarity, in some embodiments, the lines 1528a and the vias 1528b may be structurally and / or materially contiguous (e.g., filled simultaneously in a dual damascene process).

[0162] A third interconnect layer 1510 (referred to as Metal 3 or "M3") (and additional interconnect layers if desired) may be formed successively on the second interconnect layer 1508 according to similar techniques and configurations described in connection with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 1504) in the metallization stack 1519 of the integrated circuit device 1500 may be thicker than lower interconnect layers in the metallization stack 1519, wherein the lines 1528a and vias 1528b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0163] The integrated circuit device 1500 may include a solder resist material 1534 (eg, polyimide or similar material) formed on the interconnect layers 1506-1510 and one or more conductive contacts 1536. Fig.15 , the conductive contact 1536 is shown as taking the form of a bonding pad. The conductive contact 1536 can be electrically coupled to the interconnect structure 1528 and configured to transmit electrical signals of one or more transistors 1540 to an external device. For example, solder bonds can be formed on one or more conductive contacts 1536 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1500 to other components (e.g., a printed circuit board). The integrated circuit device 1500 may include additional or alternative structures to transmit electrical signals from the interconnect layers 1506--1510; for example, the conductive contact 1536 may include other similar features (e.g., a column) that transmit electrical signals to external components. The conductive contact 1536 can be used as any conductive contact described throughout the present disclosure.

[0164] In some embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) located on the opposite side of the device layer 1504. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1506--1510, thereby providing conductive paths (e.g., including conductive lines and vias) between the device layer 1504 and additional conductive contacts (not shown) located on the side of the integrated circuit device 1500 opposite the conductive contacts 1536. These additional conductive contacts may be used as any of the conductive contacts described throughout this disclosure.

[0165] In other embodiments where the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include one or more through-silicon vias (TSVs) extending through the die substrate 1502; these TSVs may make contact with the device layer 1504 and may provide a conductive path between the device layer 1504 and additional conductive contacts (not shown) located on the side of the integrated circuit device 1500 opposite the conductive contacts 1536. These additional conductive contacts may be used as any conductive contacts described throughout the present disclosure. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from conductive contacts located on the side of the integrated circuit device 1500 opposite the conductive contacts 1536 to the transistor 1540 and any other components integrated within the die 1500, and the metallization stack 1519 may be used to transmit I / O signals from the conductive contacts 1536 to the transistor 1540 and any other components integrated within the die 1500.

[0166] Multiple integrated circuit devices 1500 can be stacked, wherein one or more TSVs in each stacked device provide a connection between one of the devices in the stack and any other device. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between each HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0167] Fig.171700 (e.g., an IC component transferred from a donor wafer) that may include any embodiment disclosed herein. In some embodiments, the integrated circuit device assembly 1700 may be a microelectronic assembly. The integrated circuit device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be a motherboard, a system board, a mainboard, etc.). The integrated circuit device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; in general, the components may be disposed on one or both of the sides 1740 and 1742. Any integrated circuit component discussed below with reference to the integrated circuit device assembly 1700 may take the form of any suitable embodiment in the embodiments of the microelectronic assembly 100 disclosed herein.

[0168] In some embodiments, circuit board 1702 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers can be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1702 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 1702 may be a substrate other than a PCB. Fig.17 The integrated circuit device assembly 1700 shown in FIG. 1 includes a package structure on an interposer 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package structure on the interposer 1736 to the circuit board 1702 and can include solder balls (e.g., Fig.17 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. Coupling component 1716 can be used as a coupling component illustrated or described for any substrate assembly or substrate assembly component described herein, as appropriate.

[0169] The package-on-interposer structure 1736 may include an integrated circuit component 1720 coupled to the interposer 1704 via a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1716. Fig.17 A single integrated circuit component 1720 is shown, but multiple integrated circuit components may be coupled to interposer 1704; indeed, additional interposers may be coupled to interposer 1704. Interposer 1704 may provide an intervening substrate for bridging circuit board 1702 and integrated circuit component 1720.

[0170] Integrated circuit component 1720 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Fig.14 The tube core 1402, Fig.15 The integrated circuit device 1500 of the packaged integrated circuit device 1500) and / or one or more other appropriate components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 1720, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. These solder bumps allow the die to be directly attached to the interposer 1704. The integrated circuit component 1720 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 1720 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic dischargers (ESD) devices and memory devices.

[0171] In embodiments where the integrated circuit component 1720 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die base circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0172] In addition to including one or more processor units, integrated circuit component 1720 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)) or a combination thereof is provided.

[0173] In general, interposer 1704 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1704 can couple integrated circuit component 1720 to a set of ball grid array (BGA) conductive contacts of coupling component 1716 for coupling to circuit board 1702. Fig.17 In the illustrated embodiment, integrated circuit component 1720 and circuit board 1702 are attached to opposite sides of interposer 1704; in other embodiments, integrated circuit component 1720 and circuit board 1702 may be attached to the same side of interposer 1704. In some embodiments, three or more components may be interconnected via interposer 1704.

[0174] In some embodiments, interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 1704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through-hole vias 1710-1 (extending from the first side 1750 of the interposer 1704 to the second side 1754 of the interposer 1704), blind vias 1710-2 (extending from the first or second side 1750 or 1754 of the interposer 1704 to internal metal layers), and buried vias 1710-3 (connecting internal metal layers).

[0175] In some embodiments, interposer 1704 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1704 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 1704 to an opposite second side of interposer 1704.

[0176] The interposer 1704 may further include embedded devices 1714, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices may also be formed on the interposer 1704, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices. In embodiments where the interposer is a non-printed circuit board, the interposer package structure 1736 may take the form of any interposer package structure known in the art.

[0177] The integrated circuit device assembly 1700 may include an integrated circuit component 1724 coupled to the first side 1740 of the circuit board 1702 via a coupling component 1722. The coupling component 1722 may take the form of any of the embodiments discussed above with reference to the coupling component 1716, and the integrated circuit component 1724 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1720.

[0178] Fig.17 The integrated circuit device assembly 1700 shown in FIG. 1 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling component 1728. The package-on-package structure 1734 may include an integrated circuit component 1726 and an integrated circuit component 1732 coupled together via a coupling component 1730 such that the integrated circuit component 1726 is disposed between the circuit board 1702 and the integrated circuit component 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the integrated circuit components 1726 and 1732 may take the form of any of the embodiments of the integrated circuit component 1720 discussed above. The package-on-package structure 1734 may be configured according to any package-on-package structure known in the art.

[0179] Fig.18 1 is a block diagram of an exemplary electrical device 1800 that may include one or more of the embodiments disclosed herein. For example, any suitable component in the components of electrical device 1800 may include one or more selectively transferred IC components disclosed herein (e.g., as described above), integrated circuit device assembly 1700, integrated circuit component 1720, integrated circuit device 1500, or integrated circuit die 1402. Fig.18Several components are shown as included in electrical device 1800, but any one or more of these components may be omitted or duplicated where appropriate for the application. In some embodiments, some or all of the components included in electrical device 1800 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0180] Furthermore, in various embodiments, the electrical device 1800 may not include Fig.18 1800 may include one or more of the components shown, but the electrical device 1800 may include an interface circuit system for coupling to the one or more components. For example, the electrical device 1800 may not include the display device 1806, but may include a display device interface circuit system (e.g., a connector and a driver circuit system), and the display device 1806 may be coupled to the display device interface circuit system. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include an audio input or output device interface circuit system (e.g., a connector and a supporting circuit system), and the audio input device 1824 and the audio output device 1808 may be coupled to the audio input or output device interface circuit system.

[0181] The electrical device 1800 may include one or more processor units 1802 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0182] The electrical device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1804 may include memory located on the same integrated circuit die as the processor unit 1802. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0183] In some embodiments, the electrical device 1800 may include one or more processor units 1802 that are heterogeneous or asymmetric with respect to another processor unit 1802 in the electrical device 1800. There may be various differences between the processing units 1802 in the system in terms of a spectrum of figures of merit, including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may manifest themselves substantially as asymmetry and heterogeneity between the processor units 1802 in the electrical device 1800.

[0184] In some embodiments, electrical device 1800 may include communication component 1812 (e.g., one or more communication components). For example, communication component 1812 may manage wireless communications for data transfer to and from electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that are capable of transmitting data through a non-solid medium via the use of modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0185] The communication component 1812 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks, WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication component 1812 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1812 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), its derivative standards, and any other wireless protocols designated as 3G, 4G, 5G and higher standards. In other embodiments, the communication component 1812 can operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0186] In some embodiments, the communication component 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1812 may include multiple communication components. For example, the first communication component 1812 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1812 may be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication component 1812 may be dedicated to wireless communications, and the second communication component 1812 may be dedicated to wired communications.

[0187] The electrical device 1800 may include a battery / power circuit system 1814. The battery / power circuit system 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0188] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as described above). The display device 1806 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0189] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as described above). The audio output device 1808 may include any embedded or wired or wirelessly connected external device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0190] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 1800 may include a global navigation satellite system (GNSS) device 1818 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 1818 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1800 based on information received from one or more GNSS satellites, as is known in the art.

[0191] The electrical device 1800 may include other output devices 1810 (or corresponding interface circuitry, as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0192] The electrical device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0193] The electrical device 1800 may have any desired form factor, such as a portable or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop, a 2-in-1 convertible computer, a portable all-in-one computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or slide computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1800 may be any other electronic device that processes data. In some embodiments, the electrical device 1800 may include multiple discrete physical components. In view of the range of devices that the electrical device 1800 can be in various embodiments, in some embodiments, the electrical device 1800 may be referred to as a computing device or a computing system.

[0194] Example

[0195] Illustrative examples of the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include any one or more of the examples described below and any combination thereof. In some embodiments, at least one of the systems or components set forth in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes and / or methods set forth in the following examples.

[0196] Example 1 is a microelectronic component comprising: a substrate; a plurality of mesa structures on a surface of the substrate; and an integrated circuit (IC) component on each corresponding mesa structure, wherein each IC component comprises a hydrophobic line on a surface of the IC component in contact with the mesa structure.

[0197] Example 2 includes the subject matter of Example 1, wherein the hydrophobic line defines an area on the surface of the IC component that contacts the mesa structure.

[0198] Example 3 includes the subject matter of Example 2, wherein each IC component further comprises a hydrophilic layer in the area defined by the hydrophobic lines.

[0199] Example 4 includes the subject matter of any of Examples 1-3, wherein the mesa structure comprises at least one of a dielectric material or a metal.

[0200] Example 5 includes the subject matter of any of Examples 1-4, wherein each mesa structure has a similar footprint as the IC component thereon.

[0201] Example 6 includes the subject matter of any of Examples 1-5, wherein the IC component has a thickness of 5 μm or less.

[0202] Example 7 includes the subject matter of any of Examples 1-6, wherein the IC component has a diameter less than 1 mm. 2 area.

[0203] Example 8 includes the subject matter of any of Examples 1-7, wherein the IC component includes one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

[0204] Example 9 is an integrated circuit device, comprising: a substrate including a plurality of mesa structures; a plurality of integrated circuit (IC) components located on the substrate, each IC component being located on a corresponding mesa structure, wherein each IC component includes a hydrophobic line located on a surface of the IC component in contact with the mesa structure; and a plurality of building layers located on the substrate, wherein a gap exists between each IC component and a portion of the building layer surrounding the IC component.

[0205] Example 10 includes the subject matter of Example 9, wherein the hydrophobic line defines an area on the surface of the IC component that contacts the mesa structure.

[0206] Example 11 includes the subject matter of Example 10, wherein each IC component further comprises a hydrophilic layer in the area defined by the hydrophobic lines.

[0207] Example 12 includes the subject matter of any of Examples 9-11, wherein the mesa structure comprises at least one of a dielectric material or a metal.

[0208] Example 13 includes the subject matter of any of Examples 9-12, wherein the layer of the IC component includes one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

[0209] Example 14 includes the subject matter of any of Examples 9-13, further comprising an integrated circuit (IC) die coupled to the IC component.

[0210] Example 15 includes the subject matter of any of Examples 9-14, wherein the IC component has a thickness of 5 μm or less.

[0211] Example 16 includes the subject matter of any of Examples 9-15, wherein the IC component has a thickness of less than 1 mm. 2 area.

[0212] Example 17 is a method comprising: dispensing droplets into a subset of a plurality of areas of a second substrate, the areas of the second substrate being defined by hydrophobic lines on the second substrate, the lines being patterned to match a layout of integrated circuit (IC) components on a first substrate; bringing the first substrate close to the second substrate so that a subset of the IC components on the first substrate contacts the droplets on the second substrate; and moving the first substrate away from the second substrate, wherein, when the first substrate is separated from the second substrate, the subset of the IC components is separated from the first substrate and remains on the second substrate.

[0213] Example 18 includes the subject matter of Example 17, wherein the droplets include water.

[0214] Example 19 includes the subject matter of Example 17 or 18, wherein the volume of each droplet is 5 μL or less.

[0215] Example 20 includes the subject matter of any of Examples 17-19, wherein the region of the second substrate includes a hydrophilic layer located between the hydrophobic lines.

[0216] Example 21 includes the subject matter of any of Examples 17-20, wherein the layer of the IC component includes one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

[0217] Example 22 includes the subject matter of any of Examples 17-21, wherein the first substrate comprises a base substrate and a release layer, wherein the release layer is located between the base substrate and the layer of the IC component.

[0218] Example 23 includes the subject matter of Example 22, further comprising at least partially releasing the IC component from the release layer of the first substrate before bringing the first substrate into proximity with the second substrate.

[0219] Example 24 includes the subject matter of Example 23, wherein at least partially releasing the IC component from the release layer of the first substrate comprises peeling the IC component from the release layer using a laser or weakening the release layer using a laser.

[0220] Example 25 includes the subject matter of any of Examples 17-24, further comprising: removing the droplets and the subset of IC components from the second substrate; distributing the droplets to a new subset of the area of ​​the second substrate; bringing a third substrate close to the second substrate so that the subset of IC components on the third substrate contacts the droplets on the second substrate; and moving the third substrate away from the second substrate, wherein, when the third substrate is separated from the second substrate, the subset of IC components is separated from the third substrate and remains on the second substrate.

[0221] Example 26 includes the subject matter of any of Examples 17-25, wherein the layer of the IC component includes one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

[0222] Example 27 is a device formed by the method according to any of Examples 17-26.

[0223] Although the concepts of the present disclosure may have various modifications and alternative forms, specific embodiments of the present disclosure are shown by way of example in the accompanying drawings and described in detail in the text. However, it should be understood that there is no intention to limit the concepts of the present disclosure to the specific forms disclosed, but on the contrary, it is intended to cover all modifications, equivalents and alternatives consistent with the present disclosure and the appended claims.

[0224] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be appreciated that such a specific arrangement and / or order may not be necessary. On the contrary, in some embodiments, such features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a certain structural or method feature in a particular drawing is not intended to imply that such a feature is required for all embodiments, and in some embodiments, the feature may not be included, or it may be combined with other features. In addition, it should be understood that the various embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale.

[0225] In addition, for ease of understanding, the illustrations and / or descriptions of the various embodiments may be simplified or approximated, and as a result, they may not necessarily reflect the precise level or variations that may exist in actual embodiments. For example, although some of the drawings generally indicate straight lines, right angles, and smooth surfaces, given the real-world limitations of manufacturing processes, actual implementations of the disclosed embodiments may have non-ideal straight lines and right angles, and some features may have surface topography or otherwise exhibit non-smoothness. Similarly, for ease of understanding, the illustrations and / or descriptions of how components are arranged may be simplified or approximated, and certain error margins may vary in actual embodiments (e.g., due to manufacturing processes, etc.).

[0226] Unless otherwise indicated, the use of ordinal adjectives such as "first", "second", "third", etc. to describe common objects simply indicates that different instances of similar objects are being referenced, and does not imply that the objects described must be in a certain temporal or spatial order in an arranged manner or in any other way.

[0227] The words "substantially," "close," "approximately," "close to," and "about" generally refer to being within + / - 10% of a target value (unless otherwise indicated). Similarly, terms describing spatial relationships, such as "perpendicular," "orthogonal," or "coplanar" can refer to being substantially within the described spatial relationship (e.g., within + / - 10 degrees of orthogonal).

[0228] Certain terms have also been used in the foregoing description for reference purposes only, and thus these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings for which reference is provided. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of certain portions of a component within a consistent but arbitrary frame of reference, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0229] As used herein, the terms "over," "below," "between," "adjacent," "to," and "on" may refer to the relative position of one layer or component with respect to other layers or components. For example, a layer that is "over," "below," or "on," "adjacent," or bonded "to" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" layers may be directly in contact with the layers or may have one or more intervening layers.

[0230] The meanings of “a”, “an” and “the” include plural referents. The meaning of “in” includes “in” and “on”.

[0231] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0232] The illustrations labeled "section", "profile" and "plane" correspond to orthogonal planes in a Cartesian coordinate system. Thus, section and profile views are taken along the xz plane, and plan views are taken along the xy plane. Typically, a profile view in the xz plane is a cross-sectional view.

[0233] The term "package" generally refers to a self-contained carrier with one or more dies, wherein the die is attached to or embedded in a package substrate and may be encapsulated for protection, with integrated or wire-bonded interconnects between the die and leads, pins, or bumps on the exterior of the package substrate. A package may contain a single die, multiple dies, and thus provide the corresponding functionality. The package may be mounted on a printed circuit board to enable interconnection with other packaged integrated circuits and discrete components to form a larger circuit.

[0234] The term "core" refers to the substrate of the integrated circuit package being constructed on a board, card or wafer comprising a non-flexible rigid material. Typically, a small printed circuit board is used as the core to which the integrated circuit devices and discrete passive components can be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be directly coupled to circuitry on the opposite side of the core. The core can also be used as a platform for constructing layers of conductors and dielectric materials.

[0235] The term "coreless" generally refers to the substrate of the integrated circuit package being devoid of a core. The absence of a core can allow for a higher density package architecture because through vias can have relatively larger sizes and pitches compared to high density interconnects.

[0236] The "land side" generally refers to the side of the substrate of an integrated circuit package that is closest to the attachment plane to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which generally refers to the side of the substrate of an integrated circuit package to which one or more dies are attached.

[0237] The terms "dielectric" and "dielectric material" generally refer to any type or amount of non-conductive material. In some cases, dielectric materials can be used to form the structure of a package substrate. For example, dielectric materials can be incorporated into an integrated circuit package as a laminate film or as a resin that is molded onto an integrated circuit die mounted on a substrate.

[0238] Here, the term "metallization" generally refers to metal layers formed on, over and / or through the dielectric material of the package substrate. These metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of the package substrate can be confined to a single layer or can be located in multiple layers separated by dielectric layers.

[0239] The term "bond pad" generally refers to the metallization structure that terminates integrated traces and vias within integrated circuit packages and dies. The term "solder pad" may occasionally be used in place of "bond pad" and may convey the same or similar meaning.

[0240] The term "bump" generally refers to a conductive layer or structure formed on a bonding pad, usually made of solder or metal and having a rounded or curved shape, hence the term "bump".

[0241] The term "substrate" generally refers to a planar platform including dielectric and / or metallization structures. The substrate can mechanically support and electrically couple one or more IC dies on a single platform, wherein the one or more IC dies are encapsulated by a moldable dielectric material. The substrate can include bumps or pads on one or both sides as bonding interconnects. For example, the side of the substrate, generally referred to as the "die side", can include bumps or pads for chip or die bonding. The opposite side of the substrate, generally referred to as the "land side", can include bumps or pads for bonding the package to a printed circuit board.

[0242] The term "assemble" generally refers to the combination of parts into a single functional unit. For example, certain parts can be permanently bonded together, integrated together, and / or mechanically assembled (e.g., where the parts can be removed) into a functional unit.

[0243] The term "coupled" or "connected" means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluid connection between the things connected or an indirect connection through one or more passive or active intermediary devices.

[0244] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide the desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal or data / clock signal.

Claims

1. A microelectronic assembly comprising: substrate; a plurality of mesa structures on a surface of the substrate; as well as An integrated circuit (IC) component on each respective mesa structure, wherein each IC component includes a hydrophobic line on a surface of the IC component that contacts the mesa structure.

2. The microelectronic assembly according to claim 1, wherein: The hydrophobic line defines an area on the surface of the IC component that contacts the mesa structure.

3. The microelectronic assembly according to claim 2, wherein: Each IC component also includes a hydrophilic layer located in the area defined by the hydrophobic lines.

4. The microelectronic assembly according to claim 1, wherein: The mesa structure includes at least one of a dielectric material or a metal.

5. The microelectronic assembly according to claim 1, wherein: Each mesa structure has a similar footprint as the IC component thereon.

6. The microelectronic assembly according to claim 1, wherein: The IC component has a thickness of 5 μm or less.

7. The microelectronic assembly of claim 1, wherein: The IC component has a size less than 1 mm 2 area.

8. A microelectronic assembly according to any one of claims 1 to 7, wherein: The IC components include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

9. An integrated circuit device comprising: a substrate including a plurality of mesa structures; a plurality of integrated circuit (IC) components on the substrate, each IC component being located on a respective mesa structure, wherein each IC component comprises a hydrophobic line located on a surface of the IC component in contact with the mesa structure; A plurality of build-up layers are provided on the substrate, wherein a gap exists between each IC component and a portion of the build-up layer surrounding the IC component.

10. The device according to claim 9, wherein The hydrophobic line defines an area on the surface of the IC component that contacts the mesa structure.

11. The device according to claim 10, wherein Each IC component also includes a hydrophilic layer located in the area defined by the hydrophobic lines.

12. The device according to claim 9, wherein The mesa structure includes at least one of a dielectric material or a metal.

13. The device according to claim 9, wherein The layers of IC components include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

14. The device of any of claims 9-13, further comprising an integrated circuit (IC) die coupled to the IC component.

15. The device according to any one of claims 9 to 13, wherein: The IC component has a thickness of 5 μm or less.

16. The device according to any one of claims 9 to 13, wherein: The IC component has a size less than 1 mm 2 area.

17. A method comprising: dispensing droplets into a subset of a plurality of regions of a second substrate, the regions of the second substrate being defined by hydrophobic lines on the second substrate, the lines being patterned to match a layout of integrated circuit (IC) components on the first substrate; bringing the first substrate into proximity with the second substrate such that a subset of the IC components on the first substrate contacts the droplets on the second substrate; as well as The first substrate is moved away from the second substrate, wherein the subset of the IC components are separated from the first substrate and remain on the second substrate when the first substrate is separated from the second substrate.

18. The method according to claim 17, wherein: The volume of each droplet is 5 μL or less.

19. The method according to claim 17, wherein: The droplets include water.

20. The method according to claim 17, wherein: The region of the second substrate includes a hydrophilic layer between the hydrophobic lines.

21. The method according to any one of claims 17 to 20, wherein: The layers of IC components include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

22. The method according to any one of claims 17 to 20, wherein: The first substrate includes a base substrate and a release layer, wherein the release layer is located between the base substrate and a layer of the IC component.

23. The method of claim 22, further comprising, before bringing the first substrate into proximity with the second substrate, at least partially releasing the IC component from the release layer of the first substrate.

24. The method according to claim 23, wherein: At least partially releasing the IC component from the release layer of the first substrate includes peeling the IC component from the release layer using a laser or weakening the release layer using a laser.

25. The method according to any one of claims 17 to 20, further comprising: removing the droplet and a subset of the IC components from the second substrate; distributing droplets to a new subset of the area of ​​the second substrate; bringing a third substrate into proximity with the second substrate such that a subset of the IC components on the third substrate contacts the droplets on the second substrate; as well as The third substrate is moved away from the second substrate, wherein the subset of the IC components are separated from the third substrate and remain on the second substrate when the third substrate is separated from the second substrate.

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