A gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip and a preparation method thereof

Abstract

The application discloses a kind of gallium nitride and gallium arsenide three-dimensional hetero integrated radio frequency chip and preparation method thereof, the structure includes back metal from bottom to top, substrate, gallium nitride device epitaxial layer, bonding medium layer, gallium arsenide device epitaxial layer, gallium nitride device electrode source, gallium nitride device electrode gate, gallium nitride device electrode drain, gallium arsenide device electrode source, gallium arsenide device electrode gate, gallium arsenide device electrode drain, gallium nitride back via, gallium arsenide back via, front via, gallium nitride outer surface electrode source, gallium nitride outer surface electrode drain, electrode on the upper surface of gallium arsenide device epitaxial layer is interconnected as required, and the integrated circuit with certain function is formed.The electrode of gallium nitride and gallium arsenide radio frequency device can have very small space interval according to the application, the loss of long-distance transmission signal under high frequency and the influence of parasitic parameter are reduced, and chip area and chip volume are reduced, packaging cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip and a preparation method thereof. BACKGROUND

[0002] With the advent of the 5G era, the communication system has higher technical requirements such as reducing size, improving density, improving efficiency, reducing energy consumption, and reducing cost. In addition to continuing to improve the indicators such as communication speed, capacity, latency, and spatial range in the post-5G and 6G communication system, it is also necessary to solve the important problems encountered in the current 5G communication system, that is, high cost and high power consumption. In the process of evolution from 4G to 5G and post-5G, 6G communication systems, the communication system needs to handle more and more frequency bands; in addition, with the widespread application of large-scale multiple-input multiple-output (MIMO) technology and carrier aggregation technology, communication base stations and terminal devices need to integrate large-scale arrays composed of multiple radio frequency transceiver modules and antennas, thereby causing the cost and power consumption of the system to rise sharply. Due to the significant decline in the efficiency of high-frequency radio frequency front-end modules, the extension of communication carrier frequencies to the millimeter wave band has further exacerbated the power consumption of base stations and terminal electronic devices. High-density system integration can effectively reduce the high cost and high power consumption of 5G, post-5G, and 6G communication devices.

[0003] As the third generation of semiconductor, gallium nitride has excellent characteristics such as wide band gap, high electron mobility, and high electron saturation velocity, and has wide application potential in the field of next-generation radio frequency devices and power electrical devices. Gallium nitride-based devices have the advantages of high power and high efficiency at the transmitting end; while gallium arsenide-based devices have the advantages of low noise and high gain at the receiving end. Therefore, if high-density micro-nano hetero-integration of gallium nitride and gallium arsenide microwave chips can be achieved, it will be of great significance to solve the current problems of communication systems. However, there are still many difficulties in material compatibility, process compatibility, thermal compatibility, and electromagnetic compatibility between gallium nitride and gallium arsenide.

[0004] Therefore, it is urgent to provide a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip structure and a preparation method thereof. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip and a preparation method thereof.

[0006] To achieve the above purpose, the present application is implemented according to the following technical solutions:

[0007] One of the purposes of the present application is to provide a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip, which comprises, from bottom to top, a back metal, a substrate, a gallium nitride device epitaxial layer, a bonding medium layer, and a gallium arsenide device epitaxial layer.

[0008] The upper surface of the gallium nitride device epitaxial layer is provided with a gallium nitride device electrode source, a gallium nitride device electrode gate and a gallium nitride device electrode drain;

[0009] The upper surface of the gallium arsenide device epitaxial layer is provided with a gallium arsenide device electrode source, a gallium arsenide device electrode gate and a gallium arsenide device electrode drain;

[0010] A gallium nitride back via is arranged to pass through the substrate and the gallium nitride device epitaxial layer from bottom to top, and the gallium nitride back via connects the back metal and the gallium nitride device electrode source;

[0011] A gallium arsenide back via is arranged to pass through the substrate, the bonding medium layer and the gallium arsenide device epitaxial layer from bottom to top, and the gallium arsenide back via connects the back metal and the gallium arsenide device electrode source;

[0012] A front via is arranged to pass through the bonding medium layer and the gallium arsenide device epitaxial layer from bottom to top, and the gallium nitride device electrode gate and the gallium nitride device electrode drain buried in the bonding medium layer are connected to the gallium nitride outer surface electrode source and the gallium nitride outer surface electrode drain on the upper surface of the gallium arsenide device epitaxial layer through the metal deposited in the front via, respectively; the gallium nitride outer surface electrode source and the gallium nitride outer surface electrode drain on the upper surface of the gallium arsenide device epitaxial layer, the gallium arsenide device electrode source, the gallium arsenide device electrode gate and the gallium arsenide device electrode drain are interconnected as required to form an integrated circuit.

[0013] The gallium nitride device epitaxial material and the gallium arsenide device epitaxial material of the structure are stacked in the same direction through wafer-level bonding to realize three-dimensional heterojunction integration. The wafer of the three-dimensional integration has a same-direction bonding structure and shares a substrate for gallium nitride epitaxy. The gallium nitride radio frequency device and the gallium arsenide radio frequency device are connected to the grounding metal on the back surface of the substrate through the back via and connected to the electrodes on the upper surface of the wafer material through the front via. Thus, the electrodes of the gallium nitride and gallium arsenide radio frequency devices have a minimum spatial distance, the loss of long-distance signal transmission and the influence of parasitic parameters under high frequency are reduced, the chip area and volume are reduced, the packaging cost is reduced, and a high-density, high-performance and multi-functional gallium nitride and gallium arsenide heterojunction radio frequency chip is realized.

[0014] Further, the material of the substrate is one of silicon carbide, silicon, gallium nitride, aluminum nitride and diamond, and the thickness is 30-500 mu m. The material of the bonding medium layer is one of silicon oxide, silicon nitride, aluminum oxide and aluminum nitride, and the thickness is 10 nm-5 mu m.

[0015] Further, the material of the gallium nitride device epitaxial layer is one or more of gallium nitride, aluminum nitride, and indium nitride; the gallium nitride device epitaxial layer comprises, from bottom to top, a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer; the material of the nitride nucleation layer is aluminum nitride, and the thickness is 50-300 nm; the material of the nitride transition layer is gradually changing aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice, and the thickness is 500-1000 nm; the material of the nitride buffer layer is gallium nitride, and the thickness is 100-1000 nm; the material of the nitride channel layer is gallium nitride, indium gallium nitride, or aluminum gallium nitride, and the thickness is 50-500 nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, and the thickness is 5-30 nm; a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, serving as a conductive channel of the gallium nitride radio frequency device.

[0016] The material of the gallium arsenide device epitaxial layer is one or more of gallium arsenide, indium arsenide, aluminum arsenide, and indium phosphide; the gallium arsenide device epitaxial layer comprises, from bottom to top, an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer; the material of the arsenide buffer layer is gallium arsenide, and the thickness is 50-1000 nm; the material of the arsenide channel layer is gallium arsenide or indium gallium arsenide, and the thickness is 50-300 nm; the material of the arsenide isolation layer is aluminum gallium arsenide, indium aluminum arsenide, indium aluminum gallium arsenide, or indium gallium phosphide, and the thickness is 1-5 nm; the material of the arsenide barrier layer is aluminum gallium arsenide, indium aluminum arsenide, indium aluminum gallium arsenide, or indium gallium phosphide, and the thickness is 5-30 nm; the material of the arsenide cap layer is aluminum gallium arsenide, indium aluminum arsenide, indium aluminum gallium arsenide, or indium gallium phosphide, and the thickness is 2-10 nm; a two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer, serving as a conductive channel of the gallium arsenide device.

[0017] Further, the electrode gate of the gallium nitride device is a multilayer metal material, the lowest layer is one of Ni, Ti, TiN, and TaN, and the second layer or layers are one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu;

[0018] The electrode source of the gallium nitride device is a multilayer metal material, the lowest two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the other layers of metal include one or more of Ti, Al, Ni, Au, Mo, Pt, and W;

[0019] The electrode drain of the gallium nitride device is a multilayer metal material, the lowest two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the other layers of metal include one or more of Ti, Al, Ni, Au, Mo, Pt, and W.

[0020] The electrode gate of the gallium arsenide device is a multilayer metal material, the lowermost layer is one of Ti, Ta, Ni, TiN and TaN, and the second layer or the second layer or more is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W and Cu;

[0021] The electrode drain of the gallium arsenide device is a multilayer metal material, the lowermost two layers are Ni and Ge from bottom to top, or Mo and Al; the other layers of metal include one or more of Ni and Au;

[0022] The electrode source of the gallium arsenide device is a multilayer metal material, the lowermost two layers are Ni and Ge from bottom to top, or Mo and Al; the other layers of metal include one or more of Ni and Au.

[0023] Further, the back metal, the metal deposited in the front via and the metal material in the gallium nitride back via are all multilayer metal materials, and the multilayer metal material is one of Ni / Au, Ti / Au, Ni / Cu and Ti / Cu from bottom to top.

[0024] The second object of the present application is to provide a preparation method of a gallium nitride and gallium arsenide three-dimensional heterojunction integrated radio frequency chip, comprising the following steps:

[0025] S1: epitaxially growing a gallium nitride device epitaxial layer on a substrate to obtain a raw gallium nitride wafer;

[0026] S2: performing process preparation of a gallium nitride device on the raw gallium nitride wafer obtained in step S1;

[0027] S3: selecting a second substrate, epitaxially growing a gallium arsenide device epitaxial layer to obtain a raw gallium arsenide wafer; the material of the second substrate is gallium arsenide or silicon;

[0028] S4: front bonding a transition carrier on the raw gallium arsenide wafer obtained in step S3 to obtain a first gallium arsenide wafer;

[0029] S5: removing the second substrate of the first gallium arsenide wafer obtained in step S4 to obtain a second gallium arsenide wafer, and the back of the gallium arsenide device epitaxial layer of the second gallium arsenide wafer is exposed outside;

[0030] S6: bonding the second gallium arsenide wafer obtained in step S5 with the raw gallium nitride wafer obtained in step S2, which has completed the process preparation of the gallium nitride device, to obtain a first heterojunction wafer, and the back of the second gallium arsenide wafer is connected with the front of the gallium nitride device epitaxial layer of the raw gallium nitride wafer through a bonding medium layer;

[0031] S7: removing the transition carrier wafer of the first hetero-integrated wafer obtained in step S5 to expose the front surface of the gallium arsenide device epitaxial layer, and obtaining a gallium nitride and gallium arsenide three-dimensional hetero-integrated wafer provided by the application;

[0032] S8: performing process preparation of the gallium arsenide device on the three-dimensional hetero-integrated wafer obtained in step S6;

[0033] S9: etching the gallium arsenide device epitaxial layer and the bonding medium layer in a partial region to make a front surface via hole, depositing metal in the front surface via hole, and performing interconnection of the front surface electrode of the three-dimensional hetero-integrated wafer;

[0034] S9: etching the substrate and the gallium nitride device epitaxial layer in a partial region to make a gallium nitride back via hole; etching the substrate, the gallium nitride device epitaxial layer, the bonding medium layer and the gallium arsenide device epitaxial layer in a partial region to make a gallium arsenide back via hole;

[0035] S10: depositing a back metal in the substrate back surface and the gallium nitride back via hole and the gallium arsenide back via hole to obtain a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip.

[0036] Compared with the prior art, the application has the following beneficial effects:

[0037] 1) The application adopts a material structure combining gallium nitride and gallium arsenide, breaks through the limitation of the performance of single material devices, and cooperatively improves the power, efficiency and noise performance of the millimeter wave radio frequency front end;

[0038] 2) The gallium nitride device and the gallium arsenide device of the application are three-dimensionally hetero-integrated in a same direction, have high integration density, short metal interconnection distance, small occupied area, have the smallest space interval, and the silicon carbide substrate of the gallium nitride wafer helps heat dissipation of the high-power device;

[0039] 3) The substrate used for gallium nitride epitaxy of the three-dimensional hetero-integrated wafer of the application has high thermal conductivity, improves the heat dissipation capacity of the hetero-integrated radio frequency chip, and thus has better output power and efficiency;

[0040] 4) The application first completes process preparation of the gallium nitride device, then performs wafer bonding, makes a three-dimensional hetero-integrated wafer and performs process preparation of the gallium arsenide device, and the process technology of the gallium nitride device is flexible and has high process flow compatibility.

[0041] 5) The gallium nitride and gallium arsenide epitaxial material growth and device processing preparation of the application are performed by using existing mature process technology, have low cost and high feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a structure schematic diagram of a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip provided by an embodiment of the application.

[0043] Figure 2 A flowchart of a preparation method of a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip provided by an embodiment of the present application.

[0044] Figure 3 A device flowchart of a preparation method of a gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip provided by an embodiment of the present application.

[0045] Explanation of reference signs:

[0046] 1 - back metal; 2 - substrate; 3 - gallium nitride device epitaxial layer; 4 - bonding medium layer; 5 - gallium nitride back via; 6 - gallium arsenide back via; 61 gallium nitride device electrode source; 62 - gallium nitride device electrode gate; 63 - gallium nitride device electrode drain; 7 - front via; 71 - gallium arsenide device electrode source; 72 - gallium arsenide device electrode gate; 73 - gallium arsenide device electrode drain; 8 - gallium arsenide device epitaxial layer; 621 - gallium nitride outer surface electrode source; 631 - gallium nitride outer surface electrode drain; 14 - transition carrier. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the present application clearer and more apparent, the present application will be further described in detail below in combination with embodiments. The specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0048] As Figure 1As shown, the embodiment exemplarily shows a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip, including back metal 1, substrate 2, gallium nitride device epitaxial layer 3, bonding medium layer 4, and gallium arsenide device epitaxial layer 8 from bottom to top. The upper surface of the gallium nitride device epitaxial layer 3 is provided with gallium nitride device electrode source 61, gallium nitride device electrode gate 62, and gallium nitride device electrode drain 63. The upper surface of the gallium arsenide device epitaxial layer 8 is provided with gallium arsenide device electrode source 71, gallium arsenide device electrode gate 72, and gallium arsenide device electrode drain 73. The gallium nitride back via 5 passes through the substrate 2 and the gallium nitride device epitaxial layer 3 from bottom to top, and connects the back metal 1 and the gallium nitride device electrode source 61. The gallium arsenide back via 6 passes through the substrate 2, the bonding medium layer 4, and the gallium arsenide device epitaxial layer 8 from bottom to top, and connects the back metal 1 and the gallium arsenide device electrode source 71. The front via 7 passes through the bonding medium layer 4 and the gallium arsenide device epitaxial layer 8 from bottom to top, and connects the buried gallium nitride device electrode gate 62 and the gallium nitride device electrode drain 63 in the bonding medium layer 4 to the gallium nitride outer surface electrode source 621 and the gallium nitride outer surface electrode drain 631 on the upper surface of the gallium arsenide device epitaxial layer 8, respectively. The gallium nitride outer surface electrode source 621 and the gallium nitride outer surface electrode drain 631 on the upper surface of the gallium arsenide device epitaxial layer 8, the gallium arsenide device electrode source 71, the gallium arsenide device electrode gate 72, and the gallium arsenide device electrode drain 73 are interconnected as needed to form an integrated circuit.

[0049] The principle of the embodiment is that the gallium nitride device epitaxial material and the gallium arsenide device epitaxial material are integrated in the same direction by wafer-level bonding. The wafer of the three-dimensional integrated structure is bonded in the same direction, and shares the substrate used for gallium nitride epitaxy. The gallium nitride radio frequency device and the gallium arsenide radio frequency device are connected to the ground metal on the back surface of the substrate through the back via, and are interconnected with the electrodes on the upper surface of the wafer material through the front via. In this way, the electrodes of the gallium nitride and gallium arsenide radio frequency devices have a very small spatial distance, reducing the loss of long-distance signal transmission and the influence of parasitic parameters at high frequency, and reducing the chip area and volume, reducing the packaging cost, and realizing high-density, high-performance, and multi-functional gallium nitride and gallium arsenide heterogeneous integrated radio frequency chip.

[0050] In the embodiment, the material of the substrate 2 can be one of silicon carbide, silicon, gallium nitride, aluminum nitride, and diamond substrate, and the thickness is 30-500 μm. Preferably, the material of the substrate 2 is silicon carbide, and the thickness is 100 μm.

[0051] In the embodiment, the material of the bonding medium layer 4 can be one or more of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride, and the thickness is 10 nm-5 μm. Preferably, the material of the bonding medium layer 4 can be silicon oxide, and the thickness is 500 nm.

[0052] In this embodiment, the gallium nitride device epitaxial layer 3 comprises a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride, and the thickness is 50-300 nm; the material of the nitride transition layer is graded aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, and the thickness is 500-1000 nm; the material of the nitride buffer layer is gallium nitride, and the thickness is 100-1000 nm; the material of the nitride channel layer is gallium nitride, or indium gallium arsenide, or aluminum gallium nitride, and the thickness is 50-500 nm; the material of the nitride barrier layer is aluminum gallium nitride, or indium aluminum arsenide, and the thickness is 5-30 nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, serving as a conductive channel of the gallium nitride radio frequency device. Preferably, the material of the nitride nucleation layer is aluminum nitride, and the thickness is 200 nm; the material of the nitride transition layer is graded aluminum gallium nitride, and the thickness is 8000 nm; the material of the nitride buffer layer is gallium nitride, and the thickness is 500 nm; the material of the nitride channel layer is gallium nitride, and the thickness is 200 nm; and the material of the nitride barrier layer is aluminum gallium nitride, and the thickness is 20 nm.

[0053] In this embodiment, the gallium arsenide device epitaxial layer 8 is made of a group III arsenide or a group III phosphide material, and is a compound composed of one or more of gallium arsenide, indium arsenide, aluminum arsenide, and indium phosphide. The gallium arsenide device epitaxial layer 8 comprises an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer. The material of the arsenide buffer layer is gallium arsenide, and the thickness is 50-1000 nm; the material of the arsenide channel layer is gallium arsenide, or indium gallium arsenide, and the thickness is 50-300 nm; the material of the arsenide isolation layer is aluminum gallium arsenide, or indium aluminum arsenide, or indium aluminum gallium arsenide, or indium phosphide, or indium gallium phosphide, and the thickness is 1-5 nm; the material of the arsenide barrier layer is aluminum gallium arsenide, or indium aluminum arsenide, or indium aluminum gallium arsenide, or indium aluminum gallium arsenide, or indium gallium phosphide, and the thickness is 5-30 nm; and the material of the arsenide cap layer is aluminum gallium arsenide, or indium aluminum arsenide, or indium aluminum gallium arsenide, or indium aluminum gallium arsenide, or indium gallium phosphide, and the thickness is 2-10 nm. A two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer, serving as a conductive channel of the gallium arsenide device. Preferably, the material of the arsenide buffer layer is gallium arsenide, and the thickness is 500 nm; the material of the arsenide channel layer is indium gallium arsenide, and the thickness is 100 nm; the material of the arsenide isolation layer is indium gallium phosphide, and the thickness is 3 nm; the material of the arsenide barrier layer is indium aluminum arsenide, and the thickness is 20 nm; and the material of the arsenide cap layer is indium gallium phosphide, and the thickness is 5 nm.

[0054] In this embodiment, the material of the electrode gate 62 of the gallium nitride device is Ni, or Ti, or TiN, or TaN in the bottom layer, and Al, Au, Ti, Ta, Pt, TiN, TaN, W, Cu in the second layer or above. Preferably, the material of the electrode gate 62 of the gallium nitride device is Ni, Au in turn from bottom to top, with thicknesses of 50 nm and 400 nm respectively.

[0055] In this embodiment, the material of the electrode source 61 of the gallium nitride device is Ti, Al, or Ta, Al, or Mo, Al in the bottom two layers from bottom to top; and the metal of other layers includes one or more of Ti, Al, Ni, Au, Mo, Pt, and W. Preferably, the material of the electrode source 83 of the gallium nitride device is Ti, Al, Ni, Au in turn from bottom to top, with thicknesses of 20 nm, 120 nm, 40 nm, and 50 nm respectively.

[0056] In this embodiment, the material of the electrode drain 61 of the gallium nitride device is Ti, Al, or Ta, Al, or Mo, Al in the bottom two layers from bottom to top; and the metal of other layers includes one or more of Ti, Al, Ni, Au, Mo, Pt, and W. Preferably, the material of the electrode drain 63 of the gallium nitride device is Ti, Al, Ni, Au in turn from bottom to top, with thicknesses of 20 nm, 120 nm, 40 nm, and 50 nm respectively.

[0057] In this embodiment, the material of the electrode gate 72 of the gallium arsenide device is Ti, or Ta, or Ni, or TiN, or TaN in the bottom layer, and Al, Au, Ti, Ta, Pt, TiN, TaN, W, Cu in the second layer or above. Preferably, the material of the electrode gate 72 of the gallium arsenide device is Ti, Pt, Au in turn from bottom to top, with thicknesses of 50 nm, 50 nm, and 300 nm respectively.

[0058] In this embodiment, the material of the electrode drain 71 of the gallium arsenide device is Ni, Ge, or Mo, Al in the bottom two layers from bottom to top, and one or more of Ni and Au in other layers. Preferably, the material of the electrode drain 71 of the gallium arsenide device is Ni, Ge, Au, Ni, Au in turn from bottom to top, with thicknesses of 5 nm, 20 nm, 100 nm, 25 nm, and 100 nm respectively.

[0059] In this embodiment, the material of the electrode source 73 of the gallium arsenide device is Ni, Ge, or Mo, Al in the bottom two layers from bottom to top, and one or more of Ni and Au in other layers. Preferably, the material of the electrode source 73 of the gallium arsenide device is Ni, Ge, Au, Ni, Au in turn from bottom to top, with thicknesses of 5 nm, 20 nm, 100 nm, 25 nm, and 100 nm respectively.

[0060] In this embodiment, the back metal, the metal deposited in the front via hole 7 and the metal material in the gallium nitride back via hole are all multi-layer metal materials, and the multi-layer metal material is one of Ni / Au, Ti / Au, Ni / Cu and Ti / Cu from bottom to top. Preferably, the back metal 1, the metal deposited in the front via hole 7 and the metal material in the gallium nitride back via hole are Ti / Au, and the thickness is 100 nm and 5 μm.

[0061] Referring to Figure 2 , Figure 3 , when the above-mentioned gallium nitride and gallium arsenide three-dimensional hetero-integrated radio frequency chip is prepared, the specific preparation process is as follows:

[0062] S1: selecting a substrate, epitaxially growing a gallium nitride device epitaxial layer on the substrate to obtain a raw gallium nitride wafer;

[0063] S2: performing process preparation of the gallium nitride device on the raw gallium nitride wafer obtained in step S1;

[0064] S3: selecting a second substrate, epitaxially growing a gallium arsenide device epitaxial layer on the second substrate to obtain a raw gallium arsenide wafer; the material of the second substrate can be gallium arsenide or silicon;

[0065] S4: bonding a transition carrier on the front surface of the raw gallium arsenide wafer obtained in step S3 to obtain a first gallium arsenide wafer;

[0066] S5: removing the second substrate of the first gallium arsenide wafer obtained in step S3 to obtain a second gallium arsenide wafer, and the back surface of the gallium arsenide device epitaxial layer of the second gallium arsenide wafer is exposed outside;

[0067] S6: bonding the second gallium arsenide wafer obtained in step S4 with the raw gallium nitride wafer obtained in step S2, which has completed the process preparation of the gallium nitride device, to obtain a first hetero-integrated wafer, and the back surface of the second gallium arsenide wafer is connected with the front surface of the gallium nitride device epitaxial layer of the raw gallium nitride wafer through a bonding medium layer;

[0068] S6: removing the transition carrier of the first hetero-integrated wafer obtained in step S5 to expose the front surface of the gallium arsenide device epitaxial layer, thereby obtaining the gallium nitride and gallium arsenide three-dimensional hetero-integrated wafer proposed in the present application.

[0069] S7: performing process preparation of the gallium arsenide device on the three-dimensional hetero-integrated wafer obtained in step S6;

[0070] S8: etching part of the gallium arsenide device epitaxial layer and the bonding medium layer to make a front via hole, depositing metal in the front via hole, and interconnecting the front electrode of the three-dimensional hetero-integrated wafer;

[0071] S9: etching the substrate and the gallium nitride device epitaxial layer in a partial region to form a gallium nitride back via hole; etching the substrate, the gallium nitride device epitaxial layer, the bonding medium layer and the gallium arsenide device epitaxial layer in a partial region to form a gallium arsenide back via hole;

[0072] S10: depositing a back metal on the back surface of the substrate and in the gallium nitride back via hole and the gallium arsenide back via hole.

[0073] Thus far, the preparation of the three-dimensional hetero vertical integrated device of the gallium nitride device and the gallium arsenide device is completed.

[0074] The technical scheme of the present application is not limited to the above specific embodiments, and any technical modification made according to the technical scheme of the present application falls within the protection scope of the present application.

Claims

1. A three-dimensional heterogeneous integrated radio frequency chip of gallium nitride and gallium arsenide, comprising, from bottom to top, a back metal (1), a substrate (2), a gallium nitride device epitaxial layer (3), a bonding dielectric layer (4), and a gallium arsenide device epitaxial layer (8); characterized in that: The upper surface of the gallium nitride device epitaxial layer (3) is provided with a gallium nitride device electrode source (61), a gallium nitride device electrode gate (62), and a gallium nitride device electrode drain (63); A gallium arsenide device electrode source (71), a gallium arsenide device electrode gate (72), and a gallium arsenide device electrode drain (73) are provided on the upper surface of the gallium arsenide device epitaxial layer (8); A gallium nitride back via (5) is provided to pass through the substrate (2) and the gallium nitride device epitaxial layer (3) from bottom to top, and the gallium nitride back via (5) is connected to the back metal (1) and the gallium nitride device electrode source (61); A gallium arsenide back via (6) is provided to pass through the substrate (2), the bonding dielectric layer (4), and the gallium arsenide device epitaxial layer (8) from bottom to top, and the gallium arsenide back via (6) is connected to the back metal (1) and the gallium arsenide device electrode source (71); A front through hole (7) is provided to pass through the bonding dielectric layer (4) and the gallium arsenide device epitaxial layer (8) from bottom to top, and the gallium nitride device electrode gate (62) and the gallium nitride device electrode drain (63) buried in the bonding dielectric layer (4) are connected to the gallium nitride external surface electrode source (621) and the gallium nitride external surface electrode drain (631) on the upper surface of the gallium arsenide device epitaxial layer (8) through metal deposited in the front through hole (7); the gallium nitride external surface electrode source (621), the gallium nitride external surface electrode drain (631), the gallium arsenide device electrode source (71), the gallium arsenide device electrode gate (72) and the gallium arsenide device electrode drain (73) on the upper surface of the gallium arsenide device epitaxial layer (8) are interconnected as needed to form an integrated circuit.

2. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The material of the substrate (2) is one of silicon carbide, silicon, gallium nitride, aluminum nitride, and diamond, and has a thickness of 30-500 μm; the material of the bonding medium layer (4) is one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride, and has a thickness of 10 nm-5 μm.

3. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The material of the gallium nitride device epitaxial layer (3) is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride; the gallium nitride device epitaxial layer (3) comprises, from bottom to top, a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer; the material of the nitride nucleation layer is aluminum nitride, with a thickness of 50-300 nm; the material of the nitride transition layer is graded aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000 nm; the material of the nitride buffer layer is gallium nitride, with a thickness of 100-1000 nm; the material of the nitride channel layer is gallium nitride or indium gallium nitride or aluminum gallium nitride, with a thickness of 50-500 nm. nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, and the thickness is 5-30nm; a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, which serves as a conductive channel of the gallium nitride radio frequency device; The material of the gallium arsenide device epitaxial layer (8) is a compound composed of one or more of gallium arsenide, indium arsenide, aluminum arsenide, and indium phosphide; the gallium arsenide device epitaxial layer (8) comprises, from bottom to top, an arsenide buffer layer, an arsenide channel layer, an arsenide isolation layer, an arsenide barrier layer, and an arsenide cap layer, wherein the material of the arsenide buffer layer is gallium arsenide, and has a thickness of 50-1000 nm; the material of the arsenide channel layer is gallium arsenide or indium gallium arsenic, and has a thickness of 50-300 nm; the material of the arsenide isolation layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium phosphide or indium gallium phosphide, and has a thickness of 1-5 nm; the material of the arsenide barrier layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, and has a thickness of 5-30 nm; the material of the arsenide cap layer is aluminum gallium arsenic or indium aluminum arsenic or indium aluminum gallium arsenic or indium aluminum gallium arsenic or indium gallium phosphide, and has a thickness of 2-10 nm; a two-dimensional electron gas is formed between the arsenide channel layer and the arsenide isolation layer, which serves as a conductive channel of the gallium arsenide device.

4. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The gallium nitride device electrode gate (62) is a multi-layer metal material, the bottom layer is one of Ni, Ti, TiN, and TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The gallium nitride device electrode source (61) is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The gallium nitride device electrode drain (63) is a multi-layer metal material, the bottom two layers from bottom to top are Ti and Al, or Ta and Al, or Mo and Al; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The GaAs device electrode grid (72) is a multi-layer metal material, the bottom layer is one of Ti, Ta, Ni, TiN, and TaN, and the second layer or the layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The GaAs device electrode drain (73) is a multi-layer metal material, wherein the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of the other layers include one or more of Ni and Au; The gallium arsenide device electrode source (71) is a multi-layer metal material, wherein the bottom two layers from bottom to top are Ni and Ge, or Mo and Al; the metals of other layers include one or more of Ni and Au.

5. The gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip according to claim 1, characterized in that: The back metal (1), the metal deposited in the front through hole (7), and the metal material in the gallium nitride back through hole (5) are all multilayer metal materials, and the multilayer metal material is one of Ni / Au, Ti / Au, Ni / Cu, and Ti / Cu from bottom to top.

6. A method for preparing a three-dimensional heterogeneously integrated radio frequency chip of gallium nitride and gallium arsenide according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: epitaxially growing a gallium nitride device epitaxial layer (3) on a substrate (2) to obtain an original gallium nitride wafer; S2: Performing process preparation of GaN devices on the original GaN wafer obtained in step S1; S3: Selecting a second substrate, epitaxially growing a gallium arsenide device epitaxial layer (8) to obtain an original gallium arsenide wafer; the material of the second substrate is gallium arsenide or silicon; S4: bonding the transition carrier (14) to the front side of the original gallium arsenide wafer obtained in step S3 to obtain a first gallium arsenide wafer; S5: removing the second substrate of the first gallium arsenide wafer obtained in step S4 to obtain a second gallium arsenide wafer, wherein the back side of the gallium arsenide device epitaxial layer (8) of the second gallium arsenide wafer is exposed to the outside; S6: Bonding the second gallium arsenide wafer obtained in step S5 to the original gallium nitride wafer obtained in step S2 and prepared by the gallium nitride device process to obtain a first heterogeneous integrated wafer, wherein the back surface of the second gallium arsenide wafer is connected to the front surface of the gallium nitride device epitaxial layer (3) of the original gallium nitride wafer via a bonding dielectric layer (4); S7: removing the transition carrier (14) of the first heterogeneous integrated wafer obtained in step S5, exposing the front surface of the gallium arsenide device epitaxial layer (8) to the outside, and obtaining a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated wafer; S8: performing a process for preparing a gallium arsenide device on the three-dimensional heterogeneous integrated wafer obtained in step S6; S9: etching the GaAs device epitaxial layer (8) and the bonding dielectric layer (4) in a partial area, making a front through hole (7), depositing metal in the front through hole (7), and interconnecting the front electrodes of the three-dimensional heterogeneous integrated wafer; S9: etching a portion of the substrate (2) and the gallium nitride device epitaxial layer (3) to form a gallium nitride back via (5); etching a portion of the substrate (2), the gallium nitride device epitaxial layer (3), the bonding dielectric layer (4) and the gallium arsenide device epitaxial layer (8) to form a gallium arsenide back via (6); S10: Depositing back metal (1) on the back side of the substrate (2) and in the gallium nitride back through hole (5) and the gallium arsenide back through hole (6) to produce a gallium nitride and gallium arsenide three-dimensional heterogeneous integrated radio frequency chip.

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