Semiconductor device

Abstract

A semiconductor device includes: first conductive lines spaced apart from each other; and a conductive structure in contact with the upper surface of the first conductive line, where the conductive structure includes a lower portion of the conductive structure in contact with the upper surface of the first conductive line and an upper portion of the conductive structure on the lower portion of the conductive structure, where the upper portion of the conductive structure is in contact with the upper surface of the first conductive line. A width of a lower portion of the conductive structure decreases as a distance between the lower portion of the conductive structure and an upper surface of the first conductive line decreases, and wherein a width of an upper portion of the conductive structure increases as the distance between the upper portion of the conductive structure and the upper surface of the first conductive line decreases.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0133537 filed in the Korean Intellectual Property Office on October 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices, and in particular, to semiconductor devices having conductive structures. Background Art

[0004] The semiconductor device may include an integrated circuit including a metal oxide semiconductor field effect transistor (MOSFET). In order to meet the increasing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs are being scaled down.

[0005] Scaling down of MOSFETs may lead to deterioration in operating characteristics of semiconductor devices. Various studies are being conducted to overcome technical limitations associated with scaling down of semiconductor devices and to realize high-performance semiconductor devices. Summary of the invention

[0006] Some embodiments of the inventive concept may provide semiconductor devices having improved electrical and reliability characteristics.

[0007] According to an embodiment conceived in the present invention, a semiconductor device may include: first conductive lines spaced apart from each other; and a conductive structure in contact with an upper surface of the first conductive line, wherein the conductive structure includes a lower portion of the conductive structure and an upper portion of the conductive structure, wherein the lower portion of the conductive structure is in contact with the upper surface of the first conductive line, wherein the upper portion of the conductive structure is on the lower portion of the conductive structure, wherein a width of the lower portion of the conductive structure decreases as a distance between the lower portion of the conductive structure and the upper surface of the first conductive line decreases, and wherein a width of the upper portion of the conductive structure increases as a distance between the upper portion of the conductive structure and the upper surface of the first conductive line decreases.

[0008] According to an embodiment conceived in the present invention, a semiconductor device may include: a first interlayer insulating layer; an etch stop layer on the first interlayer insulating layer; a second interlayer insulating layer on the etch stop layer; a third interlayer insulating layer on the second interlayer insulating layer; first conductive wires spaced apart from each other and extending in the first interlayer insulating layer; and a conductive structure extending in the second interlayer insulating layer, the third interlayer insulating layer, and the etch stop layer and contacting an upper surface of the first conductive wire, wherein the first interlayer insulating layer includes an intermediate portion between the first conductive wires, wherein an upper surface of the first conductive wire is coplanar with an upper surface of the intermediate portion, and wherein a lower surface of the conductive structure contacts an upper surface of the first conductive wire and an upper surface of the intermediate portion.

[0009] According to an embodiment of the present invention, a semiconductor device may include: a substrate including an active pattern; a source / drain pattern on the active pattern; a channel structure between the source / drain patterns; a gate electrode overlapping the channel structure; an active contact located on each of the source / drain patterns; a capping insulating layer on the active contact; a first etch stop layer on the capping insulating layer; a first interlayer insulating layer on the first etch stop layer; first wires spaced apart from each other and extending in the first etch stop layer and the first interlayer insulating layer; a second etch stop layer on the first interlayer insulating layer and the first wire; a second interlayer insulating layer on the second etch stop layer; a third interlayer insulating layer on the second interlayer insulating layer; and a conductive structure contacting an upper surface of the first wire and extending in the second etch stop layer, the second interlayer insulating layer, and the third interlayer insulating layer, wherein each of the first wires is electrically connected to the active contact or the gate electrode, wherein the conductive structure includes a barrier layer and a conductive layer on the barrier layer, wherein an outer surface of the barrier layer contacts the second interlayer insulating layer, and wherein an outer surface of the conductive layer contacts the third interlayer insulating layer.

[0010] According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a first interlayer insulating layer; forming first conductive lines spaced apart from each other and extending in the first interlayer insulating layer; forming an etch stop layer on the first interlayer insulating layer and the first conductive line; forming a second interlayer insulating layer on the etch stop layer; etching the second interlayer insulating layer to form a first opening; etching the stop layer through the first opening to form a second opening, wherein the second opening exposes an upper surface of the first conductive line; forming an initial barrier layer in contact with an upper surface of the first conductive line, a side surface of the etch stop layer, and a side surface and an upper surface of the second interlayer insulating layer; forming an initial conductive layer on the initial barrier layer; forming a mask layer on the initial conductive layer; and

[0011] The initial conductive layer and the initial barrier layer are etched using the mask layer as an etching mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1 to 3 is a simplified diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0013] Figure 4A is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0014] Figure 4B is along Figure 4A A cross-sectional view taken along line A1-A1'.

[0015] Figure 4C is along Figure 4A A cross-sectional view taken along line B1-B1'.

[0016] Figure 4D It is shown Figure 4B An enlarged view of part E1.

[0017] Figure 4E It is shown Figure 4C An enlarged view of portion E2.

[0018] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It shows the manufacturing FIG. 4A to FIG. 4E A cross-sectional view of a method for a semiconductor device.

[0019] Fig.11 is an enlarged cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0020] Fig.12 is an enlarged cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0021] Fig.13 is an enlarged cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0022] Fig.14 is an enlarged cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0023] Fig.15 is an enlarged cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0024] Fig.16 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0025] Figures 1 to 3 is a simplified diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0026] Reference Figure 1 , a single height cell SHC may be provided. The first power line M1_R1 and the second power line M1_R2 may be provided on the substrate 100. The first power line M1_R1 may be a conductive path provided with a source voltage VSS. In some embodiments, the first power line M1_R1 may be a conductive path provided with a ground voltage. The second power line M1_R2 may be a conductive path provided with a drain voltage VDD. In some embodiments, the second power line M1_R2 may be a conductive path provided with a power supply voltage.

[0027] The single-height cell SHC may be defined between (a portion of (a central portion in the first direction D1)) the first power line M1_R1 and (a portion of (a central portion in the first direction D1)) the second power line M1_R2. The single-height cell SHC may include a first active area AR1 and a second active area AR2. One of the first active area AR1 and the second active area AR2 may be a PMOSFET area, and the other of the first active area AR1 and the second active area AR2 may be an NMOSFET area. The single-height cell SHC may have a CMOS structure disposed between (a portion of (a central portion in the first direction D1)) the first power line M1_R1 and (a portion of (a central portion in the first direction D1)) the second power line M1_R2.

[0028] Each of the first active area AR1 and the second active area AR2 may have a first width WI1 in the first direction D1. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be (substantially) equal to a distance (e.g., spacing) between (a portion (central portion in the first direction D1) of the first power line M1_R1) and (a portion (central portion in the first direction D1) of the second power line M1_R2).

[0029] The single height cell SHC may constitute a single logic unit. In this specification, a logic unit may represent a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) configured to perform a specific function. A logic unit may include transistors constituting the logic device and interconnects connecting the transistors to each other (e.g., electrically connected). It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on another element or layer, directly connected to or directly coupled to another element or layer, or there may be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive" to another element or "directly on another element," there are no intermediate elements. In addition, "electrically connected" conceptually includes physical connections and physical disconnections.

[0030] Reference Figure 2 , a double height cell DHC may be provided. In detail, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 may be provided on the substrate 100. The first power line M1_R1 may be provided between the second power line M1_R2 and the third power line M1_R3 (in the first direction D1). The third power line M1_R3 may be a conductive path to which a source voltage VSS is provided.

[0031] The double height cell DHC may be defined between the second power line M1_R2 (a (center) portion in the first direction D1) and the third power line M1_R3 (a (center) portion in the first direction D1). The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0032] One of the two second active regions AR2 may be adjacent to the second power line M1_R2. The other of the two second active regions AR2 may be adjacent to the third power line M1_R3. Two (or a pair of) first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be disposed (in the first direction D1) between the pair of first active regions AR1.

[0033] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The pair of first active regions AR1 of the double height cell DHC may be merged into a single active region.

[0034] Figure 2 The double height cell DHC shown in can be defined as a multi-height cell. In some embodiments, the multi-height cell may include a triple height cell, whose cell height is approximately three times the cell height of the single height cell SHC.

[0035] Reference Figure 3 , the first single height cell SHC1, the second single height cell SHC2, and the double height cell DHC may be two-dimensionally disposed on the substrate 100. The first single height cell SHC1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The second single height cell SHC2 may be disposed between the first power line M1_R1 and the third power line M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0036] The double height cell DHC may be disposed between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

[0037] The partitioning structure DB may be disposed between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The active area (e.g., the first active area AR1 and / or the second active area AR2) of the double height cell DHC may be electrically separated from the active area (e.g., the first active area AR1 and / or the second active area AR2) of each of the first single height cell SHC1 and the second single height cell SHC2 by the partitioning structure DB. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. When following a list of elements, expressions such as "at least one of" modify the entire list of elements without modifying the individual elements of the list.

[0038] Figure 4A is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. Figure 4B is along Figure 4A A cross-sectional view taken along line A1-A1'. Figure 4C is along Figure 4A A cross-sectional view taken along line B1-B1'. Figure 4D It is shown Figure 4B An enlarged view of part E1. Figure 4E It is shown Figure 4C An enlarged view of portion E2.

[0039] Reference FIG. 4A to FIG. 4C , the semiconductor device may include a substrate 100. A single height cell SHC may be disposed on the substrate 100. A logic unit may be disposed on the single height cell SHC. In some embodiments, the substrate 100 may include (e.g., may be) a semiconductor substrate. As an example, the substrate 100 may be formed of or include silicon, germanium, silicon germanium, GaP, and / or GaAs. In some embodiments, the substrate 100 may include (e.g., may be) an insulating substrate, a silicon on insulator (SOI) substrate, and / or a germanium on insulator (GOI) substrate. The substrate 100 may be a plate-shaped structure extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may not be parallel to each other. The first direction D1 and the second direction D2 may be parallel to an upper surface of the substrate 100. The first direction D1 and the second direction D2 may be horizontal directions intersecting (e.g., orthogonal) with each other.

[0040] The substrate 100 may include an active pattern AP. The active pattern AP may be defined by a trench on the substrate 100 (which will be at least partially filled with a device isolation layer ST described below). For example, the active pattern AP may be adjacent to the trench (or the device isolation layer ST). The active pattern AP may extend in the second direction D2. The active pattern AP may be a portion of the substrate 100 formed to protrude in the third direction D3. The third direction may be perpendicular to the upper surface of the substrate 100. The third direction D3 may not be parallel to the first direction D1 and the second direction D2. The third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2.

[0041] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may (at least partially) fill the trench on the substrate 100. The device isolation layer ST may include an insulating material. For example, the device isolation layer ST may be formed of or include at least one of oxide materials.

[0042] The source / drain patterns SD may be disposed on the active pattern AP. In some embodiments, the source / drain patterns SD may be arranged on the active pattern AP along the second direction D2 (eg, may be spaced apart from each other).

[0043] The source / drain pattern SD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The source / drain pattern SD may include a semiconductor material. In some embodiments, the source / drain pattern SD may be formed of or include silicon (Si), silicon germanium (SiGe), and / or germanium (Ge). In some embodiments, the source / drain pattern SD connected (e.g., electrically connected) to one of the active patterns AP may be doped with p-type impurities to have a p-type conductivity type, and the source / drain pattern SD connected (e.g., electrically connected) to another of the active patterns AP may be doped with n-type impurities to have an n-type conductivity type.

[0044] A channel structure CH may be provided. The channel structure CH may be provided between source / drain patterns SD adjacent to each other. The channel structure CH may overlap the active pattern AP in the third direction D3. The channel structure CH overlapping each active pattern AP in the third direction D3 may be arranged in the second direction D2 (e.g., may be spaced apart from each other). As used herein, “element A overlaps element B in direction X (or similar language)” means that there is at least one line extending in direction X and intersecting both elements A and B.

[0045] Each of the channel structures CH may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 spaced apart from each other in the third direction D3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may overlap each other in the third direction D3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include a semiconductor material. As an example, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include silicon.

[0046] The number of semiconductor patterns SP1, SP2, and SP3 in each channel structure CH is not limited to the illustrated example. In some embodiments, the number of semiconductor patterns SP1, SP2, and SP3 in each channel structure CH may be less than or equal to two, or may be greater than or equal to four.

[0047] The gate electrode GE may be disposed to extend in the first direction D1. The gate electrode GE may be disposed to cross at least one of the active patterns AP. The gate electrode GE may be disposed to cross at least one of the channel structures CH. The gate electrode GE may overlap the channel structure CH in the third direction D3.

[0048] The gate electrode GE may include a first electrode portion PO1 between the active pattern AP and the first semiconductor pattern SP1, a second electrode portion PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third electrode portion PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth electrode portion PO4 on the third semiconductor pattern SP3. The gate electrode GE may include a conductive material. The gate electrode GE and the first to third semiconductor patterns SP1, SP2, and SP3 may constitute a three-dimensional field effect transistor (e.g., MBCFET or GAAFET). In some embodiments, the channel structure CH may have a monomer structure (e.g., a fin structure) rather than a structure including separate semiconductor patterns.

[0049] A pair of gate spacers GS may be respectively disposed on the (e.g., opposite) sides of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE and extend in the first direction D1. The upper (e.g., uppermost) surface of the gate spacer GS may be higher than the upper (e.g., uppermost) surface of the gate electrode GE. In some embodiments, the upper (e.g., uppermost) surface of the gate spacer GS may be coplanar with the upper (e.g., uppermost) surface of the first insulating layer 110 to be described below. The vertical level may be a relative position (e.g., distance) from the upper (or lower) surface of the substrate 100 in the vertical direction (e.g., in the third direction D3). For example, when element A is higher than element B, element A may be farther from the upper surface of the substrate 100 in the third direction D3 than element B.

[0050] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping pattern GP may include an insulating material having an etching selectivity with respect to a first insulating layer 110 and a second insulating layer 120 to be described below. For example, the gate capping pattern GP may be formed of or include at least one of nitride materials.

[0051] A gate insulating layer GI may be provided. The gate insulating layer GI may separate (e.g., electrically separate) the gate electrode GE from the semiconductor patterns SP1, SP2, and SP3. For example, the gate insulating layer GI may be located between the gate electrode GE (e.g., the first electrode portion PO1, the second electrode portion PO2, the third electrode portion PO3, and the fourth electrode portion PO4). The gate insulating layer GI may contact the gate electrode GE (e.g., the first electrode portion PO1, the second electrode portion PO2, the third electrode portion PO3, and the fourth electrode portion PO4) and the semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may include an insulating material. As an example, the gate insulating layer GI may be formed of or include at least one of oxide materials.

[0052] The first insulating layer 110 may be disposed on the gate spacer GS and the source / drain pattern SD. The upper (e.g., uppermost) surface of the first insulating layer 110 may be coplanar with the upper (e.g., uppermost) surface of the gate capping pattern GP and the upper (e.g., uppermost) surface of the gate spacer GS. The second insulating layer 120 may be disposed on the first insulating layer 110 and the gate capping pattern GP. The covering insulating layer 130 may be disposed on the second insulating layer 120. The first insulating layer 110, the second insulating layer 120, and the covering insulating layer 130 may include insulating materials. As an example, the first insulating layer 110, the second insulating layer 120, and the covering insulating layer 130 may be formed of at least one of oxide materials or include at least one of oxide materials. In some embodiments, each of the first insulating layer 110, the second insulating layer 120, and the covering insulating layer 130 may have a multilayer structure including a plurality of insulating layers.

[0053] The active contact AC may be provided to extend in the first insulating layer 110 and the second insulating layer 120 (e.g., extend through or penetrate the first insulating layer 110 and the second insulating layer 120). The active contact AC may be electrically connected to the source / drain pattern SD. The gate electrode GE may be provided between the active contacts AC adjacent to each other in the second direction D2. The active contact AC may be a stripe pattern extending in the first direction D1.

[0054] In some embodiments, a metal semiconductor compound layer may be interposed between the active contact AC and the source / drain pattern SD. In this case, the active contact AC may be electrically connected to the source / drain pattern SD through the metal semiconductor compound layer. For example, the metal semiconductor compound layer may be formed of or include titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0055] In some embodiments, the active contact AC may include a conductive pattern and a blocking pattern. The blocking pattern may be on the side and lower (e.g., lowermost) surface of the conductive pattern (e.g., covering the side and lower surface of the conductive pattern or overlapping the side and lower surface of the conductive pattern). For example, the conductive pattern may be formed of or include aluminum, copper, tungsten, molybdenum and / or cobalt, and the blocking pattern may be formed of or include titanium, tantalum, tungsten, nickel, cobalt, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN) and / or platinum nitride (PtN).

[0056] The conductive contact 131 may be disposed to extend in the cover insulating layer 130 (e.g., extend through or penetrate the cover insulating layer 130). The conductive contact 131 may electrically connect a first conductive line 143 to be described below to an active contact AC, or may electrically connect the first conductive line 143 to the gate electrode GE. The conductive contact 131 may include a conductive material.

[0057] The first etch stop layer 141 may be disposed on the capping insulating layer 130. The first interlayer insulating layer 142 may be disposed on the first etch stop layer 141. The second etch stop layer 151 may be disposed on the first interlayer insulating layer 142. The second interlayer insulating layer 152 may be disposed on the second etch stop layer 151. The third interlayer insulating layer 153 may be disposed on the second interlayer insulating layer 152.

[0058] The first etch stop layer 141 and the first interlayer insulating layer 142 may include insulating materials having etching selectivity relative to each other. As an example, the first etch stop layer 141 may be formed of or include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), aluminum nitride (AlN) and / or aluminum oxide (AlO), and the first interlayer insulating layer 142 may be formed of or include a low-k dielectric material, tetraethyl orthosilicate (TEOS), silicon carbide (SiC) and / or silicon oxide (SiO).

[0059] The second etch stop layer 151 and the second interlayer insulating layer 152 may include an insulating material having an etching selectivity relative to each other. As an example, the second etch stop layer 151 may be formed of or include silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiCO), aluminum nitride (AlN) and / or aluminum oxide (AlO), and the second interlayer insulating layer 152 may be formed of or include a low-k dielectric material, TEOS, silicon carbide (SiC) and / or silicon oxide (SiO). The third interlayer insulating layer 153 may include an insulating material.

[0060] The first conductive line 143 may be arranged to extend in the first interlayer insulating layer 142 and the first etch stop layer 141 (e.g., extend through or penetrate the first interlayer insulating layer 142 and the first etch stop layer 141). The first conductive line 143 may extend along the second direction D2. The first conductive line 143 may be spaced apart from each other in the first direction D1. The first conductive line 143 may include a conductive material. As an example, the first conductive line 143 may be formed of or include Ru, Mo, W, Cu, and / or Co.

[0061] The conductive structure 170 may be arranged to extend in the second etch stop layer 151, the second interlayer insulating layer 152, and the third interlayer insulating layer 153 (e.g., extend through or penetrate the second etch stop layer 151, the second interlayer insulating layer 152, and the third interlayer insulating layer 153). The conductive structure 170 may include a lower portion 171 and an upper portion 172 on the lower portion 171. The lower portion 171 of the conductive structure 170 may extend in the second etch stop layer 151 and the second interlayer insulating layer 152 (e.g., extend through or penetrate the second etch stop layer 151 and the second interlayer insulating layer 152). The upper portion 172 of the conductive structure 170 may extend in the third interlayer insulating layer 153 (e.g., extend through or penetrate the third interlayer insulating layer 153). For example, the lower portion 171 of the conductive structure 170 may be defined as a portion of the conductive structure 170 in the second etch stop layer 151 and the second interlayer insulating layer 152. For example, the upper portion 172 of the conductive structure 170 may be defined as the portion of the conductive structure 170 in the third interlayer insulating layer 153. The lower portion 171 of the conductive structure 170 may be at least partially surrounded by the second etch stop layer 151 and the second interlayer insulating layer 152 (e.g., at least partially enclosed by the second etch stop layer 151 and the second interlayer insulating layer 152). For example, the side surface of the lower portion 171 of the conductive structure 170 may be surrounded by the second etch stop layer 151 and the second interlayer insulating layer 152. The upper portion 172 of the conductive structure 170 may be at least partially surrounded by the third interlayer insulating layer 153 (e.g., at least partially enclosed by the third interlayer insulating layer 153). For example, the side surface of the upper portion 172 of the conductive structure 170 may be surrounded by the third interlayer insulating layer 153. The boundary between the lower portion 171 and the upper portion 172 of the conductive structure 170 may be located at substantially the same level as the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 and the lower (e.g., lowermost) surface 153_B (in the third direction D3) of the third interlayer insulating layer 153. The lower portion 171 of the conductive structure 170 may be disposed at a level lower than the upper surface 152_T of the second interlayer insulating layer 152 and the lower surface 153_B of the third interlayer insulating layer 153. The upper portion 172 of the conductive structure 170 may be disposed at a level higher than the upper surface 152_T of the second interlayer insulating layer 152 and the lower surface 153_B of the third interlayer insulating layer 153.

[0062] The width of the lower portion 171 of the conductive structure 170 (in the first direction D1 and / or the second direction D2) may decrease as the distance from the first conductive line 143 (in the third direction D3) decreases. As an example, the width W1 of the lower portion 171 of the conductive structure 170 in the second direction D2 may decrease as the distance from the first conductive line 143 (in the third direction D3) decreases, and the width W3 of the lower portion 171 of the conductive structure 170 in the first direction D1 may decrease as the distance from the first conductive line 143 (in the third direction D3) decreases. The width of the lower portion 171 of the conductive structure 170 may decrease as the vertical level (of the lower portion 171 of the conductive structure 170) decreases.

[0063] The width of the upper portion 172 of the conductive structure 170 (in the first direction D1 and / or the second direction D2) may increase as the distance from the first conductive line 143 (in the third direction D3) decreases. As an example, the width W2 of the upper portion 172 of the conductive structure 170 in the second direction D2 may increase as the distance from the first conductive line 143 (in the third direction D3) decreases, and the width W4 of the upper portion 172 of the conductive structure 170 in the first direction D1 may increase as the distance from the first conductive line 143 (in the third direction D3) decreases. The width of the upper portion 172 of the conductive structure 170 may increase as the vertical level (of the upper portion 172 of the conductive structure 170) decreases.

[0064] The middle portion IN of the first interlayer insulating layer 142 may be defined between the pair of first conductive lines 143 adjacent to each other in the first direction D1. The middle portion IN of the first interlayer insulating layer 142 may contact the pair of first conductive lines 143 adjacent to each other in the first direction D1.

[0065] The lower (e.g., lowermost) surface 170_B of the conductive structure 170 may be in contact with the upper (e.g., uppermost) surface 143_T of a pair of first conductive wires 143 adjacent to each other in the first direction D1 and the upper (e.g., uppermost) surface IN_T of the middle portion IN. The upper surface 143_T of the pair of first conductive wires 143 adjacent to each other in the first direction D1 may be coplanar with the upper surface IN_T of the middle portion IN. The upper surface 143_T of the pair of first conductive wires 143 adjacent to each other in the first direction D1 may be located at the same level (in the third direction D3) as the upper surface IN_T of the middle portion IN. The lower surface 170_B of the conductive structure 170 may be flat. The lower surface 170_B of the conductive structure 170 may be the lower (e.g., lowermost) surface of the lower portion 171 of the conductive structure 170.

[0066] The width of the lower surface 170_B of the conductive structure 170 in the first direction D1 may be greater than the sum of the width of the upper surface 143_T of a pair (e.g., two) of first conductive lines 143 adjacent to each other in the first direction D1 and the width of the upper surface IN_T of the middle portion IN (between the pair of first conductive lines 143) in the first direction D1.

[0067] Conductive structure 170 may include barrier layer 174 and conductive layer 173 on barrier layer 174. Barrier layer 174 may contact upper (e.g., uppermost) surface 143_T of first conductive line 143 adjacent to each other in first direction D1 and upper (e.g., uppermost) surface IN_T of middle part IN. Barrier layer 174 may include conductive material. As an example, barrier layer 174 may be formed of or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and / or transition metal chalcogenide (e.g., MoS and WS). Conductive layer 173 may include conductive material. As an example, conductive layer 173 may be formed of or include Ru, Mo, W, Cu and / or Co.

[0068] The second conductive line 160 may be arranged to extend in the third interlayer insulating layer 153 (e.g., extend through or penetrate the third interlayer insulating layer 153). The second conductive line 160 may be at least partially surrounded by the third interlayer insulating layer 153 (e.g., at least partially enclosed by the third interlayer insulating layer 153). For example, the third interlayer insulating layer 153 may extend around the side surface of the second conductive line 160. The lower (e.g., lowermost) surface 160_B of the second conductive line 160 may contact the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152. The second conductive line 160 may be arranged at the same level as the upper portion 172 of the conductive structure 170. For example, the second conductive line 160 may overlap the upper portion 172 of the conductive structure 170 in the first direction D1 and / or the second direction D2. A lower (eg, lowermost) surface 160_B of the second conductive line 160 may be located at substantially the same level (in the third direction D3 ) as a boundary between the lower portion 171 and the upper portion 172 of the conductive structure 170 .

[0069] The width of the second conductive line 160 (in the first direction D1 and / or the second direction D2) may increase as the distance from the first conductive line 143 (in the third direction D3) decreases. As an example, the width W5 of the second conductive line 160 in the first direction D1 may increase as the distance from the first conductive line 143 (in the third direction D3) decreases. The width of the second conductive line 160 may increase as the vertical level (of the second conductive line 160) decreases.

[0070] The second conductive line 160 may include a wire barrier layer 161 and a wire conductive layer 162 on the wire barrier layer 161. A lower (e.g., lowermost) surface of the wire barrier layer 161 may be a lower (e.g., lowermost) surface 160_B of the second conductive line 160. A side surface 161_S of the wire barrier layer 161 and a side surface 162_S of the wire conductive layer 162 may contact a side surface of the third interlayer insulating layer 153. The side surface 161_S of the wire barrier layer 161 may be coplanar with a side surface 162_S of the wire conductive layer 162. The side surface 161_S of the wire barrier layer 161 and the side surface 162_S of the wire conductive layer 162 may be inclined at a certain angle relative to an upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 and a lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153. The angle between the side surface 161_S of the wire barrier layer 161 and the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153 may be an obtuse angle at a portion where the side surface 161_S of the wire barrier layer 161 is connected to the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153.

[0071] The wire barrier layer 161 may include the same conductive material as the barrier layer 174. The wire conductive layer 162 may include the same conductive material as the conductive layer 173.

[0072] Reference Figure 4D and Figure 4E , the barrier layer 174 may include a lower portion 174a and an upper portion 174b on the lower portion 174a. The conductive layer 173 may include a lower portion 173a and an upper portion 173b on the lower portion 173a. The lower portion 171 of the conductive structure 170 may include the lower portion 174a of the barrier layer 174 and the lower portion 173a of the conductive layer 173. The upper portion 172 of the conductive structure 170 may include the upper portion 174b of the barrier layer 174 and the upper portion 173b of the conductive layer 173. The lower portion 173a of the conductive layer 173 may be at least partially enclosed by the lower portion 174a of the barrier layer 174. For example, the lower portion 174a of the barrier layer 174 may extend around the side surface of the lower portion 173a of the conductive layer 173.

[0073] The outer side surface 174a_S1 of the lower portion 174a of the barrier layer 174 may be in contact with the side surface of the second interlayer insulating layer 152. For example, the lower portion 174a of the barrier layer 174 may be defined as the portion of the barrier layer 174 in the second interlayer insulating layer 152. The inner side surface 174a_S2 of the lower portion 174a of the barrier layer 174 may be in contact with the lower portion 173a of the conductive layer 173. The outer side surface 174a_S1 and the inner side surface 174a_S2 of the lower portion 174a of the barrier layer 174 may be inclined at an angle relative to the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 and the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153. When Figure 4D or Figure 4E When viewed in a cross-sectional view of , the outer side surface 174a_S1 and the inner side surface 174a_S2 of the lower portion 174a of the barrier layer 174 may extend to be parallel to each other. The lower portion 174a of the barrier layer 174 may have a substantially constant width (in a horizontal direction, such as the second direction D2). As an example, the width W7 of the lower portion 174a of the barrier layer 174 in the second direction D2 may be substantially constant (regardless of the level of the lower portion 174a of the barrier layer 174 in the third direction D3). The outer side surface 174a_S1 of the lower portion 174a of the barrier layer 174 may be the outer side surface of the lower portion 171 of the conductive structure 170.

[0074] The outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 may contact the side surface of the third interlayer insulating layer 153. For example, the upper portion 174b of the barrier layer 174 may be defined as a portion of the barrier layer 174 in the third interlayer insulating layer 153. The inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 may contact the upper portion 173b of the conductive layer 173. The outer side surface 174b_S1 and the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 may be inclined at an angle relative to the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 and the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153. For example, the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 may be inclined at an angle relative to an imaginary line extending from the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 and / or the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153 along the second direction D2. Figure 4D or Figure 4E When viewed in a cross-sectional view of , the outer side surface 174b_S1 and the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 may extend in two different directions that are not parallel to each other. The width of the upper portion 174b of the barrier layer 174 (in the first direction D1 and / or the second direction D2) may increase as the distance from the first conductive line 143 (in the third direction D3) decreases. As an example, the width W6 of the upper portion 174b of the barrier layer 174 in the second direction D2 may increase as the distance from the first conductive line 143 decreases. The width of the upper portion 174b of the barrier layer 174 may increase as the vertical level (of the upper portion 174b of the barrier layer 174) decreases.

[0075] The inner side surface 174a_S2 of the lower portion 174a of the barrier layer 174 may be coplanar with the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174. Figure 4D and Figure 4EWhen viewed in a cross-sectional view of , the inner side surface 174a_S2 of the lower portion 174a of the barrier layer 174 and the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 may be located on (may be formed by) a single straight line.

[0076] The outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 may include a first portion P1. The outer side surface 174a_S1 of the lower portion 174a of the barrier layer 174 may include a second portion P2. The first portion P1 and the second portion P2 may be spaced apart from each other. The upper portion 174b of the barrier layer 174 may include a connection surface 174b_S3 connecting the first portion P1 to the second portion P2. For example, the connection surface 174b_S3 may be located between the first portion P1 and the second portion P2 (in the second direction D2). The connection surface 174b_S3 may contact the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152. For example, the connection surface 174b_S3 may be coplanar with the upper surface 152_T of the second interlayer insulating layer 152 and the lower surface 153_B of the third interlayer insulating layer 153.

[0077] The outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 may include a third portion P3. The outer side surface 174a_S1 of the lower portion 174a of the barrier layer 174 may include a fourth portion P4. The third portion P3 and the fourth portion P4 may be connected to each other. The connection portion between the third portion P3 and the fourth portion P4 may be at the same vertical level as the upper surface 152_T of the second interlayer insulating layer 152 and / or the lower surface 153_B of the third interlayer insulating layer 153 (substantially).

[0078] The upper (e.g., uppermost) surface 174b_S4 of the upper portion 174b of the barrier layer 174 may connect the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 to the outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174. The upper (e.g., uppermost) surface 174b_S4 of the upper portion 174b of the barrier layer 174 may be located between the inner side surface 174b_S2 of the upper portion 174b of the barrier layer 174 and the outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 in the second direction D2. The upper (e.g., uppermost) surface 174b_S4 of the upper portion 174b of the barrier layer 174 may contact the upper portion 173b of the conductive layer 173.

[0079] The lower portion 173a of the conductive layer 173 may be spaced apart from the second interlayer insulating layer 152 by the lower portion 174a of the barrier layer 174. The upper portion 173b of the conductive layer 173 may contact the third interlayer insulating layer 153. The outer side surface 173b_S1 of the upper portion 173b of the conductive layer 173 may contact the side surface of the third interlayer insulating layer 153.

[0080] The outer side surface 173b_S1 of the upper portion 173b of the conductive layer 173 may be coplanar with the outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174. Figure 4D and Figure 4E When viewed in a cross-sectional view of , the outer side surface 173b_S1 of the upper portion 173b of the conductive layer 173 and the outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 may be located on a single straight line (may be formed by a single straight line). The outer side surface of the upper portion 172 of the conductive structure 170 may include the outer side surface 174b_S1 of the upper portion 174b of the barrier layer 174 and the outer side surface 173b_S1 of the upper portion 173b of the conductive layer 173.

[0081] An angle AN1 between the first portion P1 and the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153 may be an obtuse angle at a portion where the first portion P1 is connected to the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153. An angle AN2 between the second portion P2 and the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152 may be an obtuse angle at a portion where the second portion P2 is connected to the upper (e.g., uppermost) surface 152_T of the second interlayer insulating layer 152. An angle AN3 between the third portion P3 and the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153 may be an obtuse angle at a portion where the third portion P3 is connected to the lower (e.g., lowermost) surface 153_B of the third interlayer insulating layer 153. An angle AN4 between the fourth portion P4 and the upper (eg, uppermost) surface 152_T of the second interlayer insulating layer 152 may be an obtuse angle at a portion where the fourth portion P4 is connected to the upper (eg, uppermost) surface 152_T of the second interlayer insulating layer 152 .

[0082] In the semiconductor device according to some embodiments of the present invention, the lower (e.g., lowermost) surface 170_B of the conductive structure 170 may have a substantially flat shape, and therefore, in the process of forming the conductive structure 170, the first conductive wire 143 and the middle portion IN located below the conductive structure 170 will not be damaged.

[0083] In the semiconductor device according to some embodiments of the present inventive concept, since the lower (eg, lowermost) surface 170_B of the conductive structure 170 has a substantially flat shape, the barrier layer 174 may have a constant (uniform) thickness and the reliability of the barrier layer 174 may be improved.

[0084] In the semiconductor device according to some embodiments of the present inventive concept, since the pair of first conductive lines 143 are connected (e.g., electrically connected) to each other through the conductive structure 170, an additional interconnection structure for electrically connecting the pair of first conductive lines 143 to each other can be omitted. As a result, the size of the semiconductor device can be reduced and the degree of freedom in designing the semiconductor device can be increased.

[0085] In the semiconductor device according to some embodiments of the present inventive concept, the maximum width of the upper portion 172 of the conductive structure 170 in the first direction D1 may be equal to the maximum width of the lower portion 171 of the conductive structure 170 in the first direction D1. Therefore, the length of the upper portion 172 of the conductive structure 170 in the first direction D1 may be reduced, and the degree of freedom in designing the semiconductor device may be increased.

[0086] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It shows the manufacturing FIG. 4A to FIG. 4E A cross-sectional view of a method for a semiconductor device.

[0087] Reference Figure 5 , an active pattern AP may be formed in the substrate 100. A device isolation layer ST may be formed. A channel structure CH, a source / drain pattern SD (eg, see Figure 4B ), a gate electrode GE, a gate insulating layer GI (eg, see Figure 4B ), gate spacer GS (see, for example, Figure 4B ), the gate capping pattern GP, ​​the first insulating layer 110 (eg, see Figure 4B ), the second insulating layer 120 and the active contact AC (eg, see Figure 4B ).

[0088] A capping insulating layer 130 may be formed on the second insulating layer 120. A conductive contact 131 (eg, Figure 4B ) may be formed to extend in the cover insulating layer 130 (eg, penetrate the cover insulating layer 130 ).

[0089] A first etch stop layer 141 may be formed on the capping insulating layer 130. A first interlayer insulating layer 142 may be formed on the first etch stop layer 141. A first conductive line 143 may be formed in the first etch stop layer 141 and the first interlayer insulating layer 142. The formation of the first conductive line 143 may include etching the first interlayer insulating layer 142 and the first etch stop layer 141, and forming the first conductive line 143 in an empty space formed by etching the first interlayer insulating layer 142 and the first etch stop layer 141. The first etch stop layer 141 may be used as an etch stop layer in the process of etching the first interlayer insulating layer 142.

[0090] A second etch stop layer 151 may be formed on the first interlayer insulating layer 142 and the first conductive line 143. A second interlayer insulating layer 152 may be formed on the second etch stop layer 151.

[0091] Reference Figure 6 , the first opening OP1 may be formed to extend in the second interlayer insulating layer 152 (e.g., extend through or penetrate the second interlayer insulating layer 152). The first opening OP1 may be formed by etching the second interlayer insulating layer 152. The first opening OP1 may be at least partially surrounded by the second interlayer insulating layer 152 (e.g., at least partially enclosed). The first opening OP1 may be formed to expose at least a portion of the upper (e.g., uppermost) surface of the second etch stop layer 151. The second etch stop layer 151 may be used as an etch stop layer in the process of forming the first opening OP1. The width of the first opening OP1 in the first direction D1 may decrease as the distance from the first conductive line 143 (in the third direction D3) decreases. The upper (e.g., uppermost) surface (of the exposed portion) of the second etch stop layer 151 and the (exposed) side surface of the second interlayer insulating layer 152 may define the first opening OP1.

[0092] Reference Figure 7 , the first opening OP1 may be enlarged. For example, the first opening OP1 may be extended by etching (the exposed portion of the upper surface of) the second etch stop layer 151 exposed by the first opening OP1. (Part of) the first conductive line 143 and the middle portion IN of the first interlayer insulating layer 142 may be exposed by the extended first opening OP1. The extended first opening OP1 may be referred to as the second opening OP2. The upper (e.g., uppermost) surface of the first interlayer insulating layer 142, the upper (e.g., uppermost) surface of the first conductive line 143, the side surface of the second etch stop layer 151, and the side surface of the second interlayer insulating layer 152 may define the second opening OP2. For example, the second opening OP2 may expose (at least a portion of) the upper (e.g., uppermost) surface of the first interlayer insulating layer 142 (e.g., middle portion IN), the upper (e.g., uppermost) surface of the first conductive line 143, the side surface of the second etch stop layer 151, and the side surface of the second interlayer insulating layer 152.

[0093] Reference Figure 8, an initial barrier layer p174 may be formed. The initial barrier layer p174 may be conformally formed on the upper (e.g., uppermost) surface of the second interlayer insulating layer 152, the side surface of the second interlayer insulating layer 152, the upper (e.g., uppermost) surface of the first conductive line 143, the upper (e.g., uppermost) surface of the first interlayer insulating layer 142, and the side surface of the second etch stop layer 151. The initial barrier layer p174 may be in contact with the upper (e.g., uppermost) surface of the second interlayer insulating layer 152, the side surface of the second interlayer insulating layer 152, the upper (e.g., uppermost) surface of the first conductive line 143, the upper (e.g., uppermost) surface of the first interlayer insulating layer 142, and the side surface of the second etch stop layer 151.

[0094] The initial barrier layer p174 may include a conductive material. In some embodiments, the initial barrier layer p174 may be formed of or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and / or transition metal chalcogenides (e.g., MoS and WS).

[0095] Reference Fig. 9 , an initial conductive layer p173 may be formed on the initial barrier layer p174. The initial conductive layer p173 may include a conductive material. In some embodiments, the initial conductive layer p173 may be formed of Ru, Mo, W, Cu and / or Co or include Ru, Mo, W, Cu and / or Co.

[0096] Reference Fig.10 , a mask layer MA may be formed on the preliminary conductive layer p173. The formation of the mask layer MA may include forming a preliminary mask layer on the preliminary conductive layer p173 and patterning the preliminary mask layer to form the mask layer MA. The mask layer MA may include an insulating material.

[0097] The initial conductive layer p173 and the initial barrier layer p174 may be etched using the mask layer MA as an etching mask. As a result of etching the initial barrier layer p174, a barrier layer 174 and a line barrier layer 161 spaced apart from each other may be formed. As a result of etching the initial conductive layer p173, a conductive layer 173 and a line conductive layer 162 may be formed. The line barrier layer 161 and the line conductive layer 162 may constitute a second conductive line 160. The barrier layer 174 and the conductive layer 173 may constitute a conductive structure 170. The lower portion 171 (e.g., see FIG. 1 ) of the conductive structure 170 may be formed. Figure 4B and Figure 4C ) may be disposed in the second opening OP2. The upper portion 172 of the conductive structure 170 (eg, see Figure 4B and Figure 4C ) may be disposed at a level higher than the second opening OP2 in the third direction D3.

[0098] In some embodiments, the initial conductive layer p173 and the initial blocking layer p174 can be etched so that the width of the upper portion 172 of the conductive structure 170 (in the first direction D1 and / or the second direction D2) is equal to or greater than the width of the lower portion 171 of the conductive structure 170 (in the first direction D1 and / or the second direction D2).

[0099] In some embodiments, when measured in the first direction D1, the maximum width of a portion of the mask layer MA overlapping with the second opening OP2 in the third direction D3 (in the first direction D1 and / or the second direction D2) may be smaller than the maximum width of the second opening OP2 (in the first direction D1 and / or the second direction D2).

[0100] As a result of etching of the preliminary conductive layer p173 and the preliminary barrier layer p174, at least a portion of an upper (eg, uppermost) surface of the second interlayer insulating layer 152 may be exposed.

[0101] Reference Figure 4B and Figure 4C , the mask layer MA may be removed, and a third interlayer insulating layer 153 may be formed.

[0102] In the manufacturing method of some embodiments conceived according to the present invention, since the second opening OP2 is formed to have a width greater than (or equal to) the first wire 143 (in the first direction D1 and / or the second direction D2), and the lower portion 171 of the conductive structure 170 is formed in the second opening OP2, the technical difficulty in the process of forming the conductive structure 170 can be reduced.

[0103] In the manufacturing method according to some embodiments of the inventive concept, since the upper portion 172 of the conductive structure 170 is formed by etching the preliminary conductive layer p173 and the preliminary barrier layer p174 , the length of the upper portion 172 of the conductive structure 170 may be reduced.

[0104] Fig.11 1 is an enlarged cross-sectional view showing a semiconductor device according to some embodiments of the present invention. In addition to the features described below, Fig.11 The semiconductor device can be similar to the reference FIG. 4A to FIG. 4E A semiconductor device is described. Fig.11 Corresponds to Figure 4C Section E3.

[0105] Reference Fig.11, the first etch stop layer 241 located between the capping insulating layer 130 and the first interlayer insulating layer 142 may include a first layer 241a and a second layer 241b. The first layer 241a and the second layer 241b may be formed of or include insulating materials different from each other. In some embodiments, the first etch stop layer 241 may include three or more layers.

[0106] The second etch stop layer 251 located between the first interlayer insulating layer 142 and the second interlayer insulating layer 152 may include a third layer 251a and a fourth layer 251b. The third layer 251a and the fourth layer 251b may be formed of or include insulating materials different from each other. In some embodiments, the second etch stop layer 251 may include three or more layers.

[0107] The connection surface 274b_S3 of the upper portion 272 of the conductive structure 270 may connect the outer side surface of the upper portion 272 of the conductive structure 270 to the outer side surface of the lower portion 271 of the conductive structure 270. For example, the connection surface 274b_S3 of the upper portion 272 of the conductive structure 270 may be located between the outer side surface of the upper portion 272 of the conductive structure 270 and the outer side surface of the lower portion 271 of the conductive structure 270 in the first direction D1. When viewed in a plan view, the connection surface 274b_S3 of the upper portion 272 of the conductive structure 270 may have a ring shape.

[0108] Fig.12 1 is an enlarged cross-sectional view showing a semiconductor device according to some embodiments of the present invention. In addition to the features described below, Fig.12 The semiconductor device can be similar to FIG. 4A to FIG. 4E semiconductor device. Fig.12 Corresponds to Figure 4C Section E3.

[0109] Reference Fig.12 , the maximum width of the upper portion 372 of the conductive structure 370 in the first direction D1 may be smaller than the maximum width of the lower portion 371 of the conductive structure 370 in the first direction D1. The third interlayer insulating layer 353 may include a filling portion 353a that protrudes toward the lower portion 371 of the conductive structure 370 and the second interlayer insulating layer 352. For example, the third interlayer insulating layer 353 may include a filling portion 353a that at least partially extends into the lower portion 371 of the conductive structure 370 and the second interlayer insulating layer 352. The filling portion 353a may be disposed at a lower level (in the third direction D3) than the upper portion 372 of the conductive structure 370. The filling portion 353a may be disposed between the lower portion 371 of the conductive structure 370 and the second interlayer insulating layer 352.

[0110] The second interlayer insulating layer 352 may include a first curved surface 352_S in contact with the filling portion 353a. The barrier layer 374 may include a second curved surface 374_S in contact with the filling portion 353a. The lower portion of the conductive layer 373 may include a third curved surface 373a_S in contact with the filling portion 353a. The bottom surface of the filling portion 353a may have a curved shape. The lower surface of the filling portion 353a may be in contact with the first curved surface 352_S, the second curved surface 374_S, and the third curved surface 373a_S. The third curved surface 373a_S may be connected to the outer side surface 372_S of the upper portion 372 of the conductive structure 370.

[0111] As a result of the process of etching the initial conductive layer and the initial barrier layer, the first curved surface 352_S, the second curved surface 374_S, and the third curved surface 373a_S may be formed. In the process of forming the third interlayer insulating layer 353, an empty space defined by the first curved surface 352_S, the second curved surface 374_S, and the third curved surface 373a_S may be filled with a filling portion 353a.

[0112] Fig.13 1 is an enlarged cross-sectional view showing a semiconductor device according to some embodiments of the present invention. In addition to the features to be described below, Fig.13 The semiconductor device can be similar to the reference FIG. 4A to FIG. 4E A semiconductor device is described. Fig.13 Corresponds to Figure 4C Section E3.

[0113] Reference Fig.13 The conductive layer 473 of the conductive structure 470 may include a penetration portion 473a extending in (eg, extending through or penetrating) the barrier layer 474. The penetration portion 473a may contact an upper (eg, uppermost) surface of the first conductive line 143.

[0114] The barrier layer 474 may contact the first interlayer insulating layer 142, the second etch stop layer 151, and the second interlayer insulating layer 152. The conductive layer 473 may be spaced apart from the first interlayer insulating layer 142, the second etch stop layer 151, and the second interlayer insulating layer 152 by the barrier layer 474.

[0115] and Figure 8 Similar to the embodiment of FIG. 1 , in the process of forming the initial barrier layer, the initial barrier layer may be selectively formed on the first interlayer insulating layer 142, the second etch stop layer 151, and the second interlayer insulating layer 152. The initial barrier layer may not be formed on the first conductive line 143. The first conductive line 143 may be (at least partially) exposed through the initial barrier layer.

[0116] and Fig. 9Similar to the embodiment of FIG. 1 , in the process of forming the preliminary conductive layer, the first conductive line 143 exposed through the preliminary barrier layer may contact the preliminary conductive layer.

[0117] Fig.14 1 is an enlarged cross-sectional view showing a semiconductor device according to some embodiments of the present invention. In addition to the features described below, Fig.14 The semiconductor device can be similar to the reference FIG. 4A to FIG. 4E A semiconductor device is described. Fig.14 Corresponds to Figure 4C Section E3.

[0118] Reference Fig.14 , the conductive structure 570 may not include a barrier layer. The conductive structure 570 may include an upper portion 572 and a lower portion 571 connected to each other to form a single object without an interface (a visible interface therebetween). The conductive structure 570 may be formed of or include Ru, Mo, W, Cu, and / or Co.

[0119] Fig.15 is an enlarged cross-sectional view showing a semiconductor device according to some embodiments of the present invention. In addition to the features described below, Fig.15 The semiconductor device can be similar to the reference FIG. 4A to FIG. 4E A semiconductor device is described. Fig.15 Corresponds to Figure 4C Section E3.

[0120] Reference Fig.15 , the lower portion 671 of the conductive structure 670 may include a barrier layer 674 and a first conductive layer 675 in (on) the barrier layer 674. The conductive structure 670 may further include a second conductive layer 672. The second conductive layer 672 may be an upper portion of the conductive structure 670.

[0121] The first conductive layer 675 and the second conductive layer 672 may include conductive materials different from each other. In some embodiments, the first conductive layer 675 and the second conductive layer 672 may be formed of or include two different materials, each selected from the group consisting of Ru, Mo, W, Cu, Co, alloys, or combinations thereof.

[0122] The upper (e.g., uppermost) surface of the barrier layer 674 and the upper (e.g., uppermost) surface of the first conductive layer 675 may be in contact with the lower (e.g., lowermost) surface of the second conductive layer 672. The upper (e.g., uppermost) surface of the barrier layer 674, the upper (e.g., uppermost) surface of the first conductive layer 675, and the upper (e.g., uppermost) surface of the second interlayer insulating layer 152 may be coplanar with each other. The lower (e.g., lowermost) surface of the second conductive layer 672 may be coplanar with the lower (e.g., lowermost) surface of the third interlayer insulating layer 153. The upper (e.g., uppermost) surface of the barrier layer 674, the upper (e.g., uppermost) surface of the first conductive layer 675, the upper (e.g., uppermost) surface of the second interlayer insulating layer 152, the lower (e.g., lowermost) surface of the second conductive layer 672, and the lower (e.g., lowermost) surface of the third interlayer insulating layer 153 may be located at substantially the same level (in the third direction D3).

[0123] Fig.16 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0124] Reference Fig.16 , the semiconductor device may include a substrate 700. A first etch stop layer 741 may be disposed on the substrate 700. A first interlayer insulating layer 742 may be disposed on the first etch stop layer 741.

[0125] In some embodiments, the electronic component and an insulating layer on the electronic component (e.g., covering the electronic component or overlapping the electronic component) may be disposed between the substrate 700 and the first etch stop layer 741. In some embodiments, the electronic component may include a transistor, a capacitor, a resistor, and / or a diode. The electronic component may be electrically connected to a wire 743 to be described below.

[0126] The first etch stop layer 741 may include a first layer 741a located on the substrate 700 and a second layer 741b located on the first layer 741a. The first layer 741a and the second layer 741b may be formed of or include insulating materials different from each other. The first interlayer insulating layer 742 may include an insulating material having an etching selectivity relative to the first etch stop layer 741.

[0127] The wire 743 may be disposed to extend in (eg, extend through or penetrate) the first etch stop layer 741 and the first interlayer insulating layer 742. The wire 743 may include a conductive material.

[0128] The second etch stop layer 751 may be disposed on the first interlayer insulating layer 742. The second interlayer insulating layer 752 may be disposed on the second etch stop layer 751. The third interlayer insulating layer 753 may be disposed on the second interlayer insulating layer 752.

[0129] The second etch stop layer 751 may include a third layer 751a on the first interlayer insulating layer 742 and a fourth layer 751b on the third layer 751a. The third layer 751a and the fourth layer 751b may be formed of or include insulating materials different from each other. The second interlayer insulating layer 752 may include an insulating material having an etching selectivity relative to the second etch stop layer 751. The third interlayer insulating layer 753 may include an insulating material.

[0130] The conductive structure 770 may be arranged to extend in the second etch stop layer 751, the second interlayer insulating layer 752, and the third interlayer insulating layer 753 (e.g., extend through the second etch stop layer 751, the second interlayer insulating layer 752, and the third interlayer insulating layer 753 or penetrate the second etch stop layer 751, the second interlayer insulating layer 752, and the third interlayer insulating layer 753). The conductive structure 770 may contact the conductive wires 743 adjacent to each other. The lower portion 771 of the conductive structure 770 may be (at least partially) surrounded (e.g., at least partially enclosed) by the second etch stop layer 751 and the second interlayer insulating layer 752. For example, the second etch stop layer 751 and the second interlayer insulating layer 752 may extend around the side surface of the lower portion 771 of the conductive structure 770. The upper portion 772 of the conductive structure 770 may be (at least partially) surrounded (e.g., at least partially surrounded) by the third interlayer insulating layer 753. For example, the third interlayer insulating layer 753 may extend around the side surface of the upper portion 772 of the conductive structure 770 .

[0131] The conductive structure 770 may include a barrier layer 774 and a conductive layer 773 on the barrier layer 774. The barrier layer 774 may contact the upper (e.g., uppermost) surface of the conductive line 743, the side surface of the second etch stop layer 751, the side surface and the upper (e.g., uppermost) surface of the second interlayer insulating layer 752, and the side surface of the third interlayer insulating layer 753. The conductive layer 773 may be separated from the upper (e.g., uppermost) surface of the conductive line 743, the side surface of the second etch stop layer 751, and the side surface and the upper (e.g., uppermost) surface of the second interlayer insulating layer 752 by the barrier layer 774. The conductive layer 773 may contact the side surface of the third interlayer insulating layer 753.

[0132] In a semiconductor device according to some embodiments of the inventive concept, the length of an upper portion of a conductive structure may be minimized, which may increase the degree of freedom in designing the semiconductor device.

[0133] In the semiconductor device according to some embodiments of the present inventive concept, the lower portion of the conductive structure may be formed by a damascene process, and the upper portion of the conductive structure may be formed by an etching process. Therefore, the difficulty in the process of forming the conductive structure may be reduced.

[0134] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: first conductive lines spaced apart from each other; as well as a conductive structure in contact with an upper surface of the first conductive line, The conductive structure includes a lower portion of the conductive structure and an upper portion of the conductive structure. wherein the lower portion of the conductive structure contacts the upper surface of the first conductive wire, wherein the upper portion of the conductive structure is located on the lower portion of the conductive structure, wherein the width of the lower portion of the conductive structure decreases as the distance between the lower portion of the conductive structure and the upper surface of the first conductive line decreases, and The width of the upper portion of the conductive structure increases as the distance between the upper portion of the conductive structure and the upper surface of the first conductive line decreases.

2. The semiconductor device according to claim 1, wherein: The conductive structure includes a barrier layer in contact with an upper surface of the first conductive line, and Wherein, the conductive structure includes a conductive layer on the barrier layer.

3. The semiconductor device according to claim 2, wherein: The barrier layer includes a lower portion of the barrier layer and an upper portion of the barrier layer, wherein the lower portion of the barrier layer contacts the upper surface of the first conductive line, wherein the upper portion of the barrier layer is located on the lower portion of the barrier layer, and The width of the upper portion of the barrier layer increases as the distance between the upper portion of the barrier layer and the upper surface of the first conductive line decreases.

4. The semiconductor device according to claim 3, wherein: The conductive layer includes a lower portion of the conductive layer and an upper portion of the conductive layer, wherein the lower portion of the barrier layer extends around the lower portion of the conductive layer, wherein the upper portion of the conductive layer is located on the lower portion of the conductive layer, wherein the inner surface of the lower portion of the barrier layer is coplanar with the inner surface of the upper portion of the barrier layer, and Wherein, the outer surface of the upper portion of the barrier layer is coplanar with the outer surface of the upper portion of the conductive layer.

5. The semiconductor device according to claim 4, further comprising: a first interlayer insulating layer extending around a lower portion of the barrier layer and a lower portion of the conductive layer; as well as a second interlayer insulating layer extending around an upper portion of the barrier layer and an upper portion of the conductive layer, The outer surface of the upper portion of the barrier layer and the outer surface of the upper portion of the conductive layer are in contact with the second interlayer insulating layer.

6. The semiconductor device according to claim 5, wherein: The upper portion of the barrier layer includes a connection surface between an outer side surface of the upper portion of the barrier layer and an outer side surface of the lower portion of the barrier layer, and The connection surface is in contact with an upper surface of the first interlayer insulating layer.

7. The semiconductor device according to claim 5, wherein: An angle between an outer side surface of an upper portion of the barrier layer and a lower surface of the second interlayer insulating layer is an obtuse angle, and Wherein, an angle between an outer surface of a lower portion of the barrier layer and an upper surface of the first interlayer insulating layer is an obtuse angle.

8. The semiconductor device according to claim 1, further comprising: a first interlayer insulating layer extending around a lower portion of the conductive structure; as well as a second interlayer insulating layer extending around an upper portion of the conductive structure, The angle between the outer surface of the lower portion of the conductive structure and the upper surface of the first interlayer insulating layer is an obtuse angle, and Wherein, an angle between an outer surface of an upper portion of the conductive structure and a lower surface of the second interlayer insulating layer is an obtuse angle.

9. The semiconductor device according to claim 8, further comprising a second conductive line in contact with an upper surface of the first interlayer insulating layer, in, The second interlayer insulating layer extends around the second conductive line, and The width of the second conductive line increases as the distance between the second conductive line and the upper surface of the first conductive line decreases.

10. A semiconductor device comprising: a first interlayer insulating layer; an etch stop layer, which is located on the first interlayer insulating layer; a second interlayer insulating layer, which is located on the etching stop layer; a third interlayer insulating layer, which is located on the second interlayer insulating layer; first conductive lines spaced apart from each other and extending in the first interlayer insulating layer; as well as a conductive structure extending in the second interlayer insulating layer, the third interlayer insulating layer and the etching stop layer and contacting an upper surface of the first conductive line, wherein the first interlayer insulating layer includes a middle portion between the first conductive lines, wherein the upper surface of the first conductive line is coplanar with the upper surface of the middle portion, and The lower surface of the conductive structure contacts the upper surface of the first conductive line and the upper surface of the middle portion.

11. The semiconductor device according to claim 10, wherein: The lower surface of the conductive structure is flat.

12. The semiconductor device according to claim 10, wherein: The width of the lower surface of the conductive structure is greater than the sum of the width of the upper surface of the first conductive line and the width of the upper surface of the middle portion.

13. The semiconductor device according to claim 10, wherein: The conductive structure includes a lower portion of the conductive structure and an upper portion of the conductive structure, wherein the second interlayer insulating layer extends around the lower portion of the conductive structure, wherein the third interlayer insulating layer extends around the upper portion of the conductive structure, The width of the lower portion of the conductive structure decreases as the distance between the lower portion of the conductive structure and the upper surface of the first conductive line decreases, and The width of the upper portion of the conductive structure increases as the distance between the upper portion of the conductive structure and the upper surface of the first conductive line decreases.

14. The semiconductor device according to claim 10, further comprising: source / drain patterns spaced apart from each other; a channel structure located between the source / drain patterns; as well as a gate electrode overlapping the channel structure, Wherein, the channel structure includes semiconductor patterns overlapping each other, wherein the gate electrode includes an electrode portion between the semiconductor patterns, and Each of the first conductive lines is electrically connected to a corresponding one of the source / drain patterns or the gate electrode.

15. The semiconductor device according to claim 10, wherein: The conductive structure includes an upper portion of the conductive structure and a lower portion of the conductive structure, The upper portion of the conductive structure contacts the side surface of the third interlayer insulating layer. wherein the lower portion of the conductive structure contacts the side surface of the second interlayer insulating layer, wherein the third interlayer insulating layer includes a filling portion protruding toward the second interlayer insulating layer and a lower portion of the conductive structure, wherein the second interlayer insulating layer includes a first curved surface in contact with the filling portion, and The lower portion of the conductive structure includes a second curved surface in contact with the filling portion.

16. The semiconductor device according to claim 15, wherein: The filling portion is located between the lower portion of the conductive structure and the second interlayer insulating layer, and Wherein, the second curved surface is connected to an outer side surface of an upper portion of the conductive structure.

17. The semiconductor device according to claim 10, wherein: The conductive structure comprises a barrier layer and a conductive layer, wherein the barrier layer is in contact with the first interlayer insulating layer, the etching stop layer and the second interlayer insulating layer, Wherein, the conductive layer is located on the barrier layer, wherein the conductive layer is separated from the first interlayer insulating layer, the etching stop layer and the second interlayer insulating layer via the barrier layer, and Wherein, the conductive layer contacts the upper surface of the first conductive line.

18. The semiconductor device according to claim 17, wherein: The conductive layer includes a penetrating portion extending in the barrier layer, and The penetration portions are in contact with upper surfaces of the first conductive lines respectively.

19. The semiconductor device according to claim 10, wherein: The conductive structure comprises: a barrier layer in contact with an upper surface of the first conductive line; A first conductive layer located on the barrier layer; and a second conductive layer in contact with an upper surface of the barrier layer and an upper surface of the first conductive layer, The first conductive layer includes a first conductive material, and the second conductive layer includes a second conductive material different from the first conductive material.

20. A semiconductor device comprising: a substrate including an active pattern; a source / drain pattern located on the active pattern; a channel structure located between the source / drain patterns; a gate electrode overlapping the channel structure; an active contact located on each of the source / drain patterns; a covering insulating layer, which is located on the active contact; a first etch stop layer located on the capping insulating layer; a first interlayer insulating layer, which is located on the first etch stop layer; first conductive lines spaced apart from each other and extending in the first etch stop layer and the first interlayer insulating layer; a second etching stop layer, which is located on the first interlayer insulating layer and the first conductive line; a second interlayer insulating layer, which is located on the second etch stop layer; a third interlayer insulating layer, which is located on the second interlayer insulating layer; as well as a conductive structure that contacts an upper surface of the first conductive line and extends in the second etch stop layer, the second interlayer insulating layer, and the third interlayer insulating layer, wherein each of the first conductive lines is electrically connected to the active contact or the gate electrode, Wherein, the conductive structure comprises a barrier layer and a conductive layer on the barrier layer, wherein the outer surface of the barrier layer contacts the second interlayer insulating layer, and Wherein, the outer surface of the conductive layer is in contact with the third interlayer insulating layer.

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