Semiconductor device

Abstract

The invention relates to a semiconductor device. Provided is a highly productive semiconductor device capable of obtaining good characteristics for transistors having different characteristics. The semiconductor device includes: a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a first gate insulating layer between the first semiconductor layer and the first gate electrode; a first insulating layer provided above the first gate electrode; a first electrode provided in a region overlapping the first semiconductor layer in plan view and electrically connected to the first semiconductor layer; a second semiconductor layer made of a material different from that of the first semiconductor layer; a second gate electrode facing the second semiconductor layer; a second gate insulating layer between the second semiconductor layer and the second gate electrode; a second electrode provided in a region overlapping the second semiconductor layer in plan view and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices that use transistors of different semiconductor materials as semiconductor layers formed on the same substrate has been advancing. For example, transistors using silicon are used for transistors that require high-speed operation, and transistors using oxide semiconductors are used for transistors that require switching operation. This allows transistors with different characteristics corresponding to the required functions to be formed on the same substrate.

[0003] Patent Document 1 discloses a display device in which transistors using silicon are formed in a driver circuit and transistors using oxide semiconductor are formed in a display region on the same substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-128693 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In one embodiment of the present invention, one of its objects is to provide a semiconductor device with high productivity that can obtain good characteristics for transistors with different characteristics.

[0009] Means for solving problems

[0010] A semiconductor device according to one embodiment of the present invention comprises: a first semiconductor layer; a first gate electrode opposite to the first semiconductor layer; a first gate insulating layer between the first semiconductor layer and the first gate electrode; a first insulating layer arranged above the first gate electrode; a first electrode arranged in a region overlapping with the first semiconductor layer when viewed from above and electrically connected to the first semiconductor layer; a second semiconductor layer composed of a material different from that of the first semiconductor layer; a second gate electrode opposite to the second semiconductor layer; a second gate insulating layer between the second semiconductor layer and the second gate electrode; a second electrode arranged in a region overlapping with the second semiconductor layer when viewed from above and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a top view illustrating a semiconductor device according to one embodiment of the present invention.

[0012] Figure 2 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0013] Figure 3 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0014] Figure 4 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0015] Figure 5 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0016] Figure 6 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0017] Figure 7 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0018] Figure 8 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0019] Fig. 9 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] Fig.10 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] Fig.11 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] Fig.12 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0023] Fig.13 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0024] Fig.14 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0025] Fig.15 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] Fig.16 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0027] Fig.17 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] Fig.18 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] Fig.19 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] Fig. 20 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0031] Description of Reference Numerals

[0032] 100: semiconductor device, 101: substrate, 110: transistor, 111: semiconductor layer, 111a: channel region, 111b, 111c: low-concentration impurity region, 111d: source region, 111e: drain region, 112: gate insulating layer, 113: gate electrode, 114: interlayer insulating layer, 115a, 115b, 115c: opening, 116: interlayer insulating layer, 117a: source electrode, 117b: drain electrode, 118: metal nitride material layer, 119: wiring, 120: transistor, 121: oxide semiconductor layer, 121a: channel region, 121d: source region, 121e: drain region, 122: gate insulating layer, 123: gate electrode, 124: metal nitride layer, 125: conductive layer, 125a, 125c: source electrode, 125b, 125d: drain electrode, 126: interlayer insulating layer, 127d, 127e: opening, 128: gate electrode, 129: gate insulating layer DETAILED DESCRIPTION

[0033] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is exemplary only. While maintaining the gist of the invention, the configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment is certainly included in the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically represent the width, thickness, shape, etc. of each part compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same configuration as that described above with respect to the existing figure, and the detailed description is sometimes appropriately omitted.

[0034] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. On the contrary, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the above or below phrases are used for explanation, but for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a different direction than that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is merely an explanation of the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure formed by stacking a plurality of layers, and in the case of a pixel electrode above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, when expressed as a pixel electrode vertically above a transistor, it refers to a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0035] In the present specification, the term "film" and the term "layer" can be used interchangeably depending on circumstances.

[0036] The so-called "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as polarization components, backlights, touch panels, etc.) are installed on the display unit. In the "electro-optical layer", as long as there is no technical contradiction, a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer may be included. Therefore, in the embodiments described below, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0037] In this specification, the expressions such as “α includes A, B or C”, “α includes any one of A, B and C”, and “α includes one selected from the group consisting of A, B and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. In addition, these expressions do not exclude the case where α includes other elements.

[0038] In addition, the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0039] [1. First embodiment]

[0040] Reference Figure 1 to Figure 6 An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described.

[0041] [1-1. Configuration of semiconductor device]

[0042] Figure 1 1 is a top view of a semiconductor device 100 according to an embodiment of the present invention. Figure 2 Yes Figure 1 The semiconductor device 100 shown in FIG. 1 is a cross-sectional view when cut along line A1-A2. Figure 1 and Figure 2 As shown, a semiconductor device 100 according to one embodiment of the present invention includes a transistor 110 provided on a substrate 101 and a transistor 120 provided above the transistor 110 .

[0043] The transistor 110 includes a semiconductor layer 111 , a gate insulating layer 112 , and a gate electrode 113 .

[0044] Either an N-type transistor or a P-type transistor can be used as the transistor 110. In this embodiment, an example in which a top-gate N-type transistor using polycrystalline silicon for a semiconductor layer is used as the transistor 110 will be described.

[0045] The semiconductor layer 111 in the N-type transistor has a channel region 111a, a source region 111d, a drain region 111e, and low-concentration impurity regions 111b and 111c. The low-concentration impurity region 111b is provided between the channel region 111a and the source region 111d. The low-concentration impurity region 111c is provided between the channel region 111a and the drain region 111e. The source and the drain can be interchanged according to the operation of the transistor 110. That is, the region 111d can also function as a drain region, and the region 111e can also function as a source region.

[0046] The semiconductor layer 111 in the channel region 111a has semiconductor properties. That is, the semiconductor layer 111 in the channel region 111a switches between a state in which it functions as a current path and a state in which it does not function as a current path according to the voltage applied to the gate electrode 113. The carrier concentration in the semiconductor layer 111 in the source region 111d and the drain region 111e is greater than the carrier concentration in the semiconductor layer 111 in the channel region 111a.

[0047] Interlayer insulating layers 114 and 116 are provided on the transistor 110. A source electrode 117a and a drain electrode 117b are provided on the interlayer insulating layers 114 and 116. The source electrode 117a and the drain electrode 117b are connected to the source region 111d and the drain region 111e via openings 115a and 115b provided in the interlayer insulating layers 114 and 116.

[0048] The transistor 120 is provided in a region different from the region where the transistor 110 is provided. The transistor 120 includes an oxide semiconductor layer 121, a gate insulating layer 122, a gate electrode 123, a gate electrode 128, and a gate insulating layer 129. An interlayer insulating layer 126 is provided over the gate electrode 123. The oxide semiconductor layer 121 is polycrystalline, and details thereof will be described later.

[0049] The gate electrode 128 is provided between the gate insulating layer 112 and the interlayer insulating layer 114. The gate electrode 128 is provided in a region overlapping with the oxide semiconductor layer 121 (particularly the channel region 121a) in a plan view. A wiring 119 is provided on the interlayer insulating layers 114 and 116. The wiring 119 is connected to the gate electrode 128 through an opening 115c provided in each of the interlayer insulating layers 114 and 116. The wiring 119 is in the same layer as the source electrode 117a and the drain electrode 117b. In other words, the wiring 119 is in contact with the interlayer insulating layer 116 in the same manner as the source electrode 117a and the drain electrode 117b.

[0050] The oxide semiconductor layer 121 includes a channel region 121 a , a source region 121 d , and a drain region 121 e . The source region 121 d and the drain region 121 e are adjacent to the channel region 121 a . The channel region 121 a overlaps with the gate electrode 123 in a plan view.

[0051] The oxide semiconductor layer 121 in the channel region 121a has semiconductor properties. That is, the oxide semiconductor layer 121 in the channel region 121a switches between a state in which it functions as a current path and a state in which it does not function as a current path, depending on the voltage applied to the gate electrodes 123 and 128. The carrier concentration in the oxide semiconductor layer 121 in the source region 121d and the drain region 121e is greater than the carrier concentration in the oxide semiconductor layer 121 in the channel region 121a.

[0052] For example, the sheet resistance of the oxide semiconductor layer 121 of the source region 121d and the drain region 121e is 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less. In other words, the oxide semiconductor layer 121 of the channel region 121a has a higher resistivity (or lower conductivity) than the oxide semiconductor layer 121 of each of the source region 121d and the drain region 121e.

[0053] A voltage for controlling the channel region 121a is supplied to the gate electrodes 123 and 128, respectively. That is, in this embodiment, a dual-gate transistor using an N-type oxide semiconductor is exemplified as the transistor 120. However, the transistor 120 may be a bottom-gate transistor having only the gate electrode 128 or a top-gate transistor having only the gate electrode 123.

[0054] The gate insulating layer 122 and the interlayer insulating layer 126 are provided with respective openings 127d and 127e that reach the source region 121d and the drain region 121e of the oxide semiconductor layer 121. Metal nitride layers 124c and 124d are provided inside the opening 127d, inside the opening 127e, and on the source region 121d and the drain region 121e. The metal nitride layers 124c and 124d are in contact with the upper surface of the oxide semiconductor layer 121 and the upper surface of the interlayer insulating layer 126. A source electrode 125c and a drain electrode 125d are provided inside the opening 127d, inside the opening 127e, and on the metal nitride layers 124c and 124d.

[0055] Regarding the above-mentioned structure, the semiconductor layer 111 is sometimes referred to as the “first semiconductor layer”, the gate electrode 113 is sometimes referred to as the “first gate electrode”, the gate insulating layer 112 is sometimes referred to as the “first gate insulating layer”, the interlayer insulating layer 114 is sometimes referred to as the “first insulating layer”, and the source electrode 117a and the drain electrode 117b are sometimes referred to as the “first electrode”. Similarly, the oxide semiconductor layer 121 is sometimes referred to as the “second semiconductor layer”, the gate electrode 123 is sometimes referred to as the “second gate electrode”, the gate insulating layer 122 is sometimes referred to as the “second gate insulating layer”, the gate electrode 128 is sometimes referred to as the “third gate electrode”, the gate insulating layer 129 is sometimes referred to as the “third gate insulating layer”, the metal nitride layers 124c and 124d are sometimes referred to as the “first metal nitride layer”, and the source electrode 125c and the drain electrode 125d are sometimes referred to as the “second electrode”. Similarly, the interlayer insulating layer 116 is sometimes referred to as the “second insulating layer”. On the other hand, unlike the above, the gate electrode 123 may be called the "third gate electrode", the gate insulating layer 122 may be called the "third gate insulating layer", the gate electrode 128 may be called the "second gate electrode", and the gate insulating layer 129 may be called the "second gate insulating layer".

[0056] In the case of the above description, the structure of the semiconductor device 100 can be expressed as follows. The first gate electrode (gate electrode 113) is opposite to the first semiconductor layer (semiconductor layer 111). The first gate insulating layer (gate insulating layer 112) exists between the first semiconductor layer (semiconductor layer 111) and the first gate electrode (gate electrode 113). The first insulating layer (interlayer insulating layer 114) is provided above the first gate electrode (gate electrode 113). The first electrode (source electrode 117a and drain electrode 117b) is provided in a region overlapping with the first semiconductor layer (semiconductor layer 111) in a plan view, and is electrically connected to the first semiconductor layer (semiconductor layer 111). The second semiconductor layer (oxide semiconductor layer 121) is composed of a material different from that of the first semiconductor layer (semiconductor layer 111). The second semiconductor layer (oxide semiconductor layer 121) is provided above the first insulating layer (interlayer insulating layer 114). The second gate electrode (gate electrode 123) is opposite to the second semiconductor layer (oxide semiconductor layer 121) below the second semiconductor layer (oxide semiconductor layer 121). The second gate insulating layer (gate insulating layer 122) exists between the second semiconductor layer (oxide semiconductor layer 121) and the second gate electrode (gate electrode 123). The second electrode (source electrode 125c and drain electrode 125d) is provided in a region overlapping with the second semiconductor layer (oxide semiconductor layer 121) in a plan view and is electrically connected to the second semiconductor layer (oxide semiconductor layer 121). The first metal nitride layer (metal nitride layers 124c, 124d) exists between the second semiconductor layer (oxide semiconductor layer 121) and the second electrode (source electrode 125c and drain electrode 125d).

[0057] Similarly, the structure of the semiconductor device 100 can also be expressed as follows. The first metal nitride layer (metal nitride layers 124c, 124d) is in contact with the second semiconductor layer (oxide semiconductor layer 121). The second insulating layer (interlayer insulating layer 116) is provided above the first insulating layer (interlayer insulating layer 114). The third gate electrode (gate electrode 128) is opposite to the second semiconductor layer (oxide semiconductor layer 121) below the first insulating layer (interlayer insulating layer 114). The third gate insulating layer (gate insulating layer 129) exists between the second semiconductor layer (oxide semiconductor layer 121) and the third gate electrode (gate electrode 128). The second gate electrode (gate electrode 123) is provided above the second insulating layer (interlayer insulating layer 116). The first insulating layer (interlayer insulating layer 114) and the second insulating layer (interlayer insulating layer 116) are provided with openings 115a and 115b, respectively. The first electrode (source electrode 117a and drain electrode 117b) is provided above the second insulating layer (interlayer insulating layer 116) and inside the openings 115a and 115b. The first electrode (source electrode 117a and drain electrode 117b) and the second gate electrode (gate electrode 123) are in the same layer.

[0058] In the past, when a transistor using polysilicon and a transistor using an oxide semiconductor are formed on the same substrate, the following problems have arisen. When the oxide semiconductor is processed into a desired shape, and when a conductive layer in contact with the oxide semiconductor is processed, damage sometimes occurs on the surface of the oxide semiconductor. The oxide semiconductor in the damaged area contains a large number of oxygen vacancies. When oxygen vacancies are generated in the oxide semiconductor, the off-state leakage current of the transistor increases. In order to solve this problem, it is necessary to fully introduce oxygen into the oxide semiconductor by heat treatment. However, through this heat treatment, the source electrode and the drain electrode react with the oxide semiconductor, and the problem of reduced on-state current of the transistor occurs. Therefore, in one embodiment of the present invention, a metal nitride layer is provided between the oxide semiconductor layer and the source electrode and between the oxide semiconductor layer and the drain electrode. The reaction between the oxide semiconductor and the electrode caused by the heat treatment is suppressed by the metal nitride layer.

[0059] On the other hand, when a metal nitride layer is provided between the polysilicon and the source electrode and between the polysilicon and the drain electrode, nitrogen is injected into the polysilicon when the metal nitride layer is formed. As a result, the contact resistance between the source electrode and the drain electrode and the polysilicon separated by the metal nitride layer increases. In one embodiment of the present invention, a structure in which a metal nitride layer is provided only in a transistor using an oxide semiconductor is illustrated. That is, the polysilicon is in direct contact with the source electrode and the drain electrode without passing through the metal nitride layer. On the other hand, the oxide semiconductor is connected to the source electrode and the drain electrode through the metal nitride layer. As a result, good characteristics can be obtained in each transistor.

[0060] [1-2. Materials of Components of Semiconductor Device 100]

[0061] As the substrate 101, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 101 needs to be flexible, a substrate containing resin such as a polyimide substrate, an acrylic substrate, a siloxane-based substrate, or a fluororesin substrate can be used as the substrate 101. When a substrate containing resin is used as the substrate 101, impurities can also be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 101. In particular, when the semiconductor device 100 is a top emission type display, since the substrate 101 does not need to be transparent, impurities that deteriorate the transparency of the substrate 101 can also be used. When the semiconductor device 100 is used in an integrated circuit of a non-display device, as the substrate 101, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, or other substrates that are not light-transmitting can be used.

[0062] As the semiconductor layer 111 , for example, low-temperature polysilicon, amorphous silicon, or single crystal silicon is used.

[0063] As the conductive layer including the gate electrode 113, the source electrode 117a, the drain electrode 117b, the wiring 119, the gate electrodes 123 and 128, the source electrode 125c, and the drain electrode 125d, a general metal material can be used. For example, as the above-mentioned components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. As the above-mentioned conductive layer, the above-mentioned materials can be used as a single layer or as a stacked layer.

[0064] A general insulating material is used as the insulating layer including the gate insulating layer 112, the interlayer insulating layers 114, 116, and 126, and the gate insulating layers 122 and 129. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ), aluminum nitride (AlN x O y ) and other inorganic insulating layers.

[0065] As the interlayer insulating layer 126, an insulating layer having a function of releasing oxygen by heat treatment can be used. That is, an oxide insulating layer containing an excessive amount of oxygen can be used as the interlayer insulating layer 126. The temperature of the heat treatment for releasing oxygen from the interlayer insulating layer 126 is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the interlayer insulating layer 126 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 100 when, for example, a glass substrate is used as the substrate 101.

[0066] As the gate insulating layers 112, 122, and 129, an insulating layer with few defects can be used. For example, when the composition ratio of oxygen in the gate insulating layers 112, 122, and 129 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layers 112, 122, and 129 (hereinafter referred to as "other insulating layers"), the composition ratio of oxygen in the gate insulating layers 112, 122, and 129 is closer to the stoichiometric ratio of the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layers 112, 122, and 129 and the interlayer insulating layer 126, the composition ratio of oxygen in the silicon oxide used as the gate insulating layers 112, 122, and 129 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the interlayer insulating layer 126. For example, as the gate insulating layers 112, 122, and 129, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) may be used.

[0067] The above SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio less than that of nitrogen (x>y).

[0068] As the oxide semiconductor layer 121, a metal oxide having semiconductor properties can be used. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) can also be used as the oxide semiconductor layer 121. For example, as the oxide semiconductor layer 121, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can also be used. However, the oxide semiconductor containing In, Ga, Zn and O used in this embodiment is not limited to the above-mentioned components. As the oxide semiconductor, an oxide semiconductor of a composition different from that described above can be used. For example, in order to improve mobility, an oxide semiconductor layer having an In ratio greater than that described above can also be used. On the other hand, in order to increase the band gap and reduce the influence of light irradiation, an oxide semiconductor layer having a Ga ratio greater than that described above can also be used.

[0069] As the oxide semiconductor layer 121, an oxide semiconductor containing two or more metals including indium (In) may also be used. In this case, in the oxide semiconductor layer 121, the ratio of the indium element to all metal elements may be 50% or more in terms of atomic ratio. As the oxide semiconductor layer 121, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr) or lanthanide elements may also be used. As the oxide semiconductor layer 121, other elements other than the above may also be used.

[0070] As the oxide semiconductor layer 121, other elements may be added to the oxide semiconductor containing In, Ga, Zn and O. For example, metal elements such as Al and Sn may be added. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn and Zn (ITZO), an oxide semiconductor containing In and W, etc. may be used as the oxide semiconductor layer 121.

[0071] When the ratio of the indium element is large, the oxide semiconductor layer 121 is easily crystallized. As described above, in the oxide semiconductor layer 121, by using a material in which the ratio of the indium element to all metal elements is 50% or more, an oxide semiconductor layer 121 having a polycrystalline structure can be obtained. The oxide semiconductor layer 121 preferably contains gallium as another metal element other than indium. Gallium and indium both belong to the 13th group element. Therefore, the crystallinity of the oxide semiconductor layer 121 is not hindered by gallium, and the oxide semiconductor layer 121 has a polycrystalline structure.

[0072] The detailed manufacturing method of the oxide semiconductor layer 121 is described later, and the oxide semiconductor layer 121 can be formed using a sputtering method. The composition of the oxide semiconductor layer 121 formed by the sputtering method depends on the composition of the sputtering target. Even in the case where the oxide semiconductor layer 121 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 121 are roughly the same. In this case, the composition of the metal element of the oxide semiconductor layer 121 can be determined based on the composition of the metal element of the sputtering target.

[0073] In the case where the oxide semiconductor layer 121 has a polycrystalline structure, the composition of the oxide semiconductor layer can also be determined by an X-ray diffraction (XRD) method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method, the composition of the metal elements of the oxide semiconductor layer can be determined. Furthermore, the composition of the metal elements of the oxide semiconductor layer 121 can also be determined by fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. However, the oxygen element contained in the oxide semiconductor layer 121 varies depending on the process conditions of sputtering, etc., and therefore sometimes cannot be determined by these methods.

[0074] As described above, the oxide semiconductor layer 121 may include an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure may be prepared using the Poly-OS (Poly-crystalline Oxide Semiconductor; polycrystalline oxide semiconductor) technology described later. In the following description, when distinguishing from an oxide semiconductor having an amorphous structure, an oxide semiconductor having a polycrystalline structure is sometimes described as Poly-OS for description.

[0075] Note that a semiconductor other than an oxide semiconductor may be used instead of the oxide semiconductor layer 121. In this case, the semiconductor used instead of the oxide semiconductor is formed of a material or a composition different from that of the semiconductor used for the semiconductor layer 111. That is, the transistor 110 has characteristics different from those of the transistor 120.

[0076] A metal oxide layer may be provided between the gate insulating layer 129 and the oxide semiconductor layer 121. In this case, the metal oxide layer may also be in contact with the oxide semiconductor layer 121. As the metal oxide layer, a metal oxide containing aluminum as a main component is used. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN xO y ) and other inorganic insulating layers. “Metal oxide layer with aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer can be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio can be a mass ratio or a weight ratio.

[0077] As the metal nitride layers 124c and 124d, nitrides of general metal materials can be used. For example, as the metal nitride layers 124c and 124d, titanium nitride, molybdenum nitride, tungsten nitride, and tantalum nitride can be used. The metal nitride layers 124c and 124d contain the same metal element as the metal element contained in the source electrode 125c and the drain electrode 125d. For example, when the structure of the source electrode 125c and the drain electrode 125d is Al / Ti (upper layer / lower layer), the metal nitride layers 124c and 124d can also be titanium nitride.

[0078] At this time, the lower layer (Ti) contained in the source electrode 125c and the drain electrode 125d (the second electrode) is sometimes referred to as the "first conductive layer", and the upper layer (Al) thereof is referred to as the "second conductive layer". In the case of the above-mentioned description, the structure of the semiconductor device 100 can be expressed as follows. The second electrode (the source electrode 125c and the drain electrode 125d) includes the first conductive layer (Ti) and the second conductive layer (Al) on the first conductive layer (Ti). The first conductive layer (Ti) is in contact with the first metal nitride layer (metal nitride layers 124c, 124d). The first metal nitride layer (metal nitride layers 124c, 124d) (for example, TiN) includes the same metal element as the metal element contained in the first conductive layer (Ti).

[0079] [1-3.Poly-OS technology]

[0080] The Poly-OS included in the oxide semiconductor layer is formed by sputtering and heat treatment. Here, the method for forming the oxide semiconductor layer is described.

[0081] First, an oxide semiconductor layer is formed by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, an amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an oxide semiconductor layer having an amorphous structure is observed using an XRD method, no specific peak based on a crystal structure is obtained in the diffraction pattern. An oxide semiconductor layer having an amorphous structure sometimes has a short-range ordered structure in a tiny region. However, such an oxide semiconductor layer does not show the characteristics of Poly-OS and can therefore be classified as an oxide semiconductor layer having an amorphous structure.

[0082] In the Poly-OS technology, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate during the formation of the oxide semiconductor layer is high, microcrystals are easily generated in the formed oxide semiconductor. The oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and further preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excess oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor layer becomes uneven, and an oxide semiconductor layer containing a large number of microcrystals is formed, or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0083] Next, the oxide semiconductor layer formed by sputtering is heat treated. The heat treatment is performed in the air, but the atmosphere of the heat treatment is not limited thereto. The temperature of the heat treatment is 300°C to 500°C, preferably 350°C to 450°C. The time of the heat treatment is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized to form an oxide semiconductor layer containing Poly-OS.

[0084] [1-4. Characteristics of Oxide Semiconductor Layer 121]

[0085] Next, characteristics of an oxide semiconductor layer including Poly-OS used as the oxide semiconductor layer 121 are described below.

[0086] The oxide semiconductor layer has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer in etching using an etchant for wet etching is very small. This means that the oxide semiconductor layer is hardly etched by the etchant. When the oxide semiconductor layer is etched using an etchant containing phosphoric acid as a main component at a temperature of about 40°C, the etching rate is less than 3nm / min, less than 2nm / min or less than 1nm / min. The proportion of phosphoric acid in the etchant is greater than 50%, greater than 60% or greater than 70%. In addition to phosphoric acid, nitric acid and acetic acid may also be contained in the etchant. The above-mentioned temperature of about 40°C is the set temperature of the device for maintaining the etchant, and the actual temperature of the etchant is greater than 35°C and less than 45°C.

[0087] On the other hand, for an oxide semiconductor layer not including Poly-OS, for example, an oxide semiconductor layer having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor layer is etched at a temperature of about 40° C. using an etchant containing phosphoric acid as a main component is greater than 100 nm / min.

[0088] When etching the oxide semiconductor layer including Poly-OS using a 0.5% hydrofluoric acid solution at room temperature (e.g., about 22°C), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Here, room temperature refers to 25°C ± 5°C. The actual temperature of the etching solution at this time is 20°C to 30°C.

[0089] On the other hand, when the oxide semiconductor layer not containing Poly-OS was etched using a 0.5% hydrofluoric acid solution at room temperature, the etching rate was 15 nm / min or more.

[0090] Here, an embodiment of an oxide semiconductor layer is shown in Table 1. In Table 1, the etching rates in a mixed acid etching solution and a 0.5% hydrofluoric acid solution are shown for each sample produced. As a mixed acid etching solution, "Mixed Acid AT-2F (product name)" of LASA Industries, Ltd. was used. The proportion of phosphoric acid in the mixed acid etching solution was about 65%. When each sample was etched, the temperature of the mixed acid etching solution was about 40°C, and the temperature of the 0.5% hydrofluoric acid solution was room temperature. In Table 1, Sample 1 is an oxide semiconductor layer containing Poly-OS, Sample 2 is an oxide semiconductor layer having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor layer of indium gallium zinc oxide (IGZO) containing an indium ratio of less than 50%.

[0091] [Table 1]

[0092] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0093] As shown in Table 1, sample 1 (an oxide semiconductor layer containing Poly-OS) is hardly etched by the mixed acid etching solution, and is only etched at 2 nm / min even when a 0.5% hydrofluoric acid solution is used. In the mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 2 (an oxide semiconductor layer having an amorphous structure before heat treatment). In a 0.5% hydrofluoric acid solution, the etching rate of sample 1 is less than about 1 / 10 of the etching rate of sample 2. In the mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 3 (an oxide semiconductor layer containing IGZO having an indium ratio of less than 50%). That is, compared with samples 2 and 3, the etching resistance of sample 1 is greatly superior.

[0094] The excellent etching resistance of the oxide semiconductor layer containing Poly-OS is a property that cannot be obtained by oxide semiconductors with a polycrystalline structure manufactured by conventional processes below 500° C. The detailed mechanism of the excellent etching resistance of the oxide semiconductor layer containing Poly-OS is not yet clear, but it is believed that Poly-OS has a polycrystalline structure different from the conventional one.

[0095] As described above, the etching rate of the oxide semiconductor layer containing Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layer. Therefore, in the case of forming an island-shaped oxide semiconductor layer, the oxide semiconductor layer having an amorphous structure before the heat treatment is patterned into an island shape, and then, by performing the heat treatment, the oxide semiconductor layer patterned into an island shape is crystallized. Thus, an island-shaped oxide semiconductor layer containing Poly-OS is formed.

[0096] [1-5. Method for Manufacturing Semiconductor Device 100]

[0097] Reference Figure 3 to Figure 6 A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Figure 3 to Figure 6 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0098] like Figure 3 As shown, first, a semiconductor layer made of polycrystalline silicon is formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 111. Then, a gate insulating layer 112 is formed on the substrate 101 and the semiconductor layer 111. Next, a conductive layer is formed on the gate insulating layer 112, and the conductive layer is processed by a photolithography process to form a gate electrode 113 overlapping the semiconductor layer 111 and a gate electrode 128 included in the transistor 120.

[0099] Next, using the gate electrode 113 as a mask, impurities are injected into the semiconductor layer 111 through the gate insulating layer 112. By injecting impurities, a channel region 111a and other impurity regions are formed. Then, using a resist or the like, a mask covering the channel region 111a and the regions corresponding to the low-concentration impurity regions 111b and 111c is formed, and additional impurities are injected. By injecting additional impurities, a source region 111d and a drain region 111e are formed in the regions adjacent to the low-concentration impurity regions 111b and 111c. The low-concentration impurity regions 111b and 111c may also be omitted. In this case, the channel region 111a is adjacent to the source region 111d and the drain region 111e.

[0100] Next, an interlayer insulating layer 114 is formed over the gate insulating layer 112 and the gate electrodes 113 and 128. Next, an oxide semiconductor layer is formed over the interlayer insulating layer 114, and the semiconductor layer is processed by a photolithography process to form an oxide semiconductor layer 121. Then, an insulating layer is formed over the interlayer insulating layer 114 and the oxide semiconductor layer 121. This insulating layer functions as the interlayer insulating layer 116 in the transistor 110 and as the gate insulating layer 122 in the transistor 120.

[0101] like Figure 4 As shown, the gate insulating layer 112 and the interlayer insulating layers 114 and 116 are processed by a photolithography process, thereby forming openings 115a and 115b that reach the source region 111d and the drain region 111e of the semiconductor layer 111, and an opening 115c that reaches the gate electrode 128. Next, a conductive layer is formed on the interlayer insulating layer 116 and inside the openings 115a, 115b, and 115c. The formed conductive layer is processed by a photolithography process to form a source electrode 117a, a drain electrode 117b, a wiring 119, and a gate electrode 123.

[0102] Next, using the gate electrode 123 as a mask, impurities are implanted into the oxide semiconductor layer 121 via the gate insulating layer 122. The implantation of impurities forms a channel region 121a, a source region 121d, and a drain region 121e. The details of the method for forming the source region 121d and the drain region 121e will be described later.

[0103] like Figure 5 As shown, an interlayer insulating layer 126 covering the source electrode 117a, the drain electrode 117b, the wiring 119, and the gate 123 is formed on the interlayer insulating layer 116. The interlayer insulating layers 116 and 126 are processed by a photolithography process to form openings 127d and 127e reaching the source region 121d and the drain region 121e of the oxide semiconductor layer 121.

[0104] like Figure 6 As shown in FIG. 1 , a metal nitride layer 124 and a conductive layer 125 are formed on the interlayer insulating layer 126 and inside the openings 127d and 127e. The formed metal nitride layer 124 and the conductive layer 125 are processed by a photolithography process to form Figure 2 The metal nitride layers 124c, 124d, the source electrode 125c and the drain electrode 125d are shown.

[0105] As described above, the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, so that the contact resistance can be suppressed. Furthermore, the semiconductor layer 111 is in contact with the source electrode 117a and the drain electrode 117b without the metal nitride layer, so that the contact resistance can be suppressed.

[0106] [1-6. Method for Forming Source Region 121d and Drain Region 121e]

[0107] use Figure 4 The method of forming the source region 121d and the drain region 121e is described below. Figure 4 As shown in FIG. 1 , in a state where a gate insulating layer 122 and a gate electrode 123 are formed over the oxide semiconductor layer 121, ion implantation is performed on the oxide semiconductor layer 121. For example, boron (B) is implanted as an impurity element into the oxide semiconductor layer 121 by ion implantation. However, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer 121 instead of boron.

[0108] In the region where the gate electrode 123 is not provided (the source region 121d and the drain region 121e), the impurity element passes through the gate insulating layer 122 and reaches the oxide semiconductor layer 121. However, in the region where the gate electrode 123 is provided (the channel region 121a), the impurity element is blocked by the gate electrode 123 and thus does not reach the oxide semiconductor layer 121.

[0109] By the above-mentioned ion implantation, a source region 121d and a drain region 121e implanted with impurity elements are formed in the oxide semiconductor layer 121. By the implantation of impurity elements, oxygen defects are formed in the oxide semiconductor layer 121 in the source region 121d and the drain region 121e. Therefore, the resistance of the oxide semiconductor layer 121 in the source region 121d and the drain region 121e is reduced. In the oxide semiconductor layer 121 including Poly-OS, the source region 121d and the drain region 121e implanted with impurity elements sometimes have crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structures of the source region 121d and the drain region 121e are respectively the same as the crystal structures of the channel region 121a.

[0110] [2. Second embodiment]

[0111] Reference Figure 7 to Figure 11 An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described.

[0112] [2-1. Configuration of semiconductor device]

[0113] Figure 7 and Figure 1 Similarly, this is a cross-sectional view of the semiconductor device 100 when it is cut along the line A1-A2. Figure 1 and Figure 7 As shown, a semiconductor device 100 according to one embodiment of the present invention includes a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110 .

[0114] Figure 7 The transistors 110 and 120 are configured as follows: Figure 2 The transistors 110 and 120 have the same structure, so the description is omitted. Figure 7 As shown, metal nitride layers 124a and 124b are provided on the interlayer insulating layer 126. A source electrode 125a and a drain electrode 125b are provided on the metal nitride layers 124a and 124b. The source electrode 125a and the drain electrode 125b are connected to the source region 111d and the drain region 111e via openings 115a and 115b provided in the interlayer insulating layers 114, 116, and 126. The metal nitride layers 124a and 124b are formed only on the upper surface of the interlayer insulating layer 126, and are not formed on the side walls of the openings 115a and 115b, the upper surface of the source region 111d, and the upper surface of the drain region 111e.

[0115] The metal nitride layers 124a and 124b can be made of the same material as that of the metal nitride layers 124c and 124d. The source electrode 125a and the drain electrode 125b can be made of the same material as that of the source electrode 125c and the drain electrode 125d.

[0116] Regarding the above-mentioned structure, the metal nitride layers 124a and 124b are sometimes referred to as "second metal nitride layers", and the source electrode 125a and the drain electrode 125b are sometimes referred to as "first electrodes". In the case of such a description, the structure of the above-mentioned semiconductor device 100 can be expressed as follows. The second insulating layer (interlayer insulating layer 116) is provided above the first insulating layer (interlayer insulating layer 114). Openings 115a and 115b are provided in each of the first insulating layer (interlayer insulating layer 114) and the second insulating layer (interlayer insulating layer 116). The first electrode (source electrode 125a and drain electrode 125b) are provided above the second insulating layer (interlayer insulating layer 116) and inside the openings 115a and 115b, and are in contact with the first semiconductor layer (semiconductor layer 111). The second metal nitride layer (metal nitride layers 124a and 124b) is provided above the second insulating layer (interlayer insulating layer 116) and between the second insulating layer (interlayer insulating layer 116) and the first electrode (source electrode 125a and drain electrode 125b).

[0117] [2-2. Method for Manufacturing Semiconductor Device 100]

[0118] Reference Figure 8 to Figure 11 A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Figure 8 to Figure 11 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0119] like Figure 8 As shown, first, a semiconductor layer made of polycrystalline silicon is formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 111. Then, a gate insulating layer 112 is formed on the substrate 101 and the semiconductor layer 111. Next, a conductive layer is formed on the gate insulating layer 112, and the conductive layer is processed by a photolithography process to form a gate electrode 113 overlapping with the semiconductor layer 111 and a gate electrode 128 included in the transistor 120.

[0120] Next, using the gate electrode 113 as a mask, impurities are injected into the semiconductor layer 111 through the gate insulating layer 112. By injecting impurities, a channel region 111a and other impurity regions are formed. Then, a mask covering the channel region 111a and the regions corresponding to the low-concentration impurity regions 111b and 111c is formed using a resist or the like, and additional impurities are injected. By injecting additional impurities, a source region 111d and a drain region 111e are formed in the regions adjacent to the low-concentration impurity regions 111b and 111c. The low-concentration impurity regions 111b and 111c may also be omitted. In this case, the channel region 111a is adjacent to the source region 111d and the drain region 111e.

[0121] Next, an interlayer insulating layer 114 is formed on the gate insulating layer 112 and the gate electrodes 113 and 128. Next, a semiconductor layer is formed on the interlayer insulating layer 114, and the semiconductor layer is processed by a photolithography process to form an oxide semiconductor layer 121. Then, an insulating layer is formed on the interlayer insulating layer 114 and on the oxide semiconductor layer 121. This insulating layer functions as the interlayer insulating layer 116 in the transistor 110 and as the gate insulating layer 122 in the transistor 120.

[0122] Next, the interlayer insulating layers 114 and 116 are processed by a photolithography process to form an opening 115c that reaches the gate electrode 128. Next, a conductive layer is formed on the interlayer insulating layer 116 and inside the opening 115c. The formed conductive layer is processed by a photolithography process to form the wiring 119 and the gate electrode 123.

[0123] like Fig. 9As shown, an interlayer insulating layer 126 is formed on the interlayer insulating layer 116, on the wiring 119, and on the gate electrode 123. The interlayer insulating layers 116 and 126 are processed by a photolithography step to form openings 127d and 127e reaching the source region 121d and the drain region 121e of the oxide semiconductor layer 121.

[0124] like Fig.10 As shown, first, a metal nitride layer 124 is formed on the interlayer insulating layer 126 and inside the openings 127d and 127e. The formed metal nitride layer 124, the gate insulating layer 112, and the interlayer insulating layers 114, 116, and 126 are processed by a photolithography process, thereby forming openings 115a and 115b that reach the source region 111d and the drain region 111e of the semiconductor layer 111.

[0125] like Fig.11 As shown in FIG. 1 , a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a and 115b. The formed conductive layer 125 is processed by a photolithography process, thereby forming Figure 7 The source electrode 125a and the drain electrode 125b are shown.

[0126] As described above, the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, so that the contact resistance can be suppressed. Furthermore, the semiconductor layer 111 is in contact with the source electrode 125a and the drain electrode 125b without the metal nitride layer, so that the contact resistance can be suppressed.

[0127] [3. Third embodiment]

[0128] Reference Figure 12 to Figure 15 An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described.

[0129] [3-1. Configuration of semiconductor device]

[0130] Fig.12 and Figure 1 Similarly, this is a cross-sectional view of the semiconductor device 100 when it is cut along the line A1-A2. Figure 1 and Fig.12 As shown, a semiconductor device 100 according to one embodiment of the present invention includes a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110 .

[0131] Fig.12 The transistor 110 shown is constructed in the same manner as Figure 7 The structure of transistor 110 shown is substantially the same. Figure 7 In the embodiment, the insulating layers provided between the semiconductor layer 111 and the source electrode 125a (and the drain electrode 125b) are the gate insulating layer 112 and the interlayer insulating layers 114, 116, and 126. Fig.12 In the embodiment, the insulating layer is the gate insulating layer 112 and the interlayer insulating layer 114. Fig.12 In the embodiment, the metal nitride layers 124 a and 124 b are in contact with the upper surface of the interlayer insulating layer 114 .

[0132] like Fig.12 As shown in FIG. 1 , a metal nitride layer 118 is provided on the interlayer insulating layer 114. A wiring 119 is provided on the metal nitride layer 118. The wiring 119 is connected to the gate electrode 128 via an opening 115c provided in the interlayer insulating layer 114. The metal nitride layer 118 is formed only on the upper surface of the interlayer insulating layer 114, and is not formed on the sidewall of the opening 115c and the upper surface of the gate electrode 128.

[0133] like Fig.12 As shown, an oxide semiconductor layer 121 is provided on a gate insulating layer 129. Metal nitride layers 124c and 124d are provided on the upper surface and side surfaces of the oxide semiconductor layer 121. A source electrode 125c and a drain electrode 125d are provided on the upper surfaces of the metal nitride layers 124c and 124d.

[0134] The source electrode 125c and the metal nitride layer 124c are provided in a region including the source region 121d. The drain electrode 125d and the metal nitride layer 124d are provided in a region including the drain region 121e. The metal nitride layers 124c, 124d, the source electrode 125c, and the drain electrode 125d are not provided in the channel region 121a. In other words, the oxide semiconductor layer 121 of the channel region 121a is exposed from the metal nitride layer and the conductive layer formed on the oxide semiconductor layer 121.

[0135] exist Fig.12 In the transistor 120 shown in the figure, a voltage for controlling the channel region 121a is supplied to the gate electrode 128. That is, the transistor 120 is a bottom-gate transistor.

[0136] The above structure can be expressed as follows. The first insulating layer (interlayer insulating layer 114) and the third gate insulating layer (gate insulating layer 129) are the same layer. The first gate electrode (gate electrode 113) and the third gate electrode (gate electrode 128) are the same layer. The first metal nitride layer (metal nitride layers 124c, 124d) are in contact with the upper surface and side surfaces of the second semiconductor layer (oxide semiconductor layer 121). Openings 115a and 115b are provided in the first insulating layer (interlayer insulating layer 114). The first electrode (source electrode 125a and drain electrode 125b) is provided above the first insulating layer (interlayer insulating layer 114) and inside the openings 115a and 115b, and is in contact with the first semiconductor layer (semiconductor layer 111). The second metal nitride layer (metal nitride layers 124 a and 124 b ) is provided above the first insulating layer (interlayer insulating layer 114 ) and between the first insulating layer (interlayer insulating layer 114 ) and the first electrode (source electrode 125 a and drain electrode 125 b ).

[0137] [3-2. Method for Manufacturing Semiconductor Device 100]

[0138] Reference Figure 13 to Figure 15 A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Figure 13 to Figure 15 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0139] Fig.13 In the manufacturing method shown in FIG. 1 , the steps up to the step of forming the oxide semiconductor layer 121 are the same as those of FIG. Figure 3 The manufacturing method is the same as shown, so the description is omitted. Fig.13 As shown, after the oxide semiconductor layer 121 is formed, the metal nitride layer 124 is formed over the interlayer insulating layer 114 and over the oxide semiconductor layer 121 .

[0140] like Fig.14 As shown, the formed metal nitride layer 124, the gate insulating layer 112 and the interlayer insulating layer 114 are processed by a photolithography process to form openings 115a and 115b reaching the source region 111d and the drain region 111e of the semiconductor layer 111, and an opening 115c reaching the gate electrode 128.

[0141] like Fig.15 As shown in FIG. 1 , a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a, 115b, and 115c. The conductive layer 125 is processed by a photolithography process to form Fig.12 The metal nitride layers 124a, 124b, 124c, 124d, 118, source electrodes 125a, 125c, drain electrodes 125b, 125d and wiring 119 are shown.

[0142] As described above, the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, so that the contact resistance can be suppressed. Furthermore, the semiconductor layer 111 is in contact with the source electrode 125a and the drain electrode 125b without the metal nitride layer, so that the contact resistance can be suppressed.

[0143] [4. Fourth embodiment]

[0144] Reference Figure 16 to Figure 19 An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described.

[0145] [4-1. Configuration of semiconductor device]

[0146] Fig.16 and Figure 1 Similarly, this is a cross-sectional view of the semiconductor device 100 when it is cut along the line A1-A2. Figure 1 and Fig.16 As shown, a semiconductor device 100 according to one embodiment of the present invention includes a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110 .

[0147] Fig.16 The transistors 110 and 120 are respectively configured as shown in FIG. Fig.12 The transistors 110 and 120 shown have similar structures, but their structures differ in the region where the metal nitride layer is provided.

[0148] exist Fig.12 In the transistor 110 shown in FIG. 1 , metal nitride layers 124 a and 124 b are provided between the source electrode 125 a and the interlayer insulating layer 114 and between the drain electrode 125 b and the interlayer insulating layer 114. Fig.16 In the transistor 120 shown in the figure, the metal nitride layer is not provided at the same position as described above. That is, the source electrode 125 a and the drain electrode 125 b are in contact with the upper surface of the interlayer insulating layer 114 .

[0149] Similarly, in Fig.12 In the transistor 120 shown in the figure, a metal nitride layer 118 is provided between the wiring 119 and the interlayer insulating layer 114, but Fig.16 In the transistor 120 shown in the figure, the metal nitride layer is not provided at the same position as described above. That is, the source electrode 125 a and the drain electrode 125 b are in contact with the upper surface of the interlayer insulating layer 114 .

[0150] Similarly, in Fig.12In the transistor 120 shown in FIG. 1 , the metal nitride layers 124 c and 124 d are formed from the upper surface of the oxide semiconductor layer 121 to the upper surface of the interlayer insulating layer 114 across the side surfaces of the oxide semiconductor layer 121. Fig.16 In the transistor 120 shown, the metal nitride layers 124c and 124d are formed only on the upper surface of the oxide semiconductor layer 121. That is, the metal nitride layers 124c and 124d are not formed on the side surfaces of the oxide semiconductor layer 121. The side surfaces of the oxide semiconductor layer 121 are in contact with the source electrode 125c and the drain electrode 125d provided above the metal nitride layers 124c and 124d.

[0151] [4-2. Method for Manufacturing Semiconductor Device 100]

[0152] Reference Figure 17 to Figure 19 A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Figure 17 to Figure 19 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0153] Fig.17 In the manufacturing method shown in the figure, the steps up to the step of forming the interlayer insulating layer 114 are the same as those of Figure 3 The manufacturing method shown is the same, and therefore the description thereof is omitted. After the interlayer insulating layer 114 is formed, the oxide semiconductor layer 121 and the metal nitride layer 124 are formed on the interlayer insulating layer 114 .

[0154] like Fig.18 As shown, the formed oxide semiconductor layer 121 and the metal nitride layer 124 are processed by a photolithography process. Next, the gate insulating layer 112 and the interlayer insulating layer 114 are processed by a photolithography process, thereby forming openings 115a and 115b reaching the source region 111d and the drain region 111e of the semiconductor layer 111 and an opening 115c reaching the gate electrode 128.

[0155] like Fig.19 As shown in FIG. 1 , a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a, 115b, and 115c. The formed conductive layer 125 is processed by a photolithography process to form Fig.16 The metal nitride layers 124c, 124d, source electrodes 125a, 125c, drain electrodes 125b, 125d and wiring 119 are shown.

[0156] As described above, the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, so that the contact resistance can be suppressed. Furthermore, the semiconductor layer 111 is in contact with the source electrode 125a and the drain electrode 125b without the metal nitride layer, so that the contact resistance can be suppressed.

[0157] [5. Fifth embodiment]

[0158] Reference Fig. 20 An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described.

[0159] [5-1. Configuration of semiconductor device]

[0160] Fig. 20 and Figure 1 Similarly, this is a cross-sectional view of the semiconductor device 100 when it is cut along the line A1-A2. Figure 1 and Fig. 20 As shown, a semiconductor device 100 according to one embodiment of the present invention includes a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110 .

[0161] Fig. 20 The transistor 120 shown is constructed in the same manner as Fig.12 The transistor 120 shown in FIG. 1 has similar structures to those of the transistor 120 , except that a gate electrode 123 is provided above the oxide semiconductor layer 121 . Fig.12 The transistor 120 shown is different. Fig. 20 In the transistor 120 shown, a voltage for controlling the channel region 121a is supplied to the gate electrodes 123 and 128. That is, the transistor 120 is a dual-gate transistor. In the transistor 120, the voltage for controlling the channel region 121a may not be supplied to the gate electrode 128, or a predetermined fixed voltage may be supplied. The gate electrode 128 may be floating. The transistor 120 may also be a top-gate transistor in which the gate electrode 128 is omitted and only the voltage for controlling the channel region 121a is supplied to the gate electrode 123.

[0162] Relative to Fig.12 The transistor 120 shown, Fig. 20 The transistor 120 shown is obtained by forming an interlayer insulating layer 126, forming a conductive layer over the interlayer insulating layer 126, and processing the conductive layer into a shape of a gate electrode 123 by a photolithography process. The interlayer insulating layer 126 functions as a gate insulating layer.

[0163] The semiconductor device 100 of this embodiment can also obtain the same effects as those of the other embodiments described above.

[0164] As embodiments of the present invention, the above-mentioned embodiments can be appropriately combined and implemented as long as they are not contradictory. Based on the embodiments, embodiments obtained by adding, deleting or designing components appropriately by those skilled in the art, or embodiments obtained by adding, omitting or changing conditions of processes, are included in the scope of the present invention as long as they have the gist of the present invention.

[0165] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, the effects that are clear based on the description of this specification or the effects that can be easily predicted by those skilled in the art are of course understood as the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: A first semiconductor layer; a first gate electrode facing the first semiconductor layer; a first gate insulating layer between the first semiconductor layer and the first gate electrode; a first insulating layer disposed above the first gate electrode; a first electrode disposed in a region overlapping the first semiconductor layer in a plan view and electrically connected to the first semiconductor layer; a second semiconductor layer, which is disposed on the first insulating layer and is made of a material different from that of the first semiconductor layer; a second gate electrode facing the second semiconductor layer; a second gate insulating layer between the second semiconductor layer and the second gate electrode; a second electrode provided in a region overlapping with the second semiconductor layer in a plan view and electrically connected to the second semiconductor layer; and a first metal nitride layer located between the second semiconductor layer and the second electrode, wherein the second semiconductor layer is polycrystalline, The second semiconductor layer has an etching rate of less than 3 nm / min in an etching solution containing phosphoric acid as a main component at a temperature of 40° C.

2. The semiconductor device according to claim 1, wherein The first metal nitride layer includes the same metal element as that included in the second electrode.

3. The semiconductor device according to claim 1, wherein The second electrode includes a first conductive layer and a second conductive layer on the first conductive layer. The first conductive layer is in contact with the first metal nitride layer. The first metal nitride layer includes the same metal element as that included in the first conductive layer.

4. The semiconductor device according to claim 1, wherein The first metal nitride layer is in contact with the second semiconductor layer.

5. The semiconductor device according to claim 1, further comprising: a second insulating layer above the first insulating layer; a third gate electrode disposed below the first insulating layer and facing the second semiconductor layer; and a third gate insulating layer between the second semiconductor layer and the third gate electrode, The second gate electrode is disposed above the second insulating layer, The first insulating layer and the second insulating layer each have an opening. The first electrode is provided above the second insulating layer and inside the opening. The first electrode and the second gate electrode are in the same layer.

6. The semiconductor device according to claim 1, further comprising: a second metal nitride layer; and a second insulating layer above the first insulating layer, The first insulating layer and the second insulating layer each have an opening. The first electrode is provided above the second insulating layer and inside the opening, and is in contact with the first semiconductor layer.

7. The semiconductor device according to claim 6, wherein: The second metal nitride layer is provided above the second insulating layer and between the second insulating layer and the first electrode.

8. The semiconductor device according to claim 5, wherein: The first insulating layer and the third gate insulating layer are the same layer, The first gate electrode and the third gate electrode are in the same layer.

9. The semiconductor device according to claim 8, wherein: The first metal nitride layer is in contact with the upper surface and side surfaces of the second semiconductor layer.

10. The semiconductor device according to claim 8, further comprising a second metal nitride layer. The first insulating layer has an opening. The first electrode is provided above the first insulating layer and inside the opening, and is in contact with the first semiconductor layer.

11. The semiconductor device according to claim 10, wherein The second metal nitride layer is provided above the first insulating layer and between the first insulating layer and the first electrode.

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