A back-contact battery and its manufacturing method

Abstract

The present invention belongs to the technical field of back-contact batteries, and specifically relates to a back-contact battery and a preparation method thereof, which include the following steps: S2. A first semiconductor layer and a mask layer are sequentially formed on the back surface of the silicon wafer, and the mask layer is a phosphorus-doped silicon oxide layer; S3. A second semiconductor opening region is formed on the back surface; S4. First, the front surface wrap-around coating layer is removed by using a mixed solution containing hydrofluoric acid and hydrogen peroxide, and then texturing and cleaning are performed; S5. A passivation layer and an antireflection layer are sequentially formed on the front surface; S6. The antireflection layer wrap-around coating and the passivation layer wrap-around coating are removed, and then oxidation cleaning is performed; the process of oxidation cleaning includes first oxidation, first pickling, alkali washing, second oxidation, and second pickling in sequence. Both the first oxidation and the second oxidation use a mixed solution containing ozone and hydrochloric acid; S7. A second semiconductor layer is deposited on the back surface. The process flow of the present invention directly shortens two steps, has low cost, and at the same time, the fill factor of the battery is improved, thereby improving the conversion efficiency and yield of the battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery and a preparation method thereof. Background Art

[0002] Currently, the process flow of back-contact batteries with low equipment cost is generally as follows:

[0003] S101. Provide a silicon wafer with a double-sided polished structure;

[0004] S102. Deposit a first semiconductor layer on the back surface of the silicon wafer in sequence. The first semiconductor layer is formed by LPCVD or tube PECVD, and the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer;

[0005] S103. Clean and remove the PSG layer on the surface of the first semiconductor layer;

[0006] S104. Deposit a mask layer on the first semiconductor layer;

[0007] S105. Laser or etch an opening on the back surface of the silicon wafer to remove the first mask layer and part of the first semiconductor layer, and form a second semiconductor region opening;

[0008] S106. Texturize and clean to form a textured surface on the second semiconductor opening region on the back surface and the front surface, and remove more than half of the mask layer;

[0009] S107. Form a passivation layer and an antireflection layer on the front surface of the silicon wafer;

[0010] S108. Remove the bypass plating layer and then perform backwashing;

[0011] S109. Form a second semiconductor layer on the back surface. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped P-type amorphous or microcrystalline silicon layer formed in sequence on the back surface;

[0012] S110. Laser or etch an opening on the back surface of the silicon wafer to form a first semiconductor region arranged alternately with the second semiconductor region;

[0013] S111. Deposit a conductive film on the back surface of the silicon wafer;

[0014] S112. Form an insulating groove between the first semiconductor region and the second semiconductor region by laser or etching;

[0015] S113. Form metal electrodes on the first semiconductor region and the second semiconductor region of the silicon wafer.

[0016] However, the process of back-contact batteries generally has more than 10 steps. Among them, there are many process procedures, and the consumption of chemical solutions and gases is large. On the one hand, the cost is increased, and on the other hand, the increase in process procedures reduces the battery conversion efficiency and the yield rate.

[0017] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or the well-known technology. Summary of the Invention

[0018] The object of the present invention is to overcome the defects of the existing back-contact battery, which has many processes, resulting in high cost, low battery conversion efficiency and low yield rate. The present invention provides a back-contact battery and a preparation method thereof. The process flow of the present invention directly shortens two steps, has low cost, and at the same time, the fill factor of the battery is increased, thereby improving the battery conversion efficiency and the yield rate.

[0019] To achieve the above object, in the first aspect, the present invention provides a method for preparing a back-contact battery, including the following steps:

[0020] S1. Provide a double-sided polished silicon wafer;

[0021] S2. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The mask layer is a phosphorus-doped silicon oxide layer, and the thickness of the phosphorus-doped silicon oxide layer is 20-60 nm, and a front-side wrap-around coating layer is naturally formed;

[0022] S3. Etch an opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0023] S4. First, use a mixed solution containing hydrofluoric acid and hydrogen peroxide to remove the front-side wrap-around coating layer, and then use a texturing solution containing a film-forming protective agent for texturing cleaning, and at the same time form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region;

[0024] S5. Sequentially form a passivation layer and an anti-reflection layer on the front surface;

[0025] S6. Remove the anti-reflection layer wrap-around coating layer and the passivation layer wrap-around coating layer, and then perform oxidation cleaning; the process of oxidation cleaning includes first oxidation, first pickling, alkali washing, second oxidation, and second pickling in sequence. Both the first oxidation and the second oxidation use a mixed solution containing ozone and hydrochloric acid;

[0026] S7. Deposit a second semiconductor layer on the back surface.

[0027] In some preferred embodiments of the present invention, in S4, the mass concentration of hydrofluoric acid in the mixed solution containing hydrofluoric acid and hydrogen peroxide is 10%-15%, and the mass concentration of hydrogen peroxide is 2%-10%.

[0028] In some preferred embodiments of the present invention, in S4, the conditions for removing the front-side wrap-around coating layer include: the reaction temperature is 20-35 °C, and the reaction time is 60-240 s.

[0029] In some preferred embodiments of the present invention, the mass content of the film-forming protective agent in the S4 texturing solution is 0.1% - 1%.

[0030] In some preferred embodiments of the present invention, the film-forming protective agent is selected from sodium lignosulfonate and / or sodium dodecylbenzenesulfonate.

[0031] In some preferred embodiments of the present invention, in S4, the texturing solution further contains an alkali and a texturing additive. The mass content of the alkali is 1% - 5%, and the mass content of the texturing additive is 0.1% - 1%.

[0032] In some preferred embodiments of the present invention, the conditions for texturing and cleaning in S4 include: the texturing time is 6 - 10 min, and the texturing temperature is 65°C - 85°C.

[0033] In some preferred embodiments of the present invention, the process of removing the anti-reflection layer winding coating and the passivation layer winding coating in S6 includes: first using an aqueous solution containing hydrofluoric acid to remove the anti-reflection layer winding coating, and then using a mixed solution containing an alkali and hydrogen peroxide to remove the passivation layer winding coating; wherein, the mass concentration of hydrofluoric acid in the aqueous solution containing hydrofluoric acid is 5% - 10%, the mass concentration of the alkali in the mixed solution containing an alkali and hydrogen peroxide is 2% - 5%, and the mass concentration of hydrogen peroxide is 0.2% - 1%.

[0034] In some preferred embodiments of the present invention, in S6, a chain-type cleaning machine is used to remove the anti-reflection layer winding coating. The conditions for removing the anti-reflection layer winding coating include: the reaction temperature is 20 - 35°C, and the speed of the driving roller of the chain-type machine is 1.2 - 3.0 m / min; a tank-type cleaning machine is used to remove the passivation layer winding coating. The conditions for removing the passivation layer winding coating include: the reaction temperature is 25 - 35°C, and the reaction time is 60 - 240 s.

[0035] In some preferred embodiments of the present invention, in S6, the ozone concentration in the mixed solution containing ozone and hydrochloric acid is 20 - 80 ppm, and the mass concentration of hydrochloric acid is 0.5% - 4%.

[0036] In some preferred embodiments of the present invention, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation is greater than the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the second oxidation.

[0037] In some preferred embodiments of the present invention, in S6, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation is 50 - 80 ppm, and the mass concentration of hydrochloric acid is 0.5% - 4%; the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the second oxidation is 20 - 50 ppm, and the mass concentration of hydrochloric acid is 0.5% - 4%.

[0038] In some preferred embodiments of the present invention, in S6, the conditions for the first oxidation include: a reaction time of 60 - 500 s and a reaction temperature of 20 - 25°C; the conditions for the second oxidation include: a reaction time of 60 - 240 s and a reaction temperature of 20 - 25°C.

[0039] In some preferred embodiments of the present invention, in S6, the first pickling uses a first hydrofluoric acid solution with a hydrofluoric acid mass concentration of 0.1% - 1%, and the second pickling uses a second hydrofluoric acid solution with a hydrofluoric acid mass concentration of 1% - 5%; the reaction time for the first pickling is 15 - 30 s, and the reaction time for the second pickling is 30 - 120 s.

[0040] In some preferred embodiments of the present invention, in S6, the hydrofluoric acid concentration of the first hydrofluoric acid solution is less than that of the second hydrofluoric acid solution.

[0041] In some preferred embodiments of the present invention, in S6, the alkali washing uses a mixed solution containing ammonia water or strong alkali and H2O2, the mass concentration of ammonia water or strong alkali is 2% - 5%, and the mass concentration of H2O2 is 3% - 5%; the conditions for the alkali washing include: a reaction temperature of 60 - 80°C and a reaction time of 120 - 240 s.

[0042] In some preferred embodiments of the present invention, in S6, the oxidation cleaning further includes a process of slow lifting and drying in sequence after the second pickling.

[0043] In some preferred embodiments of the present invention, in S2, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, the thickness of the first tunneling oxide layer is 1 - 2 nm, and the thickness of the first doped polysilicon layer is 80 - 200 nm.

[0044] In some preferred embodiments of the present invention, the first semiconductor layer and the phosphorus-doped silicon oxide layer are deposited in sequence by a tube PECVD method and subjected to high-temperature annealing, controlling the deposition temperature to be 400 - 500°C and the high-temperature annealing temperature to be 850 - 950°C.

[0045] In some preferred embodiments of the present invention, the formation process of the first semiconductor layer and the mask layer in S2 includes: in the first stage, nitrous oxide is introduced, glow discharge is initiated, and a first tunneling oxide layer is formed; in the second stage, silane, phosphine, and hydrogen are introduced, glow discharge is initiated, and a first phosphorus-doped amorphous silicon layer with a thickness of 30 - 80 nm is formed; in the third stage, silane, phosphine, and hydrogen are introduced, glow discharge is initiated, and a second phosphorus-doped amorphous silicon layer with a thickness of 40 - 120 nm is formed, and the phosphorus doping amount of the second phosphorus-doped amorphous silicon layer is higher than that of the first phosphorus-doped amorphous silicon layer; in the fourth stage, silane and nitrous oxide are introduced, glow discharge is initiated, and a silicon oxide layer with a thickness of 20 - 60 nm is formed; then high-temperature annealing is carried out under the condition of introducing nitrogen, the high-temperature annealing temperature is 850 - 950 °C, and each phosphorus-doped amorphous silicon layer forms a first phosphorus-doped polysilicon layer under the high-temperature annealing condition, and the silicon oxide layer forms a phosphorus-doped silicon oxide layer under the high-temperature annealing condition.

[0046] In some more preferred embodiments of the present invention, the flow rate of nitrous oxide introduced in the first stage is 8000 - 30000 sccm; the flow rate of silane introduced in the second stage is 1000 - 3000 sccm, the flow rate of phosphine is 100 - 500 sccm, and the flow rate of hydrogen is 7000 - 9000 sccm; the flow rate of silane introduced in the third stage is 1000 - 3000 sccm, the flow rate of phosphine is 200 - 1000 sccm, and the flow rate of hydrogen is 7000 - 9000 sccm; the flow rate of silane introduced in the fourth stage is 500 - 1000 sccm, and the flow rate of nitrous oxide is 5000 - 8000 sccm.

[0047] In some more preferred embodiments of the present invention, in the first stage, the reaction pressure is controlled to be 100 - 200 Pa, the power is 3000 - 10000 W, and the reaction time is 20 - 100 s; in the second stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 2000 - 4000 W, and the reaction time is 300 - 1500 s; in the third stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 3000 - 7000 W, and the reaction time is 200 - 1000 s; in the fourth stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 3000 - 7000 W, and the reaction time is 50 - 200 s; in the high-temperature annealing, the annealing pressure is controlled to be 5000 - 50000 Pa, the annealing time is 60 - 120 min, and the nitrogen flow rate is 2000 sccm - 8000 sccm.

[0048] In some preferred embodiments of the present invention, in S4, the passivation layer includes a second tunneling oxide layer and a second doped amorphous silicon layer; the thickness of the second tunneling oxide layer is 1 - 2 nm, and the thickness of the second doped amorphous silicon layer is 1 - 10 nm.

[0049] In some preferred embodiments of the present invention, the antireflection layer is a stack including silicon nitride and silicon oxynitride arranged in sequence, the thickness ratio of silicon nitride to silicon oxynitride in the stack is 1-3:1, and the total thickness of the stack is 70-120 nm.

[0050] In some preferred embodiments of the present invention, in S4, the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer formed in sequence on the back surface, the thickness of the intrinsic silicon layer is 5-15 nm, and the thickness of the second doped silicon layer is 5-20 nm.

[0051] In some preferred embodiments of the present invention, the method for preparing the back contact battery further includes the following steps:

[0052] S8. Perform a second etching opening on a part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region;

[0053] S9. Deposit a conductive film layer on the back surface obtained in S8;

[0054] S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0055] S11. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0056] In a second aspect, the present invention provides a back contact battery prepared by the method for preparing the back contact battery described in the first aspect.

[0057] Beneficial effects:

[0058] Through the above technical solutions, especially S2, S4, and S6, the process flow of the present invention is directly shortened by two steps, and at the same time, the fill factor of the battery is increased, thereby improving the conversion efficiency and yield rate of the battery.

[0059] Among them, on the one hand, in the present invention, S2 uses a phosphorus-doped silicon oxide layer as a mask layer, eliminating the S103 one-step backwashing and S104 one-step mask layer plating processes required after the S102 process in the conventional method. However, since the phosphorus-doped silicon oxide layer is easily corroded as a mask layer, a texturing solution containing a film-forming protective agent must be used for texturing to protect the mask layer from corrosion. At the same time, the front-side wrap-around coating layer corresponding to the first semiconductor layer (such as the tunneling oxide layer included) will also be protected. Therefore, the front-side wrap-around plating area cannot fully form texture, the texture surface size is uneven, and there is color difference. In response to this, in the present invention, S4 uses a mixed solution containing hydrofluoric acid and hydrogen peroxide to remove the front-side wrap-around coating layer. Since hydrogen peroxide will oxidize the polycrystalline layer and hydrofluoric acid can continuously corrode the oxide layer, in the repeated oxidation and removal process, the thinner front-side wrap-around coating layer is continuously removed, thus ensuring that normal texture can be formed on the front side. Compared with the conventional method of etching the front side with strong acids such as nitric acid, it can hardly etch the silicon wafer, and greatly reduces the chemical cost and the waste liquid treatment cost.

[0060] On the other hand, since the phosphorus-doped silicon oxide layer is extremely easy to corrode compared with the conventional silicon nitride mask layer, it will be removed during the S4 texturing cleaning and is difficult to retain after S4. Therefore, during the front-side coating process, the metal ions and other contaminants on the back surface of the silicon wafer will diffuse into the silicon wafer body and cannot be completely removed only by simple backwashing. In response to this, the present invention also cooperates with a wet oxidation method to grow an oxide layer on the back surface of the silicon wafer and then continuously remove it, so that a clean interface can be obtained in the second semiconductor opening area to facilitate the passivation of the second semiconductor opening area. The solutions used for the two wet oxidations are mixed solutions containing ozone and hydrochloric acid. Among them, the first oxidation uses the strong oxidizing property of ozone to quickly form a relatively thick oxide layer on the interface to wrap the impurity contamination in the oxide layer, and then the first pickling is used to remove the oxide layer on the back surface of the silicon wafer in a short time. The alkali washing can neutralize the acid solution and remove the organic matter on the silicon wafer surface. After the second oxidation, an oxide layer will be formed on the silicon wafer interface to further wrap the impurities deeper in the bulk silicon in the oxide layer. The second pickling, on the one hand, removes the oxide layer, and on the other hand, effectively chemically passivates the second semiconductor opening area, reducing its interface state density, thereby obtaining a clean interface and improving passivation. The fill factor of the battery is increased, and thus the battery conversion efficiency and the yield are improved. The preparation method of the present invention directly shortens the process flow by two steps. At the same time, through the subsequent two oxidation cleaning methods, the fill factor of the battery is increased, and thus the battery conversion efficiency and the yield are improved. The present invention also adds a film-forming protective agent to the texturing solution, which will adsorb on the phosphorus-doped silicon oxide layer during the texturing process to protect the mask layer from corrosion, so as to protect the film layer under the mask layer from being damaged during the texturing process, and remove the mask layer in the cleaning step during the subsequent texturing cleaning, thus eliminating the two processes of separate backwashing and mask layer plating, and simplifying the process flow.

[0061] In conventional processes, a mixed solution containing hydrofluoric acid, hydrochloric acid and ozone is usually used to remove surface impurities. However, since the first semiconductor layer is repeatedly oxidized and corroded in the above solution, the surface becomes black, the film layer is severely damaged, and the passivation effect is poor. In this regard, the present invention adopts an oxidation cleaning method of oxidation followed by corrosion to clean the silicon wafer after S5. On the one hand, the two oxidation and corrosion cleaning methods ensure the cleanliness of the tank solution, making the cleaning of the silicon wafer cleaner. On the other hand, after two wet oxidations, the second semiconductor opening area effectively removes the metal impurities introduced during the front coating process, reduces the recombination of carriers, and thus improves the battery's fill factor and battery conversion efficiency and yield. Among them, the first oxidation and the second oxidation both use a mixed solution containing ozone and hydrochloric acid. Adding hydrochloric acid to the corresponding mixed solution of the two-step oxidation can enhance the stability of ozone in the solution on the one hand, and can chelate and remove metal ions on the surface of the silicon wafer on the other hand. DETAILED DESCRIPTION

[0062] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0063] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0064] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0065] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0066] In a first aspect, the present invention provides a method for preparing a back-contact battery, comprising the following steps:

[0067] S1. Provide a double-sided polished silicon wafer;

[0068] S2. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The mask layer is a phosphorus-doped silicon oxide layer with a thickness of 20 - 60 nm, and a front-side wrap-around coating layer is naturally formed;

[0069] S3. Etch an opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0070] S4. First, use a mixed solution containing hydrofluoric acid and hydrogen peroxide to remove the front-side wrap-around coating layer, and then use a texturing solution containing a film-forming protective agent for texturing and cleaning, while forming a textured surface on the front surface of the silicon wafer and the second semiconductor opening region;

[0071] S5. Sequentially form a passivation layer and an antireflection layer on the front surface;

[0072] S6. Remove the antireflection layer wrap-around coating and the passivation layer wrap-around coating, and then perform oxidation cleaning; the process of oxidation cleaning includes first oxidation, first pickling, alkali washing, second oxidation, and second pickling in sequence. Both the first oxidation and the second oxidation use a mixed solution containing ozone and hydrochloric acid;

[0073] S7. Deposit a second semiconductor layer on the back surface.

[0074] The thickness of the phosphorus-doped silicon oxide layer is 20 - 60 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, etc. and the range between any two point values, and 20 - 46 nm can be preferred.

[0075] In some preferred embodiments of the present invention, in S4, the mass concentration of hydrofluoric acid in the mixed solution containing hydrofluoric acid and hydrogen peroxide is 10% - 15%, and the mass concentration of hydrogen peroxide is 2% - 10%.

[0076] In some preferred embodiments of the present invention, in S4, the conditions for removing the front-side wrap-around coating layer include: the reaction temperature is 20 - 35 °C, and the reaction time is 60 - 240 s.

[0077] The equipment for removing the front-side wrap-around coating layer in the present invention is preferably a chain cleaner.

[0078] The texturing cleaning in S4 can remove the residual mask layer and the first semiconductor layer in the second semiconductor opening region.

[0079] In some preferred embodiments of the present invention, the mass content of the film-forming protective agent in the S4 texturing solution is 0.1% - 1%. For example, specifically, it can be 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, etc., as well as the range between any two point values. Preferably, it can be 0.6% - 1%. Using an appropriate amount of the film-forming protective agent is more conducive to protecting the passivation film layer under the phosphorus-doped silicon oxide layer from being corroded.

[0080] In some preferred embodiments of the present invention, the film-forming protective agent is selected from sodium lignosulfonate and / or sodium dodecylbenzenesulfonate.

[0081] In some preferred embodiments of the present invention, in S4, the texturing solution further contains an alkali and a texturing additive. The mass content of the alkali is 1% - 5%, and the mass content of the texturing additive is 0.1% - 1%. The texturing additive is a commercially available product and will not be elaborated here.

[0082] More preferably, the alkali is selected from potassium hydroxide and / or sodium hydroxide.

[0083] In some preferred embodiments of the present invention, the conditions for texturing and cleaning in S4 include: the texturing time is 6 - 10 min, and the texturing temperature is 65°C - 85°C.

[0084] The texturing and cleaning in the present invention at least includes texturing and cleaning. The mask layer will be removed in the cleaning step. Exemplarily, the process of texturing and cleaning can, for example, include texturing, cleaning by the RCA standard cleaning method, and cleaning with an HF solution in sequence. In the HF solution cleaning, the mask layer will be almost completely removed. The HF concentration can be determined according to the mask layer to be removed as long as the desired purpose is achieved. The RCA standard solution used in the RCA standard cleaning method can be an existing corresponding cleaning solution such as the No. 1 standard cleaning solution or the No. 2 standard cleaning solution, which are prior arts and can all be used in the present invention. Among them, the specific composition of the No. 1 standard cleaning solution can, for example, be a mixture of ammonia water / hydrogen peroxide / water in a mass ratio of 1:1:5, and the specific composition of the No. 2 standard cleaning solution can, for example, be a mixture of hydrochloric acid / hydrogen peroxide / water in a mass ratio of 1:1:6.

[0085] In some preferred embodiments of the present invention, the process of removing the antireflection layer wrap plating and the passivation layer wrap plating in S6 includes: first, removing the antireflection layer wrap plating with an aqueous solution containing hydrofluoric acid, and then removing the passivation layer wrap plating with a mixed solution containing an alkali and hydrogen peroxide. The preferred solution of using different solutions to remove different wrap platings is more conducive to reducing the damage to the passivation film layer.

[0086] Further preferably, the mass concentration of hydrofluoric acid in the aqueous solution containing hydrofluoric acid is 5% - 10%.

[0087] Further preferably, in the mixed solution containing alkali and hydrogen peroxide, the mass concentration of the alkali is 2% - 5%, and the mass concentration of the hydrogen peroxide is 0.2% - 1%.

[0088] In some preferred embodiments of the present invention, in S6, a chain type cleaning machine is used to remove the anti-reflection layer around the coating.

[0089] Further preferably, the conditions for removing the anti-reflection layer around the coating include: the reaction temperature is 20 - 35 °C, and the speed of the driving roller of the chain type machine is 1.2 - 3.0 m / min. Adopting this preferred solution is more conducive to protecting the anti-reflection layer on the front side from being corroded.

[0090] Preferably, a tank type cleaning machine is used to remove the passivation layer around the coating in the present invention.

[0091] Further preferably, the conditions for removing the passivation layer around the coating include: the reaction temperature is 25 - 35 °C, and the reaction time is 60 - 240 s. Adopting this preferred solution is more conducive to not damaging the film layers on the front and back sides at all.

[0092] In some preferred embodiments of the present invention, in S6, in the mixed solution containing ozone and hydrochloric acid, the ozone concentration is 20 - 80 ppm, and the mass concentration of the hydrochloric acid is 0.5% - 4%.

[0093] In some preferred embodiments of the present invention, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation is greater than the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the second oxidation. Adopting this preferred solution is more conducive to forming a thicker oxide layer during the first oxidation, so as to wrap the impurities with a higher concentration at the interface therein and then remove them, thereby reducing the risk of contaminating the subsequent tank and ensuring a cleaner interface after the second oxidation.

[0094] Further preferably, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation is 1 - 4 times, preferably 1.1 - 4 times, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the second oxidation, which is more conducive to forming a thicker oxide layer in a short time.

[0095] Preferably, the hydrochloric acid concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation in the present invention is less than the hydrochloric acid concentration in the mixed solution containing ozone and hydrochloric acid used for the second oxidation, which is more conducive to enhancing the stability of ozone in the corresponding solution, more effectively complexing and effectively removing metal ions on the surface of the silicon wafer.

[0096] In some preferred embodiments of the present invention, in S6, in the mixed solution containing ozone and hydrochloric acid used for the first oxidation, the ozone concentration is 50 - 80 ppm, and the mass concentration of hydrochloric acid is 0.5% - 4%; in the mixed solution containing ozone and hydrochloric acid used for the second oxidation, the ozone concentration is 20 - 50 ppm, and the mass concentration of hydrochloric acid is 0.5% - 4%. By adopting this preferred scheme, different oxidations use different appropriate ranges of ozone and hydrochloric acid concentrations, which is more conducive to effectively removing the metal impurities introduced during the front coating process, reducing the recombination of carriers, and thus improving the fill factor and conversion efficiency of the battery.

[0097] In some preferred embodiments of the present invention, in S6, the conditions for the first oxidation include: the reaction time is 60 - 500 s, and the reaction temperature is 20 - 25 °C.

[0098] Preferably, the conditions for the second oxidation include: the reaction time is 60 - 240 s, and the reaction temperature is 20 - 25 °C.

[0099] In some preferred embodiments of the present invention, in S6, the first pickling uses a first hydrofluoric acid solution with a hydrofluoric acid mass concentration of 0.1% - 1%, and the reaction time for the first pickling is 15 - 30 s. By adopting this preferred scheme, it is more conducive to effectively removing the oxide film layer on the back, while hardly damaging the antireflection layer on the front.

[0100] Preferably, in the present invention, the second pickling uses a second hydrofluoric acid solution with a hydrofluoric acid mass concentration of 1% - 5%, and the reaction time for the second pickling is 30 - 120 s. By adopting this preferred scheme, it is more conducive to effectively chemically passivating the second semiconductor opening region while removing the back oxide layer, and reducing its interface state density.

[0101] In some preferred embodiments of the present invention, in S6, the hydrofluoric acid concentration of the first hydrofluoric acid solution is less than that of the second hydrofluoric acid solution. By adopting this preferred scheme, it is more conducive to ensuring that the damage to the front antireflection film layer is minimized on the premise of removing the oxide layer.

[0102] Further preferably, the ratio of the hydrofluoric acid concentration of the first hydrofluoric acid solution to that of the second hydrofluoric acid solution is 1:1 - 50, preferably 1:1.1 - 50.

[0103] In some preferred embodiments of the present invention, in S6, the alkali washing uses a mixed solution containing ammonia water or strong alkali and H2O2, the mass concentration of ammonia water or strong alkali is 2% - 5%, and the mass concentration of H2O2 is 3% - 5%. By adopting this preferred scheme, it is more conducive to neutralizing the acid solution and removing the organic matter on the silicon wafer surface. Further preferably, the mass concentration of ammonia water is relatively high, and the mass concentration of strong alkali is relatively low compared to ammonia water.

[0104] Preferably, the strong alkali is KOH and / or NaOH.

[0105] Preferably, the conditions for the caustic washing include: the reaction temperature is 60 - 80°C, and the reaction time is 120 - 240 s.

[0106] In some preferred embodiments of the present invention, in S6, the oxidative cleaning further includes a process of slow lifting and drying in sequence after the second pickling. The slow lifting is a conventional existing process and will not be elaborated here.

[0107] In S2 of the present invention, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer.

[0108] Preferably, the thickness of the first tunneling oxide layer is 1 - 2 nm, and the thickness of the first doped polysilicon layer is 80 - 200 nm.

[0109] In some preferred embodiments of the present invention, in S4, the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer formed in sequence on the back surface. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. The present invention adopts the first semiconductor layer of tunneling polycrystal, in combination with this second semiconductor layer, to form a combined passivation structure, which is more conducive to improving the open - circuit voltage and the conversion efficiency of the battery.

[0110] Preferably, the thickness of the intrinsic silicon layer is 5 - 15 nm, and the thickness of the second doped silicon layer is 5 - 20 nm.

[0111] In the present invention, one of the first doped polysilicon layer and the second doped silicon layer is N - type, and the other is P - type. The doping concentrations of the first doped polysilicon layer and the second doped silicon layer can refer to their respective ranges in the prior art. Exemplarily, the effective doping concentration of the first doped polysilicon layer is 5e18 cm -3 -1e21 cm -3 , and the effective doping concentration of the second doped silicon layer is 1e18 cm -3 -5e19 cm -3 .

[0112] In some preferred embodiments of the present invention, the first semiconductor layer and the phosphorus - doped silicon oxide layer are deposited in sequence by the tube - type PECVD method and then subjected to high - temperature annealing. The deposition temperature is controlled at 400 - 500°C, and the high - temperature annealing temperature is 850 - 950°C.

[0113] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling oxide layer and a first phosphorus-doped polysilicon layer arranged in sequence. Correspondingly, the formation process of the first semiconductor layer and the mask layer in S2 includes: in the first stage, nitrous oxide is introduced and glow discharge is started to form the first tunneling oxide layer; in the second stage, silane, phosphine and hydrogen are introduced and glow discharge is started to form a first phosphorus-doped amorphous silicon layer with a thickness of 30-80 nm; in the third stage, silane, phosphine and hydrogen are introduced and glow discharge is started to form a second phosphorus-doped amorphous silicon layer with a thickness of 40-120 nm, and the phosphorus doping amount of the second phosphorus-doped amorphous silicon layer is higher than that of the first phosphorus-doped amorphous silicon layer; in the fourth stage, silane and nitrous oxide are introduced and glow discharge is started to form a silicon oxide layer with a thickness of 20-60 nm; then high-temperature annealing is carried out under the condition of introducing nitrogen, and the high-temperature annealing temperature is 850-950 °C. Each phosphorus-doped amorphous silicon layer forms a first phosphorus-doped polysilicon layer under the high-temperature annealing condition, and the silicon oxide layer forms a phosphorus-doped silicon oxide layer under the high-temperature annealing condition. The present invention forms the phosphorus-doped amorphous silicon layer twice and then performs high-temperature annealing to form the first phosphorus-doped polysilicon layer, which is beneficial to improving the passivation level of the first semiconductor layer. Among them, a phosphosilicate glass layer will be naturally formed during high-temperature annealing, but the thickness of the oxide layer is relatively thin and the protection is not good. For this reason, the present invention generates a controllable silicon oxide layer on the polycrystalline surface, and then high-temperature annealing will enhance the densification of the silicon oxide layer and the protection is better.

[0114] In some more preferred embodiments of the present invention, the flow rate of nitrous oxide introduced in the first stage is 8000-30000 sccm; the flow rate of silane introduced in the second stage is 1000-3000 sccm, the flow rate of phosphine is 100-500 sccm, and the flow rate of hydrogen is 7000-9000 sccm; the flow rate of silane introduced in the third stage is 1000-3000 sccm, the flow rate of phosphine is 200-1000 sccm, and the flow rate of hydrogen is 7000-9000 sccm; the flow rate of silane introduced in the fourth stage is 500-1000 sccm, and the flow rate of nitrous oxide is 5000-8000 sccm.

[0115] In some more preferred embodiments of the present invention, in the first stage, the reaction pressure is controlled to be 100 - 200 Pa, the power is 3000 - 10000 W, and the reaction time is 20 - 100 s; in the second stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 2000 - 4000 W, and the reaction time is 300 - 1500 s; in the third stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 3000 - 7000 W, and the reaction time is 200 - 1000 s; in the fourth stage, the reaction pressure is controlled to be 300 - 500 Pa, the power is 3000 - 7000 W, and the reaction time is 50 - 200 s; in the high-temperature annealing, the annealing pressure is controlled to be 5000 - 50000 Pa, the annealing time is 60 - 120 min, and the nitrogen flow rate is 2000 sccm - 8000 sccm. By adopting this preferred scheme, it is more beneficial to the distribution of the phosphorus doping concentration in the first semiconductor layer and makes the mask layer denser.

[0116] In some preferred embodiments of the present invention, in S4, the passivation layer includes a second tunneling oxide layer and a second doped amorphous silicon layer; the thickness of the second tunneling oxide layer is 1 - 2 nm, and the thickness of the second doped amorphous silicon layer is 1 - 10 nm.

[0117] In some preferred embodiments of the present invention, the antireflection layer is a stack including silicon nitride and silicon oxynitride arranged in sequence, and the total thickness of the stack is 70 - 120 nm. By adopting this preferred scheme, it is more beneficial to enhance the antireflection effect on the front side and improve the short-circuit current of the battery.

[0118] Further preferably, the thickness ratio of silicon nitride to silicon oxynitride in the stack is 1 - 3:1.

[0119] The second tunneling oxide layer, the second doped amorphous silicon layer, and the antireflection layer can be formed by using, for example, the tube PECVD method respectively.

[0120] In some preferred embodiments of the present invention, the preparation method of the back contact battery further includes the following steps:

[0121] S8. Perform a second etching opening on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0122] S9. Deposit a conductive film layer on the back obtained in S8;

[0123] S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an insulating groove;

[0124] S11. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located respectively.

[0125] In a second aspect, the present invention provides a back-contact battery, which is obtained by the preparation method of the back-contact battery described in the first aspect.

[0126] Embodiments of the present invention will be described in detail below. They are exemplary and are only used to explain the present invention and should not be construed as limiting the present invention.

[0127] Example 1

[0128] A back-contact battery is prepared by the following preparation method:

[0129] S1. Provide a double-sided polished silicon wafer (N-type single-crystalline silicon wafer);

[0130] S2. Sequentially form a first semiconductor layer and a phosphorous-doped silicon oxide layer mask layer on the back surface of the silicon wafer in S1;

[0131] The first semiconductor layer includes a first tunneling oxide layer and an N-type first doped polysilicon layer formed in sequence. The thickness of the first tunneling oxide layer is 1.5 nm, the thickness of the first doped polysilicon layer is 100 nm, and the effective doping concentration is 5e19 cm -3 , and the mask layer is a phosphorous-doped silicon oxide layer with a thickness of 30 nm.

[0132] The first tunneling oxide layer, the first doped polysilicon layer, and the mask layer are sequentially deposited by a tube-type PECVD method and annealed at a high temperature. The deposition temperature is 450 °C. The specific preparation process is as follows:

[0133] In the first stage, nitrous oxide is introduced, and glow discharge is started to form the first tunneling oxide layer. During this period, the nitrous oxide flow rate is 8000 sccm, the reaction time is 40 s, the reaction pressure is 120 Pa, and the power is 4000 W;

[0134] In the second stage, silane, phosphine, and hydrogen are introduced. The flow rate of silane is 2000 sccm, the flow rate of phosphine is 200 sccm, and the flow rate of hydrogen is 8000 sccm. Glow discharge is started to form a first phosphorous-doped amorphous silicon layer. During this period, the reaction time is 1000 s, the reaction pressure is 400 Pa, the power is 3000 W, and the thickness of the first phosphorous-doped amorphous silicon layer is 60 nm;

[0135] In the third stage, silane, phosphine, and hydrogen are introduced. The flow rate of silane is 2000 sccm, the flow rate of phosphine is 500 sccm, and the flow rate of hydrogen is 8000 sccm. Glow discharge is started to form a second phosphorous-doped amorphous silicon layer. The reaction time is 450 s, the reaction pressure is 400 Pa, the power is 5000 W, the thickness of the second phosphorous-doped amorphous silicon layer is 40 nm, and the phosphorus doping amount of the second phosphorous-doped amorphous silicon layer is higher than that of the first phosphorous-doped amorphous silicon layer;

[0136] In the fourth stage, silane and nitrous oxide are introduced. The flow rate of silane is 600 sccm, and the flow rate of nitrous oxide is 6000 sccm. Glow discharge is initiated to form a silicon oxide layer with a thickness of 30 nm. The reaction time is 100 s, the reaction pressure is 400 Pa, and the power is 4000 W.

[0137] Then, high-temperature annealing is carried out under the condition of introducing nitrogen. The annealing pressure is 10000 Pa, the annealing temperature is 900 °C, the annealing time is 90 min, and the nitrogen flow rate is 3000 sccm. The phosphorus-doped amorphous silicon layer forms a phosphorus-doped polycrystalline silicon layer under the annealing condition, and the silicon oxide layer forms a phosphorus-doped silicon oxide layer under the annealing condition.

[0138] S3. The first semiconductor layer is etched on the back mask layer of the S2 silicon wafer to remove part of the first semiconductor layer and its corresponding mask layer, forming second semiconductor opening areas distributed at intervals.

[0139] S4. The front wrap-around coating layer is removed, and then texturing cleaning is carried out to form a textured surface on the back in the second semiconductor opening areas and on the front simultaneously.

[0140] Specifically, a chain cleaning machine is used to remove the front wrap-around coating layer (i.e., the wrap-around coating layer of the first semiconductor layer and the phosphorus-doped silicon oxide layer on the front). A mixed solution containing hydrofluoric acid and hydrogen peroxide is used to remove the front wrap-around plating. The mass concentration of hydrofluoric acid is 12%, the mass concentration of hydrogen peroxide is 3%, and the balance is water. During this period, the reaction temperature is controlled at 25 °C, and the reaction time is 120 s.

[0141] Then, texturing cleaning is carried out. The texturing solution is a mixed solution of potassium hydroxide, a texturing additive (commercially available product), a film-forming protective agent, and water. The mass percentage content of potassium hydroxide is 2%, the mass percentage content of the texturing additive is 0.2%, the mass percentage content of the film-forming protective agent (specifically sodium lignosulfonate) is 0.8%, and the balance is water; the texturing time is 8 min, and the texturing temperature is 75 °C. The process of texturing cleaning includes texturing, backwashing with an RCA standard solution (the RCA standard solution is No. 1 standard cleaning solution, and the specific composition is a mixture of ammonia water / hydrogen peroxide / water in a mass ratio of 1:1:5), and cleaning with an HF solution (the concentration of HF in the HF solution is 2 wt%). In the HF solution cleaning, the mask layer is almost completely removed.

[0142] S5. A passivation layer and an antireflection layer are sequentially formed on the front of the silicon wafer. The passivation layer includes a second tunneling silicon oxide layer and an N-type second doped amorphous silicon layer arranged in sequence; the thickness of the second tunneling silicon oxide layer is 1 nm, and the thickness of the second doped amorphous silicon layer is 5 nm, which is prepared by a tube-type PECVD method.

[0143] The anti-reflection layer is a stack of silicon nitride and silicon oxynitride arranged in sequence. The thickness ratio of silicon nitride to silicon oxynitride in the stack is 7:3, and the total thickness of the stack is 100 nm, which is formed by the tube PECVD method.

[0144] S6. After removing the bypass plating layer, perform oxidation cleaning to obtain a clean interface;

[0145] Specifically, use a chain cleaning machine to remove the anti-reflection layer bypass plating. The solution for removing the film layer is an aqueous solution containing hydrofluoric acid. The mass concentration of hydrofluoric acid is 6%, the reaction temperature is 25 °C, and the speed of the chain machine driving roller is 2.4 m / min.

[0146] Use a tank cleaning machine to remove the passivation layer bypass plating. The solution for removing the film layer is a mixed solution of potassium hydroxide and hydrogen peroxide. The mass concentration of potassium hydroxide is 3%, the mass concentration of hydrogen peroxide is 0.5%, the reaction temperature is 30 °C, and the reaction time is 150 s.

[0147] The steps of oxidation cleaning are as follows: perform first oxidation – first pickling – alkali cleaning – second oxidation – second pickling – slow lifting – drying in sequence.

[0148] The solution for the first oxidation is a mixed solution of ozone and hydrochloric acid. The concentration of ozone is 60 ppm, the mass concentration of hydrochloric acid is 0.5%, the reaction time is 300 s, and the reaction temperature is 25 °C. After the first oxidation, a relatively thick oxide layer will be formed on the silicon wafer interface to wrap the impurity contamination inside the oxide layer.

[0149] The solution for the first pickling is the first hydrofluoric acid solution. The mass concentration of hydrofluoric acid is 0.2%, the reaction temperature is room temperature, and the reaction time is 20 s. The first hydrofluoric acid solution for the first pickling can remove the oxide layer on the back of the silicon wafer in a short time.

[0150] The solution for the alkali cleaning is a mixed solution of ammonia water and H2O2. The mass concentration of ammonia water is 5%, the mass concentration of H2O2 is 4%, the reaction temperature is 70 °C, and the reaction time is 180 s. Alkali cleaning can neutralize the acid solution and remove the organic matter on the silicon wafer surface.

[0151] The solution for the second oxidation is a mixed solution of ozone and hydrochloric acid. The concentration of ozone is 30 ppm, the mass concentration of hydrochloric acid is 2%, the reaction time is 120 s, and the reaction temperature is 25 °C. After the second oxidation, an oxide layer will be formed on the silicon wafer interface to further wrap the impurities deeper inside the bulk silicon in the oxide layer.

[0152] The solution for the second pickling is the second hydrofluoric acid solution. The mass concentration of hydrofluoric acid is 2%, the reaction temperature is room temperature, and the reaction time is 80 s. The second pickling solution removes the oxide layer on the one hand and effectively chemically passivates the second semiconductor opening area on the other hand, reducing its interface state density.

[0153] S7. A second semiconductor layer is formed on the back surface. The second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type second doped amorphous silicon layer that are sequentially formed on the back surface.

[0154] The thickness of the intrinsic amorphous silicon layer is 10 nm, the thickness of the second doped amorphous silicon layer is 15 nm, and the effective doping concentration is 5e18 cm -3 .

[0155] S8. A second etching is performed on the polished area of the back surface of the S7 silicon wafer to remove the second semiconductor layer, forming a first semiconductor opening area that is arranged at intervals from the second semiconductor opening area.

[0156] S9. A transparent conductive film layer is formed to completely cover the back surface of the silicon wafer.

[0157] S10. A third etching is performed on a part of the transparent conductive film layer in the superimposed area between the first semiconductor opening area and the second semiconductor opening area on the back surface of the silicon wafer to form an insulating groove. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0158] S11. Metal electrodes are respectively formed on the outer surfaces of the corresponding areas of the first semiconductor opening area and the second semiconductor opening area on the back surface of the silicon wafer.

[0159] Example 2

[0160] The method of Example 1 is referred to, with the difference that in S2, the reaction time is adjusted so that the thickness of the mask layer is 50 nm.

[0161] Example 3

[0162] The method of Example 1 is referred to, with the difference that in S4, the hydrogen peroxide content is adjusted so that the mass concentration of hydrogen peroxide in the mixed solution containing hydrofluoric acid and hydrogen peroxide is 5%, and the concentration of hydrofluoric acid remains unchanged.

[0163] Example 4

[0164] The method of Example 1 is referred to, with the difference that in S4, the film-forming protective agent content is adjusted so that the mass concentration of the film-forming protective agent in the texturing solution is 0.5%, and the concentrations of other solutes remain unchanged.

[0165] Example 5

[0166] The method of Example 1 is referred to, with the difference that in S6, the ozone content is adjusted so that the ozone concentration in the mixed solution containing ozone and hydrochloric acid used for the first oxidation and the second oxidation is 50 ppm, and the concentrations of other solutes remain unchanged.

[0167] Example 6

[0168] It was carried out according to the method of Example 1, except that in S6, the hydrochloric acid content was adjusted so that the mass concentration of hydrochloric acid in the mixed solution containing ozone and hydrochloric acid used in the first oxidation was 1%, and the concentrations of other solutes remained unchanged.

[0169] Comparative Example 1

[0170] It was carried out according to the method of Example 1, except that in S2, the thickness of the mask layer was adjusted to 10 nm.

[0171] Comparative Example 2

[0172] It was carried out according to the method of Example 1, except that in the front side wrap-around coating removal, an aqueous hydrofluoric acid solution was used, that is, hydrogen peroxide was not added, and the concentration of hydrofluoric acid remained unchanged.

[0173] Comparative Example 3

[0174] It was carried out according to the method of Example 1, except that the film-forming protective agent was not added to the texturing solution.

[0175] Comparative Example 4

[0176] It was carried out according to the method of Example 1, except that after removing the anti-reflection layer wrap-around coating and the passivation layer wrap-around coating in S6, it was first alkali-washed and then oxidation-cleaned. The oxidation cleaning was carried out using a conventional cleaning solution: a mixed solution containing hydrofluoric acid, hydrochloric acid, ozone, and water, for one-step oxidation cleaning, replacing the multi-step oxidation cleaning (first oxidation, first pickling, alkali-washing, second oxidation, second pickling) in S6; among them, in the mixed solution containing hydrofluoric acid, hydrochloric acid, ozone, and water, the mass concentration of hydrofluoric acid was 2%, the mass concentration of hydrochloric acid was 1%, and the mass concentration of ozone was 60 ppm.

[0177] Comparative Example 5

[0178] It was carried out according to the method of Example 1, except that the second oxidation and the second pickling were not carried out during the oxidation cleaning.

[0179] Test Example

[0180] The back-contact batteries obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The fill factor was obtained through IV testing. The test method for the battery yield was: in a batch production, divided by a battery efficiency of 26.7%, the yield = the number of battery wafers with a yield ≥ 26.7% / the total number of wafers produced × 100%.

[0181] Table 1

[0182]

[0183] From the above results, it can be seen that compared with the comparative example, by adopting the embodiment scheme of the present invention, the process flow is directly shortened by two steps, the cost is low, and at the same time, the fill factor of the battery is increased, thereby improving the battery conversion efficiency and the yield. Among them, in Comparative Example 3, since the film-forming protective agent is not added, the PSG layer and the first semiconductor layer will be corroded during the texturing process, and there will be basically no high-efficiency battery chips, and the battery yield is extremely low.

[0184] Furthermore, according to Embodiment 1 and Embodiments 2-6, it can be seen that by adopting the preferred scheme of the present invention, it is more conducive to improving the fill factor of the battery, thereby improving the battery conversion efficiency and the yield.

[0185] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer in sequence, wherein the mask layer is a phosphorus-doped silicon oxide layer and the thickness of the phosphorus-doped silicon oxide layer is 20-60 nm, and a front-side coating layer is naturally formed at the same time; S3, etching an opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, first using a mixed solution containing hydrofluoric acid and hydrogen peroxide to remove the front side coating layer, then using a texturing solution containing a film-forming protective agent to perform texturing cleaning, and at the same time forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening area; S5, forming a passivation layer and an anti-reflection layer in sequence on the front surface; S6, removing the anti-reflection layer coating and the passivation layer coating, and then performing oxidation cleaning; the oxidation cleaning process includes sequentially performing a first oxidation, a first acid wash, an alkali wash, a second oxidation, and a second acid wash, the first oxidation and the second oxidation both use a mixed solution containing ozone and hydrochloric acid, the ozone concentration in the mixed solution containing ozone and hydrochloric acid is 20-80ppm, and the mass concentration of hydrochloric acid is 0.5%-4%; S7. Depositing a second semiconductor layer on the back side.

2. The method for preparing a back contact battery according to claim 1, characterized in that: In S4, the mass concentration of hydrofluoric acid in the mixed solution containing hydrofluoric acid and hydrogen peroxide is 10%-15%, and the mass concentration of hydrogen peroxide is 2%-10%; and / or, In S4, the conditions for removing the front side coating layer include: a reaction temperature of 20-35° C. and a reaction time of 60-240 s.

3. The method for preparing a back contact battery according to claim 1, characterized in that: The mass content of the film-forming protective agent in the S4 texturing solution is 0.1%-1%, and / or the film-forming protective agent is selected from sodium lignin sulfonate and / or sodium dodecylbenzene sulfonate.

4. The method for preparing a back contact battery according to claim 1, characterized in that: In S4, the texturing liquid also contains alkali and texturing additives, the mass content of the alkali is 1%-5%, and the mass content of the texturing additive is 0.1%-1%; And / or, the conditions for the texturing and cleaning in S4 include: the texturing time is 6-10 minutes, and the texturing temperature is 65°C-85°C.

5. The method for preparing a back contact battery according to claim 1, characterized in that: The process of removing the anti-reflection layer and the passivation layer in S6 includes: firstly removing the anti-reflection layer by using an aqueous solution containing hydrofluoric acid, and then removing the passivation layer by using a mixed solution containing alkali and hydrogen peroxide; wherein the mass concentration of hydrofluoric acid in the aqueous solution containing hydrofluoric acid is 5%-10%, the mass concentration of alkali in the mixed solution containing alkali and hydrogen peroxide is 2%-5%, and the mass concentration of hydrogen peroxide is 0.2%-1%; and / or, In S6, a chain cleaning machine is used to remove the anti-reflection layer, and the conditions for removing the anti-reflection layer include: a reaction temperature of 20-35°C, and a chain machine drive roller speed of 1.2-3.0m / min; a tank cleaning machine is used to remove the passivation layer, and the conditions for removing the passivation layer include: a reaction temperature of 25-35°C, and a reaction time of 60-240s.

6. The method for preparing a back contact battery according to claim 1, characterized in that: In S6, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used in the first oxidation is greater than the ozone concentration in the mixed solution containing ozone and hydrochloric acid used in the second oxidation.

7. The method for preparing a back contact battery according to claim 6, characterized in that: In S6, the ozone concentration in the mixed solution containing ozone and hydrochloric acid used in the first oxidation is 50-80ppm, and the mass concentration of hydrochloric acid is 0.5%-4%; the ozone concentration in the mixed solution containing ozone and hydrochloric acid used in the second oxidation is 20-50ppm, and the mass concentration of hydrochloric acid is 0.5%-4%; and / or, In S6, the conditions for the first oxidation include: reaction time of 60-500 s, reaction temperature of 20-25°C; the conditions for the second oxidation include: reaction time of 60-240 s, reaction temperature of 20-25°C.

8. The method for preparing a back contact battery according to claim 1, characterized in that: In S6, the first pickling adopts a first hydrofluoric acid solution with a hydrofluoric acid mass concentration of 0.1%-1%, and the second pickling adopts a second hydrofluoric acid solution with a hydrofluoric acid mass concentration of 1%-5%; the reaction time of the first pickling is 15-30s, and the reaction time of the second pickling is 30-120s; And / or, in S6, the hydrofluoric acid concentration of the first hydrofluoric acid solution is lower than the hydrofluoric acid concentration of the second hydrofluoric acid solution.

9. The method for preparing a back contact battery according to claim 1, characterized in that: In S6, the alkali washing uses a mixed solution containing ammonia water or a strong base and H2O2, the mass concentration of ammonia water or a strong base is 2%-5%, and the mass concentration of H2O2 is 3%-5%; the conditions of the alkali washing include: a reaction temperature of 60-80°C, and a reaction time of 120-240s; and / or, In S6, the oxidation cleaning also includes the process of slow pulling and drying in sequence after the second pickling.

10. The method for preparing a back contact battery according to claim 1, characterized in that: In S2, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, the first tunneling oxide layer has a thickness of 1-2 nm, and the first doped polysilicon layer has a thickness of 80-200 nm; and / or, The first semiconductor layer and the phosphorus-doped silicon oxide layer are formed by sequentially depositing and high-temperature annealing using a tubular PECVD method, with the deposition temperature controlled at 400-500°C and the high-temperature annealing temperature at 850-950°C.

11. The method for preparing a back contact battery according to claim 1 or 10, characterized in that: The formation process of the first semiconductor layer and the mask layer in S2 includes: in the first stage, nitrous oxide is introduced, the glow is turned on, and the first tunneling oxide layer is formed; in the second stage, silane, phosphine and hydrogen are introduced, the glow is turned on, and the first phosphorus-doped amorphous silicon layer with a thickness of 30-80nm is formed; in the third stage, silane, phosphine and hydrogen are introduced, the glow is turned on, and the second phosphorus-doped amorphous silicon layer with a thickness of 40-120nm is formed, and the phosphorus doping amount of the second phosphorus-doped amorphous silicon layer is higher than the phosphorus doping amount of the first phosphorus-doped amorphous silicon layer; in the fourth stage, silane and nitrous oxide are introduced, the glow is turned on, and the silicon oxide layer with a thickness of 20-60nm is formed; then, high-temperature annealing is performed under the condition of nitrogen introduction, and the high-temperature annealing temperature is 850-950°C, each phosphorus-doped amorphous silicon layer forms a first phosphorus-doped polycrystalline silicon layer under the high-temperature annealing condition, and the silicon oxide layer forms a phosphorus-doped silicon oxide layer under the high-temperature annealing condition; wherein, The laughing gas flow rate in the first stage is 8000-30000sccm; the silane flow rate in the second stage is 1000-3000sccm, the phosphine flow rate is 100-500sccm, and the hydrogen flow rate is 7000-9000sccm; the silane flow rate in the third stage is 1000-3000sccm, the phosphine flow rate is 200-1000sccm, and the hydrogen flow rate is 7000-9000sccm; the silane flow rate in the fourth stage is 500-1000sccm, and the laughing gas flow rate is 5000-8000sccm; and / or, In the first stage, the reaction pressure is controlled to be 100-200Pa, the power is 3000-10000W, and the reaction time is 20-100s; in the second stage, the reaction pressure is controlled to be 300-500Pa, the power is 2000-4000W, and the reaction time is 300-1500s; in the third stage, the reaction pressure is controlled to be 300-500Pa, the power is 3000-7000W, and the reaction time is 200-1000s; in the fourth stage, the reaction pressure is controlled to be 300-500Pa, the power is 3000-7000W, and the reaction time is 50-200s; in high temperature annealing, the annealing pressure is controlled to be 5000-50000Pa, the annealing time is 60-120min, and the nitrogen flow rate is 2000sccm-8000sccm.

12. The method for preparing a back contact battery according to claim 1, characterized in that: In S4, the passivation layer includes a second tunneling oxide layer and a second doped amorphous silicon layer; the thickness of the second tunneling oxide layer is 1-2 nm, and the thickness of the second doped amorphous silicon layer is 1-10 nm; and / or, The anti-reflection layer is a stacked layer comprising silicon nitride and silicon oxynitride arranged in sequence, the thickness ratio of silicon nitride to silicon oxynitride in the stacked layer is 1-3:1, and the total thickness of the stacked layer is 70-120nm.

13. The method for preparing a back contact battery according to claim 1, characterized in that: In S4, the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer sequentially formed on the back side, the intrinsic silicon layer has a thickness of 5-15 nm, and the second doped silicon layer has a thickness of 5-20 nm; and / or, The method for preparing the back contact battery further comprises the following steps: S8, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S9, depositing a conductive film layer on the back surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove; S11, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

14. A back contact battery, characterized in that: The back contact battery is prepared by the method for preparing a back contact battery as claimed in any one of claims 1 to 13.

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