Epitaxial structure, manufacturing method thereof and LED chip

Abstract

The invention provides an epitaxial structure and a manufacturing method thereof, and an LED chip, and the epitaxial structure delays electrons from an N-type semiconductor layer through a built-in electric field constructed by a first electric field modulation layer in the growth direction, so as to achieve the effect of electron deceleration, and improve the performance of the epitaxial structure. The spatial distribution of the V-pits structures in the V-pits forming layer in the active region can be regulated and controlled through the first electric field modulation layer so as to reduce electric leakage channels. Besides, the direction of the built-in electric field of the first electric field modulation layer is opposite to the injection direction of the holes, so that the holes can be stored in the V-pits structure under the action of the built-in electric field of the first electric field modulation layer, and the recombination probability of carriers in the active region is further effectively improved.

Description

Technical Field

[0001] The invention relates to the field of light emitting diodes, and in particular to an epitaxial structure and a manufacturing method thereof, and an LED chip. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor electronic component that can emit light. Epitaxial wafers are the primary finished product in the LED manufacturing process. Existing LED epitaxial wafers include substrates, N-type semiconductor layers, active layers, and P-type semiconductor layers. The substrate is used to provide a growth surface for the epitaxial material, the N-type semiconductor layer is used to provide electrons for compound luminescence, the P-type semiconductor layer is used to provide holes for compound luminescence, and the active region is used for radiation compound luminescence of electrons and holes.

[0003] Due to their excellent physical and chemical properties (large bandgap, high breakdown electric field, high electron saturation mobility, etc.), III-V compound materials have received extensive attention and applications in the fields of electricity and optics, such as the popular Micro and Mini LEDs on the market. However, in real applications, due to the different physical properties of electrons and holes (relative mass / migration rate differences, etc.), it is inevitable to cause carrier transport imbalance, that is, electrons with relatively small mass have a high migration rate and are prone to electron leakage; holes with relatively large mass have a low migration rate and are prone to insufficient injection, resulting in unbalanced carrier injection, which limits the improvement of device luminous efficiency. Therefore, reducing electron overflow and increasing hole injection have become important ways to improve LED luminous efficiency.

[0004] Currently, an electron blocking layer is usually inserted into the active region near the P-type semiconductor layer. However, while the electron blocking layer blocks electron overflow, it also inevitably blocks hole injection. Thus, there is still a carrier injection imbalance phenomenon to varying degrees.

[0005] In view of this, the inventor specially designed an epitaxial structure and a method for manufacturing the same, which resulted in the present case. Summary of the invention

[0006] The object of the present invention is to provide an epitaxial structure and a manufacturing method thereof, and an LED chip, so as to solve the problem of unbalanced carrier injection in the existing LED chip.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] An epitaxial structure comprising:

[0009] A substrate and an epitaxial stack arranged on the surface of the substrate; the epitaxial stack at least comprises an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region and a P-type semiconductor layer which are grown in sequence;

[0010] Wherein, the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

[0011] Preferably, the first electric field modulation layer includes a first N-type layer, a first undoped layer and a first P-type layer stacked in sequence.

[0012] Preferably, a first barrier layer is provided on a surface of the first P-type layer on a side away from the first non-doped layer.

[0013] Preferably, the first barrier layer comprises an intrinsic semiconductor layer, and a thickness of the first barrier layer is not greater than a thickness of the first non-doped layer.

[0014] Preferably, the thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first undoped layer is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0015] Preferably, the N-type semiconductor layer includes an N-type GaN layer, and the P-type semiconductor layer includes a P-type GaN layer; then the first N-type layer includes an N-type GaN layer, the first undoped layer includes an AlInGaN layer, and the first P-type layer includes a P-type GaN layer.

[0016] Preferably, the first barrier layer comprises an AlInGaN layer.

[0017] Preferably, a second electric field modulation layer is further provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in a reverse growth direction through a heterojunction.

[0018] Preferably, the second electric field modulation layer includes a second P-type layer, a second undoped layer and a second N-type layer stacked in sequence.

[0019] Preferably, a second barrier layer is provided on a surface of the second N-type layer on a side away from the second non-doped layer.

[0020] Preferably, the second barrier layer comprises an intrinsic semiconductor layer, and a thickness of the second barrier layer is not greater than a thickness of the second non-doped layer.

[0021] Preferably, the second P-type layer includes a P-type GaN layer, the second undoped layer includes an AlInGaN layer, and the second N-type layer includes an N-type GaN layer.

[0022] Preferably, the second barrier layer comprises an AlInGaN layer.

[0023] Preferably, the V-pits forming layer forms V-pits by utilizing the difference in growth rates of Ga atoms on different planes in an InGaN / GaN superlattice structure.

[0024] The present invention also provides a method for manufacturing an epitaxial structure, comprising the following steps:

[0025] providing a substrate;

[0026] Growing an epitaxial stack on the surface of the substrate, wherein the epitaxial stack at least includes an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer that are grown in sequence;

[0027] Wherein, the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

[0028] Preferably, the first electric field modulation layer includes a first N-type layer, a first undoped layer and a first P-type layer stacked in sequence.

[0029] Preferably, a first barrier layer is provided on a surface of the first P-type layer on a side away from the first non-doped layer;

[0030] And the thickness of the first barrier layer is not greater than the thickness of the first non-doped layer.

[0031] Preferably, a second electric field modulation layer is further provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in a reverse growth direction through a heterojunction.

[0032] Preferably, the second electric field modulation layer includes a second P-type layer, a second undoped layer and a second N-type layer stacked in sequence.

[0033] Preferably, a second barrier layer is provided on a surface of the second N-type layer on a side away from the second non-doped layer;

[0034] And the thickness of the second barrier layer is not greater than the thickness of the second non-doped layer.

[0035] The present invention provides an LED chip, comprising:

[0036] An epitaxial structure comprising any one of the above items;

[0037] An N-type electrode, the N-type electrode forming contact with the N-type semiconductor layer;

[0038] A P-type electrode is in contact with the P-type semiconductor layer.

[0039] It can be known from the above technical scheme that the epitaxial structure provided by the present invention includes: a substrate and an epitaxial stack arranged on the surface of the substrate; the epitaxial stack at least includes an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region and a P-type semiconductor layer that are stacked and grown in sequence; wherein the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction. Based on this, the epitaxial structure delays the electrons from the N-type semiconductor layer through the built-in electric field along the growth direction constructed by the first electric field modulation layer to achieve the effect of electron deceleration, and the spatial distribution of the V-pits structure in the V-pits formation layer in the active region can be regulated by the first electric field modulation layer to reduce the leakage channel. In addition, because the built-in electric field direction of the first electric field modulation layer is opposite to the injection direction of the holes, the holes can be retained in the V-pits structure through the built-in electric field of the first electric field modulation layer, thereby effectively improving the recombination probability of carriers in the active region.

[0040] Secondly, the first electric field modulation layer includes a first N-type layer, a first non-doped layer and a first P-type layer stacked in sequence to form the built-in electric field; further, a first blocking layer is provided on the surface of the first P-type layer on the side away from the first non-doped layer. Through the synergistic effect of the first blocking layer and the built-in electric field of the first electric field modulation layer, holes can be blocked from penetrating into the N-type semiconductor layer through the V-pits, further improving the retention capacity of holes in the V-pits structure; at the same time, the first blocking layer can also avoid the formation of a PN junction in the recombination area caused by the direct contact between the first electric field modulation layer and the active area.

[0041] Then, by setting "the first barrier layer includes an intrinsic semiconductor layer, and the thickness of the first barrier layer is not greater than the thickness of the first non-doped layer"; further, the thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first non-doped layer is D4, then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2. In this way, the influence of the first barrier layer on the interface charge due to being too thin can be avoided, and at the same time, the strain between the materials due to being too thick can be avoided, which can also prevent the crystal quality of the epitaxial structure from being deteriorated due to the increase of strain between the materials.

[0042] Based on the above configuration, further, a second electric field modulation layer is provided between the active region and the P-type semiconductor layer in the present application. The second electric field modulation layer generates a built-in electric field in the reverse growth direction through the heterojunction to accelerate the holes originating from the P-type semiconductor layer. In this way, it can cooperate with the first electric field modulation layer to increase the probability of radiation recombination of carriers in the active region.

[0043] Finally, the second electric field modulation layer includes a second P-type layer, a second non-doped layer and a second N-type layer stacked in sequence; further, a second blocking layer is provided on the surface of the second N-type layer on the side away from the second non-doped layer, so that hole injection can be increased while achieving an electron blocking effect.

[0044] The present invention also provides a method for preparing an LED epitaxial structure, which is simple to operate and easy to implement while achieving the above technical effects.

[0045] The present invention also provides an LED chip, which is formed by utilizing the aforementioned LED epitaxial structure and has a simple structure and greatly improves the luminous efficiency and reliability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the structure of an epitaxial structure provided by an embodiment of the present invention;

[0048] Figure 2 A schematic structural diagram of a first electric field modulation layer provided in an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of a V-pits structure and its internal electric field provided by an embodiment of the present invention;

[0050] Figure 4 A schematic structural diagram of a second electric field modulation layer provided in an embodiment of the present invention;

[0051] Figures 5 to 13 A schematic structural diagram corresponding to the steps of the method for manufacturing an epitaxial structure provided in an embodiment of the present invention;

[0052] Explanation of symbols in the figure:

[0053] 1. Substrate;

[0054] 2. Buffer layer;

[0055] 3. Unintentional doping layer;

[0056] 4. N-type semiconductor layer;

[0057] 5. V-pits formation layer, 51. InGaN layer, 52. GaN layer, 53. V-pits structure;

[0058] 6. a first electric field modulation layer, 61. a first N-type layer, 62. a first non-doped layer, 63. a first P-type layer, 64. a first blocking layer;

[0059] 7. Active region, 71. Quantum barrier, 72. Quantum well;

[0060] 8. a second electric field modulation layer, 81. a second N-type layer, 82. a second non-doped layer, 83. a second P-type layer, 84. a second blocking layer;

[0061] 9. P-type semiconductor layer;

[0062] 10. Penetrating dislocation line;

[0063] E1, electric field direction of the first electric field modulation layer;

[0064] E2, the electric field direction of the second electric field modulation layer;

[0065] h”, the moving direction of the hole. DETAILED DESCRIPTION

[0066] To make the content of the present invention clearer, the content of the present invention is further described below in conjunction with the accompanying drawings. The present invention is not limited to this specific embodiment. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0067] like Figure 1 As shown, an epitaxial structure comprises:

[0068] A substrate 1 and an epitaxial stack arranged on the surface of the substrate 1; the epitaxial stack at least comprises an N-type semiconductor layer 4, a V-pits forming layer 5, a first electric field modulation layer 6, an active region 7 and a P-type semiconductor layer 9 which are grown in sequence;

[0069] The first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction.

[0070] It is worth mentioning that the type of the substrate 1 is not limited in this embodiment. For example, the substrate 1 includes any one of sapphire, silicon carbide, silicon, gallium nitride, and aluminum nitride.

[0071] Further, based on the above embodiments of the present invention, Figure 2 As shown, the first electric field modulation layer 6 includes a first N-type layer 61 , a first non-doped layer 62 and a first P-type layer 63 which are stacked in sequence.

[0072] Further, based on the above embodiment of the present invention, a first barrier layer 64 is provided on a surface of the first P-type layer 63 which is away from the first non-doped layer 62 .

[0073] Further, based on the above embodiment of the present invention, the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first undoped layer 62 .

[0074] Further, based on the above-mentioned embodiment of the present invention, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first undoped layer 62 is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0075] Further, based on the above-mentioned embodiment of the present invention, the N-type semiconductor layer 4 includes an N-type GaN layer, and the P-type semiconductor layer 9 includes a P-type GaN layer; then the first N-type layer 61 includes an N-type GaN layer, the first undoped layer 62 includes an AlInGaN layer, and the first P-type layer 63 includes a P-type GaN layer.

[0076] Further, based on the above embodiment of the present invention, the first barrier layer 64 includes an AlInGaN layer.

[0077] Furthermore, based on the above-mentioned embodiment of the present invention, a second electric field modulation layer 8 is further provided between the active region 7 and the P-type semiconductor layer 9, and the second electric field modulation layer 8 generates a built-in electric field in the reverse growth direction through a heterojunction.

[0078] Further, based on the above embodiments of the present invention, Figure 4 As shown, the second electric field modulation layer 8 includes a second P-type layer 83 , a second non-doped layer 82 and a second N-type layer 81 which are stacked in sequence.

[0079] Furthermore, based on the above embodiment of the present invention, a second barrier layer 84 is provided on a surface of the second N-type layer 81 which is away from the second non-doped layer 82 .

[0080] Further, based on the above embodiment of the present invention, the second barrier layer 84 includes an intrinsic semiconductor layer, and the thickness of the second barrier layer 84 is not greater than the thickness of the second undoped layer 82 .

[0081] Further, based on the above embodiment of the present invention, the second P-type layer 83 includes a P-type GaN layer, the second undoped layer 82 includes an AlInGaN layer, and the second N-type layer 81 includes an N-type GaN layer.

[0082] Further, based on the above embodiment of the present invention, the second barrier layer 84 includes an AlInGaN layer.

[0083] Further, based on the above-mentioned embodiment of the present invention, the V-pits forming layer 5 forms V-pits by utilizing the difference in growth rates of Ga atoms on different planes in the InGaN / GaN superlattice structure.

[0084] The embodiment of the present invention also provides a method for manufacturing an epitaxial structure, wherein the equipment used is MOCVD, trimethyl / ethyl gallium TMGa / TEGa, trimethyl aluminum TMAl, and ammonia NH3 are Ga source, Al source, and nitrogen source respectively, N2 is used as a carrier gas, and the N-type and P-type doping sources are silane SiH4 and bis(cyclopentadienyl)magnesium CP2Mg respectively, including the following:

[0085] S01, such as Figure 5 As shown, a substrate 1 is provided;

[0086] It is worth mentioning that the type of the substrate 1 is not limited in this embodiment. For example, the substrate 1 includes any one of sapphire, silicon carbide, silicon, gallium nitride, and aluminum nitride.

[0087] S02, such as Figure 6 As shown, a buffer layer 2, an unintentionally doped layer 3 and an N-type semiconductor layer 4 are grown on the surface of the substrate 1;

[0088] Furthermore, based on the above-mentioned embodiments of the present invention, the N-type semiconductor layer 4 includes a superlattice structure composed of an AlGaN layer and an N-type GaN layer, so that under the premise of ensuring that the N-type semiconductor layer 4 provides electrons, the superlattice structure can be used to further block dislocations and improve the crystal quality, while discontinuous doping (i.e., doped / undoped / doped / undoped state) can be used to further enhance the current expansion capability.

[0089] Further, based on the above embodiment of the present invention, the N-type semiconductor layer 4 has a threading dislocation line.

[0090] Specifically, in this step, the substrate 1 is placed in a MOCVD reaction chamber, and high-purity hydrogen is introduced for hydrogenation for about 5 minutes at a temperature of about 1100°C. The temperature is then lowered to about 950°C to 970°C, and an Al source and a nitrogen source are introduced to grow an undoped AlN buffer layer 2 with a thickness of about 10nm to 20nm.

[0091] Continue to raise the temperature to 1000℃-1150℃, turn off the Al source, introduce the Ga source, and grow a 2um-3um undoped GaN layer. The purpose is to reduce the lattice mismatch between the substrate 1 and the subsequent grown film layer material by growing a high-quality unintentionally doped layer 3.

[0092] Then, the temperature is adjusted to 980-1020 degrees, and an Al source is introduced to grow an AlGaN layer with a thickness of 10-20nm; then, the Al source is turned off, and silane is introduced to grow a 5-10nm thick Si-doped GaN layer (i.e., an N-type GaN layer), wherein the Si doping concentration is 5-10*10 18 cm -3 Finally, the above cycle is repeated, the growth cycle is N, N is 10 to 20, and an N-type semiconductor layer 4 is formed.

[0093] S03, such as Figure 7 As shown, a V-pits forming layer 5 is grown on the surface of the N-type semiconductor layer 4;

[0094] Further, based on the above-mentioned embodiment of the present invention, the V-pits forming layer 5 forms a V-pits structure 53 by utilizing the growth rate difference of Ga atoms on different planes in the InGaN / GaN superlattice structure. And the V-pits structure 53 is formed on the top of the threading dislocation line 10 to form a leakage channel.

[0095] Specifically, in this step, the temperature is lowered to 800-850 degrees, the Al source and silane are turned off, the Ga source and nitrogen source are introduced, and the InGaN layer 51 and the GaN layer 52 (such as Figure 8 As shown in FIG. 1 ), a 5-10 period InGaN / GaN superlattice structure is grown; a threading dislocation line is formed, thereby generating a tip starting point of the V-pits. It should be emphasized that in this embodiment, there is no specific limitation on the slope and height of the V-pits.

[0096] S04, such as Fig. 9 As shown, a first electric field modulation layer 6 is grown, wherein the first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction;

[0097] Further, based on the above embodiments of the present invention, Figure 2 As shown, the first electric field modulation layer 6 includes a first N-type layer 61 , a first non-doped layer 62 and a first P-type layer 63 which are stacked in sequence.

[0098] Further, based on the above embodiment of the present invention, a first barrier layer 64 is provided on a surface of the first P-type layer 63 which is away from the first non-doped layer 62 .

[0099] Further, based on the above embodiment of the present invention, the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first undoped layer 62 .

[0100] Further, based on the above-mentioned embodiment of the present invention, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first undoped layer 62 is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0101] Further, based on the above-mentioned embodiment of the present invention, the N-type semiconductor layer 4 includes an N-type GaN layer, and the P-type semiconductor layer 9 includes a P-type GaN layer; then the first N-type layer 61 includes an N-type GaN layer, the first undoped layer 62 includes an AlInGaN layer, and the first P-type layer 63 includes a P-type GaN layer.

[0102] Further, based on the above embodiment of the present invention, the first barrier layer 64 includes an AlInGaN layer.

[0103] Specifically, in this step, SiH4 is introduced with a doping concentration of 5-10*10 18 cm -3 , an N-type GaN layer with a thickness of 1-5nm is formed to obtain the first N-type layer 61; then, SiH4 is turned off, Al source and In source are introduced, and an undoped AlInGaN layer with a thickness of 1-3nm is grown to obtain the first non-doped layer 62; then, Al source and In source are turned off, Cp2Mg is introduced, and a thickness of 1-5nm is grown, and a doping concentration of 5-10*10 17 cm -3 A P-type GaN layer is formed to obtain the first P-type layer 63.

[0104] Finally, Cp2Mg is turned off, and Al source and In source are introduced to grow an undoped AlInGaN layer with a thickness of 1-2 nm to obtain the first barrier layer 64 .

[0105] S05, such as Fig.10 As shown, an active region 7 is grown;

[0106] Further, based on the above embodiments of the present invention, Fig.11 As shown, the active region 7 includes a plurality of quantum barrier 71 layers and quantum well 72 layers stacked alternately.

[0107] Specifically, in this step: the temperature is lowered to 700-800 degrees, the Al source and the In source are turned off, and a GaN quantum barrier 71 layer with a thickness of 7nm to 16nm is grown; then the In source is introduced to grow an InGaN quantum well 72 layer with a thickness of 1nm to 5nm; finally, the above cycle is repeated, the growth cycle is N, N is 6 to 15, and the active area 7 is formed.

[0108] S06, such as Fig.12As shown, a second electric field modulation layer 8 is grown, and the second electric field modulation layer 8 generates a built-in electric field in the reverse growth direction through a heterojunction;

[0109] Further, based on the above embodiments of the present invention, Figure 4 As shown, the second electric field modulation layer 8 includes a second P-type layer 83 , a second non-doped layer 82 and a second N-type layer 81 which are stacked in sequence.

[0110] Furthermore, based on the above embodiment of the present invention, a second barrier layer 84 is provided on a surface of the second N-type layer 81 which is away from the second non-doped layer 82 .

[0111] Further, based on the above embodiment of the present invention, the second barrier layer 84 includes an intrinsic semiconductor layer, and the thickness of the second barrier layer 84 is not greater than the thickness of the second undoped layer 82 .

[0112] Further, based on the above embodiment of the present invention, the second P-type layer 83 includes a P-type GaN layer, the second undoped layer 82 includes an AlInGaN layer, and the second N-type layer 81 includes an N-type GaN layer.

[0113] Further, based on the above embodiment of the present invention, the second barrier layer 84 includes an AlInGaN layer.

[0114] Specifically, in this step, Cp2Mg is introduced with a doping concentration of 5-10*10 17 cm -3 , a P-type GaN layer with a thickness of 1-5nm is formed to obtain the second P-type layer 83; then, Cp2Mg is turned off, Al source and In source are introduced, and an undoped AlInGaN layer with a thickness of 1-3nm is grown to obtain the second undoped layer 82; then, Al source and In source are turned off, SiH4 is introduced, and a thickness of 1-5nm is grown, and the doping concentration is 5-10*10 18 cm -3 An N-type GaN layer is formed to obtain the second N-type layer 81.

[0115] Finally, SiH4 is turned off, and Al source and In source are introduced to grow an undoped AlInGaN layer with a thickness of 1-2 nm to obtain the second barrier layer 84.

[0116] S07, such as Fig.13 As shown, a P-type semiconductor layer 9 is manufactured;

[0117] Specifically, on the basis of the above steps, in this step, the temperature is adjusted to 900-1000°C, and TMGa source and bismuthocene magnesium are introduced to grow a P-type GaN layer with a thickness of 10-50nm and a magnesium doping concentration of 5-10*10 18 cm-3 ; and annealing at 850-900°C for 20 to 30 minutes in a N2 atmosphere to finally form a P-type semiconductor layer 9.

[0118] An embodiment of the present invention further provides an LED chip, comprising:

[0119] An epitaxial structure comprising any one of the above items;

[0120] An N-type electrode, the N-type electrode is in contact with the N-type semiconductor layer 4;

[0121] A P-type electrode, wherein the P-type electrode is in contact with the P-type semiconductor layer 9 .

[0122] It can be known from the above technical scheme that the epitaxial structure provided by the embodiment of the present invention includes: a substrate 1 and an epitaxial stack arranged on the surface of the substrate 1; the epitaxial stack at least includes an N-type semiconductor layer 4, a V-pits formation layer 5, a first electric field modulation layer 6, an active area 7 and a P-type semiconductor layer 9 that are stacked and grown in sequence; wherein the first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction. Based on this, the epitaxial structure delays the electrons from the N-type semiconductor layer 4 through the built-in electric field along the growth direction constructed by the first electric field modulation layer 6 to achieve the effect of electron deceleration, and the spatial distribution of the V-pits structure in the V-pits formation layer 5 in the active area 7 can also be regulated by the first electric field modulation layer 6 to reduce leakage channels. In addition, as Figure 3 As shown, since the built-in electric field direction E1 of the first electric field modulation layer 6 is opposite to the hole injection direction h″, the holes can be retained in the structure of the V-pits structure 53 through the built-in electric field of the first electric field modulation layer 6, thereby effectively improving the recombination probability of carriers in the active region 7.

[0123] Secondly, the first electric field modulation layer 6 includes a first N-type layer 61, a first non-doped layer 62 and a first P-type layer 63 stacked in sequence to form the built-in electric field; further, a first blocking layer 64 is provided on the surface of the first P-type layer 63 facing away from the first non-doped layer 62. Through the synergistic effect of the first blocking layer 64 and the built-in electric field of the first electric field modulation layer 6, holes can be blocked from penetrating into the N-type semiconductor layer 4 through the V-pits 53, further improving the retention capacity of holes in the V-pits structure 53; at the same time, the first blocking layer 64 can also avoid the formation of a PN junction in the recombination area caused by the direct contact between the first electric field modulation layer 6 and the active area 7.

[0124] Then, by setting "the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first non-doped layer 62"; further, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first non-doped layer 62 is D4, then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2. In this way, the influence of the first barrier layer 64 on the interface charge due to its excessive thinness can be avoided, and at the same time, the strain between the materials due to its excessive thickness can be avoided to increase, which can deteriorate the crystal quality of the epitaxial structure.

[0125] Based on the above configuration, further, a second electric field modulation layer 8 is provided between the active area 7 and the P-type semiconductor layer 9 in the present application. The second electric field modulation layer 8 generates a built-in electric field E2 in the reverse growth direction through the heterojunction to accelerate the holes originating from the P-type semiconductor layer 9, thereby cooperating with the first electric field modulation layer 6 to increase the radiation recombination probability of carriers in the active area 7.

[0126] Finally, the second electric field modulation layer 8 includes a second P-type layer 83, a second non-doped layer 82 and a second N-type layer 81 stacked in sequence; further, a second blocking layer 84 is provided on the surface of the second N-type layer 81 facing away from the second non-doped layer 82, so that hole injection can be increased while achieving an electron blocking effect.

[0127] The present invention also provides a method for preparing an LED epitaxial structure, which is simple to operate and easy to implement while achieving the above technical effects.

[0128] The present invention also provides an LED chip, which is formed by utilizing the aforementioned LED epitaxial structure and has a simple structure and greatly improves the luminous efficiency and reliability of the LED chip.

[0129] The device provided in the embodiment of the present invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference can be made to the corresponding contents in the aforementioned method embodiment. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the aforementioned systems, devices and units can all refer to the corresponding processes in the aforementioned method embodiment, and will not be repeated here.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0132] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial structure, characterized in that: include: A substrate and an epitaxial stack arranged on the surface of the substrate; the epitaxial stack at least comprises an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region and a P-type semiconductor layer which are grown in sequence; Wherein, the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

2. The epitaxial structure according to claim 1, characterized in that: The first electric field modulation layer includes a first N-type layer, a first non-doped layer and a first P-type layer stacked in sequence.

3. The epitaxial structure according to claim 2, characterized in that: A first barrier layer is provided on a surface of the first P-type layer on a side away from the first non-doped layer.

4. The epitaxial structure according to claim 3, characterized in that: The first barrier layer includes an intrinsic semiconductor layer, and a thickness of the first barrier layer is not greater than a thickness of the first non-doped layer.

5. The epitaxial structure according to claim 4, characterized in that: The thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first undoped layer is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

6. The epitaxial structure according to claim 2, characterized in that: The N-type semiconductor layer includes an N-type GaN layer, and the P-type semiconductor layer includes a P-type GaN layer; the first N-type layer includes an N-type GaN layer, the first undoped layer includes an AlInGaN layer, and the first P-type layer includes a P-type GaN layer.

7. The epitaxial structure according to claim 3, characterized in that: The first barrier layer includes an AlInGaN layer.

8. The epitaxial structure according to claim 1, characterized in that: A second electric field modulation layer is further provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in a reverse growth direction through a heterojunction.

9. The epitaxial structure according to claim 8, characterized in that: The second electric field modulation layer includes a second P-type layer, a second non-doped layer and a second N-type layer stacked in sequence.

10. The epitaxial structure according to claim 9, characterized in that: A second barrier layer is provided on a surface of the second N-type layer on a side away from the second non-doped layer.

11. The epitaxial structure according to claim 10, characterized in that: The second barrier layer includes an intrinsic semiconductor layer, and a thickness of the second barrier layer is not greater than a thickness of the second non-doped layer.

12. The epitaxial structure according to claim 9, characterized in that: The second P-type layer includes a P-type GaN layer, the second undoped layer includes an AlInGaN layer, and the second N-type layer includes an N-type GaN layer.

13. The epitaxial structure according to claim 10, characterized in that: The second barrier layer includes an AlInGaN layer.

14. The epitaxial structure according to claim 1, characterized in that: The V-pits forming layer forms V-pits by utilizing the difference in growth rates of Ga atoms on different surfaces in an InGaN / GaN superlattice structure.

15. A method for manufacturing an epitaxial structure, characterized in that: These include: providing a substrate; Growing an epitaxial stack on the surface of the substrate, wherein the epitaxial stack at least includes an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer that are grown in sequence; Wherein, the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

16. The method for manufacturing an epitaxial structure according to claim 15, characterized in that: The first electric field modulation layer includes a first N-type layer, a first non-doped layer and a first P-type layer stacked in sequence.

17. The method for manufacturing an epitaxial structure according to claim 16, characterized in that: A first barrier layer is provided on a surface of the first P-type layer on a side away from the first non-doped layer; And the thickness of the first barrier layer is not greater than the thickness of the first non-doped layer.

18. The method for manufacturing an epitaxial structure according to claim 15, characterized in that: A second electric field modulation layer is further provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in a reverse growth direction through a heterojunction.

19. The method for manufacturing an epitaxial structure according to claim 18, characterized in that: The second electric field modulation layer includes a second P-type layer, a second non-doped layer and a second N-type layer stacked in sequence.

20. The method for manufacturing an epitaxial structure according to claim 19, characterized in that: A second barrier layer is provided on a surface of the second N-type layer on a side away from the second non-doped layer; And the thickness of the second barrier layer is not greater than the thickness of the second non-doped layer.

21. An LED chip, characterized in that: include; The epitaxial structure according to any one of claims 1 to 14; An N-type electrode, the N-type electrode forming contact with the N-type semiconductor layer; A P-type electrode is in contact with the P-type semiconductor layer.

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