Display device

Abstract

There is provided a display device including: a base layer; a circuit layer on the base layer; and an element layer on the circuit layer and including a light emitting element and a hybrid element, in which the hybrid element includes: a hybrid anode electrode; a light receiving stack on the hybrid anode electrode; a light emitting stack on the light receiving stack; and a mixed cathode electrode on the light-emitting stack, in which the light-emitting element is configured to be turned on in a light-emitting mode and a light-receiving mode to emit light of a first color, in which the mixed element is configured to be turned on in the light-emitting mode to output light of a second color, and in which the mixed cathode electrode is configured to be turned on in the light-receiving mode to emit light of the second color. The mixing element is configured to be turned on in a light receiving mode to receive the first color light.

Description

Technical Field

[0001] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0002] The display device displays an image to provide information to the user, or provides various functions capable of organically communicating with the user, such as a function of sensing the user's input. Today, the display device includes a function of sensing the user's biometric information.

[0003] Biometric information may be recognized by using a capacitive method of sensing a change in capacitance formed between electrodes, an optical method of sensing incident light through a photo sensor, an ultrasonic method of sensing vibration using a piezoelectric body, and the like.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure relate to a display device having a function of recognizing biometric information.

[0006] Aspects of some embodiments of the present disclosure include a display device capable of recognizing biometric information while preventing a reduction in resolution.

[0007] According to some embodiments, a display device includes a base layer, a circuit layer on the base layer, and an element layer on the circuit layer and including a light emitting element and a mixing element.

[0008] According to some embodiments, a hybrid element includes a hybrid anode electrode, a light receiving stack on the hybrid anode electrode, a light emitting stack on the light receiving stack, and a hybrid cathode electrode on the light emitting stack.

[0009] According to some embodiments, in the light emitting mode and the light receiving mode, the light emitting element is turned on to emit the first color light. In the light emitting mode, the mixing element is turned on to output the second color light. In the light receiving mode, the mixing element is turned on to receive the first color light.

[0010] According to some embodiments, a display device includes a base layer, a circuit layer on the base layer, and an element layer on the circuit layer and including a light emitting element and a mixing element.

[0011] According to some embodiments, the circuit layer includes a pixel circuit connected to the light emitting element, a pixel circuit unit connected to the mixing element and identical in circuit structure to the pixel circuit, and a sensor circuit unit connected to the mixing element and the pixel circuit unit.

[0012] According to some embodiments, the hybrid element includes a light emitting unit turned on by the pixel circuit unit in a reverse bias state and a light receiving unit turned on by the sensor circuit unit in a forward bias state. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features according to the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0014] Figure 1 is a perspective view showing a display device according to some embodiments of the present disclosure.

[0015] Figure 2 is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0016] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0017] Figure 4 is an enlarged plan view of a partial area of ​​a display panel according to some embodiments of the present disclosure.

[0018] Figure 5A It is shown Figure 4 Circuit diagram of a green normal pixel shown in .

[0019] Figure 5B Is used to describe Figure 5A : A waveform diagram of the operation of a green normal pixel is shown in FIG.

[0020] Figure 5C It is shown Figure 4 Circuit diagram of a hybrid pixel shown in .

[0021] Figure 6 is a cross-sectional view showing a green normal pixel, a red normal pixel, a blue normal pixel, and a mixed pixel according to some embodiments of the present disclosure.

[0022] Fig. 7A is a diagram showing a case where a display panel according to some embodiments of the present disclosure operates in a light emitting mode.

[0023] Figure 7B is a diagram illustrating a case where a display panel according to some embodiments of the present disclosure operates in a light receiving mode.

[0024] Fig. 8A is a conceptual diagram illustrating a case where a hybrid pixel operates in a light emitting mode according to some embodiments of the present disclosure.

[0025] Figure 8B is a conceptual diagram illustrating a case where a hybrid pixel operates in a light receiving mode according to some embodiments of the present disclosure.

[0026] Fig. 9 is an enlarged plan view of a partial area of ​​a display panel according to some embodiments of the present disclosure.

[0027] Fig. 10A is a diagram showing a case where a display panel according to some embodiments of the present disclosure operates in a light emitting mode.

[0028] Fig. 10B is a diagram illustrating a case where a display panel according to some embodiments of the present disclosure operates in a light receiving mode. DETAILED DESCRIPTION

[0029] In the specification, the expression that a first component (or region, layer, part or portion) is "on", "connected to" or "coupled to" a second component means that the first component is directly on / directly connected to / directly coupled to the second component, or means that a third component is interposed between the first and second components.

[0030] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to effectively describe the technical content. The term "and / or" includes one or more combinations of related elements in each combination.

[0031] Although the terms "first", "second", etc. may be used to describe various components, these components should not be limited by the terms. The terms are only used to distinguish one component from another. For example, a first component may be referred to as a "second component" and similarly, a second component may be referred to as a "first component" without departing from the scope and spirit of the invention. The articles "a", "an", and "the" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0032] Additionally, the terms "below," "beneath," "on," "over," etc. are used to describe the relationship of components shown in the drawings. The terms are relative and are described with respect to the directions indicated in the drawings.

[0033] It will also be understood that the terms “includes,” “comprising,” “having,” etc. indicate the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0035] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure, Figure 2 is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0036] Reference Figure 1 and Figure 2 , the display device DD may be in the shape of a rectangle having short sides (or edges) parallel to the first direction DR1 and long sides (or edges) parallel to the second direction DR2 crossing the first direction DR1. According to some embodiments, the display device DD may have rounded (rounded) corners at the junctions between the short sides and the long sides. However, the embodiments according to the present disclosure are not limited thereto. For example, the display device DD may be implemented in various shapes (such as a circle and a polygon) or any other suitable shape according to the design of the display device DD.

[0037] The display device DD may be a device activated according to an electrical signal. The display device DD may include various embodiments. For example, the display device DD may be applied to an electronic device such as a smart watch, a tablet PC, a notebook computer, a computer, or a smart TV.

[0038] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the specification, the expression "when viewed from above a plane" or "in a plan view" may mean "when viewed from the third direction DR3".

[0039] An upper surface of the display device DD may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface IS.

[0040] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area where an image IM is displayed. The user visually perceives the image IM through the transmission area TA. According to some embodiments, the transmission area TA is shown in the shape of a quadrilateral whose vertices are round. However, this is provided as an example. The transmission area TA may be implemented in various shapes (e.g., circular, elliptical, or any other suitable shape according to the design of the display device DD), and may not be limited to any one embodiment.

[0041] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a given color. The border area BZA may surround the transmission area TA. In this way, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is provided as an example. The border area BZA may be positioned adjacent to only one side of the transmission area TA, or may be omitted.

[0042] The display device DD may sense an external input (e.g., a touch input) applied from the outside or from an external source. The external input may include various types of input provided from the outside of the display device DD. For example, in addition to contact by a part of a human body (such as a user's hand US_F) or contact by a separate device (e.g., an active pen or a digitizer), the external input may include an external input (e.g., hovering) applied in a state where the user's hand US_F approaches the display device DD or is close to the display device DD within a given distance. In addition, the external input may have various types such as a force type, a pressure type, a temperature type, and a light type.

[0043] The display device DD can sense the biometric information of the user applied from the outside. The biometric information sensing area capable of sensing the biometric information of the user can be set on the display surface IS of the display device DD. The biometric information sensing area can be set in the entire area of ​​the transmission area TA, or can be set in a partial area of ​​the transmission area TA. Examples of the present disclosure are Figure 1 It is shown in FIG. 1 that the entire transmission area TA is used as a biometric information sensing area.

[0044] The display device DD may include a window WM, a display module DM, and a case EDC. According to some embodiments, the appearance of the display device DD may be realized by combining the window WM and the case EDC.

[0045] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent material. For example, the window WM may include glass or plastic. The window WM may be a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other by an adhesive, or may have a glass substrate and a plastic film bonded to each other by an adhesive.

[0046] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0047] The display panel DP according to some embodiments of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Below, a description will be given in the case where the display panel DP is an organic light-emitting display panel.

[0048] Reference Figure 2 , the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to some embodiments of the present disclosure may be a flexible display panel. However, the embodiments of the present disclosure are not limited thereto. For example, the display panel DP may be a rigid display panel or a foldable display panel folded about a folding axis.

[0049] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0050] The circuit layer DP_CL is located on the base layer BL. The circuit layer DP_CL is located between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a circuit element. Below, the insulating layer included in the circuit layer DP_CL is referred to as an "intermediate insulating layer". The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include an ordinary pixel circuit included in each of a plurality of ordinary pixels for displaying an image. In addition, the circuit element may include a pixel circuit, a sensor circuit, etc. included in each of a plurality of hybrid pixels capable of identifying external information and displaying an image. The external information may be biometric information. As an example of the present disclosure, the sensor may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, an illuminance sensor, etc. In addition, the sensor may include an optical sensor that optically recognizes biometric information. The circuit layer DP_CL may also include a signal line connected to a pixel drive circuit and / or a sensor drive circuit.

[0051] The element layer DP_ED may include a common pixel PX (refer to Figure 3 ) in each of the light emitting elements and included in the hybrid pixel PXs (refer to Figure 3 ) in each of the above. According to some embodiments of the present disclosure, the hybrid element may emit light in a light emitting mode and may receive light in a light receiving mode. In the light receiving mode, the hybrid element may react to or sense light reflected by a user's fingerprint.

[0052] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The inorganic layer may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but is not particularly limited thereto according to the embodiments of the present disclosure. The organic layer may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0053] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly located on the encapsulation layer TFE. According to some embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by the same process as the display panel DP. That is, when the input sensing layer ISL is directly located on the display panel DP, the adhesive film is not located between the input sensing layer ISL and the encapsulation layer TFE. Optionally, the adhesive film may be located between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured by the same process as the display panel DP. For example, the input sensing layer ISL may be manufactured by a process independent of the process of the display panel DP, and may then be fixed to the upper surface of the display panel DP by an adhesive film.

[0054] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed input into a given input signal, and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input in a capacitive method. The display panel DP may receive an input signal from the input sensing layer ISL, and may generate an image corresponding to the input signal.

[0055] The display module DM may further include a color filter layer CFL. As an example of the present disclosure, the color filter layer CFL may be located on the input sensing layer ISL. However, the embodiments of the present disclosure are not limited thereto. The color filter layer CFL may be located between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0056] The structures of the input sensing layer ISL and the color filter layer CFL will be described in detail later.

[0057] The display device DD according to some embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the input sensing layer ISL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0058] The housing EDC is coupled to the window WM. The housing EDC is coupled to the window WM to provide a given internal space. The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. According to some embodiments, a battery module that supplies power required for the overall operation of the display device DD may be located between the display module DM and the housing EDC.

[0059] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0060] Reference Figure 3 , the display device DD includes a display panel DP, a panel driver and a driving controller 100. According to some embodiments of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400 and a readout circuit 500.

[0061] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image signal RGB according to the specification of the interface with the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0062] The data driver 200 receives the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into data signals and outputs the data signals to a plurality of data lines DL1 to DLm to be described later. The data signals refer to analog voltages corresponding to grayscale values ​​of the image data DATA.

[0063] The scan driver 300 receives a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS.

[0064] The voltage generator 400 generates voltages required for the operation of the display panel DP. According to some embodiments, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, and a reset voltage Vrst.

[0065] The display panel DP may include a transmissive area TA ( Figure 1 ) and the corresponding display area DA and the frame area BZA (in Figure 1 ) corresponds to a non-display area NDA (eg, outside the occupied area of ​​the display area DA or in the periphery of the display area DA).

[0066] The display panel DP may include a plurality of normal pixels PX located in the display area DA and a plurality of hybrid pixels PXs located in the display area DA. According to some embodiments of the present disclosure, each of the plurality of hybrid pixels PXs may be positioned adjacent to at least one of the normal pixels PX in the first direction DR1 or the second direction DR2. According to some embodiments of the present disclosure, the number of hybrid pixels PXs may be less than the number of normal pixels PX.

[0067] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn extend in the first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1. Here, n, m, and h are natural numbers of 1 or greater.

[0068] A plurality of normal pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. For example, each of the plurality of normal pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each normal pixel PX is not limited thereto and may be changed. A corresponding data line among the data lines DL1 to DLm is connected to each normal pixel PX. Here, the normal pixel PX is a pixel that is not connected to the readout lines RL1 to RLh.

[0069] A plurality of hybrid pixels PXs are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. Each of the plurality of hybrid pixels PXs may be electrically connected to four scan lines. One corresponding data line among the data lines DL1 to DLm and one corresponding readout line among the readout lines RL1 to RLh are electrically connected to each hybrid pixel PXs.

[0070] According to some embodiments of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 3 or 1 / 4 of the number of data lines DL1 to DLm.

[0071] The scan driver 300 may be located in the non-display area NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 outputs an initialization scan signal to the initialization scan lines SIL1 to SILn, and may output a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, in response to the first control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn, and may output a black scan signal to the black scan lines SBL1 to SBLn. Optionally, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0072] The emission driver 350 may be located in the non-display area NDA of the display panel DP. The emission driver 350 receives the second control signal ECS from the drive controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0073] The readout circuit 500 receives the fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive the sensing signal from the sensing lines RL1 to RLh in response to the fourth control signal RCS. The readout circuit 500 may process the sensing signal received from the sensing lines RL1 to RLh, and may provide the sensing signal S_FS as a processing result to the driving controller 100. The driving controller 100 may recognize the biometric information based on the sensing signal S_FS.

[0074] Figure 4 is an enlarged plan view of a partial area of ​​a display panel according to some embodiments of the present disclosure.

[0075] Reference Figure 4 , the display panel DP includes a plurality of normal pixels PXG, PXR and PXB and a plurality of hybrid pixels PXs.

[0076] A plurality of normal pixels PXG, PXR and PXB and a plurality of mixed pixels PXs may be grouped into a plurality of reference pixel units RPU. According to some embodiments of the present disclosure, each reference pixel unit RPU may include three normal pixels PXG, PXR and PXB and one mixed pixel PXs. The three normal pixels PXG, PXR and PXB may be a first normal pixel PXG (hereinafter referred to as a "green normal pixel"), a second normal pixel PXR (hereinafter referred to as a "red normal pixel") and a third normal pixel PXB (hereinafter referred to as a "blue normal pixel"). However, the number of normal pixels PXG, PXR and PXB included in each reference pixel unit RPU is not limited thereto. Optionally, each reference pixel unit RPU may include two normal pixels (i.e., a red normal pixel PXR and a blue normal pixel PXB) and two mixed pixels (i.e., a first mixed pixel PXs1 and a second mixed pixel PXs2 (hereinafter referred to as a "blue normal pixel"). Fig. 9 )).

[0077] The green normal pixel PXG includes a green light emitting element ED_G. The red normal pixel PXR includes a red light emitting element ED_R, and the blue normal pixel PXB includes a blue light emitting element ED_B. The hybrid pixel PXs includes a hybrid element HD_G. According to some embodiments of the present disclosure, the green light emitting element ED_G outputs a first color light (or a first green light) in a light emitting mode and a light receiving mode. The hybrid element HD_G outputs a second color light (or a second green light) in a light emitting mode and receives the first color light in a light receiving mode. The first color light and the second color light may be light within the same wavelength range (e.g., a green wavelength range).

[0078] The red light emitting element ED_R outputs a third color light (e.g., red light) different from the first color light, and the blue light emitting element ED_B outputs a fourth color light (e.g., blue light) different from the first color light and the third color light. In the light emitting mode, the red light emitting element ED_R and the blue light emitting element ED_B output the third color light and the fourth color light, respectively. However, in the light receiving mode, the red light emitting element ED_R and the blue light emitting element ED_B may be turned off and may not emit the third color light and the fourth color light, respectively.

[0079] The red light emitting element ED_R and the blue light emitting element ED_B may be repeatedly and alternately arranged in the first direction DR1. The green light emitting element ED_G and the mixed element HD_G may be repeatedly and alternately arranged in the first direction DR1. The red light emitting element ED_R is repeatedly arranged at a first column parallel to the second direction DR2, and the green light emitting element ED_G is repeatedly arranged at a second column parallel to the second direction DR2. The blue light emitting element ED_B is repeatedly arranged at a third column parallel to the second direction DR2, and the mixed element HD_G is repeatedly arranged at a fourth column parallel to the second direction DR2. The placement of the light emitting elements ED_G, ED_R, and ED_B is not limited thereto. For example, the red light emitting element ED_R and the blue light emitting element ED_B may be repeatedly and alternately arranged in the first direction DR1 and the second direction DR2.

[0080] According to some embodiments of the present disclosure, the size of the red light emitting element ED_R may be greater than or equal to the size of the green light emitting element ED_G. In addition, the size of the blue light emitting element ED_B may be greater than or equal to the size of the red light emitting element ED_R. The size of each of the light emitting elements ED_G, ED_R, and ED_B is not limited thereto and may be changed and applied differently. According to some embodiments of the present disclosure, the light emitting elements ED_G, ED_R, and ED_B may have the same size. The size of the mixing element HD_G may be equal to or different from the size of the green light emitting element ED_G.

[0081] The light-emitting elements ED_G, ED_R, and ED_B may have the same shape. According to some embodiments of the present disclosure, each of the light-emitting elements ED_G, ED_R, and ED_B may be in the shape of a rhombus. Alternatively, the light-emitting elements ED_G, ED_R, and ED_B may be in the shape of a polygon (e.g., one of an octagon, a square, and a rectangle) or a circle. However, the present disclosure is not limited thereto. For example, the light-emitting elements ED_G, ED_R, and ED_B may have different shapes. The mixing element HD_G and the green light-emitting element ED_G may have the same shape or different shapes. For example, the green light-emitting element ED_G and the mixing element HD_G may have the same size (or area), but may have different shapes. In addition, the green light-emitting element ED_G and the mixing element HD_G may have different sizes (or areas), but may have the same shape.

[0082] The green light emitting element ED_G is electrically connected to the green pixel circuit G_PD (or the first common pixel circuit). The red light emitting element ED_R is electrically connected to the red pixel circuit R_PD (or the second common pixel circuit). The blue light emitting element ED_B is electrically connected to the blue pixel circuit B_PD (or the third common pixel circuit). The red pixel circuit R_PD, the green pixel circuit G_PD and the blue pixel circuit B_PD may be sequentially arranged in the first direction DR1. The mixing element HD_G is electrically connected to the mixing circuit HD_C. The mixing circuit HD_C includes a pixel circuit unit P_PD and a sensor circuit unit O_SD. The mixing element HD_G is commonly connected to the pixel circuit unit P_PD and the sensor circuit unit O_SD.

[0083] The pixel circuit unit P_PD and the sensor circuit unit O_SD may be adjacent to each other in the first direction DR1. According to some embodiments of the present disclosure, the pixel circuit unit P_PD may be located between the blue pixel circuit B_PD and the sensor circuit unit O_SD.

[0084] Figure 5A is a circuit diagram showing a green normal pixel according to some embodiments of the present disclosure, Figure 5B Is used to describe Figure 5A : A waveform diagram of the operation of a green normal pixel is shown in FIG. Figure 5C It is shown Figure 4 Circuit diagram of a hybrid pixel shown in .

[0085] As an example, in Figure 5A It is shown in Figure 31 is an equivalent circuit diagram of one pixel (e.g., a green normal pixel PXG-ij) among the plurality of normal pixels PX shown in . Because the plurality of normal pixels PX have the same circuit structure, the circuit structure of the green normal pixel PXG-ij will be described, and additional descriptions associated with the remaining normal pixels may be omitted to avoid redundancy. In addition, as an example, in Figure 5C It is shown in Figure 3 FIG. 1 is an equivalent circuit diagram of one hybrid pixel PXs-dj among the multiple hybrid pixels PXs shown in FIG. 1 . Because the multiple hybrid pixels PXs have the same circuit structure, the circuit structure of the hybrid pixel PXs-dj will be described, and additional descriptions associated with the remaining hybrid pixels may be omitted to avoid redundancy. Figure 5A Various components are shown in the figure, but the embodiments according to the present disclosure are not limited thereto, and according to some embodiments, without departing from the spirit and scope of the embodiments according to the present disclosure, Figure 5A The pixel circuits shown in FIG. 1 may include additional components or fewer components.

[0086] Reference Figure 5A The green normal pixel PXG-ij is connected to the i-th data line DLi of the data lines DL1 to DLm, the j-th initialization scan line SILj of the initialization scan line SIL1 to SILn, the j-th compensation scan line SCLj of the compensation scan line SCL1 to SCLn, the j-th write scan line SWLj of the write scan line SWL1 to SWLn, the j-th black scan line SBLj of the black scan line SBL1 to SBLn, and the j-th emission control line EMLj of the emission control line EML1 to EMLn.

[0087] The green normal pixel PXG-ij includes a green light emitting element ED_G (or a first light emitting element) and a green pixel circuit G_PD (or a first normal pixel circuit). The green light emitting element ED_G may be a light emitting diode. As an example of the present disclosure, the green light emitting element ED_G may be an organic light emitting diode including an organic light emitting layer. The green light emitting element ED_G includes an anode electrode (or a first anode electrode), a cathode electrode, and a light emitting layer (or a first light emitting layer) located between the anode electrode and the cathode electrode.

[0088] The green pixel circuit G_PD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. At least one of the first transistor T1 to the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the remaining transistors may be N-type transistors. At least one of the first transistor T1 to the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS semiconductor transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0089] The configuration of the green pixel circuit G_PD according to the present disclosure is not limited to Figure 5A The embodiments shown and described. Figure 5A The green pixel circuit G_PD shown in FIG. 1 is only an example, and the configuration of the green pixel circuit G_PD may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7 may be P-type transistors or N-type transistors.

[0090] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can provide the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the green normal pixel PXG-ij. The i-th data line DLi provides the i-th data signal Di to the green normal pixel PXG-ij. The i-th data signal Di may have a value similar to that input to the display device DD (refer to Figure 3 ) of the image signal RGB (refer to Figure 3 ) corresponding to the voltage level.

[0091] According to some embodiments of the present disclosure, the green normal pixel PXG-ij may be connected to the first driving voltage line VL1 and the second driving voltage line VL2 and the first initialization voltage line VIL and the second initialization voltage line VAIL. The first driving voltage line VL1 may provide the first driving voltage ELVDD to the green normal pixel PXG-ij, and the second driving voltage line VL2 may provide the second driving voltage ELVSS to the green normal pixel PXG-ij. In addition, the first initialization voltage line VIL may provide the first initialization voltage Vint to the green normal pixel PXG-ij, and the second initialization voltage line VAIL may provide the second initialization voltage Vaint to the green normal pixel PXG-ij.

[0092] The first transistor T1 is connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the green light emitting element ED_G. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through a fifth transistor T5, a second electrode connected to an anode electrode of the green light emitting element ED_G through a sixth transistor T6, and a third electrode connected to a first end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 may be supplied with an i-th data signal Di provided through an i-th data line DLi according to a switching operation of the second transistor T2, and may supply a driving current Id to the green light emitting element ED_G.

[0093] The second transistor T2 is connected between the first electrode of the first transistor T1 and the i-th data line DLi. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on according to the j-th write scan signal SWj transmitted through the j-th write scan line SWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0094] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and may connect the third electrode and the second electrode of the first transistor T1. In this case, the first transistor T1 may be diode-connected.

[0095] The fourth transistor T4 is connected between the first initialization voltage line VIL to which the first initialization voltage Vint is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VIL through which the first initialization voltage Vint is transmitted, a second electrode connected to the first node N1, and a third electrode connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal SIj transmitted through the j-th initialization scan line SILj. The fourth transistor T4 turned on in this way transmits the first initialization voltage Vint to the first node N1, so that the potential of the third electrode of the first transistor T1 (that is, the potential of the first node N1) is initialized.

[0096] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode connected to the j-th emission control line EMLj.

[0097] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode electrode (eg, the second node N2) of the green light emitting element ED_G, and a third electrode (eg, a gate electrode) connected to the jth emission control line EMLj.

[0098] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be transmitted to the green light emitting element ED_G after being compensated via the diode-connected first transistor T1.

[0099] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VAIL through which a second initialization voltage Vaint is transmitted, a second electrode connected to a second node N2, and a third electrode connected to a j-th black scan line SBLj. The voltage level of the second initialization voltage Vaint may be lower than or equal to the voltage level of the first initialization voltage Vint.

[0100] The seventh transistor T7 is turned on according to the jth black scan signal SBj transmitted through the jth black scan line SBLj. The second initialization voltage Vaint applied by the seventh transistor T7 thus turned on can be transmitted to the anode electrode of the green light emitting element ED_G. Therefore, the anode electrode (or the second node N2) of the green light emitting element ED_G can be initialized with the second initialization voltage Vaint.

[0101] As described above, the first end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the second end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode electrode of the green light emitting element ED_G may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The voltage level of the second driving voltage ELVSS may be lower than the voltage level of the first driving voltage ELVDD. According to some embodiments of the present disclosure, the voltage level of the second driving voltage ELVSS may be lower than the voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint.

[0102] Reference Figure 5A and Figure 5B , the j-th emission control signal EMj has a high level during the non-emission period NEP. During the non-emission period NEP, the j-th initialization scan signal SIj is activated. During the activation period AP1 (hereinafter referred to as the "first activation period") of the j-th initialization scan signal SIj, when the j-th initialization scan signal SIj of a high level is provided through the j-th initialization scan line SILj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj of a high level. The first initialization voltage Vint is transmitted to the third electrode of the first transistor T1 through the fourth transistor T4 thus turned on, and the first node N1 is initialized with the first initialization voltage Vint. Therefore, the first activation period AP1 can be defined as the initialization period of the green normal pixel PXG-ij.

[0103] Next, the j-th compensation scan signal SCj is activated; during the activation period AP2 (hereinafter referred to as the "second activation period") of the j-th compensation scan signal SCj, the third transistor T3 is turned on by the j-th compensation scan signal SCj of a high level supplied through the j-th compensation scan line SCLj. The first transistor T1 is diode-connected through the third transistor T3 thus turned on to be forward biased. The first activation period AP1 may not overlap with the second activation period AP2.

[0104] The jth write scan signal SWj is activated in the second activation period AP2. The jth write scan signal SWj has a low level during the activation period AP4 (hereinafter referred to as the "fourth activation period"). During the fourth activation period AP4, the second transistor T2 is turned on by the low-level jth write scan signal SWj. In this case, the compensation voltage "Di-Vth" is applied to the third electrode of the first transistor T1. Here, the compensation voltage "Di-Vth" may correspond to a voltage obtained by subtracting the threshold voltage Vth of the first transistor T1 from the voltage of the i-th data signal Di supplied from the i-th data line DLi. That is, the potential of the third electrode of the first transistor T1 may be the compensation voltage "Di-Vth". The fourth activation period AP4 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be longer than the duration of the fourth activation period AP4.

[0105] The first driving voltage ELVDD and the compensation voltage "Di-Vth" can be applied to opposite ends of the capacitor Cst, respectively, and charges corresponding to the voltage difference between the opposite ends of the capacitor Cst can be stored in the capacitor Cst. Here, the high level period of the j-th compensation scan signal SCj can be referred to as the "compensation period" of the green normal pixel PXG-ij.

[0106] At the same time, the jth black scan signal SBj is activated in the second activation period AP2 of the jth compensation scan signal SCj. The jth black scan signal SBj has a low level during the activation period AP3 (hereinafter referred to as the "third activation period"). During the third activation period AP3, the seventh transistor T7 is turned on by the low-level jth black scan signal SBj supplied through the jth black scan line SBLj. A portion of the drive current Id may be leaked through the seventh transistor T7 as a shunt current Ibp. The third activation period AP3 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be longer than the duration of the third activation period AP3. The third activation period AP3 may be before the fourth activation period AP4 and may not overlap with the fourth activation period AP4.

[0107] When the green normal pixel PXG-ij displays a black image, the green light emitting element ED_G emits light due to the minimum driving current flowing to the first transistor T1. That is, the green normal pixel PXG-ij cannot normally display a black image. Therefore, the seventh transistor T7 of the green normal pixel PXG-ij according to some embodiments of the present disclosure can drain a portion of the minimum driving current of the first transistor T1 to a current path different from the current path to the green light emitting element ED_G as a shunt current Ibp.

[0108] Hereinafter, the minimum driving current of the first transistor T1 means the current flowing to the first transistor T1 under the condition that the gate-source voltage (Vgs) of the first transistor T1 is less than the threshold voltage (Vth) (i.e., the first transistor T1 is turned off). When the minimum driving current (e.g., a current of 10 pA or less) flowing to the first transistor T1 is transmitted to the green light emitting element ED_G under the condition that the first transistor T1 is turned off, an image of a black grayscale is displayed. When the green normal pixel PXG-ij displays a black image, the shunt current Ibp has a relatively large influence on the minimum driving current; on the contrary, when the green normal pixel PXG-ij displays an image such as a normal image or a white image, the shunt current Ibp has little influence on the driving current Id.

[0109] Therefore, when the green normal pixel PXG-ij displays a black image, the minimum light emitting current corresponding to the current Ied obtained by subtracting the shunt current Ibp flowing through the seventh transistor T7 from the minimum driving current can be provided to the green light emitting element ED_G, and thus, the black image can be clearly displayed. Therefore, the green normal pixel PXG-ij can realize an accurate black grayscale image by using the seventh transistor T7, and thus the contrast can be improved.

[0110] Next, the j-th emission control signal EMj supplied from the j-th emission control line EMLj is changed from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the low-level j-th emission control signal EMj. In this case, a driving current Id is generated according to the difference between the voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD. The driving current Id thus generated is supplied to the green light emitting element ED_G through the sixth transistor T6, and therefore, the driving current Id flows through the green light emitting element ED_G. Therefore, the green light emitting element ED_G can output the first color light (or the first green light) Lg1.

[0111] Reference FIG. 5A to FIG. 5C The hybrid pixel PXs-dj is connected to the i-th data line DLi of the data lines DL1 to DLm, the j-th initialization scan line SILj of the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj of the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj of the write scan lines SWL1 to SWLn, the j-th black scan line SBLj of the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj of the emission control lines EML1 to EMLn. The hybrid pixel PXs-dj is connected to the d-th readout line RLd among the readout lines RL1 to RLh.

[0112] The hybrid pixel PXs-dj may include a hybrid element HD_G and a hybrid circuit HD_C electrically connected to the hybrid element HD_G. The hybrid circuit HD_C includes a pixel circuit unit P_PD and a sensor circuit unit O_SD. The hybrid element HD_G is commonly connected to the pixel circuit unit P_PD and the sensor circuit unit O_SD. The pixel circuit unit P_PD may have Figure 5A Therefore, additional description associated with the pixel circuit unit P_PD will be omitted to avoid redundancy.

[0113] The sensor circuit unit O_SD is connected to the dth readout line RLd, the jth write scan line SWLj and the reset control line SRL. The sensor circuit unit O_SD includes three transistors ST1 to ST3. The three transistors ST1 to ST3 may be a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifying transistor ST2 and the output transistor ST3 may be an oxide semiconductor transistor. According to some embodiments of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS semiconductor transistors. However, embodiments of the present disclosure are not limited thereto. For example, at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS semiconductor transistor.

[0114] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the other transistors therein may be N-type transistors. According to some embodiments of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be PMOS transistors, and the reset transistor ST1 may be an NMOS transistor. However, embodiments of the present disclosure are not limited thereto. For example, all transistors ST1, ST2, and ST3 may be N-type transistors or P-type transistors.

[0115] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (for example, the reset transistor ST1) may be implemented with transistors of the same type as the third transistor T3 and the fourth transistor T4 of the pixel circuit unit P_PD. The amplifying transistor ST2 and the output transistor ST3 may be implemented with transistors of the same type as the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7 of the pixel circuit unit P_PD.

[0116] The circuit configuration of the sensor circuit unit O_SD according to the present disclosure is not limited to Figure 5C . Figure 5CThe sensor circuit unit O_SD shown in FIG. 1 is only an example, and the configuration of the sensor circuit unit O_SD may be modified and performed. Figure 5C Various components are shown in the figure, but the embodiments according to the present disclosure are not limited thereto, and according to some embodiments, without departing from the spirit and scope of the embodiments according to the present disclosure, Figure 5C The sensor circuit unit shown in FIG. 1 may include additional components or fewer components.

[0117] The reset transistor ST1 includes a first electrode receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal SR. The reset transistor ST1 can reset the potential of the first sensing node SN1 with the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR may be a signal provided by a reset control line SRL. The reset control signal SR may be a signal that is activated in a light receiving mode and disabled in a light emitting mode. According to some embodiments of the present disclosure, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS at least during the activation period of the reset control signal SR. The reset voltage Vrst may be transmitted to the sensor circuit unit O_SD through the reset voltage line VRL. The reset voltage Vrst may be a DC voltage maintained at a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0118] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter referred to as "first sub-reset transistor and second sub-reset transistor"). In this case, the third electrode of the first sub-reset transistor and the third electrode of the second sub-reset transistor are connected to the reset control line SRL. In addition, the second electrode of the first sub-reset transistor and the first electrode of the second sub-reset transistor may be electrically connected. In addition, the reset voltage Vrst may be applied to the first electrode of the first sub-reset transistor, and the second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto, and may be variously changed or modified.

[0119] The amplifier transistor ST2 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on according to the potential of the first sensing node SN1, and the sensing drive voltage SLVD can be applied to the second sensing node SN2. According to some embodiments of the present disclosure, the sensing drive voltage SLVD can correspond to the first drive voltage ELVDD and one of the first initialization voltage Vint and the second initialization voltage Vaint. When the sensing drive voltage SLVD corresponds to the first drive voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first drive voltage line VL1. When the sensing drive voltage SLVD corresponds to the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VIL; when the sensing drive voltage SLVD corresponds to the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VAIL.

[0120] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 can transmit the sensing signal FSd to the dth readout line RLd in response to the output control signal. The output control signal can be the jth write scan signal SWj supplied through the jth write scan line SWLj. That is, the output transistor ST3 can receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0121] The hybrid element HD_G includes an anode electrode (or a hybrid anode electrode), a cathode electrode (or a hybrid cathode electrode), and a light emitting stack and a light receiving stack located between the anode electrode and the cathode electrode. The hybrid element HD_G may include a light emitting unit H_ED and a light receiving unit H_OPD. The light emitting unit H_ED is defined by the anode electrode, the light emitting stack, and the cathode electrode, and the light receiving unit H_OPD is defined by the anode electrode, the light receiving stack, and the cathode electrode.

[0122] The anode electrode of the hybrid element HD_G is commonly connected to the second node N2 of the pixel circuit unit P_PD and the first sensing node SN1 of the sensor circuit unit O_SD. The cathode electrode of the hybrid element HD_G may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The cathode electrode of the hybrid element HD_G may be electrically connected to the cathode electrode of the green light emitting element ED_G. According to some embodiments of the present disclosure, the cathode electrode of the hybrid element HD_G may be integrally formed with the cathode electrode of the green light emitting element ED_G to form a common cathode electrode.

[0123] When the mixing element HD_G is reverse biased (i.e., in the light emitting mode), the mixing element HD_G outputs the second color light (or the second green light) Lg2 through the light emitting unit H_ED turned on in the reverse bias state. When the mixing element HD_G is forward biased (i.e., in the light receiving mode), the mixing element HD_G can receive the first color light (or the first green light) Lg1 through the light receiving unit H_OPD turned on in the forward bias state.

[0124] In the light emitting mode, the green light emitting element ED_G may output the first color light, and the mixing element HD_G may output the second color light. In the light receiving mode, the green light emitting element ED_G may output the first color light, and the mixing element HD_G may be exposed to the first color light output from the green light emitting element ED_G. Figure 1 ) Touch display surface IS (refer to Figure 1 ), the light receiving unit H_OPD of the hybrid element HD_G generates photoelectrons corresponding to the light reflected by the ridges of the fingerprint or the valleys between the ridges. The amount of current flowing through the light receiving unit H_OPD changes according to the generated photoelectrons.

[0125] The current flowing through the light receiving unit H_OPD when the light receiving unit H_OPD receives light reflected by the ridges of the fingerprint may be referred to as a "first current", and the current flowing through the light receiving unit H_OPD when the light receiving unit H_OPD receives light reflected by the valleys of the fingerprint may be referred to as a "second current". Because there is a difference between the amount of light reflected by the ridges of the fingerprint and the amount of light reflected by the valleys of the fingerprint, the difference appears as a difference between the first current and the second current. The potential of the first sensing node SN1 formed when the first current flows through the light receiving unit H_OPD may be referred to as a "first potential", and the potential of the first sensing node SN1 formed when the second current flows through the light receiving unit H_OPD may be referred to as a "second potential". As an example of the present disclosure, the first current may be greater than the second current; in this case, the first potential may be lower than the second potential.

[0126] The amplification transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode of the amplification transistor ST2 .

[0127] During the fourth activation period AP4, the j-th write scan signal SWj of a low level is supplied to the output transistor ST3 through the j-th write scan line SWLj. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj of a low level, the sensing signal FSd corresponding to the current flowing through the amplifying transistor ST2 can be output to the d-th readout line RLd.

[0128] Next, when a high-level reset control signal SR is supplied through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period can be defined as an activation period (i.e., a high-level period) of the reset control signal SR. Alternatively, when the reset transistor ST1 is implemented with a P-type transistor, a low-level reset control signal SR can be supplied to the reset control line SRL during the reset period. During the reset period, the first sensing node SN1 can be reset with a potential corresponding to the reset voltage Vrst. As an example of the present disclosure, the voltage level of the reset voltage Vrst can be lower than the voltage level of the second drive voltage ELVSS.

[0129] Then, when the reset period ends, the light receiving unit H_OPD may generate photoelectrons corresponding to the received light, and the generated photoelectrons may be accumulated again at the first sensing node SN1.

[0130] Figure 6 is a cross-sectional view showing a green normal pixel, a red normal pixel, a blue normal pixel, and a mixed pixel according to some embodiments of the present disclosure.

[0131] Reference Figure 2 and Figure 6 , the display panel DP includes a base layer BL, a circuit layer DP_CL, a device layer DP_ED and an encapsulation layer TFE. The device layer DP_ED is located on the circuit layer DP_CL. The device layer DP_ED may include a plurality of light emitting elements ED_G, ED_R and ED_B and a mixing element HD_G. The plurality of light emitting elements ED_G, ED_R and ED_B may include a green light emitting element ED_G, a red light emitting element ED_R and a blue light emitting element ED_B.

[0132] The display area DA of the display panel DP (see Figure 3 ) may include a plurality of pixel areas PXA and a non-pixel area NPXA surrounding the plurality of pixel areas PXA. The plurality of pixel areas PXA may include a first pixel area PXA-1, a second pixel area PXA-2, and a third pixel area PXA-3. The first pixel area PXA-1, the second pixel area PXA-2, and the third pixel area PXA-3 may emit light of different wavelengths, respectively. The first pixel area PXA-1 is an area where a green light emitting element ED_G is positioned and outputs a first green light having a green wavelength. The second pixel area PXA-2 is an area where a red light emitting element ED_R is positioned and outputs red light having a red wavelength. The third pixel area PXA-3 is an area where a blue light emitting element ED_B is positioned and outputs blue light having a blue wavelength.

[0133] The plurality of pixel regions PXA may further include a hybrid pixel region PXA-4. The hybrid pixel region PXA-4 is a region where a hybrid element HD_G is located. Therefore, the hybrid pixel region PXA-4 (hereinafter referred to as "the fourth pixel region PXA-4") may output a second color light having a green wavelength in a light emitting mode (or a display mode), and may sense a first color light output from the first pixel region PXA-1 in a light receiving mode (or a sensing mode).

[0134] The non-pixel area NPXA may be an area defined between the pixel areas PXA adjacent to each other, and may be an area where the light emitting elements ED_G, ED_R, and ED_B and the mixing element HD_G are not substantially located.

[0135] The green light emitting element ED_G is arranged to overlap with the first pixel area PXA-1. The green light emitting element ED_G includes an anode electrode (or green anode electrode) EL1_G, a green light emitting layer (or first light emitting layer) G1_EML located on the green anode electrode EL1_G, and a cathode electrode (or common cathode electrode) EL2 located on the green light emitting layer G1_EML. The green light emitting element ED_G also includes a green hole transport layer HTR1_G located between the green anode electrode EL1_G and the green light emitting layer G1_EML and a common hole transport layer HTR2 located on the green hole transport layer HTR1_G. The green light emitting element ED_G also includes a common electron transport layer ETR2 located between the green light emitting layer G1_EML and the cathode electrode EL2.

[0136] The red light emitting element ED_R is arranged to overlap with the second pixel area PXA-2. The red light emitting element ED_R includes an anode electrode (or red anode electrode) EL1_R, a red light emitting layer R_EML located on the red anode electrode EL1_R, and a cathode electrode (or common cathode electrode) EL2 located on the red light emitting layer R_EML. The red light emitting element ED_R also includes a red hole transport layer HTR1_R located between the red anode electrode EL1_R and the red light emitting layer R_EML and a common hole transport layer HTR2 located on the red hole transport layer HTR1_R. The red light emitting element ED_R also includes a common electron transport layer ETR2 located between the red light emitting layer R_EML and the cathode electrode EL2.

[0137] The blue light emitting element ED_B is arranged to overlap with the third pixel area PXA-3. The blue light emitting element ED_B includes an anode electrode (or blue anode electrode) EL1_B, a blue light emitting layer B_EML located on the blue anode electrode EL1_B, and a cathode electrode (or common cathode electrode) EL2 located on the blue light emitting layer B_EML. The blue light emitting element ED_B also includes a blue hole transport layer HTR1_B located between the blue anode electrode EL1_B and the blue light emitting layer B_EML and a common hole transport layer HTR2 located on the blue hole transport layer HTR1_B. The blue light emitting element ED_B also includes a common electron transport layer ETR2 located between the blue light emitting layer B_EML and the cathode electrode EL2.

[0138] The green anode electrode EL1_G, the red anode electrode EL1_R, and the blue anode electrode EL1_B may be formed of a metal material, a metal alloy, or a conductive compound. The green anode electrode EL1_G, the red anode electrode EL1_R, and the blue anode electrode EL1_B may be a transparent electrode, a semi-transparent electrode, or a reflective electrode.

[0139] The green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B may be formed by using various methods such as a vacuum deposition method, a spin coating method, a casting method, an LB (Langmuir-Blodget) method, an inkjet printing method, a laser printing method, and a LITI (Laser Induced Thermal Imaging) method. The green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B may be patterned and disposed in the first pixel area PXA-1, the second pixel area PXA-2, and the third pixel area PXA-3, respectively, and may not overlap with the non-pixel area NPXA. In addition, the green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B may have different thicknesses. Since the green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B have different thicknesses, the resonance distance according to the wavelength of light emitted from each of the green light emitting element ED_G, the red light emitting element ED_R, and the blue light emitting element ED_B can be compensated, and therefore, the luminous efficiency of each of the green light emitting element ED_G, the red light emitting element ED_R, and the blue light emitting element ED_B can be increased. However, the present disclosure is not limited thereto. The green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B may have the same thickness. In this case, the green hole transport layer HTR1_G, the red hole transport layer HTR1_R, and the blue hole transport layer HTR1_B may be provided as a common layer to overlap with both the first pixel area PXA-1, the second pixel area PXA-2, and the third pixel area PXA-3 and the non-pixel area NPXA.

[0140] The green light emitting layer G1_EML, the red light emitting layer R_EML, and the blue light emitting layer B_EML may overlap the first pixel region PXA-1, the second pixel region PXA-2, and the third pixel region PXA-3, respectively. The green light emitting layer G1_EML, the red light emitting layer R_EML, and the blue light emitting layer B_EML may be spaced apart from each other in a plan view. The green light emitting layer G1_EML, the red light emitting layer R_EML, and the blue light emitting layer B_EML may emit light belonging to different wavelength ranges. That is, the green light emitting layer G1_EML, the red light emitting layer R_EML, and the blue light emitting layer B_EML may emit first green light, red light, and blue light, respectively.

[0141] Each of the common hole transport layer HTR2 and the common electron transport layer ETR2 may be provided in a common layer shape so as to overlap with both the first, second, and third pixel regions PXA-1, PXA-2, and PXA-3 and the non-pixel region NPXA.

[0142] The hybrid element HD_G is arranged to overlap with the fourth pixel area PXA-4. The hybrid element HD_G includes an anode electrode (or a hybrid anode electrode) EL1_H, a light receiving stack O_ST stacked on the hybrid anode electrode EL1_H, a light emitting stack E_ST located on the light receiving stack O_ST, and a cathode electrode (or a hybrid cathode electrode or a common cathode electrode) EL2 located on the light emitting stack E_ST. The hybrid anode electrode EL1_H may include the same material as the green anode electrode EL1_G, the red anode electrode EL1_R, and the blue anode electrode EL1_B.

[0143] According to some embodiments of the present disclosure, the light receiving stack O_ST may include an electron blocking layer EBL, a photoelectric conversion layer OCL, a hole blocking layer HBL, and an electron transport layer ETR1. The electron blocking layer EBL is located on the hybrid anode electrode EL1_H, and the photoelectric conversion layer OCL is located on the electron blocking layer EBL. The hole blocking layer HBL is located on the photoelectric conversion layer OCL. The photoelectric conversion layer OCL, which is a layer that converts incident light into an electrical signal, can generate electrons and holes based on light so as to be transmitted to the hybrid anode electrode EL1_H or the cathode electrode EL2.

[0144] The electron blocking layer EBL may block electrons transmitted from the light emitting stack E_ST. The hole blocking layer HBL blocks holes introduced into the light receiving stack O_ST from moving to the light emitting stack E_ST. The electron transport layer ETR1 transports electrons provided from the light emitting stack E_ST to the photoelectric conversion layer OCL. The electron blocking layer EBL, the photoelectric conversion layer OCL, the hole blocking layer HBL, and the electron transport layer ETR1 of the light receiving stack O_ST may be disposed only in the fourth pixel region PXA-4. That is, the electron blocking layer EBL, the photoelectric conversion layer OCL, the hole blocking layer HBL, and the electron transport layer ETR1 may overlap with the fourth pixel region PXA-4, and may not overlap with the first pixel region PXA-1, the second pixel region PXA-2, and the third pixel region PXA-3 and the non-pixel region NPXA.

[0145] According to some embodiments of the present disclosure, the light emitting stack E_ST includes a common hole transport layer HTR2, a light emitting layer (or a second light emitting layer) G2_EML located on the common hole transport layer HTR2, and a common electron transport layer ETR2. The light emitting layer G2_EML may overlap with the fourth pixel region PXA-4. The light emitting layer G2_EML may emit a second green light that is light belonging to the same wavelength range as the green light emitting layer G1_EML. The light emitting layer G2_EML may be spaced apart from the green light emitting layer G1_EML, the red light emitting layer R_EML, and the blue light emitting layer B_EML in a plan view.

[0146] Each of the common hole transport layer HTR2 and the common electron transport layer ETR2 may be provided in a common layer shape so as to overlap with the first, second, third, and fourth pixel regions PXA-1, PXA-2, PXA-3, and PXA-4 and the non-pixel region NPXA.

[0147] The hybrid element HD_G may further include a charge generation layer CGL between the light receiving stack O_ST and the light emitting stack E_ST. When a voltage is applied, the charge generation layer CGL may generate charges (i.e., electrons and holes) by forming a complex through an oxidation-reduction reaction. The charge generation layer CGL may provide the generated charges to the light receiving stack O_ST or the light emitting stack E_ST. The charge generation layer CGL may double the efficiency of the current generated in the light receiving stack O_ST or the light emitting stack E_ST, and may adjust the charge balance in the light receiving stack O_ST or the light emitting stack E_ST.

[0148] The charge generation layer CGL may include an n-type charge generation layer n-CGL and a p-type charge generation layer p-CGL. According to some embodiments, the n-type charge generation layer n-CGL may be positioned adjacent to the light receiving stack O_ST, and the p-type charge generation layer p-CGL may be positioned adjacent to the light emitting stack E_ST.

[0149] The n-type charge generation layer n-CGL may be a charge generation layer that generates electrons. The n-type charge generation layer n-CGL may be a layer in which a base material is doped with an n-type dopant. The p-type charge generation layer p-CGL may be a charge generation layer that generates holes. The p-type charge generation layer p-CGL may be a layer in which a base material is doped with a p-type dopant. A buffer layer may also be located between the n-type charge generation layer n-CGL and the p-type charge generation layer p-CGL.

[0150] The charge generation layer CGL may include an n-type arylamine-based material or a p-type metal oxide. For example, the charge generation layer CGL may include a charge generation compound made of an arylamine-based organic compound, a metal, a metal oxide, a carbide, a fluoride, or a mixture thereof.

[0151] The n-type charge generation layer n-CGL may overlap the fourth pixel region PXA-4 and may be located on the electron transport layer ETR1. The p-type charge generation layer p-CGL may overlap the fourth pixel region PXA-4 and may be located on the n-type charge generation layer n-CGL. The light emitting stack E_ST may be located on the p-type charge generation layer p-CGL.

[0152] As an example of the present disclosure, the distance d1 between the green anode electrode EL1_G and the green light emitting layer G1_EML may be substantially equal to the distance d2 between the hybrid anode electrode EL1_H and the light emitting layer G2_EML. Therefore, the resonance distance of the first color light Lg1 emitted from the green light emitting element ED_G may be equal to the resonance distance of the second color light Lg2 emitted from the hybrid element HD_G. This may mean that the hybrid element HD_G has the same luminous efficiency as the green light emitting element ED_G.

[0153] The encapsulation layer TFE is located on the element layer DP_ED. The encapsulation layer TFE includes at least one inorganic layer or at least one organic layer. According to some embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. According to some embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0154] The inorganic layer protects the green light emitting element ED_G, the red light emitting element ED_R, the blue light emitting element ED_B, and the mixed element HD_G from moisture / oxygen, and the organic layer protects the green light emitting element ED_G, the red light emitting element ED_R, the blue light emitting element ED_B, and the mixed element HD_G from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0155] Display device DD (refer to Figure 2 ) includes a display panel DP (reference Figure 2 ) and a color filter layer CFL located on the input sensing layer ISL. The input sensing layer ISL may be directly located on the encapsulation layer TFE. Figure 6 , a structure in which the input sensing layer ISL is directly located on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto.

[0156] The color filter layer CFL may be located on the input sensing layer ISL. The color filter layer CFL may include a first color filter G_CF, a second color filter R_CF, and a third color filter B_CF. The first color filter G_CF has a first color, the second color filter R_CF has a second color, and the third color filter B_CF has a third color. As an example of the present disclosure, the first color may be green, the second color may be red, and the third color may be blue. The first color filter G_CF is arranged to overlap with the first pixel area PXA-1 and the fourth pixel area PXA-4, and the second color filter R_CF and the third color filter B_CF are arranged to overlap with the second pixel area PXA-2 and the third pixel area PXA-3, respectively.

[0157] The color filter layer CFL may further include a black matrix BM. The black matrix BM may be arranged to correspond to the non-pixel area NPXA. The black matrix BM may not overlap the first pixel area PXA-1, the second pixel area PXA-2, the third pixel area PXA-3, and the fourth pixel area PXA-4.

[0158] Fig. 7A is a diagram showing a case where a display panel according to some embodiments of the present disclosure operates in a light emitting mode, Figure 7B is a diagram illustrating a case where a display panel according to some embodiments of the present disclosure operates in a light receiving mode. Fig. 8A is a conceptual diagram showing a case where a hybrid pixel operates in a light emitting mode according to some embodiments of the present disclosure, Figure 8B is a conceptual diagram illustrating a case where a hybrid pixel operates in a light receiving mode according to some embodiments of the present disclosure.

[0159] Reference Fig. 7A and Fig. 8A In the light emitting mode, the green light emitting element ED_G can output the first color light (or the first green light) Lg1, and the mixing element HD_G can output the second color light (or the second green light) Lg2. The mixing element HD_G can output the second color light (or the second green light) Lg2 through the light emitting stack E_ST.

[0160] In the light emitting mode, when a reverse bias is applied between the hybrid anode electrode EL1_H and the cathode electrode EL2 of the hybrid element HD_G, the holes can move from the common hole transport layer HTR2 to the light-emitting layer G2_EML, and the electrons can move from the common electron transport layer ETR2 to the light-emitting layer G2_EML. and Electronics The recombination of forms excitons in the light emitting stack E_ST. That is, light can be emitted.

[0161] In the light-emitting mode, holes are introduced into the light-receiving stack O_ST. The electrons from the light emitting stack E_ST may be blocked by the hole blocking layer HBL so as not to be provided to the light emitting stack E_ST. The electrons may be blocked by the electron blocking layer EBL. Therefore, in the light emitting mode, the light receiving stack O_ST may not operate and may be maintained in a turned-off state.

[0162] Reference Figure 7B and Figure 8BIn the light receiving mode, the green light emitting element ED_G may output the first color light (or the first green light) Lg1, and the mixing element HD_G may receive the first color light (or the first green light) Lg1. The mixing element HD_G may receive the first color light (or the first green light) Lg1 through the light receiving stack O_ST.

[0163] In the light receiving mode, the first color light (or first green light) Lg1 output from the green light emitting element ED_G may be reflected by the user's hand US_F, and the reflected first color light Lg1 may be provided to the mixing element HD_G. In this case, when a forward bias is applied between the mixing anode electrode EL1_H and the cathode electrode EL2 of the mixing element HD_G, the photoelectric conversion layer OCL generates electrons based on the first color light (or first green light) Lg1. and holes Holes generated from the photoelectric conversion layer OCL The electrons generated from the photoelectric conversion layer OCL can move to the hybrid anode electrode EL1_H. It can be moved to the cathode electrode EL2. Sensor circuit unit O_SD (refer to Figure 5C ) of the first sensing node SN1 (refer to Figure 5C ) can be generated by the holes in the light receiving stack O_ST and Electronics In the light receiving mode, the readout circuit 500 (refer to Figure 3 ) can detect the potential change of the first sensing node SN1 to sense the user's fingerprint.

[0164] In the light receiving mode, holes are introduced into the light emitting stack E_ST. The hole blocking region may be included in the common electron transport layer ETR2. In addition, in the light receiving mode, the electron The electrons may be blocked by the electron blocking layer EBL so as not to be provided to the photoelectric conversion layer OCL. Therefore, in the light receiving mode, the light emitting stack E_ST may not operate and may be maintained in a turned-off state.

[0165] The electron blocking layer EBL may have a LUMO energy level higher than the LUMO energy level of the photoelectric conversion layer OCL. As an example of the present disclosure, the LUMO energy level difference between the electron blocking layer EBL and the photoelectric conversion layer OCL may be about 3.0 eV or more. The hole blocking layer HBL may have a HUMO energy level lower than the HUMO energy level of the photoelectric conversion layer OCL. As an example of the present disclosure, the HUMO energy level difference between the hole blocking layer HBL and the photoelectric conversion layer OCL may be about -3.0 eV or more. Therefore, it is possible to ensure that the energy band gap of the photoelectric conversion layer OCL is as high as about 3.0 eV or more. In the specification, the LUMO energy level is the energy level of the lowest unoccupied molecular orbital, and the HOMO energy level is the energy level of the highest occupied molecular orbital.

[0166] In each reference pixel unit RPU, one of the light-emitting elements that output light of the same color is replaced with a hybrid element having a light-emitting function and a light-receiving function, and therefore, in addition to the light-emitting element, there is no need to add a separate light-receiving element used only for recognizing biometric information to the display panel DP. Therefore, the display device DD can recognize biometric information without reducing the overall resolution of the display panel DP.

[0167] Fig. 9 is an enlarged plan view of a partial area of ​​a display panel according to some embodiments of the present disclosure. Fig. 10A is a diagram showing a case where a display panel according to some embodiments of the present disclosure operates in a light emitting mode, Fig. 10B is a diagram illustrating a case where a display panel according to some embodiments of the present disclosure operates in a light receiving mode. Fig. 9 , Fig. 10A and Fig. 10B The components shown in Figure 4 , Fig. 7A and Figure 7B The same components as those shown in FIG. 1 are marked with the same reference numerals / symbols, and thus, additional description will be omitted to avoid redundancy.

[0168] Reference Fig. 9 , the display panel DPa includes a plurality of normal pixels PXR and PXB, a plurality of first mixed pixels PXs1 and a plurality of second mixed pixels PXs2.

[0169] A plurality of normal pixels PXR and PXB and a plurality of first mixed pixels PXs1 and a plurality of second mixed pixels PXs2 may be grouped into a plurality of reference pixel units RPUa. According to some embodiments of the present disclosure, each reference pixel unit RPUa may include two normal pixels PXR and PXB and two mixed pixels PXs1 and PXs2. The two normal pixels PXR and PXB may include a red normal pixel PXR and a blue normal pixel PXB. However, the number of normal pixels PXR and PXB included in each reference pixel unit RPUa is not limited thereto.

[0170] The red normal pixel PXR includes a red light emitting element ED_R, and the blue normal pixel PXB includes a blue light emitting element ED_B. The first mixed pixel PXs1 includes a first mixed element HD_G1, and the second mixed pixel PXs2 includes a second mixed element HD_G2. As an example of the present disclosure, the first mixed element HD_G1 can output the first color light (or the first green light) Lg1 in the light emitting mode and the light receiving mode, and the second mixed element HD_G2 can output the second color light (or the second green light) Lg2 in the light emitting mode and can receive the first color light Lg1 in the light receiving mode. Optionally, the second mixed element HD_G2 can output the second color light (or the second green light) Lg2 in the light emitting mode and the light receiving mode, and the first mixed element HD_G1 can output the first color light (or the first green light) Lg1 in the light emitting mode and can receive the second color light Lg2 in the light receiving mode.

[0171] The red light emitting elements ED_R and the blue light emitting elements ED_B may be repeatedly and alternately arranged in the first direction DR1. The first mixing elements HD_G1 and the second mixing elements HD_G2 may be repeatedly and alternately arranged in the first direction DR1.

[0172] The first mixing element HD_G1 and the second mixing element HD_G2 may have the same shape, or may have different shapes. For example, the first mixing element HD_G1 and the second mixing element HD_G2 may have the same size (or area), but may have different shapes. In addition, the first mixing element HD_G1 and the second mixing element HD_G2 may have different sizes (or areas), but may have the same shape.

[0173] The first mixing element HD_G1 is electrically connected to the first mixing circuit HD_C1, and the second mixing element HD_G2 is electrically connected to the second mixing circuit HD_C2. The first mixing circuit HD_C1 includes a first pixel circuit unit P_PD1 and a first sensor circuit unit O_SD1. The first mixing element HD_G1 is commonly connected to the first pixel circuit unit P_PD1 and the first sensor circuit unit O_SD1. The second mixing circuit HD_C2 includes a second pixel circuit unit P_PD2 and a second sensor circuit unit O_SD2. The second mixing element HD_G2 is commonly connected to the second pixel circuit unit P_PD2 and the second sensor circuit unit O_SD2.

[0174] The first pixel circuit unit P_PD1 and the first sensor circuit unit O_SD1 may be adjacent to each other in the first direction DR1. According to some embodiments of the present disclosure, the first pixel circuit unit P_PD1 may be located between the red pixel circuit R_PD and the first sensor circuit unit O_SD1. The second pixel circuit unit P_PD2 and the second sensor circuit unit O_SD2 may be adjacent to each other in the first direction DR1. According to some embodiments of the present disclosure, the second pixel circuit unit P_PD2 may be located between the blue pixel circuit B_PD and the second sensor circuit unit O_SD2.

[0175] Reference Fig. 10A and Fig. 10B , the first hybrid element HD_G1 includes an anode electrode (or a first hybrid anode electrode) EL1_H1, a first light receiving stack O_ST1 located on the first hybrid anode electrode EL1_H1, a first light emitting stack E_ST1 located on the first light receiving stack O_ST1, and a cathode electrode (or a common cathode electrode) EL2 located on the first light emitting stack E_ST1. The second hybrid element HD_G2 includes an anode electrode (or a second hybrid anode electrode) EL1_H2, a second light receiving stack O_ST2 located on the second hybrid anode electrode EL1_H2, a second light emitting stack E_ST2 located on the second light receiving stack O_ST2, and a cathode electrode (or a common cathode electrode) EL2 located on the second light emitting stack E_ST2.

[0176] The first hybrid anode electrode EL1_H1 and the second hybrid anode electrode EL1_H2 may include a red anode electrode EL1_R and a blue anode electrode EL1_B (refer to Figure 6 ) of the same material.

[0177] As an example of the present disclosure, the first light receiving stack O_ST1 may include a first electron blocking layer EBL1, a first photoelectric conversion layer OCL1, a first hole blocking layer HBL1, and a first electron transport layer ETR1-1. The first electron blocking layer EBL1 is located on the first hybrid anode electrode EL1_H1, and the first photoelectric conversion layer OCL1 is located on the first electron blocking layer EBL1. The first hole blocking layer HBL1 is located on the first photoelectric conversion layer OCL1.

[0178] The first light emitting stack E_ST1 includes a common hole transport layer HTR2, a first light emitting layer Ga_EML on the common hole transport layer HTR2, and a common electron transport layer ETR2. The first light emitting layer Ga_EML may emit a first green light as light belonging to a green wavelength range. The first light emitting layer Ga_EML may be spaced apart from the red light emitting layer R_EML and the blue light emitting layer B_EML in a plan view.

[0179] The first mixing element HD_G1 may further include a first charge generation layer CGL1 between the first light receiving stack O_ST1 and the first light emitting stack E_ST1. The first charge generation layer CGL1 may include a layer structure in which a first n-type charge generation layer n-CGL1 and a first p-type charge generation layer p-CGL1 are combined. According to some embodiments, the first n-type charge generation layer n-CGL1 may be positioned adjacent to the first light receiving stack O_ST1, and the first p-type charge generation layer p-CGL1 may be positioned adjacent to the first light emitting stack E_ST1.

[0180] As an example of the present disclosure, the second light receiving stack O_ST2 may include a second electron blocking layer EBL2, a second photoelectric conversion layer OCL2, a second hole blocking layer HBL2, and a second electron transport layer ETR1-2. The second electron blocking layer EBL2 is located on the second hybrid anode electrode EL1_H2, and the second photoelectric conversion layer OCL2 is located on the second electron blocking layer EBL2. The second hole blocking layer HBL2 is located on the second photoelectric conversion layer OCL2.

[0181] The second light emitting stack E_ST2 includes a common hole transport layer HTR2, a second light emitting layer Gb_EML on the common hole transport layer HTR2, and a common electron transport layer ETR2. The second light emitting layer Gb_EML may emit a second color light (or second green light) Lg2 as light belonging to a green wavelength range. The second light emitting layer Gb_EML may be spaced apart from the first light emitting layer Ga_EML and the red and blue light emitting layers R_EML and B_EML in a plan view.

[0182] The second hybrid element HD_G2 may further include a second charge generation layer CGL2 between the second light receiving stack O_ST2 and the second light emitting stack E_ST2. The second charge generation layer CGL2 may include a layer structure in which a second n-type charge generation layer n-CGL2 and a second p-type charge generation layer p-CGL2 are combined. According to some embodiments, the second n-type charge generation layer n-CGL2 may be positioned adjacent to the second light receiving stack O_ST2, and the second p-type charge generation layer p-CGL2 may be positioned adjacent to the second light emitting stack E_ST2.

[0183] Reference Fig. 10A In the light emitting mode, the first mixing element HD_G1 may output the first color light (or first green light) Lg1, and the second mixing element HD_G2 may output the second color light (or second green light) Lg2. The first mixing element HD_G1 may output the first green light Lg1 through the first light emitting stack E_ST1.

[0184] In the emission mode, when a reverse bias is applied between the first hybrid anode electrode EL1_H1 and the cathode electrode EL2 of the first hybrid element HD_G1, light may be emitted from the first light emitting stack E_ST1. In contrast, in the emission mode, the first light receiving stack O_ST1 may not operate and may be maintained in an off state.

[0185] Reference Fig. 10B In the light receiving mode, the first mixing element HD_G1 may output the first color light (or the first green light) Lg1, and the second mixing element HD_G2 may receive the first color light (or the first green light) Lg1. The second mixing element HD_G2 may receive the first color light (or the first green light) Lg1 through the second light receiving stack O_ST2.

[0186] In the light receiving mode, the first green light Lg1 output from the first mixing element HD_G1 may be reflected by the user's hand US_F, and the reflected first green light Lg1 may be provided to the second light receiving stack O_ST2. In this case, when a forward bias is applied between the second mixing anode electrode EL1_H2 and the cathode electrode EL2 of the second mixing element HD_G2, the second photoelectric conversion layer OCL2 generates electrons based on the first color light (or the first green light) Lg1. and holes . Sensor circuit unit O_SD (refer to Figure 5C ) of the first sensing node SN1 (refer to Figure 5C ) can be increased by the holes generated in the second light receiving stack O_ST2 and Electronics In the light receiving mode, the readout circuit 500 (refer to Figure 3 ) may detect a potential change of the first sensing node SN1 to sense a fingerprint of a user. Meanwhile, in the light receiving mode, the second light emitting stack E_ST2 of the second hybrid element HD_G2 may not operate and may be maintained in a turned-off state.

[0187] Optionally, in the light receiving mode, the second mixing element HD_G2 may output the second color light (or the second green light) Lg2, and the first mixing element HD_G1 may receive the second color light (or the second green light) Lg2. The first mixing element HD_G1 may receive the second color light (or the second green light) Lg2 through the first light receiving stack O_ST1. In this case, the first light emitting stack E_ST1 of the first mixing element HD_G1 may not operate and may be maintained in the off state.

[0188] According to some embodiments of the present disclosure, since some light-emitting elements (i.e., green light-emitting elements) that output light of the same color are replaced by hybrid elements having a light-emitting function and a light-receiving function, it is not necessary to add a separate light-receiving element for identifying biometric information to the display panel in addition to the light-emitting element. Therefore, the display device can identify biometric information without reducing the overall resolution of the display panel.

[0189] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: Base layer; A circuit layer, on the substrate layer; as well as a component layer, on the circuit layer, and including a light emitting component and a mixing component, The hybrid element includes: a hybrid anode electrode; a light receiving stack on the hybrid anode electrode; a light emitting stack on the light receiving stack; and a hybrid cathode electrode on the light emitting stack. wherein the light emitting element is configured to be turned on in a light emitting mode and a light receiving mode to emit light of a first color, wherein the mixing element is configured to be turned on in the light emitting mode to output a second color light, and The mixing element is configured to be turned on in the light receiving mode to receive the first color light.

2. The display device according to claim 1, wherein: The light-emitting element comprises a first light-emitting layer, wherein the light receiving stack includes a photoelectric conversion layer, and Wherein, the light-emitting stack includes a second light-emitting layer.

3. The display device according to claim 2, wherein: The light receiving stack further comprises: An electron blocking layer, between the hybrid anode electrode and the photoelectric conversion layer; a hole blocking layer between the photoelectric conversion layer and the second light-emitting layer; and The electron transport layer is between the hole blocking layer and the second light emitting layer.

4. The display device according to claim 3, wherein: The electron blocking layer has a LUMO energy level higher than the LUMO energy level of the photoelectric conversion layer, and The hole blocking layer has a HOMO energy level lower than a HOMO energy level of the photoelectric conversion layer.

5. The display device according to claim 4, wherein: The LUMO energy level difference between the electron blocking layer and the photoelectric conversion layer is in the range of 3.0 eV or more, and Wherein, the HUMO energy level difference between the hole blocking layer and the photoelectric conversion layer is in the range of -3.0 eV or greater.

6. The display device according to claim 3, wherein: The light emitting stack further comprises: a common hole transport layer between the electron transport layer and the second light emitting layer; and A common electron transport layer is between the second light emitting layer and the mixed cathode electrode.

7. The display device according to claim 2, wherein: The mixing element further comprises: A charge generation layer is between the light receiving stack and the light emitting stack.

8. The display device according to claim 7, wherein: The charge generation layer comprises: an n-type charge generation layer on the light receiving stack; and A p-type charge generation layer is on the n-type charge generation layer.

9. The display device according to claim 2, wherein: The light emitting element further comprises: an anode electrode; and cathode electrode, and Wherein, the first light emitting layer is between the anode electrode and the cathode electrode.

10. The display device according to claim 9, wherein: The distance between the anode electrode and the first light-emitting layer is equal to the distance between the mixed anode electrode and the second light-emitting layer.

11. The display device according to claim 10, wherein: The first color light and the second color light are lights having the same wavelength range.

12. The display device according to claim 11, wherein: The first color light and the second color light are lights in the green wavelength range.

13. The display device according to claim 11, further comprising: a color filter layer, on the element layer, The color filter layer includes: a first color filter corresponding to the light emitting element; and a second color filter corresponding to the mixing element, and The first color filter and the second color filter have the same color.

14. The display device according to claim 1, wherein: The light emitting element is identical in size and shape to the mixing element.

15. The display device according to claim 1, wherein: The circuit layer comprises: A pixel circuit connected to the light emitting element; a pixel circuit unit connected to the mixing element and having the same circuit structure as the pixel circuit; and A sensor circuit unit is connected to the mixing element and the pixel circuit unit.

16. The display device according to claim 15, wherein: The sensor circuit unit comprises: a reset transistor including a first electrode configured to receive a reset voltage, a second electrode connected to the hybrid anode electrode, and a third electrode configured to receive a reset control signal; an amplifying transistor including a first electrode configured to receive a sensing driving voltage, a second electrode connected to the hybrid anode electrode, and a third electrode connected to a sensing node; and The output transistor includes a first electrode connected to the sensing node, a second electrode connected to a readout line, and a third electrode configured to receive an output control signal.

17. A display device, comprising: Base layer; A circuit layer, on the substrate layer; as well as a component layer, on the circuit layer, and including a light emitting component and a mixing component, The circuit layer includes: a pixel circuit connected to the light emitting element; a pixel circuit unit connected to the mixing element and having the same circuit structure as the pixel circuit; and a sensor circuit unit connected to the mixing element and the pixel circuit unit, and The hybrid element includes: a light emitting unit configured to be turned on by the pixel circuit unit in a reverse bias state; and a light receiving unit configured to be turned on by the sensor circuit unit in a forward bias state.

18. The display device according to claim 17, wherein: The mixing element comprises: Mixed anode electrode; a light receiving stack on the hybrid anode electrode; a light emitting stack on the light receiving stack; and A hybrid cathode electrode is on the light emitting stack.

19. The display device according to claim 18, wherein: The light emitting unit is defined by the mixed anode electrode, the light emitting unit and the mixed cathode electrode, and Wherein, the light receiving unit is defined by the hybrid anode electrode, the light receiving stack and the hybrid cathode electrode.

20. The display device according to claim 19, wherein: The light emitting element is configured to be turned on in a light emitting mode and a light receiving mode to emit light of a first color, wherein the light emitting unit of the mixing element is configured to output a second color light in the light emitting mode, and Wherein, the light receiving unit of the mixing element is configured to receive the first color light in the light receiving mode.

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