Display panel, manufacturing method thereof and display device

Abstract

The invention relates to the technical field of display, and relates to a display panel and a manufacturing method thereof, and a display device, the display panel comprises a substrate, a first pixel definition layer, a second pixel definition layer, a light emitting layer, and a cathode layer; a first opening of the first pixel definition layer exposes part of the anode; the orthographic projection, on the substrate, of a second opening included in the second pixel definition layer is at least partially overlapped with the orthographic projection, on the substrate, of the first opening, and the display panel comprises at least one partition opening between every two adjacent sub-pixels; the partition opening comprises a first sub-partition penetrating through the second pixel definition layer and a second sub-partition penetrating through at least part of the first pixel definition layer, and the second sub-partition protrudes in the direction close to the sub-pixels relative to the first sub-partition at the junction of the first sub-partition and the second sub-partition. The manufacturing method is used for manufacturing the display panel, and the display device comprises the display panel. Color crosstalk between adjacent sub-pixels can be avoided, electrical light leakage is improved, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used in various fields because of their light weight, wide viewing angle, fast response, low temperature resistance, high luminous efficiency, and the ability to produce curved flexible display screens. OLED display devices use evaporation film formation to form organic light-emitting materials, and define the light-emitting area through the pixel definition layer. When current passes through, these organic light-emitting materials will emit light in the light-emitting area, thereby realizing display.

[0003] In the prior art, when a certain sub-pixel (target sub-pixel) is lit, due to the problem of lateral leakage current in the display panel, the adjacent sub-pixels are easily affected by the sub-pixel and light up secretly, resulting in light leakage and color cross-talk. This electrical light leakage phenomenon is particularly obvious in full-color OLED display panels, especially in low grayscale display, the color cast problem is particularly serious, thereby reducing the display quality of the OLED display panel.

[0004] Therefore, it is a technical problem that needs to be urgently solved by those skilled in the art to provide a display panel and a manufacturing method and a display device that can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time not affect the normal light emission of pixels and ensure low grayscale display effects. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a manufacturing method thereof, and a display device to solve the problem that the display device in the prior art is prone to color cast due to the lateral leakage current problem, thereby affecting the display quality.

[0006] The present disclosure provides a display panel, the display panel comprising a plurality of sub-pixels, the sub-pixels comprising an anode;

[0007] The display panel also includes:

[0008] a substrate, with the anode located on one side of the substrate;

[0009] A first pixel definition layer is located on a side of the anode away from the substrate, the first pixel definition layer comprises a plurality of first openings, and the first openings expose a portion of the anode;

[0010] A second pixel definition layer is located on a side of the first pixel definition layer away from the substrate, the second pixel definition layer comprises a plurality of second openings, and the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate;

[0011] a light-emitting layer, at least a portion of the light-emitting layer is located in the first opening;

[0012] A cathode layer, the cathode layer is located on a side of the light-emitting layer away from the substrate;

[0013] Between two adjacent sub-pixels, the display panel includes at least one partition opening, and along a direction perpendicular to the plane where the substrate is located, the partition opening includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer, and the first sub-partition is connected to the second sub-partition;

[0014] At the junction of the first sub-partition and the second sub-partition, along the direction from one sub-pixel to another adjacent sub-pixel, the second sub-partition protrudes toward the sub-pixel relative to the first sub-partition.

[0015] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display panel, the manufacturing method comprising:

[0016] providing a substrate;

[0017] Making multiple anodes, each anode corresponding to a sub-pixel;

[0018] Manufacturing a first pixel definition layer, patterning the first pixel definition layer to form a plurality of first openings, wherein the first openings expose a portion of the anode;

[0019] Manufacturing a second pixel definition layer, patterning the second pixel definition layer to form a plurality of second openings, wherein the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate;

[0020] Making a partition opening, the partition opening is located between two adjacent sub-pixels, and in a direction perpendicular to the plane where the substrate is located, the partition opening includes a first sub-partition penetrating the second pixel definition layer, and a second sub-partition penetrating at least a portion of the first pixel definition layer, and the first sub-partition and the second sub-partition are connected to form the partition opening;

[0021] At the junction of the first sub-partition and the second sub-partition, along the direction from one sub-pixel to another sub-pixel adjacent thereto, the second sub-partition protrudes in a direction close to the sub-pixel relative to the first sub-partition;

[0022] A light-emitting layer is manufactured, wherein at least a part of the light-emitting layer is located in a first opening on a side of the second pixel definition layer away from the substrate; the light-emitting layer includes a common layer, and the common layer is isolated at the isolation opening;

[0023] A cathode layer is manufactured, and the cathode layer is isolated at the isolation opening.

[0024] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above-mentioned display panel.

[0025] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0026] The display panel provided by the present disclosure is arranged between two adjacent sub-pixels, and the display panel includes at least one partition opening. Along the direction perpendicular to the plane where the substrate is located, the partition opening includes a first sub-partition penetrating the second pixel definition layer, and a second sub-partition penetrating at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected, and the partition opening is located between two adjacent sub-pixels, that is, the partition opening is located between two adjacent second openings. The structure of the partition opening provided by the present disclosure is that at the junction of the first sub-partition and the second sub-partition, along the direction from one sub-pixel to another adjacent sub-pixel, the second sub-partition protrudes in the direction close to the sub-pixel relative to the first sub-partition, thereby the structure of the double-layered first pixel definition layer and the second pixel definition layer can form a single-sided undercut structure on one side of the second sub-partition at the junction of the first sub-partition and the second sub-partition. Therefore, when the film layers of the light-emitting layer are evaporated to form films, the organic light-emitting material can be located in the first opening and the second opening to form a light-emitting layer corresponding to the anode of the sub-pixel, and due to the single-sided undercut structure of the second sub-partition, the common layer of the light-emitting layer can be effectively isolated at the second sub-partition position of the partition opening, which is equivalent to the leakage current path being isolated, and can effectively improve the color crosstalk between adjacent sub-pixels. Especially when the display panel performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels and improve electrical light leakage. At the same time, it does not affect the normal light emission of the pixels, thereby ensuring the low grayscale display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0029] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0030] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0031] Figure 3 yes Figure 2 A schematic diagram of a structure in which the light-emitting layer is located between the anode and cathode layers;

[0032] Figure 4 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0033] Figure 5 yes Figure 2 Schematic diagram of another structure in which the light-emitting layer is located between the anode and cathode layers;

[0034] Figure 6 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0035] Figure 7 It is a structural schematic diagram of a partition opening in the related art;

[0036] Figure 8 yes Figure 2 An enlarged structural schematic diagram of the location of the middle partition fracture;

[0037] Fig. 9 is a schematic diagram of a combination of a sub-pixel arrangement and a partition opening arrangement provided by an embodiment of the present disclosure;

[0038] Fig.10 is a schematic diagram of another combination of sub-pixel arrangement and partition opening arrangement provided by an embodiment of the present disclosure;

[0039] Fig.11 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0040] Fig.12 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0041] Fig.13 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0042] Fig.14 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0043] Fig.15 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0044] Fig.16 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0045] Fig.17 yes Fig.16 A schematic diagram of a cross-sectional structure along the B-B' direction;

[0046] Fig.18 is a flowchart of a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0047] Fig.19 yes Fig.18 A schematic diagram of the structure after the anode is completed in the manufacturing method;

[0048] Fig. 20 yes Fig.18 A schematic diagram of the structure after the patterned first pixel definition layer is completed in the manufacturing method;

[0049] Fig.21 yes Fig.18 A schematic structural diagram of the manufacturing method after the second opening of the second pixel definition layer is completed;

[0050] Fig. 22 yes Fig.18 A schematic diagram of the structure after the partition opening is completed in the manufacturing method;

[0051] Fig.23 yes Fig.18 A schematic diagram of the structure after the light-emitting layer is completed in the manufacturing method;

[0052] Fig.24 yes Fig.18 A schematic diagram of the structure after the cathode layer is completed in the manufacturing method;

[0053] Fig.25 is another flowchart of a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0054] Fig.26 yes Fig.25 A schematic diagram of the structure after the patterned first pixel definition layer is completed in the manufacturing method;

[0055] Fig. 27 yes Fig.25 A schematic structural diagram of the manufacturing method after the second opening of the second pixel definition layer is completed;

[0056] Fig.28 yes Fig.25 A schematic diagram of the position of a mask when making a partition opening in a manufacturing method;

[0057] Fig.29 yes Fig.25 A schematic diagram of the position of another mask when making a partition opening in a manufacturing method;

[0058] Fig.30 yes Fig.25 A schematic diagram of the structure after the light-emitting layer is completed in the manufacturing method;

[0059] Fig.31 yes Fig.25A schematic diagram of the structure after the cathode layer is completed in the manufacturing method;

[0060] Fig.32 It is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0063] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 2 yes Figure 1 A schematic cross-sectional structure diagram along the AA' line, a display panel 000 provided in this embodiment includes a plurality of sub-pixels 00, and the sub-pixel 00 includes an anode 20;

[0064] The display panel 000 further includes:

[0065] A substrate 10, wherein an anode 20 is located on one side of the substrate 10;

[0066] A first pixel definition layer 30 is located at a side of the anode 20 away from the substrate 10 , and the first pixel definition layer 30 includes a plurality of first openings 30K1 , and the first openings 30K1 expose a portion of the anode 20 ;

[0067] The second pixel definition layer 40 is located on a side of the first pixel definition layer 30 away from the substrate 10, and the second pixel definition layer 40 includes a plurality of second openings 40K1, and the orthographic projections of the second openings 40K1 on the substrate 10 at least partially overlap with the orthographic projections of the first openings 30K1 on the substrate 10;

[0068] The light-emitting layer 50, at least a part of the light-emitting layer 50 is located in the first opening 30K1; it can be understood that the light-emitting layer 50 may include a light-emitting common layer, such as a hole transport layer, an electron transport layer, a charge generation layer, etc.

[0069] A cathode layer 60, wherein the cathode layer 60 is located on a side of the light emitting layer 50 away from the substrate 10;

[0070] Between two adjacent sub-pixels 00, the display panel 000 includes at least one partition opening JK. Along a direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least a portion of the first pixel definition layer 30. The first sub-partition JK1 is connected to the second sub-partition JK2.

[0071] At the junction of the first sub-partition JK1 and the second sub-partition JK2 , along the direction from one sub-pixel 00 to another adjacent sub-pixel 00 , the second sub-partition JK2 protrudes toward the sub-pixel 00 relative to the first sub-partition JK1 .

[0072] Specifically, the display panel 000 provided in this embodiment may be an organic light emitting diode display panel. The display panel 000 includes a substrate 10 ( Figure 2 The substrate 10 is used as a supporting substrate for setting other film structures of the display panel 000; optionally, the substrate 10 of the display panel 000 in this embodiment can be a hard material such as glass, ceramic, etc., or a flexible material, such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other polymer materials. The substrate 10 can be any one of a transparent substrate, a semi-transparent substrate or an opaque substrate, which is not limited in this embodiment. The sub-pixel 00 of the display panel 000 includes an anode 20, and the anode 20 can be located on one side of the substrate 10. Optionally, along the direction Z perpendicular to the plane where the substrate 10 is located, a driving array layer 70 may be further included between the substrate 10 and the anode 20. The driving array layer 70 may be provided with thin film transistors 70T through multiple conductive film layers. Multiple thin film transistors 70T are used to form a driving circuit that provides a driving signal for the display panel 000, such as a pixel circuit, etc. The driving array layer 70 may also be used to set a driving line. The layout structure of the driving array layer 70 is not described in detail in this embodiment. For details, reference may be made to the film layer structure of the OLED display panel in the related art for understanding. The anode 20 corresponding to the sub-pixel 00 may be electrically connected to the thin film transistor 70T, and is used to transmit the driving signal of the pixel circuit to the anode 20. Optionally, the anode 20 may be formed of various conductive materials, such as the anode 20 may be formed as a transparent anode or a reflective anode according to its own purpose. When the anode 20 is formed as a transparent anode, the material of the anode 20 may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.; when the anode 20 is formed as a reflective anode, the material of the anode 20 may include silver, magnesium, aluminum, etc. or other metal mixtures, which is not specifically limited in this embodiment.

[0073] In this embodiment, the side of the anode 20 away from the substrate 10 includes a first pixel definition layer 30 and a second pixel definition layer 40. The first pixel definition layer 30 and the second pixel definition layer 40 can be stacked, that is, the surface of the first pixel definition layer 30 away from the substrate 10 can be in contact with the surface of the second pixel definition layer 40 facing the substrate 10. The first pixel definition layer 30 includes a plurality of first openings 30K1, the first openings 30K1 expose part of the anode 20, and the second pixel definition layer 40 includes a plurality of second openings 40K1, the orthographic projection of the second openings 40K1 on the substrate 10 at least partially overlaps with the orthographic projection of the first openings 30K1 on the substrate 10, that is, the at least partially overlapping first openings 30K1 and second openings 40K1 together form an opening for exposing part of the anode 20 and subsequently used to set the organic light-emitting material. The side of the second pixel definition layer 40 away from the substrate 10 includes a light-emitting layer 50, at least part of the light-emitting layer 50 is located in the first opening 30K1, and optionally, at least part of the light-emitting layer 50 is located in the second opening 40K1. The light-emitting layer 50 can be formed by evaporating an organic light-emitting material. The first opening 30K1 provided in the first pixel definition layer 30 and the second opening 40K1 provided in the second pixel definition layer 40 are used to prevent the occurrence of cross-color and color mixing between the light-emitting layers 50 of two adjacent sub-pixels 00. That is, the first opening 30K1 provided in the first pixel definition layer 30 and the second opening 40K1 provided in the second pixel definition layer 40 are used to define the light-emitting layers 50 of the organic light-emitting materials of adjacent sub-pixels 00, so as to separate the light-emitting layers 50 of different colors into relatively independent structures.

[0074] Optionally, the display panel 000 includes a plurality of sub-pixels 00, one sub-pixel 00 may be arranged corresponding to a light-emitting layer 50 provided with a first opening 30K1, and the plurality of sub-pixels 00 may include a plurality of different colors ( Figure 1 The plurality of sub-pixels 00 may be arranged in an array on the display panel 000, or the plurality of sub-pixels 00 may be arranged in other ways. For details, reference may be made to the pixel arrangement structure of the OLED display panel in the related art for understanding. Figure 1 This is only an example and does not represent the actual arrangement of the sub-pixels 00. Figure 1 The following description is only given by taking the arrangement of multiple sub-pixels 00 in an array as an example. Figure 1 In the figure, a strip-shaped orthographic projection of a sub-pixel 00 onto the light-emitting surface of the display panel 000 is taken as an example. In specific implementation, the shape of the sub-pixel 00 includes but is not limited to this shape and can be designed according to actual needs.

[0075] In this embodiment, the side of the light-emitting layer 50 away from the substrate 10 also includes a cathode layer 60. The cathode layer 60 on the light-emitting layer 50 can form a stacked arrangement of the anode 20, the light-emitting layer 50, and the cathode layer 60. By applying a voltage between the anode 20 and the cathode layer 60, the light-emitting layer 50 of different sub-pixels 00 emits visible light, thereby realizing an image that can be recognized by the user.

[0076] It is understood that the display panel 000 of this embodiment includes but is not limited to the above-mentioned film layer structure, and may also include other film layer structures, such as a thin film encapsulation layer 80 may be provided on the side of the cathode layer 60 away from the substrate 10, and the thin film encapsulation layer 80 may be used to isolate water and oxygen, and prevent water vapor and oxygen in the air from entering the light-emitting layer 50 and the drive array layer 70, thereby causing damage to the components therein, and may also include other film layer structures, such as a planarization layer, etc., which are not described in detail in this embodiment, and may be understood by referring to the structure of the organic light-emitting display panel in the related art. Optionally, the thin film encapsulation layer 80 in this embodiment may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer is used to block the organic layer, and prevent water vapor and oxygen or other impurities in the organic layer from penetrating into the light-emitting layer 50 of the organic light-emitting material to react and destroy the organic light-emitting material, causing the display panel to fail. The organic layer is used to relieve stress and prevent the inorganic layer from being broken by force, thereby causing water vapor and oxygen to invade. The second inorganic layer is used to prevent water vapor and oxygen in the external environment from invading the display panel 000. The first inorganic layer and the second inorganic layer of the thin film encapsulation layer 80 form double protection, which can further reduce the probability of being invaded.

[0077] Optional, such as Figure 1 , Figure 2 and Figure 3 As shown, Figure 3 yes Figure 2 A schematic diagram of a structure in which the light-emitting layer is located between the anode and cathode layers, the light-emitting layer 50 in this embodiment may include a hole injection layer 501, a hole transport layer 502, an organic light-emitting layer 503, a hole blocking layer 504, an electron transport layer 505, and an electron injection layer 506 stacked in a direction Z perpendicular to the plane of the substrate 10; wherein the hole injection layer 501 and the hole transport layer 502 are located between the organic light-emitting layer 503 and the anode 20, and the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506 are located between the organic light-emitting layer 503 and the cathode layer 60, and are successively close to the cathode layer 60. The light-emitting layer 50 includes a common layer; the common layer includes one or more layers of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506.

[0078] In the prior art, the mask for OLED evaporation is mainly evaporated by an open mask, that is, since the light-emitting layer of the organic light-emitting material is formed by full-surface evaporation, a hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc., a common layer (Common Layer) such as a hole injection layer and a hole transport layer are formed. The common layer can be understood as the film layer corresponding to at least three sub-pixels of different colors, which is formed by common evaporation through an open mask. The film layer will cover all sub-pixel areas and the spacing area between sub-pixels. When the OELD device is working, since the common layers of each sub-pixel are connected, the carriers will be transversely conducted in these common layers, causing the common layer to generate a transverse leakage current, resulting in a sub-pixel (target sub-pixel) being lit. Due to the problem of transverse leakage current in the display panel, the sub-pixels adjacent to it are easily affected by the sub-pixel and light up secretly, resulting in the phenomenon of light leakage and color crossover. This electrical light leakage phenomenon is particularly evident in full-color OLED display panels, especially in low grayscale displays, where the color cast problem is particularly serious, thereby reducing the display quality of the OLED display panel.

[0079] In order to solve the above problem, the present embodiment is arranged between two adjacent sub-pixels 00, and the display panel 000 includes at least one partition opening JK, such as Figure 2 and Figure 4 As shown, Figure 4 yes Figure 1 Another cross-sectional structural schematic diagram along the A-A' direction (in order to clearly illustrate the structure of the partition opening of this embodiment, Figure 4 In the embodiment of the present invention, the second pixel definition layer 40 is a first pixel definition layer 40, and the second pixel definition layer 40 is a second pixel definition layer 40. The ... Figure 4The second sub-partition JK2 protrudes toward the sub-pixel 00 relative to the first sub-partition JK1, and thus, the double-layered structure of the first pixel definition layer 30 and the second pixel definition layer 40 can form a single-sided undercut structure on at least one side of the second sub-partition JK2 at the position J1 indicated by the dotted line. Therefore, when the above-mentioned film layers of the light-emitting layer 50 are evaporated to form films, the organic light-emitting material can be located in the first opening 30K1 and the second opening 40K1 to form the light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00, and due to the single-sided undercut structure of the second sub-partition JK2 formed at the J1 position, the common layer of the light-emitting layer 50 can be effectively isolated at the J1 position, which is equivalent to the leakage current path being isolated, and can effectively improve the color crosstalk between adjacent sub-pixels. Especially when the display panel 000 performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels and improve electrical light leakage. At the same time, it does not affect the normal light emission of the pixels, thereby ensuring the low grayscale display effect.

[0080] The first pixel definition layer 30 and the second pixel definition layer 40 of this embodiment are different film layers. The first pixel definition layer 30 and the second pixel definition layer 40 can be made of different materials. Since the two are overlapped and made of different materials, it is more convenient and quick to form a single-side undercut structure of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2. Figure 2 and Figure 4 The formation of the partition opening JK shown in FIG. 1 is possible, and thus in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively partitioned at the partition opening JK, that is, Figure 2 and Figure 4 The setting of the partition port JK of the shape shown in the figure can ensure the isolation of the lateral leakage current, which is conducive to simplifying the process technology and improving the process efficiency, while also improving the color cast problem and improving the display quality.

[0081] It should be noted that, in this embodiment Figure 2 and Figure 4The form of the single-sided undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 of the partition opening JK is only exemplarily drawn. In specific implementation, the form of the single-sided undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 includes but is not limited to this, and may also include other forms, as long as it is satisfied that at the junction of the first sub-partition JK1 and the second sub-partition JK2, along the direction of one sub-pixel 00 pointing to another sub-pixel 00 adjacent to it, the second sub-partition JK2 protrudes in the direction close to the sub-pixel 00 relative to the first sub-partition JK1, and at least the common layer in the light-emitting layer 50 or other film layers with the possibility of lateral leakage current transmission can be isolated at this single-sided undercut structure. The form of the single-sided undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 is not elaborated in this embodiment.

[0082] Optional, such as Figure 1 , Figure 2 and Figure 4 As shown, the sub-pixel 00 includes a first sub-pixel 00A and a second sub-pixel 00B adjacent to each other, the colors of the first sub-pixel 00A and the second sub-pixel 00B may be different, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 includes a first end JK2A and a second end JK2B opposite to each other, and the first end JK2A is located between the second end JK2B and the first sub-pixel 00A;

[0083] At the junction of the first sub-partition JK1 and the second sub-partition JK2 (such as Figure 4 The second sub-partition JK2 is at the position J1 in the figure, relative to the first sub-partition JK1, and the first end JK2A of the second sub-partition JK2 protrudes toward the direction close to the first sub-pixel 00A, thereby forming a single-sided undercut structure of the second sub-partition JK2.

[0084] Or, it can also be understood as Figure 1 , Figure 2 and Figure 4 As shown, the second pixel definition layer 40 includes a first surface 40A in contact with the first pixel definition layer 30;

[0085] Along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A, the second sub-partition JK2 exposes a portion of the first surface 40A;

[0086] At the second end JK2B, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition opening JK, thereby forming a single-sided undercut structure of the second sub-partition JK2 on the side close to the first sub-pixel 00A, while the second sub-partition JK2 is still smooth or continuous on the side close to the second sub-pixel 00B, thereby ensuring that the common layer or cathode layer 60 included in the light-emitting layer 50 will not remain at the partition opening JK. The explanation of this structure can be specifically referred to the subsequent embodiments, and this embodiment will not be repeated here.

[0087] Optionally, other film layers may be included between the cathode layer 60 and the thin film encapsulation layer 80 of the present embodiment, such as a cathode capping layer (CPL) located on the cathode layer 60 and a lithium fluoride (LiF) layer located on the flat layer. The cathode capping layer can improve the light extraction efficiency and increase the luminescent refractive index, thereby improving the efficiency and service life of the light-emitting layer 50. It can also inhibit light absorption, reduce energy loss, and further enhance the performance of the display panel. The lithium fluoride layer can isolate ions to improve the light extraction efficiency. The present embodiment does not elaborate on the film layer structure of the display panel 000. During specific implementation, the film layer structure of the display panel includes but is not limited to this, and may also include other film layer structures that can realize display functions and improve display quality. For details, please refer to the film layer structure of the OLED display panel in the relevant technology for understanding.

[0088] Optional, such as Figure 1-Figure 2 and Figure 5 As shown, Figure 5 yes Figure 2 Another structural schematic diagram in which the light-emitting layer is located between the anode and cathode layers, the light-emitting layer 50 in this embodiment may include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 stacked in a direction Z perpendicular to the plane of the substrate 10;

[0089] The light emitting layer 50 includes a common layer;

[0090] The common layer includes one or more of the hole injection layer 5011 , the hole transport layer 5012 , the charge generation layer 5014 , the hole blocking layer 5016 , the electron transport layer 5017 , and the electron injection layer 5018 .

[0091] This embodiment explains that the light-emitting layer 50 of the display panel 000 may include at least two organic light-emitting layers, that is, the light-emitting layer 50 may include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 stacked along a direction Z perpendicular to the plane of the substrate 10, the hole injection layer 5011 and the hole transport layer 5012 are located between the anode 20 and the first organic light-emitting layer 5013, the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018 are located between the second organic light-emitting layer 5015 and the cathode layer 60, and are close to the cathode layer 60 in sequence.

[0092] In the display panel 000 of this embodiment, the light-emitting layer 50 adopts a structure of at least two organic light-emitting layers, which can be understood as more organic light-emitting layers connected in series. The light extraction efficiency can be effectively improved. Under the same current density, the brightness is also higher. Therefore, the display panel 000 adopting this structure has better light extraction efficiency and higher brightness, which is beneficial to improving the display effect.

[0093] In this embodiment, a charge generation layer 5014 is also included between the first organic light-emitting layer 5013 and the second organic light-emitting layer 5015. The charge generation layer can also be called an electron-hole pair secondary generation layer. The charge generation layer 5014 can include an electron secondary generation layer 5014A and a hole secondary generation layer 5014B. Although the charge generation layer 5014 does not need to be connected to an electrical signal and relies on electric field induction to generate electrons and holes, the charge generation layer 5014 is doped and therefore has better conductivity. Once the charge generation layer 5014 is included in the common layer of the light-emitting layer 50, the impact of the lateral leakage current is greater. Therefore, Figure 2 and Figure 4 As shown, the single-sided undercut structure of the second sub-partition JK2 is formed at the junction (at position J1) of the first sub-partition JK1 and the second sub-partition JK2 of this embodiment. The common layer of the light-emitting layer 50 including the charge generation layer 5014 can be more effectively isolated at the position J1, and the leakage current path is completely isolated, which can effectively improve the color crosstalk between adjacent sub-pixels, especially when the display panel 000 performs low grayscale display, to ensure the low grayscale display effect.

[0094] Optional, such as Figure 1 and Figure 6 As shown, Figure 6 yes Figure 1 Another cross-sectional structural diagram along the A-A' direction, the display panel 000 provided in this embodiment further includes a touch layer 90, and the touch layer 90 is located on a side of the cathode layer 60 away from the substrate 10; further optionally, the touch layer 90 is located on a side of the thin film encapsulation layer 80 away from the substrate 10;

[0095] The touch layer 90 includes a touch electrode 901 . The touch electrode 901 is a grid structure surrounding the light emitting layer 50 . The orthographic projection of the touch electrode 901 on the substrate 10 is located between two adjacent sub-pixels 00 .

[0096] This embodiment explains that the display panel 000 can realize the touch function by setting a touch layer 90, the touch layer 90 is located on the side of the cathode layer 60 away from the substrate 10, and the touch electrode 901 set in the touch layer 90 is generally a metal grid structure. The touch electrode 901 of the metal grid structure is routed around the sub-pixel 00, and the area enclosed by the touch electrode 901 of the grid structure corresponds to the position of the light-emitting layer 50, that is, the touch electrode 901 of the grid route is located between adjacent sub-pixels 00.

[0097] It can be understood that the present embodiment does not elaborate on the structure of the touch electrode 901 of the touch layer 90. The touch layer 90 may include a double-layer or single-layer conductive layer to form a grid-shaped touch electrode 901. The touch electrode 901 may include a touch driving electrode and a touch sensing electrode to realize a touch detection function. When implementing it specifically, reference may be made to the structure of the touch panel displayed in the related art for understanding, and the present embodiment does not elaborate on it here.

[0098] like Figure 7 As shown, Figure 7 is a schematic diagram of a structure of a partition opening in the related art. Since the film encapsulation layer 80' is generally thin, the distance between the touch layer 90' and the cathode layer 60' is relatively close. Therefore, when the touch electrode 901' of the touch layer 90' is located between adjacent sub-pixels 00', and a partition opening JK' is provided between adjacent sub-pixels 00', if the forming form of the partition opening JK' is as follows Figure 7 As shown, although the cathode layer 60' can be isolated at the isolation opening JK', it is likely that Figure 7 The existence of the partition opening JK' of the morphology forms cathode material residue in the partition opening JK', that is, Figure 7 The cathode layer material 601 ′ remaining in the partition opening JK′ is in a floating state. The floating cathode layer material 601 ′ is relatively close to the touch layer 90 ′, so it will interfere with the touch during touch detection and affect the touch accuracy.

[0099] Therefore, this embodiment is arranged at the junction of the first sub-partition JK1 and the second sub-partition JK2 (such as Figure 4The second sub-partition JK2 protrudes toward the sub-pixel 00 relative to the first sub-partition JK1, thereby forming a double-layer structure of the first pixel definition layer 30 and the second pixel definition layer 40, in which only one side of the second sub-partition JK2 is a single-sided undercut structure, at the position J1 indicated by the dotted circle. Therefore, when the above-mentioned film layers of the light-emitting layer 50 are evaporated to form films, the organic light-emitting material is located in the first opening 30K1 and the second opening 40K1 to form the light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00, and because of the single-sided undercut structure of the second sub-partition JK2 formed at the J1 position, the common layer of the light-emitting layer 50 can be effectively isolated at the J1 position, which is equivalent to the leakage current path being isolated, and can effectively improve the color crosstalk of adjacent sub-pixels, especially when the display panel 000 performs low grayscale display to ensure the low grayscale display effect. In addition, the cathode layer 60 can also be isolated in the partition opening JK of the second sub-partition JK2, which has only one side of the single-sided undercut structure, and it can be ensured that no cathode layer material remains in the partition opening JK.

[0100] Specifically, in the film structure of the display panel 000 of this embodiment, as Figure 4 As shown, the second pixel definition layer 40 includes a first surface 40A in contact with the first pixel definition layer 30; in the partition opening JK set between two adjacent sub-pixels 00, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A of the second sub-partition JK2, the second sub-partition JK2 exposes a portion of the first surface 40A; at the second end JK2B of the second sub-partition JK2, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition opening JK, thereby forming the second sub-partition JK2 Only the side close to the first sub-pixel 00A is in the form of a single-sided undercut structure, while the second sub-partition JK2 is still in a smooth shape on the side close to the second sub-pixel 00B. The cathode layer 60 can still form a continuous structure at the second end JK2A of the second sub-partition JK2 in the smooth shape, thereby not only ensuring that the common layer included in the light-emitting layer 50 is isolated at the partition opening JK, but also ensuring that the cathode layer 60 will not remain at the partition opening JK, which is beneficial to improving the touch performance of the display panel 000 and ensuring touch accuracy.

[0101] In some optional embodiments, please refer to Figure 1 , Figure 2 , Figure 4 and Figure 8 , Figure 8 yes Figure 2An enlarged structural schematic diagram of the position of the middle partition opening. In this embodiment, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, and along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, within the partition opening JK, the cathode layer 60 includes only one slit 60K.

[0102] This embodiment explains that in the partition opening JK set between two adjacent sub-pixels 00, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A of the second sub-partition JK2, the second sub-partition JK2 exposes a portion of the first surface 40A; at the second end JK2B of the second sub-partition JK2, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition opening JK, thereby forming a single-side undercut structure of the second sub-partition JK2 only on one side close to the first sub-pixel 00A, and the second sub-partition JK2 is not exposed in the partition opening JK. The second sub-partition JK2 is still in a smooth shape on the side close to the second sub-pixel 00B, and the cathode layer 60 can still form a continuous structure at the second end JK2A of the second sub-partition JK2 in a smooth shape, which can also be understood as the direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B. In the partition opening JK, the cathode layer 60 only includes one slit 60K, that is, one partition opening JK only corresponds to one slit 60K of the cathode layer 60, thereby more effectively ensuring that the cathode layer 60 material will not remain at the partition opening JK, thereby improving the touch sensitivity.

[0103] Optionally, in the cathode layer 60 structure provided in the present embodiment, the cathode layer 60 except for the slit 60K is a continuous structure, that is, the cathode 60 in the display panel 000 as a whole can still be understood as a whole surface, and is only interrupted at the partition opening JK to form a slit 60K of limited size, and is still continuous at the slit 60K, so the cathode layers 60 corresponding to different sub-pixels 00 do not need to be controlled separately, which is conducive to simplifying the drive.

[0104] Optional, such as Figure 1 , Figure 2 , Figure 4 , Figure 8 and Fig. 9 , Fig.10 As shown, Fig. 9 is a schematic diagram of a combination of a sub-pixel arrangement and a partition opening arrangement provided by an embodiment of the present disclosure, Fig.10 is a schematic diagram of another combination of sub-pixel arrangement and partition opening arrangement provided by an embodiment of the present disclosure. In this embodiment, Fig. 9 As shown, the arrangement of the plurality of sub-pixels 00 of the display panel 000 is illustrated by taking the diamond pentile arrangement as an example, and a partition opening JK may be provided between two adjacent sub-pixels 00; Fig.10As shown, the arrangement of multiple sub-pixels 00 of the display panel 000 is illustrated by taking the diamond pentile arrangement as an example, and two partition openings JK can be set between two adjacent sub-pixels 00. The leakage current path can be more thoroughly isolated by setting two partition openings JK between two adjacent sub-pixels 00, and the leakage improvement effect will be better, but the space between two adjacent sub-pixels 00 is limited, and the more the number of partition openings JK between two adjacent sub-pixels 00, the more difficult it is for the current in the cathode layer 60 to flow, the voltage drop will increase, and the power consumption will increase. Therefore, in this embodiment, the number of partition openings JK between two adjacent sub-pixels 00 can be set to 1-2, which can improve the color crosstalk problem, improve the influence of the residual cathode material on the touch performance, and improve the problem of high power consumption of the cathode layer, that is, this embodiment can not only improve the color cast problem, improve the display quality, but also improve the touch sensitivity, and can also ensure the current flow of the cathode layer 60 and reduce power consumption.

[0105] In some optional embodiments, please continue to refer to Figure 1 , Figure 2 and Figure 4 In this embodiment, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, such as along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the width W1 of the partition opening JK ranges from 2 to 8 um.

[0106] This embodiment explains that the width W1 of the partition opening JK is in the range of 2-8um along the direction X from the first sub-pixel 00A to the second sub-pixel 00B. The width W1 of the partition opening JK cannot be too small, otherwise it is easy to cause the common layer of the light-emitting layer 50 and the cathode layer 60 to be difficult to be separated at the partition opening JK; the width W1 of the partition opening JK cannot be too large, otherwise it is easy to affect the current flow transmission of the cathode layer 60, resulting in an increase in the current voltage drop on the cathode layer 60, which will lead to an increase in power consumption. In this embodiment, the width W1 of the partition opening JK in the direction X from the first sub-pixel 00A to the second sub-pixel 00B is set within the range of 2-8um, which can not only improve color crosstalk and color cast problems, improve display quality, but also improve touch sensitivity and reduce power consumption.

[0107] In some optional embodiments, please refer to Figure 1 and Fig.11 , Fig.11 yes Figure 1 Another schematic cross-sectional structure diagram along the AA' direction, in this embodiment, the display panel 000 further includes a color filter layer 100, and the color filter layer 100 is located on a side of the cathode layer 60 away from the substrate 10;

[0108] The color filter layer 100 includes a black matrix 1001 and a color resist 1002 disposed between the black matrix 1001;

[0109] In a direction Z perpendicular to the plane where the substrate 10 is located, the color resist 1002 corresponds to the light emitting layer 50 .

[0110] This embodiment explains that the display panel 000 is an OLED display panel. The display panel 000 may also include a color filter layer 100. The color filter layer 100 may be arranged on the side of the cathode layer 60 away from the substrate 10. Specifically, the color filter layer 100 may be arranged on the side of the thin film encapsulation layer 80 away from the substrate 10, or the color filter layer 100 may be arranged between the thin film encapsulation layer 80 and the touch layer 90. In the related art, in order to prevent the light-emitting layer 50 from reflecting ambient light and affecting the display quality, it is generally necessary to attach an anti-reflection polarizer to the display panel. The polarizer is prone to cause a certain loss of the emitted light, which may reduce the brightness of the display panel. In addition, the thickness of the polarizer is relatively thick, which is not conducive to the design of a flexible display panel. In this embodiment, a color filter layer 100 is used instead of a polarizer. The color filter layer 100 includes a black matrix 1001 and a color resist 1002 arranged between the black matrix 1001. In the direction Z perpendicular to the plane where the substrate 10 is located, the color resist 1002 corresponds to the light-emitting layer 50. The transmittance of the black matrix 1001 is relatively small. The multiple openings opened in the black matrix 1001 are the light-transmitting areas of the black matrix 1001. The color resist 1002 is arranged in the multiple openings opened in the black matrix 1001, that is, each color resist 1002 is placed in an opening corresponding to the black matrix 1001. The color resist 1002 is used to absorb light with a different color from itself, so that light with the same color as itself can pass through, thereby realizing filtering of the display panel 000. In this embodiment, through the setting of the color filter layer 100, the color gamut of the display panel can be compensated while reducing the reflection of ambient light, thereby improving the display quality.

[0111] Optional, please continue to combine reference Figure 1 and Fig.11 In this embodiment, the transmittance of the first pixel definition layer 30 is less than the transmittance of the second pixel definition layer 40 .

[0112] Further optionally, the first pixel definition layer 30 includes a black material.

[0113] This embodiment explains that when the display panel 000 includes a color film layer 100, the light transmittance of the material used to make the first pixel definition layer 30 can be lower than the light transmittance of the second pixel definition layer 40, that is, the material of the first pixel definition layer 30 can be a light-shielding material such as a black material, so that the first pixel definition layer 30 can block external light, thereby reducing the reflectivity of light irradiated to the surface of the first pixel definition layer 30, and preventing external light from irradiating the thin film transistor 70T of the drive array layer 70, which is beneficial to improving the stability of the thin film transistor 70T, and the first pixel definition layer 30 of black material can block crosstalk between adjacent sub-pixels 00, thereby improving the contrast of the display panel 000.

[0114] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In this embodiment, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10 .

[0115] This embodiment explains that the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1, that is, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap with each other to form a accommodating space for at least part of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap with each other to form a light-emitting area of ​​the sub-pixel 00.

[0116] In some optional embodiments, please refer to Figure 1 and Fig.12 , Fig.12 yes Figure 1 Another cross-sectional structural diagram along the AA' direction, in this embodiment, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10;

[0117] At the first opening 30K1 , the second pixel definition layer 40 covers the first pixel definition layer 30 .

[0118] This embodiment explains that the size of the first opening 30K1 can be slightly larger than the size of the second opening 40K1, that is, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10. In this way, after the first pixel definition layer 20 is patterned, when the second pixel definition layer 40 is made, at the first opening 30K1, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, so as to avoid the possibility of foreign matter residue at the first opening 30K1 affecting the evaporation of the light-emitting layer 50, and then causing abnormal light emission, which is beneficial to ensure the light emission quality. In this embodiment, the first pixel definition layer 30 at the first opening 30K1 can be covered by the second pixel definition layer 40. Since the second pixel definition layer 40 can adopt a coating process, it has a stronger ability to fill the gap foreign matter and is not easy to break, so it can effectively cover the foreign matter residue that may appear at the first opening 30K1, which is beneficial to improve the display and light emission quality.

[0119] In some optional embodiments, please continue to refer to Figure 1 , Figure 2, Figure 4 and Figure 6 In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-partition JK2 penetrates part of the thickness of the first pixel definition layer 30, and the first sub-partition JK1 penetrates the thickness of the second pixel definition layer 40.

[0120] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 that penetrates the second pixel definition layer 40, and a second sub-partition JK2 that penetrates part of the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are connected, that is, the second sub-partition JK2 and the first sub-partition JK1 are respectively opened in the first pixel definition layer 30 and the second pixel definition layer 40, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK, and the partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. Thus, along the direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes toward the direction close to the first sub-pixel 00A relative to the first sub-partition JK1, forming a single-sided undercut structure on one side of the second sub-partition JK2. Not only can the common layer of the light-emitting layer 50 be effectively isolated at the J1 position circled by the dotted circle, but the cathode layer 50 can also be effectively isolated at the J1 position circled by the dotted circle, and no cathode layer material will remain, which can effectively improve the color crosstalk between adjacent sub-pixels and improve the touch performance.

[0121] In some optional embodiments, please refer to Figure 1 and Fig.13 , Fig.14 , Fig.13 yes Figure 1 Another cross-sectional structure schematic diagram along the A-A' direction, Fig.14 yes Figure 1 Another cross-sectional structural schematic diagram along the A-A' direction (in order to clearly illustrate the structure of the partition opening of this embodiment, Fig.14 (The film layers above the second pixel definition layer are not shown in the figure). In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-partition opening JK2 penetrates the thickness of the first pixel definition layer 30, and the first sub-partition JK1 penetrates the thickness of the second pixel definition layer 40.

[0122] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 that penetrates the second pixel definition layer 40, and a second sub-partition JK2 that penetrates the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are connected, that is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK, and the partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. Therefore, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in the direction close to the first sub-pixel 00A, forming a single-sided undercut structure on one side of the second sub-partition JK2, so that not only the common layer of the light-emitting layer 50 can be Fig.14 The J2 position outlined by the dotted circle is effectively isolated, and the cathode layer 50 is effectively isolated at the J2 position outlined by the dotted circle, and no cathode layer material remains, which can effectively improve the color crosstalk between adjacent sub-pixels and improve the touch performance.

[0123] The partition opening JK of this embodiment is composed of a first sub-partition JK1 that runs through the entire thickness of the second pixel definition layer 40 and a second sub-partition JK2 that runs through the entire thickness of the first pixel definition layer 30. One side of the second sub-partition JK2 thus formed has a single-sided undercut structure, and the side engraving amount can be larger, which has a better partition effect.

[0124] In some optional embodiments, please continue to refer to Figure 1 , Figure 2 , Figure 4 , Figure 6 , Fig.13 and Fig.14 In this embodiment, the first pixel definition layer 30 further includes a plurality of third openings 30K2, the third openings 30K2 are located between two adjacent first openings 30K1, and the third openings 30K2 penetrate the first pixel definition layer 30;

[0125] In a direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK at least partially overlaps with the third opening 30K2 , and at least a portion of the second pixel definition layer 40 is filled in the third opening 30K2 .

[0126] This embodiment explains how to make the double-layered first pixel definition layer 30 and the second pixel definition layer 40 Figure 4 At the J1 position outlined by the dotted circle, Fig.14Only one side of the second sub-partition JK2 formed at the position J2 outlined by the dotted line is a single-sided undercut structure. When the first pixel definition layer 30 is manufactured and patterned, the first pixel definition layer 30 may include a plurality of first openings 30K1 corresponding to the anode 20, and a plurality of third openings 30K2. The third openings 30K2 are located between two adjacent first openings 30K1, that is, the third openings 30K2 are located between two adjacent sub-pixels 00, and the third openings 30K2 run through the entire thickness of the first pixel definition layer 30. In this embodiment, by setting the third openings 30K2 in the first pixel definition layer 30, after the second pixel definition layer 40 is coated, the second pixel definition layer 40 can be filled in the third openings 30K2 to cover the first pixel definition layer 30 on one side (such as Figure 4 and Fig.14 At the position J3 outlined by the dotted line in the figure, the second pixel definition layer 40 can be filled in the third opening 30K2 to cover the first pixel definition layer 30 on one side), and then after the first pixel definition layer 30 and the second pixel definition layer 40 are completed, when the partition opening JK is made, it is equivalent to the first pixel definition layer 30 on one side of the third opening 30K2 being protected, so that the single-sided undercut structure of the second sub-partition JK2 can be formed only on the side close to the first sub-pixel 00A, so that during the manufacturing process, the shape of the partition opening JK required by this embodiment becomes possible, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there will be no cathode layer material residue, which effectively improves the color crosstalk of adjacent sub-pixels and improves the touch performance.

[0127] It can be understood that the figure of this embodiment is only used as an example to illustrate that the third opening 30K2 penetrates the entire thickness of the first pixel definition layer 30. Figure 1 and Fig.15 As shown, Fig.15 yes Figure 1 Another cross-sectional structural schematic diagram along the A-A' direction, the third opening 30K2 may also only penetrate part of the thickness of the first pixel definition layer 30. Since the single-sided undercut structure of the second sub-partition JK2 is relatively shallow, the area of ​​the first pixel definition layer 30 that needs to be covered and protected by the second pixel definition layer 40 at the third opening 30K2 may also be relatively shallow. Therefore, the first pixel definition layer 30 at the third opening 30K2 may not be completely removed. It is only necessary to ensure that one side of the first pixel definition layer 30 at the third opening 30K2 can be covered by the second pixel definition layer 40 without being cut sideways. In specific implementation, the shape of the third opening 30K2 can be set according to actual needs.

[0128] In some optional embodiments, please refer to Fig.16 and Fig.17 , Fig.16is another schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure, Fig.17 yes Fig.16 A schematic cross-sectional structure diagram along the BB' direction. In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the third opening 30K2 penetrates the thickness of the first pixel definition layer 30;

[0129] The display panel 000 further includes a photosensitive element 00X. In a direction Z perpendicular to the plane where the substrate 10 is located, the photosensitive element 00X at least partially overlaps with the third opening 30K2 .

[0130] This embodiment explains that with the development of display technology, a variety of display devices with fingerprint recognition functions have appeared on the market, such as mobile phones, tablet computers, and smart wearable devices. Common fingerprint recognition methods mainly include under-screen optical fingerprint recognition and under-screen ultrasonic fingerprint recognition, among which under-screen optical fingerprint recognition has become the mainstream in the market due to its price advantage. When under-screen optical fingerprint recognition is applied to an OLED display panel, the under-screen fingerprint recognition element or a photosensitive element 00X such as a distance sensor can be set at the opening of the pixel definition layer by opening the pixel definition layer with poor light transmittance. In this embodiment, two adjacent sub-pixels 00 are provided with a third opening 30K2 that penetrates the first pixel definition layer 30. When the display panel 000 includes a photosensitive element 00X, the third opening 30K2 can be reused as the light-transmitting port of the photosensitive element 00X, and the photosensitive element 00X is set in the direction Z perpendicular to the plane where the substrate 10 is located. At least partially overlap with the third opening 30K2 to ensure that the photosensitive element 00X can be used normally, so as to realize the fingerprint recognition, palm print recognition, distance detection and other photosensitive detection functions of the display panel 000.

[0131] It can be understood that in the display panel 000 of this embodiment, a photosensitive element 00X can be set between two adjacent sub-pixels 00. The photosensitive element 00X can be a fingerprint recognition element. By integrating the photosensitive element 00X into the entire surface of the display panel 000, large-area fingerprint recognition or full-screen fingerprint recognition can be achieved.

[0132] Optionally, the film layer of the photosensitive element 00X of this embodiment can be set in the same layer as part of the film layer of the drive array layer 70, so that the photosensitive element 00X and the thin film transistor 70T or signal wiring in the drive array layer 70 are formed under the same process conditions, which is conducive to simplifying the process flow. Further optionally, the photosensitive element 00X may include a lower electrode 00X1, an upper electrode 00X2, and an intrinsic semiconductor layer 00X3 arranged between the lower electrode 00X1 and the upper electrode 00X2. It can be understood that the setting structure of the photosensitive element 00X of this embodiment is only an example. In specific implementation, the structure of the photosensitive element 00X can also be other. This embodiment is only to explain that the setting film layer of the photosensitive element 00X can be set in the same layer as part of the film layer of the drive array layer 70.

[0133] It can be understood that Fig.16 The arrangement of the sub-pixels 00 and the arrangement position of the photosensitive element 00X are merely exemplified. In specific implementation, the arrangement of the sub-pixels 00 may also be other pixel arrangement structures. In specific implementation, the arrangement may be selected according to actual needs. The number of the third openings 30K2 of this embodiment may be different from the number of the photosensitive elements 00X, that is, the photosensitive element 00X may be arranged directly below a portion of the third openings 30K2, that is, a portion of the third openings 30K2 may be reused as the light-transmitting opening of the photosensitive element 00X.

[0134] Optionally, in this embodiment, the first pixel definition layer 30 and the second pixel definition layer 40 may be made of different materials, and under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40 . The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times the etching rate of the second pixel definition layer 40 with high light transmittance. For example, the first pixel definition layer 30 is a negative material and the second pixel definition layer 40 is a positive material. When the same mask is used to make the partition opening JK, the exposure position of the mask opening of the second pixel definition layer 40 of the positive material will be removed, and the mask blocking position will be left; the exposure position of the mask opening of the first pixel definition layer 30 of the negative material will be left, and the mask blocking position will be removed, so that the partition opening JK can be formed at the junction of the first sub-partition JK1 and the second sub-partition JK2, forming a single-sided undercut structure on only one side of the second sub-partition JK2, thereby ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and no cathode layer material will remain, effectively improving the color crosstalk between adjacent sub-pixels and improving touch performance.

[0135] In some optional embodiments, please refer to Figure 1-Figure 5 , Fig.18: is a flowchart of a method for manufacturing a display panel provided in an embodiment of the present disclosure. This embodiment provides a method for manufacturing a display panel, and the manufacturing method is used to manufacture the display panel 000 in any of the above embodiments; the manufacturing method of this embodiment includes:

[0136] S10: providing a substrate 10;

[0137] S11: manufacturing a plurality of anodes 20, wherein the anodes 20 correspond to the sub-pixels 00; optionally, manufacturing the anodes 20 and the drive array layer 70 can also be completed; Fig.19 As shown, Fig.19 yes Fig.18 A schematic diagram of the structure after the anode is completed in the manufacturing method;

[0138] S12: manufacturing a first pixel definition layer 30, patterning the first pixel definition layer 30, forming a plurality of first openings 30K1, wherein the first openings 30K1 expose a portion of the anode 20; Fig. 20 As shown, Fig. 20 yes Fig.18 A schematic diagram of the structure after the patterned first pixel definition layer is completed in the manufacturing method;

[0139] S13: manufacturing a second pixel definition layer 40, patterning the second pixel definition layer 40, forming a plurality of second openings 40K1, wherein the orthographic projection of the second openings 40K1 on the substrate 10 at least partially overlaps with the orthographic projection of the first openings 30K1 on the substrate 10; Fig.21 As shown, Fig.21 yes Fig.18 A schematic structural diagram of the manufacturing method after the second opening of the second pixel definition layer is completed;

[0140] S14: making a partition opening JK, the partition opening JK is located between two adjacent sub-pixels 00, and in the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 that penetrates the second pixel definition layer 40, and a second sub-partition JK2 that penetrates at least a portion of the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are connected to form the partition opening JK; in the partition opening JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, such as along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in the direction close to the first sub-pixel 00A; Fig. 22 As shown, Fig. 22 yes Fig.18 A schematic diagram of the structure after the partition opening is completed in the manufacturing method;

[0141] S15: manufacturing a light emitting layer 50, wherein at least a portion of the light emitting layer 50 is located in the first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light emitting layer 50 includes a common layer, and the common layer is isolated at the isolation opening JK; Figure 3 As shown, the common layer may be one or more of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506. Figure 5 As shown, the common layer may be one or more of a hole injection layer 5011, a hole transport layer 5012, a charge generation layer 5014, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018; Fig.23 As shown, Fig.23 yes Fig.18 A schematic diagram of the structure after the light-emitting layer is completed in the manufacturing method;

[0142] S16: manufacturing the cathode layer 60, the cathode layer 60 is isolated at the isolation opening JK; Fig.24 As shown, Fig.24 yes Fig.18 Schematic diagram of the structure after the cathode layer is completed in the manufacturing method.

[0143] The manufacturing method of the display panel provided in the present embodiment can form at least one partition opening JK between two adjacent sub-pixels 00 by manufacturing a double-layer structure of a first pixel definition layer 30 and a second pixel definition layer 40 of different materials. Along a direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least a portion of the first pixel definition layer 30. The second sub-partition JK2 is formed when the first pixel definition layer 30 is patterned. The first sub-partition JK1 is formed when the first pixel definition layer 30 is patterned. The partition JK1 is formed when the second pixel definition layer 40 is patterned, and finally the first sub-partition JK1 and the second sub-partition JK2 are connected, that is, the second sub-partition JK2 and the first sub-partition JK1 are respectively opened in the first pixel definition layer 30 and the second pixel definition layer 40, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK, and the partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. The shape of the partition opening JK formed is at the junction of the first sub-partition JK1 and the second sub-partition JK2 (such as Figure 4The second sub-partition JK2 protrudes toward the direction close to the sub-pixel 00 relative to the first sub-partition JK1, and thus a single-sided undercut structure can be formed on one side of the second sub-partition JK2 at the position J1 indicated by the dotted line. When the film layers of the subsequent light-emitting layer 50 are evaporated to form a film, the organic light-emitting material can be located in the first opening 30K1 and the second opening 40K1 to form a light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00, and due to the single-sided undercut structure of the second sub-partition JK2 formed at the position J1, the common layer of the light-emitting layer 50 can be effectively isolated at the position J1 (such as Fig.23 As shown), it is equivalent to that the leakage current path is isolated, which can effectively improve the color crosstalk of adjacent sub-pixels. The cathode layer 60 can also be isolated at the isolation port JK of this form (as shown Fig.24 As shown), especially when the display panel 000 performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time not affect the normal light emission of pixels, thereby ensuring the low grayscale display effect and improving the touch performance.

[0144] It can be understood that the manufacturing method of this embodiment can also include manufacturing other film layer structures of the display panel 000, such as a thin film encapsulation layer 80, a touch layer 90, a color film layer 100, etc. This embodiment is not described in detail here, and the specific details can be understood by referring to the process technology of the OLED display panel in the relevant technology.

[0145] Optionally, when the cathode layer 60 is manufactured in the present embodiment, due to the existence of the partition opening JK, in the direction from one sub-pixel 00 to another adjacent sub-pixel 00, that is, in the direction X from the first sub-pixel 00A to the second sub-pixel 00B, within the partition opening JK, the cathode layer 60 includes only one slit 60K, thereby more effectively ensuring that the cathode layer 60 material will not remain at the partition opening JK, thereby improving the touch sensitivity.

[0146] Optionally, the first pixel definition layer 30 and the second pixel definition layer 40 of this embodiment are different film layers, and the materials used to make the first pixel definition layer 30 and the second pixel definition layer 40 can be different. The first pixel definition layer 30 includes a negative material, and the second pixel definition layer 40 includes a positive material. The transmittance of the first pixel definition layer 30 is less than the transmittance of the second pixel definition layer 40; under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40. Since the two are superimposed and made of different materials, it is more convenient and quick to form a single-sided undercut structure of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2 during the manufacturing process, so that Figure 2 and Figure 4The formation of the partition opening JK shown in FIG. 1 is possible, and thus in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively partitioned at the partition opening JK, that is, Figure 2 and Figure 4 The setting of the partition port JK of the shape shown in the figure can ensure the isolation of the lateral leakage current, which is conducive to simplifying the process technology and improving the process efficiency, while also improving the color cast problem and improving the display quality.

[0147] In some optional embodiments, please refer to Figure 1-Figure 5 , Fig.25 is another flowchart of a method for manufacturing a display panel provided in an embodiment of the present disclosure. This embodiment provides a method for manufacturing a display panel, and the manufacturing method is used to manufacture the display panel 000 in any of the above embodiments; the manufacturing method of this embodiment includes:

[0148] S20: providing a substrate 10;

[0149] S21: manufacturing a plurality of anodes 20, wherein the anodes 20 correspond to the sub-pixels 00; optionally, manufacturing the anodes 20 and the drive array layer 70 can also be completed, such as Fig.19 As shown;

[0150] S22: fabricating the first pixel definition layer 30, patterning the first pixel definition layer 30, forming a plurality of first openings 30K1 and a plurality of third openings 30K2, wherein the third openings 30K2 are located between two adjacent first openings 30K1, and the third openings 30K2 penetrate the thickness of the first pixel definition layer 30, and the first openings 30K1 expose a portion of the anode 20, such as Fig. 20 or the third opening 30K2 penetrates part of the thickness of the first pixel definition layer 30, as shown in FIG. Fig.26 As shown, Fig.26 yes Fig.25 Schematic diagram of the structure after the patterned first pixel definition layer is completed in the manufacturing method; Optionally, the third opening 30K2 and the first opening 30K1 can be completed in one patterning process, or can also be completed separately by two patterning processes, which is not limited in this embodiment;

[0151] S23: fabricating a second pixel definition layer 40, patterning the second pixel definition layer 40, forming a plurality of second openings 40K1, wherein the orthographic projection of the second opening 40K1 on the substrate 10 at least partially overlaps with the orthographic projection of the first opening 30K1 on the substrate 10; at least a portion of the second pixel definition layer 40 is filled in the third opening 30K2, such as Fig.21 and Fig. 27 As shown, Fig. 27 yes Fig.25Schematic diagram of the structure after the second opening of the second pixel definition layer is completed in the manufacturing method; in this process, the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1, that is, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap with each other to form a accommodating space for at least part of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap with each other to form the light-emitting area of ​​the sub-pixel 00. The size of the first opening 30K1 may also be slightly larger than the size of the second opening 40K1, that is, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10. In this way, after the first pixel definition layer 20 is patterned, when the second pixel definition layer 40 is manufactured, at the first opening 30K1, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, so as to avoid the presence of foreign matter residue at the first opening 30K1 that may affect the evaporation of the light-emitting layer 50.

[0152] S24: making a partition opening JK, the partition opening JK is located between two adjacent sub-pixels 00, and in the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 that penetrates the second pixel definition layer 40, and a second sub-partition JK2 that penetrates at least a portion of the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are connected to form the partition opening JK; in the partition opening JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, such as along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in the direction close to the first sub-pixel 00A;

[0153] S241: Making the partition opening JK includes providing a mask L1 (not filled in the figure), wherein the opening L1K of the mask L1 is located between two adjacent sub-pixels 00; etching the second pixel definition layer 40 and the first pixel definition layer 30 at the same etching rate; wherein, in a direction Z perpendicular to the plane where the substrate 10 is located, one side of the opening L1K of the mask L1 is located inside the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2;

[0154] A first sub-partition JK1 is formed between two adjacent sub-pixels 00 of the second pixel definition layer 40, and a second sub-partition JK2 is formed between two adjacent sub-pixels 00 of the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are connected in a direction Z perpendicular to the plane where the substrate 10 is located;

[0155] The second sub-partition JK2 exposes a portion of the first surface 40A of the second pixel definition layer 40, wherein the first surface 40A refers to the surface of the second pixel definition layer 40 facing the first pixel definition layer 30; Fig.28 and Fig.29 As shown, Fig.28 yes Fig.25 A schematic diagram of the position of a mask when making a partition opening in a production method, Fig.29 yes Fig.25 A schematic diagram of the position of another mask when making a partition opening in a manufacturing method;

[0156] S25: manufacturing a light emitting layer 50, wherein at least a portion of the light emitting layer 50 is located in the first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light emitting layer 50 includes a common layer, and the common layer is isolated at the isolation opening JK; Figure 3 As shown, the common layer may be one or more of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506. Figure 5 As shown, the common layer may be one or more of a hole injection layer 5011, a hole transport layer 5012, a charge generation layer 5014, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018. Fig.23 and Fig.30 As shown, Fig.30 yes Fig.25 A schematic diagram of the structure after the light-emitting layer is completed in the manufacturing method;

[0157] S26: manufacturing the cathode layer 60, the cathode layer 60 is isolated at the isolation opening JK, such as Fig.24 and Fig.31 As shown, Fig.31 yes Fig.25 Schematic diagram of the structure after the cathode layer is completed in the manufacturing method.

[0158] This embodiment explains that when the first pixel definition layer 30 is patterned, a third opening 30K2 may be formed between two adjacent first openings 30K1, and the third opening 30K2 may penetrate the thickness of the first pixel definition layer 30 (eg, Fig. 20 ), or may only penetrate a portion of the thickness of the first pixel definition layer 30 (as shown in Fig.26 As shown in FIG. 1 , the third opening 30K2 in the first pixel definition layer 30 is provided so that after the second pixel definition layer 40 is coated, the second pixel definition layer 40 can fill the third opening 30K2 and cover the first pixel definition layer 30 on one side (as shown in FIG. 1 ). Fig.21 and Fig. 27As shown, the second pixel definition layer 40 can be filled in the third opening 30K2 to cover the first pixel definition layer 30 on one side), and then after the first pixel definition layer 30 and the second pixel definition layer 40 are completed, when the partition opening JK is made, the first pixel definition layer 30 on one side of the third opening 30K2 is protected, so that the single-side undercut structure of the second sub-partition JK2 can be formed only on the side close to the first sub-pixel 00A (such as Fig.28 and Fig.29 As shown), a mask L1 is used to make the partition opening JK, and the opening L1K of the mask L1 is located between two adjacent sub-pixels 00. The second pixel definition layer 40 and the first pixel definition layer 30 are etched at the same etching rate. In the direction Z perpendicular to the plane where the substrate 10 is located, one side of the opening L1K of the mask L1 is located inside the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2. Since the materials used to make the first pixel definition layer 30 and the second pixel definition layer 40 can be different, under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40. The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times the etching rate of the second pixel definition layer 40 with high light transmittance. For example, the first pixel definition layer 30 is a negative material and the second pixel definition layer 40 is a positive material. When the same mask L1 is used to make the partition opening JK, the exposure position of the mask L1 opening L1K of the second pixel definition layer 40 of the positive material will be removed, and the mask L1 blocking position will be left; the exposure position of the mask L1 opening L1K of the first pixel definition layer 30 of the negative material will be left, and the mask L1 blocking position will be removed, so that the partition opening JK can be formed at the junction of the first sub-partition JK1 and the second sub-partition JK2, forming a single-sided undercut structure on only one side of the second sub-partition JK2. The manufacturing process of the first pixel definition layer 30 and the partition opening JK of the present embodiment makes it possible to achieve the required shape of the partition opening JK of the present embodiment during the manufacturing process, thereby ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and no cathode layer material will remain, thereby effectively improving the color crosstalk between adjacent sub-pixels and improving the touch performance.

[0159] It can be understood that, since the materials of the first pixel definition layer 30 and the second pixel definition layer 40 are different in this embodiment, the first pixel definition layer 30 can be a negative material, and the second pixel definition layer can be a positive material, so after the first pixel definition layer 30 is coated, a patterning process is performed to form the first opening 30K1 and the third opening 30K2 of the first pixel definition layer 30, and then the second pixel definition layer 40 is coated and the second opening 40K1 is opened. Finally, a mask L1 is used to form a partition opening JK including a first sub-partition JK1 and a second sub-partition JK2 between adjacent sub-pixels 00.

[0160] In some alternative embodiments, please refer to Fig.32 , Fig.32 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Fig.32 The embodiment only takes a mobile phone as an example to illustrate the display device 111. It can be understood that the display device 111 provided in the embodiment of the present disclosure can be a computer, a television, a car display device or other display device 111 with a display function, and the present invention does not specifically limit this. The display device 111 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 000 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0161] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0162] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of sub-pixels, each of which includes an anode; The display panel further includes: A substrate, wherein the anode is located on one side of the substrate; A first pixel definition layer is located on a side of the anode away from the substrate, the first pixel definition layer comprises a plurality of first openings, and the first openings expose a portion of the anode; A second pixel definition layer is located on a side of the first pixel definition layer away from the substrate, the second pixel definition layer comprises a plurality of second openings, and the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate; a light-emitting layer, at least a portion of which is located in the first opening; a cathode layer, the cathode layer being located on a side of the light-emitting layer away from the substrate; Between two adjacent sub-pixels, the display panel includes at least one partition opening, and along a direction perpendicular to the plane where the substrate is located, the partition opening includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer, and the first sub-partition is connected to the second sub-partition; At the boundary between the first sub-partition and the second sub-partition, along the direction from one sub-pixel to another adjacent sub-pixel, the second sub-partition protrudes toward the sub-pixel relative to the first sub-partition.

2. The display panel according to claim 1, characterized in that: The sub-pixel includes a first sub-pixel and a second sub-pixel that are adjacent to each other, and in a direction from the first sub-pixel to the second sub-pixel, the second sub-partition includes a first end and a second end that are opposite to each other, and the first end is located between the second end and the first sub-pixel; At the boundary between the first sub-partition and the second sub-partition, the second sub-partition is opposite to the first sub-partition, and the first end of the second sub-partition protrudes toward the direction approaching the first sub-pixel.

3. The display panel according to claim 2, characterized in that: The second pixel definition layer includes a first surface in contact with the first pixel definition layer; Along the direction from the first sub-pixel to the second sub-pixel, at the first end, the second sub-partition exposes a portion of the first surface; At the second end portion, the first surface of the second pixel definition layer is not exposed in the partition opening.

4. The display panel according to claim 1, characterized in that: Along the direction from one sub-pixel to another adjacent sub-pixel, in the partition opening, the cathode layer includes only one slit.

5. The display panel according to claim 4, characterized in that: The cathode layer is a continuous structure except for the opening.

6. The display panel according to claim 1, characterized in that: The display panel further comprises a color filter layer, and the color filter layer is located on a side of the cathode layer away from the substrate; The color filter layer includes a black matrix and a color resist arranged between the black matrix; In a direction perpendicular to the plane where the substrate is located, the color resist corresponds to the light-emitting layer.

7. The display panel according to claim 6, characterized in that: The transmittance of the first pixel definition layer is smaller than the transmittance of the second pixel definition layer.

8. The display panel according to claim 7, characterized in that: The first pixel definition layer includes a black material.

9. The display panel according to claim 1, characterized in that: The display panel further comprises a touch layer, wherein the touch layer is located on a side of the cathode layer away from the substrate; The touch layer includes a touch electrode, and the touch electrode is a grid structure surrounding the light-emitting layer. The orthographic projection of the touch electrode on the substrate is located between two adjacent sub-pixels.

10. The display panel according to claim 1, characterized in that: The orthographic projection of the first opening on the substrate is located within the orthographic projection of the second opening on the substrate.

11. The display panel according to claim 1, characterized in that: The orthographic projection of the second opening on the substrate is located within the orthographic projection of the first opening on the substrate; At the first opening, the second pixel definition layer covers the first pixel definition layer.

12. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the substrate is located, the second sub-partition penetrates part of the thickness of the first pixel definition layer, and the first sub-partition penetrates the thickness of the second pixel definition layer.

13. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the substrate is located, the second sub-partition opening penetrates through the thickness of the first pixel definition layer, and the first sub-partition penetrates through the thickness of the second pixel definition layer.

14. The display panel according to claim 1, characterized in that: The first pixel definition layer further includes a plurality of third openings, wherein the third openings are located between two adjacent first openings and penetrate the first pixel definition layer; In a direction perpendicular to the plane where the substrate is located, the partition opening and the third opening at least partially overlap, and at least a portion of the second pixel definition layer is filled in the third opening.

15. The display panel according to claim 14, characterized in that: In a direction perpendicular to the plane where the substrate is located, the third opening penetrates the thickness of the first pixel definition layer; The display panel further includes a photosensitive element, and in a direction perpendicular to the plane where the substrate is located, the photosensitive element at least partially overlaps with the third opening.

16. The display panel according to claim 1, characterized in that: The light-emitting layer includes a hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked in a direction perpendicular to the plane of the substrate; The light-emitting layer includes a common layer; the common layer includes one or more layers of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

17. The display panel according to claim 1, characterized in that: The light-emitting layer includes a hole injection layer, a hole transport layer, a first organic light-emitting layer, a charge generation layer, a second organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked in a direction perpendicular to the plane of the substrate; The light-emitting layer includes a common layer; The common layer includes one or more of the hole injection layer, the hole transport layer, the charge generation layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

18. The display panel according to claim 1, characterized in that: Under the same etching conditions, the etching rate of the first pixel definition layer is greater than the etching rate of the second pixel definition layer.

19. The display panel according to claim 18, characterized in that: The first pixel definition layer is a negative material, and the second pixel definition layer is a positive material.

20. The display panel according to claim 1, characterized in that: Along the direction from one sub-pixel to another adjacent sub-pixel, the width of the partition opening is in the range of 2-8 um.

21. A method for manufacturing a display panel, characterized in that: include: providing a substrate; Manufacturing a plurality of anodes, each of the anodes corresponding to a sub-pixel; Manufacturing a first pixel definition layer, and patterning the first pixel definition layer to form a plurality of first openings, wherein the first openings expose a portion of the anode; Manufacturing a second pixel definition layer, and patterning the second pixel definition layer to form a plurality of second openings, wherein the orthographic projections of the second openings on the substrate at least partially overlap with the orthographic projections of the first openings on the substrate; Making a partition opening, wherein the partition opening is located between two adjacent sub-pixels, and in a direction perpendicular to the plane where the substrate is located, the partition opening includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer, and the first sub-partition and the second sub-partition are connected to form the partition opening; At the junction of the first sub-partition and the second sub-partition, along the direction from one sub-pixel to another adjacent sub-pixel, the second sub-partition protrudes toward the sub-pixel relative to the first sub-partition; A light-emitting layer is manufactured, wherein at least a portion of the light-emitting layer is located in a first opening on a side of the second pixel definition layer away from the substrate; the light-emitting layer includes a common layer, and the common layer is isolated at the isolation opening; A cathode layer is manufactured, wherein the cathode layer is partitioned at the partition opening.

22. The method for manufacturing a display panel according to claim 21, characterized in that: Along the direction from one sub-pixel to another adjacent sub-pixel, in the partition opening, the cathode layer includes only one slit.

23. The method for manufacturing a display panel according to claim 21, characterized in that: The first pixel definition layer includes a negative material, the second pixel definition layer includes a positive material, and the transmittance of the first pixel definition layer is less than the transmittance of the second pixel definition layer; Under the same etching conditions, the etching rate of the first pixel definition layer is greater than the etching rate of the second pixel definition layer.

24. The method for manufacturing a display panel according to claim 23, characterized in that: The method further comprises: manufacturing a first pixel definition layer and patterning the first pixel definition layer; A third opening is formed, wherein the third opening is located between two adjacent first openings, and the third opening at least partially penetrates the thickness of the first pixel definition layer.

25. The method for manufacturing a display panel according to claim 24, characterized in that: Manufacturing a second pixel definition layer and patterning the second pixel definition layer further includes: filling at least a portion of the second pixel definition layer in the third opening; Making the partition includes: Providing a mask, wherein the opening of the mask is located between two adjacent sub-pixels; etching the second pixel definition layer and the first pixel definition layer at the same etching rate; wherein, in a direction perpendicular to the plane where the substrate is located, one side of the opening of the mask is located within the third opening, and the other side of the opening of the mask is located outside the third opening; A first sub-partition is formed between two adjacent sub-pixels of the second pixel definition layer, a second sub-partition is formed between two adjacent sub-pixels of the first pixel definition layer, and the first sub-partition is connected to the second sub-partition in a direction perpendicular to the plane where the substrate is located; The second sub-partition exposes a portion of a first surface of the second pixel definition layer, wherein the first surface refers to a surface of the second pixel definition layer facing the first pixel definition layer.

26. A display device, characterized in that: A display panel comprising any one of claims 1-20.

Images