Display device, display panel, and electronic apparatus

Abstract

The invention relates to a display device, a display panel, and an electronic apparatus. The display device may include a hole, a display element, a switching element, an encapsulation layer, a trench, a planarization layer, and a capping layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The slot may be between the aperture and the display element. A portion of the planarization layer may be located between the first edge of the planarization layer and the second edge of the planarization layer and may be located in the slot. The first edge of the planarization layer may be positioned closer to the display element than the second edge of the planarization layer. The capping layer may at least partially cover the first edge of the planarization layer.

Description

[0001] This application is a divisional application of the patent application with application number 201911198974.4 and title “Display Device” filed on November 27, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0153018 filed in the Korean Intellectual Property Office on November 30, 2018, the disclosure of which is incorporated herein by reference in its entirety.

[0004] The technical field relates to display devices. Background Art

[0005] A display device may include a display area for displaying images.

[0006] In the display area of ​​the display device, functions can be added. For example, in addition to displaying images, the display area can receive user input. Summary of the invention

[0007] Embodiments may be directed to a display device including an opening (or hole) that accommodates a functional component in a display area of ​​the display device.

[0008] One or more embodiments may be directed to a display panel including an opening (or hole) for accommodating a functional component.

[0009] According to one or more embodiments, a display device includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a plurality of display elements arranged in the second region; a thin film encapsulation layer covering the plurality of display elements and including an inorganic encapsulation layer and an organic encapsulation layer; a groove provided in the third region; a planarization layer located in the third region and above the groove; and a covering layer located on the planarization layer and at least partially covering a first end of the planarization layer adjacent to the second region.

[0010] The cover layer may include a metal layer.

[0011] The display device may further include: a first insulating layer disposed under the planarization layer.

[0012] The capping layer may include a first portion and a second portion, the first portion extending beyond the first end of the planarization layer and the second portion overlapping the planarization layer, wherein a width of the second portion may be greater than a width of the first portion.

[0013] The first insulating layer may include an inorganic insulating material.

[0014] The display device may further include: a second insulating layer disposed between the planarization layer and the cover layer.

[0015] The second insulating layer and the first insulating layer may contact each other in a region adjacent to one end of the planarization layer.

[0016] The second insulating layer may include an inorganic insulating material.

[0017] The planarization layer may be on the organic encapsulation layer, and may cover one end of the organic encapsulation layer in the third region.

[0018] The display device may further include: lines located in the third area and running around the first area, wherein the cover layer may overlap at least one of the lines.

[0019] The display device may further include: a wiring located in the third region and extending along an edge of the first region.

[0020] The cover layer may have a ring shape in which at least one side of the cover layer is an opening when viewed from a direction perpendicular to the substrate, and a portion of the wiring may be located in the opening region of the cover layer.

[0021] According to one or more embodiments, a display device includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a plurality of display elements arranged in the second region; a thin film encapsulation layer covering the plurality of display elements and including an inorganic encapsulation layer and an organic encapsulation layer; an input sensing layer located on the plurality of display elements; a planarization layer located in the third region; and a metal layer located on the planarization layer and at least partially covering a first end of the planarization layer adjacent to the second region.

[0022] The input sensing layer may include a conductive layer, and the metal layer may include the same material as that of the conductive layer.

[0023] The display device may further include: a first insulating layer under the planarization layer.

[0024] The metal layer may include a first portion and a second portion, the first portion extending beyond the first end of the planarization layer and the second portion overlapping the planarization layer, wherein a width of the second portion may be greater than a width of the first portion.

[0025] The display device may further include: a second insulating layer between the planarization layer and the metal layer.

[0026] The second insulating layer may be integral with the insulating layer included in the input sensing layer.

[0027] The display device may further include: a wiring located in the third region and between the first region and the metal layer.

[0028] A signal for detecting whether a crack occurs around the first region may be applied to the wiring.

[0029] The metal layer may have a ring shape, wherein at least a portion of the metal layer is an opening when viewed from a direction perpendicular to the substrate.

[0030] The display device may further include: wires located in the third region and surrounding the first region, wherein the metal layer may overlap at least one of the wires.

[0031] The lines may include data lines or scan lines.

[0032] The display device may further include: a shielding layer located in the third region and overlapping some of the lines.

[0033] Embodiments may relate to a display device. The display device may include: a hole, a display element, a switch element, an encapsulation layer, a groove, a planarization layer, and a cover layer. The switch element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization layer and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.

[0034] The cover layer may include a metal layer.

[0035] The display device may include: a first insulating layer disposed between the encapsulation layer and a first edge of the planarization layer.

[0036] The cover layer may include a first portion and a second portion. The first edge of the planarization layer may be located between the first portion and the second portion. The second portion may overlap the planarization layer and may be wider than the first portion.

[0037] The first insulating layer may include an inorganic insulating material.

[0038] The display device may include: a second insulating layer disposed between the planarization layer and the cover layer.

[0039] The second insulating layer and the first insulating layer may directly contact each other at the first edge of the planarization layer.

[0040] The second insulating layer may include an inorganic insulating material.

[0041] The encapsulation layer may include an organic encapsulation layer. The planarization layer may partially overlap the organic encapsulation layer. An edge of the organic encapsulation layer may be located between a first edge of the planarization layer and a second edge of the planarization layer.

[0042] The display device may include: a conductive line electrically connected to the transistor and overlapping the cover layer. The hole may be located between two portions of the conductive line. The conductive line may not cross the perimeter of the hole in a plan view of the display device.

[0043] The display device may include: a conductive wiring extending substantially along a perimeter of the hole and substantially surrounding the perimeter of the hole in a plan view of the display device.

[0044] In a plan view of the display device, the two portions of the cover layer may be spaced apart from each other and face each other. A portion of the conductive wiring may be located between the two portions of the cover layer.

[0045] Embodiments may be directed to a display device. The display device may include the following elements: a hole; a display element; a switch element electrically connected to the display element; an input sensing element; an encapsulation layer covering the display element and located between the display element and the input sensing element; a planarization layer located between the hole and the input sensing element, wherein a first edge of the planarization layer may be located closer to the input sensing element than a second edge of the planarization layer; and a metal layer at least partially covering the first edge of the planarization layer.

[0046] The input sensing element may include a conductive layer. The conductive material of the metal layer may be the same as the conductive material of the conductive layer.

[0047] The display device may include a first insulating layer between the encapsulation layer and a first edge of the planarization layer.

[0048] The metal layer may include a first portion and a second portion. The first edge of the planarization layer may be located between the first portion and the second portion. The second portion may overlap the planarization layer and may be wider than the first portion.

[0049] The display device may include: a second insulating layer between the planarization layer and the metal layer.

[0050] The second insulating layer may directly contact the metal layer and each of the conductive members of the input sensing element.

[0051] The display device may include a conductive wiring, and a portion of the conductive wiring may be located between the hole and the metal layer.

[0052] The wiring may substantially surround the perimeter of the hole in a plan view of the display device, and may receive a signal for detecting whether a crack occurs around the hole.

[0053] In a plan view of the display device, the two portions of the metal layer may be spaced apart from each other and face each other. At least a portion of the conductive wiring may be located between the two portions of the metal layer.

[0054] The display device may include a conductive line electrically connected to at least one of the transistor and the input sensing element and overlapping the metal layer. The hole may be located between two portions of the conductive line. The conductive line may not cross the perimeter of the hole in a plan view of the display device.

[0055] The conductive line may be electrically connected to a gate electrode of the switching element or a source electrode of the switching element.

[0056] The display device may include: a shielding layer located between the metal layer and the input sensing element and overlapping the conductive line. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a perspective view of a display device according to an embodiment.

[0058] Figure 2 is a cross-sectional view of a display device according to an embodiment.

[0059] Figure 3 is a plan view of a display panel according to an embodiment.

[0060] Figure 4 is an equivalent circuit diagram of one of the pixels of the display panel according to the embodiment.

[0061] Figure 5 is a plan view of a portion of a display panel according to an embodiment and shows traces located in a middle area.

[0062] Figure 6 is a plan view of a portion of a display panel according to an embodiment and illustrates a groove located in a middle area.

[0063] Figure 7 is a cross-sectional view of a display panel according to an embodiment.

[0064] Figure 8 is a plan view of an input sensing layer according to an embodiment.

[0065] Fig. 9A is a plan view of a first conductive layer of an input sensing layer according to an embodiment.

[0066] Fig. 9B is a plan view of a second conductive layer of an input sensing layer according to an embodiment.

[0067] Fig. 9C is a cross-sectional view of an input sensing layer according to an embodiment.

[0068] Fig. 10A is a plan view of a first conductive layer of an input sensing layer according to an embodiment.

[0069] Fig. 10Bis a plan view of a second conductive layer of an input sensing layer according to an embodiment.

[0070] Fig. 10C is a cross-sectional view of an input sensing layer according to an embodiment.

[0071] Fig.11A is a plan view of a first conductive layer of an input sensing layer according to an embodiment.

[0072] Fig. 11B is a plan view of a second conductive layer of an input sensing layer according to an embodiment.

[0073] Fig. 11C is a cross-sectional view of an input sensing layer according to an embodiment.

[0074] Fig.12 is a cross-sectional view of a display device according to an embodiment.

[0075] Fig.13 According to the embodiment Fig.12 Magnified view of region XIII.

[0076] Fig.14 According to the embodiment Fig.12 FIG. 4 is an enlarged view of region XIV of FIG. 1 and shows a cross-sectional view of the cover layer.

[0077] Fig.15 According to the embodiment Fig.12 FIG. 4 is an enlarged view of region XIV of FIG. 1 and shows a cross-sectional view of the cover layer.

[0078] Fig.16 According to the embodiment Fig.12 FIG. 4 is an enlarged view of region XIV of FIG. 1 and shows a cross-sectional view of the cover layer.

[0079] Fig.17 is a cross-sectional view of a display device according to an embodiment.

[0080] Fig.18 is a plan view of a first area and the vicinity of the first area of ​​a display device according to an embodiment.

[0081] Fig.19 is a plan view of an input sensing layer of a display device according to an embodiment.

[0082] Fig. 20 According to the embodiment Fig.19 A plan view of a first area and the vicinity of the first area.

[0083] Fig.21 According to the embodiment Fig. 20 Magnified view of region XXI.

[0084] Fig. 22 According to the embodiment Fig.21 A cross-sectional view taken along line XXII-XXII'.

[0085] Fig.23 According to the embodiment Fig.21 Cross-sectional views taken along lines XXIIIa-XXIIIa' and XXIIIb-XXIIIb'.

[0086] Fig.24 is a plan view of a first area and the vicinity of the first area of ​​a display device according to an embodiment.

[0087] Fig.25 According to the embodiment Fig.24 Part of the floor plan.

[0088] Fig.26 According to the embodiment Fig.25 A cross-sectional view taken along line XXVI-XXVI'.

[0089] Fig. 27 is a plan view of a first area and the vicinity of the first area of ​​a display device according to an embodiment.

[0090] Fig.28 is a plan view of an opening region of a display device according to an embodiment and the vicinity of the opening region.

[0091] Fig.29 is a cross-sectional view of a portion of a display device according to an embodiment.

[0092] Fig.30 is a plan view of a display device according to an embodiment.

[0093] Fig.31 is a plan view of a cover layer of a display device according to an embodiment. DETAILED DESCRIPTION

[0094] Example embodiments are described with reference to the accompanying drawings. Actual embodiments may be embodied in many different forms and should not be construed as limited to the described example embodiments.

[0095] In the drawings, the same reference numerals may denote the same elements or corresponding elements, and the related descriptions may not be repeated.

[0096] The term "and / or" includes any and all combinations of one or more of the associated items.

[0097] Although the terms "first", "second", etc. can be used to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first element can be referred to as the second element without departing from the teaching of one or more embodiments. The description of an element such as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. herein may also be used to distinguish between elements of different categories or sets. For simplicity, the terms "first", "second", etc. may represent "first type (or first set)", "second type (or second set)", etc., respectively.

[0098] The singular forms "a", "an" and "the" may include plural forms as well, unless the context clearly indicates otherwise.

[0099] The terms “include” and / or “comprising” may specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0100] When a first element is referred to as being “on” or “connected to” a second element, the first element may be directly or indirectly on the second element or directly or indirectly connected to the second element, and one or more intervening elements may be present between the first and second elements.

[0101] When a certain embodiment is implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described successively may be performed substantially simultaneously, or in a reverse order to the described order.

[0102] The term “conductive” may mean “electrically conductive”. The term “trace” may mean “conductive line”. The term “connected” may mean “electrically connected”. The term “insulated” may mean “electrically insulated”. The term “opening” may mean “hole”. The term “opening area” may mean “opening”. The term “end” may mean “edge”. The term “same as” may mean “equal to”. The term “different” may mean “not equivalent to”. The term “contacting” may mean “in direct contact”. The expression “A to B” may mean “in the range of A to B”.

[0103] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0104] refer to Figure 1 The display device 1 includes a first area OA and a display area DA as a second area at least partially surrounding the first area OA. The display device 1 may provide an image using light emitted from a plurality of pixels disposed in the display area DA. In an embodiment, Figure 11 and 2 show that one first area OA is disposed inside the display area DA. In another embodiment, the number of the first areas OA may be two or more. The first area OA may be completely surrounded by the display area DA. The first area OA may be an area or a hole in which a component is disposed.

[0105] The middle area MA may be set as a third area between the first area OA and the display area DA. The display area DA may be surrounded by the outer area PA as a fourth area. The middle area MA and the outer area PA may be non-display areas in which no pixels are set. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the outer area PA.

[0106] An organic light emitting display device is described as the display device 1 according to the embodiment. Alternatively, the display device 1 may be a liquid crystal display, an inorganic light emitting display, or a quantum dot light emitting display.

[0107] Figure 1 The first area OA is shown to be substantially circular. In a plan view (or when viewed from a direction perpendicular to the main surface of the substrate), the first area OA may have one or more other shapes, such as a circular shape, an elliptical shape, a polygonal shape, a star shape, and a diamond shape.

[0108] Although Figure 1 It is shown that one first area OA is provided and is basically circular, but the number of the first areas OA may be two or more, and the shape of each of the first areas OA may be a circular shape, an elliptical shape, a polygonal shape such as a triangular shape or a quadrilateral shape, a star shape, a diamond shape, or an irregular shape, and various modifications may be made.

[0109] Figure 2 is the edge of the display device 1 according to the embodiment Figure 1 A cross-sectional view taken along line II-II'.

[0110] refer to Figure 2 , the display device 1 may include a display panel 10; the display device 1 may further include an input sensing layer 40 and an optical functional layer 50 disposed on the display panel 10. These layers may be covered by a window 60. The display device 1 may include at least one of various electronic devices such as a mobile phone, a notebook computer, and / or a smart watch, may be at least one of various electronic devices such as a mobile phone, a notebook computer, and / or a smart watch, or may be included in at least one of various electronic devices such as a mobile phone, a notebook computer, and / or a smart watch.

[0111] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0112] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may sense an external input using a mutual capacitance method and / or a self-capacitance method.

[0113] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then coupled to the display panel 10 by using an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be continuously formed after a process of forming the display panel 10. In an embodiment, the adhesive layer may not be provided between the input sensing layer 40 and the display panel 10. Although Figure 2 The input sensing layer 40 is shown to be disposed between the display panel 10 and the optical functional layer 50 , but in an embodiment, the input sensing layer 40 may be disposed on the optical functional layer 50 .

[0114] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a retractable synthetic resin film, and the liquid crystal polarizer may include a liquid crystal arranged in a predetermined setting. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or their protective films may be defined as a base layer of the anti-reflection layer.

[0115] In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set by considering the color of the light emitted from the pixels of the display panel 10 respectively. In an embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged in different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may generate destructive interference, and thus the reflectivity of the external light may be reduced.

[0116] The optical function layer 50 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of the light. The lens layer may include a layer having a concave lens or a convex lens shape and / or include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include one of the anti-reflection layer and the lens layer.

[0117] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may include an opening. Figure 2 The display panel 10, the input sensing layer 40 and the optical function layer 50 are shown to include the first to third openings 10H, 40H and 50H, respectively, and the first to third openings 10H, 40H and 50H overlap each other. The first to third openings 10H, 40H and 50H are positioned to correspond to the first area OA, and the first area OA may be an opening. The sizes (or diameters) of the first to third openings 10H, 40H and 50H may be the same as or different from each other. In an embodiment, at least one of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening.

[0118] The first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) in which components 20 for adding various functions to the display device 1 are located. Figure 2 As shown by the solid lines in FIG. 1 , the component 20 may be located in the first to third openings 10H, 40H, and 50H. In an embodiment, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening.

[0119] Component 20 may include / may be an electronic component. For example, component 20 may include an electronic component that uses light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. The electronic component using light may use light in at least one of various bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first area OA may be a transmission area through which light and / or sound is output or received by component 20.

[0120] In an embodiment, in the case where the display device 1 is used as a smart watch or an instrument panel for a car, the component 20 may be a member including a needle of a clock or a needle indicating predetermined information (e.g., the speed of the vehicle, etc.). In the case where the display device 1 includes a component 20 such as a needle of a clock or an instrument panel for a car, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA. In the case where the display device 1 includes a component 20 such as a speaker, the window 60 may include an opening corresponding to the first area OA.

[0121] The component 20 may include an element related to the function of the display panel 10 or an element such as an accessory that increases the aesthetics of the display panel 10. Figure 2 Although not shown in the figure, a layer including OCA or the like may be located between the window 60 and the optical function layer 50 .

[0122] Figure 3 is a plan view of a display panel 10 according to an embodiment, and Figure 4 is an equivalent circuit diagram of one of the pixels of the display panel 10 .

[0123] refer to Figure 3 , the display panel 10 includes a first area OA, a display area DA as a second area, a middle area MA as a third area, and an outer area PA. Figure 3 FIG. 1 is a diagram of a substrate 100 that may be a display panel 10. For example, it may be understood that the substrate 100 includes a first area OA, a display area DA, a middle area MA, and an outer area PA.

[0124] The display panel 10 includes a plurality of pixels P disposed in a display area DA. Figure 4 As shown in , each pixel P includes a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light, or red light, green light, blue light, or white light through the organic light emitting diode OLED.

[0125] The second thin film transistor T2 is a switching thin film transistor and is connected to the scan line SL and the data line DL, and may transmit a data voltage input from the data line DL to the first thin film transistor T1 in response to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the second thin film transistor T2 and a first power supply voltage ELVDD supplied from the driving voltage line PL.

[0126] The first thin film transistor T1 is a driving thin film transistor and can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a predetermined brightness by using the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS.

[0127] Although Figure 4 2 shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the number of thin film transistors and the number of storage capacitors may be variously modified depending on the design of the pixel circuit PC.

[0128] Reference again Figure 3 , the middle area MA may surround the first area OA. The middle area MA is an area in which a display element such as an organic light emitting diode OLED is not disposed. Traces configured to provide signals to pixels P disposed around the first area OA may pass through the middle area MA. A scan driver 1100 configured to provide a scan signal to each pixel P, a data driver 1200 configured to provide a data signal to each pixel P, a main power wiring (not shown) configured to provide a first power voltage ELVDD and a second power voltage ELVSS, etc. may be disposed in the outer area PA. Although Figure 3 The data driver 1200 is shown to be adjacent to one side of the substrate 100 , but according to an embodiment, the data driver 1200 may be disposed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on one side of the display panel 10 .

[0129] Figure 5 is a plan view of a portion of the display panel 10 according to the embodiment, and illustrates traces located in the middle area MA.

[0130] refer to Figure 5 , the pixels P may be disposed in the display area DA, and the middle area MA may be disposed between the first area OA and the display area DA. The pixels P adjacent to the first area OA may be spaced apart from each other around the first area OA. The pixels P may be spaced up and down around the first area OA, or spaced left and right around the first area OA.

[0131] Traces adjacent to the first area OA among the traces configured to supply signals to the pixels P may be routed around the first area OA (or bypassed around the first area OA). Some of the data lines DL crossing the display area DA may extend in the y direction so as to provide data signals to the pixels P disposed at the opposite side of the first area OA, and bypass along the edge of the first area OA in the middle area MA. Some of the scan lines SL crossing the display area DA may extend in the x direction so as to provide scan signals to the pixels P disposed at the opposite side of the first area OA, and bypass along the edge of the first area OA in the middle area MA.

[0132] Figure 6 is a plan view of a portion of the display panel 10 according to the embodiment, and illustrates a groove located in the middle area MA.

[0133] refer to Figure 6 , one or more grooves G are located between the first area OA and the display area DA. Figure 6 , three grooves G are shown to be located between the first area OA and the display area DA, but according to embodiments, one, two, or four or more grooves G may be provided in the middle area MA.

[0134] In a plan view, the groove G may have an annular shape completely surrounding the first area OA and may be located in the middle area MA. In a plan view, each of the grooves G may have a radius from a center C of the first area OA greater than a radius of the first area OA. The grooves G may be spaced apart from each other.

[0135] refer to Figure 5 and Figure 6 , the groove G may be closer to the first area OA than the detour portions of the data lines DL and / or the scan lines SL that detour around the edge of the first area OA.

[0136] Figure 7 is a cross-sectional view of a display panel 10 according to an embodiment, and is Figure 6 The cross section corresponds to the line VII-VII'.

[0137] refer to Figure 7 , the display layer 200 (or pixel array layer or display unit 200) may include pixel circuits PC sequentially arranged in a direction z perpendicular to the xy plane and an organic light emitting diode OLED electrically connected to the pixel circuits PC. The display unit 200 may be arranged in a display area DA. The pixel circuit PC may be arranged on a substrate 100, and the organic light emitting diode OLED may be located on the pixel circuit PC. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst located on the substrate 100. The pixel electrode 221 is electrically connected to the thin film transistor TFT and the storage capacitor Cst.

[0138] The substrate 100 may include a polymer resin or glass. In an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). The substrate 100 may be flexible. The substrate 100 may include a SiO 2 The substrate 100 may include a glass material as a main component, or may include a resin such as reinforced plastic, and may be rigid. The substrate 100 may have a stacked structure including a layer including the above-mentioned polymer resin and a barrier layer located on the above-mentioned polymer resin layer. For example, the substrate 100 may have a stacked structure including a first polymer resin layer, a first barrier layer, a second polymer resin layer, and a second barrier layer. The substrate 100 including the polymer resin may improve flexibility. The barrier layer may include silicon nitride (SiN x ), silicon oxynitride (SiON) or / and silicon oxide (SiO x ).

[0139] A buffer layer 201 configured to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT may be provided on the substrate 100. The buffer layer 201 may include a material such as silicon nitride (SiN x , x>0), silicon oxynitride (SiON) and silicon oxide (SiO x , x>0), and may include a single-layer or multi-layer structure containing the above-mentioned inorganic insulating material.

[0140] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7 The thin film transistor TFT shown in FIG. Figure 4 A driving thin film transistor is described. Figure 7 A top gate thin film transistor TFT is shown. According to an embodiment, the thin film transistor TFT may be a bottom gate thin film transistor.

[0141] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material Mo, Mg, Al, Cu, and / or Ti. The gate electrode GE may include a single layer or a multilayer structure including the above materials.

[0142] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The gate insulating layer 203 may include a single layer or a multilayer structure including the above materials.

[0143] The source electrode SE and the drain electrode DE may include a material having excellent conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Mg, Al, Cu and / or Ti. The source electrode SE and the drain electrode DE may include a single layer or a multilayer structure including the above materials. In an embodiment, the source electrode SE and the drain electrode DE may include a multilayer structure of Ti / Al / Ti.

[0144] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 overlapping each other with a first interlayer insulating layer 205 in between. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, Figure 7 2 shows that the gate electrode GE of the thin film transistor TFT is used as the lower electrode CE1 of the storage capacitor Cst. In an embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0145] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The first and second interlayer insulating layers 205 and 207 may include a single layer or a multilayer structure including the above materials.

[0146] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include a substantially flat top surface. The planarization insulating layer 209 may include an organic insulating material including a general polymer such as polymethyl methacrylate (PMMA) and polystyrene (PS), a polymer derivative having a phenolic group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. In an embodiment, the planarization insulating layer 209 may include polyimide. Alternatively, the planarization insulating layer 209 may include an inorganic insulating material or an inorganic and organic insulating material.

[0147] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 221 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or an alloy thereof. In an embodiment, the pixel electrode 221 may further include a reflective layer including ITO, IZO, ZnO or In on and / or below the reflective layer. 2 O 3 layer.

[0148] The pixel defining layer 211 may be formed on the pixel electrode 221. The pixel defining layer 211 may include an opening exposing the top surface of the pixel electrode 221 and cover the edge of the pixel electrode 221. Alternatively, the pixel defining layer 211 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ). Alternatively, the pixel defining layer 211 may include an organic insulating material and an inorganic insulating material.

[0149] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed under the emission layer 222b and / or a second functional layer 222c disposed on the emission layer 222b. The emission layer 222b may include a low molecular weight material or a polymer organic material that emits light of a predetermined color.

[0150] The first functional layer 222a may include an organic layer. The first functional layer 222a may include a single layer or a multilayer structure. For example, in the case where the first functional layer 222a includes a polymer material, the first functional layer 222a includes a hole transport layer (HTL) having a single layer structure, and may include poly-(3,4)-ethylenedihydroxythiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0151] The second functional layer 222c may be omitted. For example, in the case where the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c is preferably provided. The second functional layer 222c may be a single layer or a multilayer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0152] The emission layer 222b of the intermediate layer 222 may be disposed in all pixels in the display area DA. The emission layer 222b may overlap a portion of the pixel electrode 221 exposed through the opening of the pixel defining layer 211. Unlike the emission layer 222b, the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 may not only be present in the display area DA, but also in the pixel electrode 221. Figure 7 The display area DA may also be present in the middle area MA (see Fig.12 ).

[0153] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca and / or alloys thereof. Alternatively, the counter electrode 223 may further include a conductive material including ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 The counter electrode 223 may be provided not only in the display area DA but also in the middle area MA. The middle layer 222 and the counter electrode 223 may be formed by a thermal deposition method.

[0154] The capping layer 230 may be disposed on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by a thermal deposition method. Alternatively, the capping layer 230 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. Alternatively, the capping layer 230 may be omitted.

[0155] The spacer 213 may be provided on the pixel defining layer 211. The spacer 213 may include an organic insulating material such as polyimide. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or include an organic insulating material and an inorganic insulating material.

[0156] The spacer 213 may include a material different from that of the pixel defining layer 211. Alternatively, the spacer 213 may include the same material as that of the pixel defining layer 211. In an embodiment, the pixel defining layer 211 and the spacer 213 may be formed simultaneously during a mask process using a half-tone mask or the like. In an embodiment, the pixel defining layer 211 and the spacer 213 may include polyimide.

[0157] The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 73 , the thin film encapsulation layer 300 includes first and second inorganic encapsulation layers 310 and 330 and an organic encapsulation layer 320 between the first and second inorganic encapsulation layers 310 and 330. In embodiments, the stacking order, the number of organic encapsulation layers, and the number of inorganic encapsulation layers may be modified.

[0158] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride or silicon oxynitride. The inorganic insulating material may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide and polyethylene.

[0159] The input sensing layer 40 may be disposed on the display panel 10 . Figure 7 4 shows that the input sensing layer 40 is directly formed on the display panel 10 and contacts the thin film encapsulation layer 300 .

[0160] Figure 8 is a plan view of the input sensing layer 40 according to an embodiment. Figure 8 The input sensing layer 40 is shown as Figure 7 The portion corresponding to the display area DA shown in .

[0161] refer to Figure 8 The input sensing layer 40 includes a first sensing electrode SP1 and a second sensing electrode SP2 located in the display area DA. The first sensing electrode SP1 is disposed in the x direction, and the second sensing electrode SP2 is disposed in the y direction crossing the first sensing electrode SP1. The first sensing electrode SP1 and the second sensing electrode SP2 may cross each other perpendicularly.

[0162] The first sensing electrodes SP1 and the second sensing electrodes SP2 may be disposed such that corners of the electrodes are adjacent to each other. Adjacent first sensing electrodes SP1 may be electrically connected to each other through the first connection electrode CP1, and adjacent second sensing electrodes SP2 may be electrically connected to each other through the second connection electrode CP2.

[0163] Fig. 9A and Fig. 9B is a plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40 according to an embodiment, and Fig. 9C is a cross-sectional view of the input sensing layer 40 according to an embodiment, and may be Figure 8 The cross section corresponds to the line VIII-VIII'.

[0164] refer to Fig. 9A and Fig. 9B, the first sensing electrode SP1 and the second sensing electrode SP2 may be disposed on the same layer. The first conductive layer 410 may include a first connection electrode CP1 (see Fig. 9A ), and the second conductive layer 420 may include a first sensing electrode SP1, a second sensing electrode SP2, and a second connection electrode CP2 (see Fig. 9B ).

[0165] The second sensing electrodes SP2 may be connected to each other through the second connection electrodes CP2 disposed on the same layer. The first sensing electrodes SP1 may be disposed in the x direction and may be connected to each other through the first connection electrodes CP1 disposed on different layers.

[0166] refer to Fig. 9C , the intermediate insulating layer 403 may be disposed between the first conductive layer 410 and the second conductive layer 420. The first sensing electrode SP1 disposed in the second conductive layer 420 may be connected to the first connection electrode CP1 disposed in the first conductive layer 410 through the contact hole CNT of the intermediate insulating layer 403. The second conductive layer 420 may be covered by the upper insulating layer 405, and the lower insulating layer 401 may be disposed under the first conductive layer 410. The lower insulating layer 401 and the intermediate insulating layer 403 may include an inorganic insulating layer such as silicon nitride. Alternatively, the lower insulating layer 401 and the intermediate insulating layer 403 may include an organic insulating layer. The upper insulating layer 405 may include an organic insulating layer. Alternatively, the upper insulating layer 405 may include an inorganic insulating layer. The first conductive layer 410 and the second conductive layer 420 may include a metal layer and / or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al and / or an alloy thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). In addition, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, carbon nanotubes, and / or graphene.

[0167] Although in Fig. 9C 4 shows that the lower insulating layer 401 is disposed between the thin film encapsulation layer 300 and the first conductive layer 410 , but in an embodiment, the lower insulating layer 401 may be omitted, and the first conductive layer 410 may be directly located on the thin film encapsulation layer 300 .

[0168] Fig. 10A and Fig. 10B is a plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40 according to an embodiment, and Fig. 10C is a cross-sectional view of the input sensing layer 40 according to an embodiment, and may be Figure 8 The cross section corresponds to the line VIII-VIII'.

[0169] refer to Fig. 10A and Fig. 10B , the first conductive layer 410 may include a first sensing electrode SP1 and a first connection electrode CP1 connected to the first sensing electrode SP1, and the second conductive layer 420 may include a second sensing electrode SP2 and a second connection electrode CP2 connected to the second sensing electrode SP2. The first conductive layer 410 may further include a second auxiliary sensing electrode S-SP2 connected to the second sensing electrode SP2, and the second conductive layer 420 may further include a first auxiliary sensing electrode S-SP1 connected to the first sensing electrode SP1.

[0170] refer to Fig. 10A As shown in the enlarged view, each of the first sensing electrodes SP1 may have a mesh structure including a plurality of holes H. The holes H may overlap with the emission region PE of the pixel. Although not shown, each of the second sensing electrode SP2, the first auxiliary sensing electrode S-SP1, and the second auxiliary sensing electrode S-SP2 may also have a mesh structure including a plurality of holes, each hole overlapping with the emission region PE of the pixel. Fig. 10A The enlarged view corresponds to the emission area PE of the pixel shown in FIG.

[0171] refer to Fig. 10C , the first auxiliary sensing electrode S-SP1 can be connected to the first sensing electrode SP1 through the contact hole CNT of the intermediate insulating layer 403, and the resistance of the first sensing electrode SP1 can be reduced by this structure. Similarly, the second sensing electrode SP2 can be connected to the second auxiliary sensing electrode S-SP2 through the contact hole of the intermediate insulating layer 403. The lower insulating layer 401 and the intermediate insulating layer 403 may include an inorganic insulating layer or an organic insulating layer such as silicon nitride. The upper insulating layer 405 may include an organic insulating layer or an inorganic insulating layer. The first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al and / or their alloys, and may include a single layer or a multilayer structure including the above materials. For example, the first conductive layer 410 and the second conductive layer 420 may include a metal layer including three sublayers of Ti / Al / Ti. The transparent conductive layer may include the above-mentioned transparent conductive layer, a conductive polymer, a metal nanowire and / or graphene.

[0172] Fig.11A and Fig. 11B is a plan view of a first conductive layer 410 and a second conductive layer 420 of an input sensing layer 40 according to an embodiment, and Fig. 11C is a cross-sectional view of the input sensing layer 40 according to an embodiment, and may be Figure 8 The cross section corresponds to the line VIII-VIII'.

[0173] refer to Fig.11A and Fig. 11B The first conductive layer 410 includes a first sensing electrode SP1 and a first connection electrode CP1 connected to the first sensing electrode SP1. The second conductive layer 420 includes a second sensing electrode SP2 and a second connection electrode CP2 connected to the second sensing electrode SP2.

[0174] refer to Fig. 11C , the intermediate insulating layer 403 may be disposed between the first conductive layer 410 and the second conductive layer 420. The intermediate insulating layer 403 does not include a separate contact hole, and the first sensing electrode SP1 and the second sensing electrode SP2 may be electrically insulated from each other using the intermediate insulating layer 403 between the first sensing electrode SP1 and the second sensing electrode SP2. The second conductive layer 420 may be covered by the upper insulating layer 405. The lower insulating layer 401 including an inorganic material or an organic material may be further disposed under the first conductive layer 410. The intermediate insulating layer 403 and the upper insulating layer 405 may include an organic insulating layer or an inorganic insulating layer. The first conductive layer 410 and the second conductive layer 420 may include a metal layer or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al and / or alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). Furthermore, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, carbon nanotubes, and / or graphene.

[0175] Fig.12 is a cross-sectional view of some layers of the display device 1 according to the embodiment, and can be compared with Figure 6 The section taken along line XII-XII' corresponds to, Fig.13 yes Fig.12 Magnified view of region XIII. Fig.14 , Fig.15 and Fig.16 Each of which is according to an embodiment Fig.12 FIG. 7 is an enlarged view of region XIV of FIG. 7 and shows a cross-sectional view of the cover layer 730 . Fig.17 is a cross-sectional view of a display device 1 according to the embodiment.

[0176] refer to Fig.12 The display panel 10 may include a first opening 10H corresponding to the first area OA. The display area DA includes a pixel circuit PC on the substrate 100 , a pixel electrode 221 connected to the pixel circuit PC, and an intermediate layer 222 and an opposing electrode 223 sequentially stacked on the pixel electrode 221 .

[0177] The substrate 100 may include a multi-layer structure. For example, the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 .

[0178] Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0179] Each of the first barrier layer 102 and the second barrier layer 104 may include / may be a barrier layer configured to prevent penetration of external foreign matter, and may include a layer including SiN x and / or SiO x A single or multilayer structure of inorganic materials.

[0180] The pixel circuit PC is disposed on the substrate 100 and includes a thin film transistor and a storage capacitor. The organic light emitting diode including the pixel electrode 221, the emission layer 222b of the intermediate layer 222, and the counter electrode 223 emits predetermined light and is covered by the thin film encapsulation layer 300. The elements disposed in the display area DA are the same as those described above with reference to FIG. Figure 7 The elements described are the same.

[0181] refer to Fig.12 The middle area MA may include a first sub-middle area SMA1 relatively adjacent to the display area DA and a second sub-middle area SMA2 relatively adjacent to the first area OA or the first opening 10H.

[0182] The first sub-middle area SMA1 may be, for example, a reference Figure 5 Describes the area through which the data line DL passes. Fig.12 The data line DL shown in the figure may correspond to a data line that detours or bypasses around the first area OA. The first sub-middle area SMA1 may include a routing area or a bypass area through which the data line DL passes. The width of the first sub-middle area SMA1 may be equal to, less than, or greater than the width of the second sub-middle area SMA2.

[0183] like Fig.12As shown in , the data lines DL may be insulated by an insulating layer. In the case where adjacent data lines DL are disposed above and below an insulating layer (e.g., the second interlayer insulating layer 207) so that the insulating layer is adjacent to the data lines DL, the gap (spacing) between the adjacent data lines DL may be reduced, and the width of the middle area MA may be reduced. In an embodiment, the data lines DL may be disposed on the same insulating layer (e.g., the second interlayer insulating layer 207). Although Fig.12 The data line DL is shown in FIG. 1 and is located in the first middle sub-area SMA1, but the above reference Figure 5 The scan lines SL described as being arranged around the first area OA may also be located in the first sub-middle area SMA1. The shielding layer 80 may be disposed on the data lines DL and / or the scan lines SL located in the first sub-middle area SMA1. The shielding layer 80 may overlap the data lines DL and / or the scan lines SL to prevent the data lines DL and / or the scan lines SL from being observed by the user. In an embodiment, the shielding layer 80 may include a metal.

[0184] The second sub-middle area SMA2 is a groove area in which the grooves are provided. Fig.12 Five grooves are shown in the second sub-middle area SMA2, but the number of grooves may be configured according to the embodiment.

[0185] Each of the grooves G may be formed in a multi-layer structure including a first layer and a second layer including different materials, respectively. Fig.12 1 and 2. It is shown that each groove G is formed in a sub-layer provided in the substrate 100.

[0186] refer to Fig.12 and Fig.13 , the groove G may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. The hole H2 passing through the second barrier layer 104 and the recess R1 formed in the second base layer 103 may be spatially connected to constitute the groove G. The second base layer 103 may correspond to the first layer of the multilayer structure, and the second barrier layer 104 may correspond to the second layer of the multilayer structure.

[0187] During the process of forming the groove G, a portion of the buffer layer 201 on the second barrier layer 104 may be removed substantially simultaneously with the second barrier layer 104 to form the second hole H2. In an embodiment, the buffer layer 201 on the substrate 100 may be a sublayer of the second barrier layer 104 having a multi-layer structure.

[0188] The width of a portion of the groove G passing through the second barrier layer 104 (e.g., the second hole H2) may be smaller than the width of a portion of the groove G passing through the second base layer 103 (e.g., the recess R1). The width W2 (or diameter) of the second hole H2 may be smaller than the width W1 (or diameter) of the recess R1, and the groove G may have an undercut cross-section.

[0189] The side surface of the second barrier layer 104 defining the second hole H2 may protrude toward the center of the groove G relative to the side surface of the second base layer 103 defining the recess R1. The portion of the second barrier layer 104 protruding toward the center of the groove G may constitute a pair of eaves (or a pair of protruding ends, or ends PT). Not only the second barrier layer 104 but also the buffer layer 201 may constitute a pair of eaves.

[0190] The groove G may be formed before the process of forming the intermediate layer 222. A portion (e.g., one or more sub-layers) 222' (e.g., one or more sub-layers) of the intermediate layer 222 extending to the intermediate region MA (e.g., may include a first functional layer 222a and / or a second functional layer 222c) may be disconnected from other portions of the intermediate layer 222 and may be located inside the groove G. Portions of the material layer of the counter electrode 223 and the capping layer 230 including LiF may be disconnected from other portions of the material layer and may be located inside the groove G. The length l of each of the pair of ends PT may be less than 2.0 μm. In an embodiment, the length l may be in the range of about 1.0 μm to about 1.8 μm.

[0191] Although Fig.12 and Fig.13 , the bottom surface of the groove G is shown to be located on a virtual plane between the bottom surface and the top surface of the second substrate layer 103, but in an embodiment, the bottom surface of the groove G may be located on the same plane as the bottom surface of the second substrate layer 103. For example, during the etching process of forming the groove G, the depth dp of the recess R1 may be substantially the same as the thickness t of the second substrate layer 103. In an embodiment, the bottom surface of the groove G may be placed on the same plane as the bottom surface of the second substrate layer 103. The depth dp of the recess R1 may be 2.0 μm or more, 2.5 μm or more, or 3.0 μm or more. In the case where the depth dp of the recess R1 is the same as the thickness t of the second substrate layer 103, the recess R1 may be a hole passing through the second substrate layer 103.

[0192] like Fig.12As shown in , the thin film encapsulation layer 300 covering the display element in the display area DA may extend to cover the middle area MA. For example, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may extend to the middle area MA. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed by CVD or the like, and may have relatively excellent step coverage compared to the portion 222' of the middle layer 222 or the counter electrode 223. Therefore, each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be continuously formed without being disconnected around the groove G. The first inorganic encapsulation layer 310 may cover the inner surface of the groove G. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have different thicknesses. For example, the first inorganic encapsulation layer 310 may have a thickness of about 1 μm, and the second inorganic encapsulation layer 330 may have a thickness of about 0.7 μm, and the thickness of the second inorganic encapsulation layer 330 is less than the thickness of the first inorganic encapsulation layer 310. Alternatively, the thickness of the first inorganic encapsulating layer 310 and the thickness of the second inorganic encapsulating layer 330 may be the same. Alternatively, the thickness of the first inorganic encapsulating layer 310 may be smaller than the thickness of the second inorganic encapsulating layer 330 .

[0193] Although Fig.12 and Fig.13 A structure in which the capping layer 230 including LiF is disconnected around the groove G is shown, but in an embodiment, the capping layer 230 may continuously cover the inner surface of the groove G without being disconnected around the groove G.

[0194] like Fig.12 As shown in , the organic encapsulation layer 320 may cover the display area DA, and the end 320E of the organic encapsulation layer 320 may be located on one side of the first partition wall 510. The organic encapsulation layer 320 may be formed by coating and hardening a monomer. The flow of the monomer may be controlled by the first partition wall 510, and the thickness of the organic encapsulation layer 320 may be controlled by the first partition wall 510. Alternatively, the organic encapsulation layer 320 may be formed by coating a polymer. Since the organic encapsulation layer 320 is separated from the first area OA, external moisture that has penetrated the first opening 10H may be prevented from diffusing to the organic light emitting diode of the display area DA through the organic encapsulation layer 320.

[0195] The first partition wall 510 may include a plurality of layers. Fig.12 The first partition wall 510 is shown to have a stacked structure including a layer including the same material as the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, and a layer including the same material as the planarization insulating layer 209 and the pixel defining layer 211. In an embodiment, the number of layers constituting the first partition wall 510 may be greater than or less than Fig.12 The number of layers shown in .

[0196] The organic material layer 320A is adjacent to the first area OA and is spaced apart from the organic encapsulation layer 320 by a predetermined interval. The organic material layer 320A may be formed during the same process as the process of forming the organic encapsulation layer 320 and may include the same material as the organic encapsulation layer 320. As the flow of the monomer is adjusted by the first partition wall 510 during the process of forming the organic encapsulation layer 320, the organic material layer 320A may be adjusted by the second partition wall 520, and the end 320AE of the organic material layer 320A may be located at one side of the second partition wall 520. Fig.12 As shown in , a portion of the first inorganic encapsulation layer 310 and a portion of the second inorganic encapsulation layer 330 may be located in the middle area MA and may contact each other. If the contact area between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 becomes a specific value or more, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 or an adjacent layer (e.g., a planarization layer 720) may float. According to an embodiment, since the organic material layer 320A is provided, the contact area between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be reduced, and thus the floating of the adjacent layers may be prevented or minimized. The organic material layer 320A may be separated from the organic encapsulation layer 320, and the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other between the end 320E of the organic encapsulation layer 320 and the end 320AE of the organic material layer 320A.

[0197] The planarization layer 720 may be disposed in the middle area MA. The planarization layer 720 may include an organic insulating layer. The planarization layer 720 may include a polymer material. For example, the planarization layer 720 may include one of a silicone resin, an acrylic resin, an epoxy resin, a polyimide, and a polyethylene. The polymer material may be transparent. In an embodiment, the planarization layer 720 may include a material different from that of the organic encapsulation layer 320. For example, the organic encapsulation layer 320 may include a silicone resin, and the planarization layer 720 may include an acrylic resin. In an embodiment, the organic encapsulation layer 320 and the planarization layer 720 may include the same material.

[0198] The planarization layer 720 may cover at least one groove G located in the middle area MA. The planarization layer 720 may improve the flatness of the display panel 10 around the first area OA by covering the area in the middle area MA that is not covered by at least the organic encapsulation layer 320. Therefore, the input sensing layer 40 (see Figure 2 ) and / or optical functional layer 50 (see Figure 2) is separated from the display panel 10 or floats. A portion of the planarization layer 720 may overlap the organic encapsulation layer 320. One end of the planarization layer 720 (eg, a first end (first edge) 720E1 adjacent to the display area DA) may be located on the organic encapsulation layer 320.

[0199] The planarization layer 720 may be formed in the middle area MA by exposure and development processes, etc. The planarization layer 720 may be located only in the middle area MA. In the case where external foreign matter (e.g., moisture) diffuses in the lateral direction (e.g., a direction parallel to the xy plane) of the display panel 10 during some processes (e.g., a washing process) in the process of forming the planarization layer 720, the organic light emitting diode of the display area DA may be damaged. In an embodiment, since the insulating layers (e.g., the first insulating layer 710 and the second insulating layer 740) are respectively disposed under and over the planarization layer 720, moisture penetration problems and / or floating of adjacent layers may be prevented during or after the process of forming the planarization layer 720.

[0200] The first insulating layer 710 may be disposed just below the planarization layer 720. The planarization layer 720 may directly contact the top surface of the first insulating layer 710. The first insulating layer 710 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON). The first insulating layer 710 may directly contact the thin film encapsulation layer 300. For example, the first insulating layer 710 may directly contact the top surface of the second inorganic encapsulation layer 330. The first insulating layer 710 may include the same material as that of the second inorganic encapsulation layer 330, or include a material different from that of the second inorganic encapsulation layer 330. For example, even when the first insulating layer 710 includes silicon nitride, as in the second inorganic encapsulation layer 330, a specific composition ratio (e.g., a content ratio of silicon and nitrogen) may be different, and an interface may be formed between the first insulating layer 710 and the second inorganic encapsulation layer 330. The thickness of the first insulating layer 710 may be less than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the first insulating layer 710 may be the same as or greater than the thickness of the second inorganic encapsulation layer 330.

[0201] The second insulating layer 740 may be disposed on the planarization layer 720, for example, directly on the planarization layer 720. The second insulating layer 740 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x) and / or silicon oxynitride (SiON). The first insulating layer 710 and the second insulating layer 740 may include the same material or different materials. The thickness of the second insulating layer 740 may be greater than the thickness of the first insulating layer 710. Alternatively, the thickness of the second insulating layer 740 may be less than the thickness of the first insulating layer 710 or the same as the thickness of the first insulating layer 710.

[0202] The planarization layer 720 may form a step difference with respect to the underlying layer. Fig.12 and Fig.14 , the first end 720E1 of the planarization layer 720 may form a step difference with respect to the underlying layer (e.g., the first insulating layer 710). In order to prevent the first end 720E1 of the planarization layer 720 from being separated or floating from the underlying layer due to the step difference during the operation of manufacturing the display panel 10 and / or when the display panel 10 is used after manufacturing, the first end 720E1 of the planarization layer 720 may be covered (and fixed) by the cover layer 730. In an embodiment, when the second insulating layer 740 is disposed between the planarization layer 720 and the cover layer 730, the first end 720E1 of the planarization layer 720 may also be covered by the second insulating layer 740.

[0203] The capping layer 730 may include a material different from that of the first insulating layer 710 and the second insulating layer 740. For example, the capping layer 730 may be formed in the same manner as the first insulating layer 710 and the second insulating layer 740. Figures 8 to 11C The cover layer 730 may be formed during the same process as the process of forming at least one conductive layer of the input sensing layer 40 described in one or more of the above. For example, the cover layer 730 may be formed during the same process as the process of forming the first conductive layer 410 or the second conductive layer 420 of the input sensing layer 40. The cover layer 730 may include the same material as the first conductive layer 410 or the second conductive layer 420 of the input sensing layer 40 located in the display area DA. In an embodiment, the cover layer 730 may include a metal layer.

[0204] Fig.14 The planarization layer 720 including the first end 720E1 is shown to have a forward tapered inclination (eg, the inclination angle is an acute angle) relative to the top surface of the first insulating layer 710. Fig.15 As shown in , one end of the planarization layer 720 including the first end 720E1 may have an inclination angle of about 90° relative to the top surface of the first insulating layer 710. Alternatively, as Fig.16 As shown in FIG. 7 , the end of the planarization layer 720 including the first end 720E1 may have a reverse tapered inclination relative to the top surface of the first insulating layer 710 . Fig.15 and Fig.16The end of the planarization layer 720 with the inclined angle shown in FIG. 7 may also be covered by the second insulating layer 740 and / or the capping layer 730. Separation or floating of the planarization layer 720 due to a step difference between the first end 720E1 of the planarization layer 720 and the first insulating layer 710 may be prevented.

[0205] The third width W3 of the cover layer 730 may be tens to hundreds of μm. For example, the third width W3 of the cover layer 730 may be about 50 μm to about 500 μm, or about 50 μm to about 400 μm, or about 50 μm to about 300 μm, or about 50 μm to about 200 μm, or about 60 μm to about 100 μm.

[0206] The capping layer 730 may be located on the planarization layer 720. For example, Figures 12 to 16 As shown in , the cover layer 730 may be directly located on the second insulating layer 740. The first end 730E1 of the cover layer 730 may extend beyond the first end 720E1 of the planarization layer 720 toward the display area DA, and thus a first portion of the cover layer 730 including the first end 730E1 does not overlap with the planarization layer 720. A second end 730E2 of the cover layer 730 opposite to the first end 730E1 may extend toward the first area OA on the planarization layer 720, and thus a second portion of the cover layer 730 including the second end 730E2 may overlap with the planarization layer 720. A width W31 of the first portion of the cover layer 730 may be smaller than a width W32 of the second portion of the cover layer 730. For example, the width W31 of the first portion of the cover layer 730 may be approximately 20 μm, and a width W32 of the second portion of the cover layer 730 may be approximately 60 μm.

[0207] The third insulating layer 750 and the fourth insulating layer 760 may be disposed on the capping layer 730. The third insulating layer 750 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiON). Alternatively, the third insulating layer 750 may include an organic insulating material. The fourth insulating layer 760 may include an inorganic insulating material or an organic insulating material. The fourth insulating layer 760 including an organic insulating material may have a relatively flat top surface. The organic insulating material may include a photoresist (negative or positive) or a polymer-based organic material.

[0208] At least one of the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may include the same as those included in the above reference. Figures 8 to 11CIn one or more of the above described materials, the first insulating layer 710, the second insulating layer 740, the third insulating layer 750, and the fourth insulating layer 760 may each be formed in the same manner as the insulating layer in the input sensing layer 40. Figures 8 to 11C One or more of the processes described in the input sensing layer 40 and at least one insulating layer are formed substantially simultaneously during the same process. Fig.12 As shown in , the first insulating layer 710 may include the same material as the first sub-lower insulating layer 401a as part of the lower insulating layer 401 of the input sensing layer 40, and may be formed as one body with the first sub-lower insulating layer 401a of the input sensing layer 40. The second insulating layer 740 may include the same material as the second sub-lower insulating layer 401b as part of the lower insulating layer 401, and may be formed as one body with the second sub-lower insulating layer 401b. The third insulating layer 750 may include the same material as the middle insulating layer 403 of the input sensing layer 40, and may be formed as one body with the middle insulating layer 403. The fourth insulating layer 760 may include the same material as the upper insulating layer 405 of the input sensing layer 40, and may be formed as one body with the upper insulating layer 405. In an embodiment, the first insulating layer 710, the second insulating layer 740, and the third insulating layer 750 may include an inorganic insulating material, and the fourth insulating layer 760 may include an organic insulating material.

[0209] The first opening 10H and the second opening 40H of the display device 1 may be formed by performing a cutting or scribing process after forming the above-mentioned elements and layers on the substrate 100. The cutting or scribing process may be performed along the first line SCL1. The end of the layer disposed around the first area OA above the substrate 100 may be aligned with the end 100E of the substrate 100 defining the first opening 10H. The end of the layer disposed around the first area OA above the substrate 100 may be located on the same vertical line as the end 100E of the substrate 100 defining the first opening 10H. For example, the end 710E of the first insulating layer 710, the second end 720E2 of the planarization layer 720, and the end 740E of the second insulating layer 740 may be located on the same vertical line as the end 100E of the substrate 100 defining the opening 100H. Similarly, the ends of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, the organic material layer 320A, and the third and fourth insulating layers 750 and 760 may be located on the same vertical line as the end 100E of the substrate 100.

[0210] Fig.12 The region from the first to n-th lines SCL1 to SCLn shown in FIG. 1 may include a region CA through which laser may pass during a cutting or scribing process when manufacturing the display panel 10. The cutting or scribing process may be performed along one of the first to n-th lines SCL1 to SCLn. Fig.17 A cross-sectional structure of the display panel 10 on which a cutting or scribing process has been performed along an n-th line SCLn is shown.

[0211] Fig.12 and Fig.16 The cross-sectional structure shown in FIG. 1 may represent a structure surrounding the first area OA. For example, the groove G between the first area OA and the display area DA may have a ring shape surrounding the first opening 10H and the first area OA, as described above with reference to FIG. Figure 6 Similarly, in the plan view, Fig.12 The planarization layer 720 may have a ring shape surrounding the first opening 10H and the first area OA. Fig.18 A planarization layer 720 is shown.

[0212] Fig.18 is a plan view of the first area OA of the display device 1 according to the embodiment and the vicinity of the first area OA, and illustrates a planarization layer 720 and a capping layer 730 .

[0213] refer to Fig.18 The planarization layer 720 may have a ring shape surrounding the first area OA. The planarization layer 720 may be located in the middle area MA, and in a plan view, a second end 720E2 of the planarization layer 720 may be substantially the same as a perimeter of the first area OA.

[0214] The cover layer 730 may at least partially cover the first end 720E1 of the planarization layer 720 . Fig.18 The capping layer 730 is shown to have a ring shape surrounding the first area OA and completely covering the first end 720E1 of the planarization layer 720. In an embodiment, the capping layer 730 may partially cover the first end 720E1 of the planarization layer 720 and have a shape partially surrounding the first area OA in a plan view.

[0215] The cover layer 730 may include the same as that included in the input sensing layer 40 (see Fig.12 ) and may be located within the input sensing layer 40 (see Fig.12 ) is disposed on the same layer thereon.

[0216] Fig.19 is a plan view of an input sensing layer 40 of a display device 1 according to an embodiment, Fig. 20 yes Fig.19 A plan view of the first area OA and the vicinity of the first area OA, Fig.21 yes Fig. 20 A magnified view of region XXI, Fig. 22 is along Fig.21A cross-sectional view taken along line XXII-XXII', and Fig.23 is along Fig.21 Cross-sectional views taken along lines XXIIIa-XXIIIa' and XXIIIb-XXIIIb'.

[0217] refer to Fig.19 , the input sensing layer 40 may include a first sensing electrode SP1, first traces 415-1, 415-2, 415-3, 415-4, and 415-5 connected to the first sensing electrode SP1, a second sensing electrode SP2, and second traces 425-1, 425-2, 425-3, and 425-4 connected to the second sensing electrode SP2.

[0218] The first sensing electrodes SP1 may be arranged in the x-direction, and the second sensing electrodes SP2 may be arranged in the y-direction intersecting the x-direction. The first sensing electrodes SP1 arranged in the x-direction may be connected to each other through the first connection electrodes CP1 between the adjacent first sensing electrodes SP1, and may constitute the first sensing lines R1, R2, R3, R4, and R5. The second sensing electrodes SP2 arranged in the y-direction may be connected to each other through the second connection electrodes CP2 between the adjacent second sensing electrodes SP2, and may constitute the second sensing lines C1, C2, C3, and C4. The first sensing lines R1, R2, R3, R4, and R5 may intersect the second sensing lines C1, C2, C3, and C4. For example, the first sensing lines R1, R2, R3, R4, and R5 may be perpendicular to the second sensing lines C1, C2, C3, and C4.

[0219] The first sensing lines R1, R2, R3, R4 and R5 and the second sensing lines C1, C2, C3 and C4 are disposed in the display area DA. The first sensing electrode SP1, the first connection electrode CP1, the second sensing electrode SP2 and the second connection electrode CP2 include a conductive material. The specific structures of the first sensing electrode SP1, the first connection electrode CP1, the second sensing electrode SP2 and the second connection electrode CP2 are the same as those in the above reference. 9A to 11C The specific structures described in one or more are the same.

[0220] The first sensing lines R1, R2, R3, R4 and R5 and the second sensing lines C1, C2, C3 and C4 may be connected to the terminals of the sensing signal pad 440 through the first traces 415-1, 415-2, 415-3, 415-4 and 415-5 and the second traces 425-1, 425-2, 425-3 and 425-4 formed in the outer area PA, respectively. The first sensing lines R1, R2, R3, R4 and R5 may be connected to the first traces 415-1, 415-2, 415-3, 415-4 and 415-5, respectively. The second sensing lines C1, C2, C3 and C4 may be connected to the second traces 425-1, 425-2, 425-3 and 425-4, respectively.

[0221] Fig.19 A dual routing structure is shown, in which the second traces 425-1, 425-2, 425-3 and 425-4 are respectively connected to the upper and lower sides of the second sensing lines C1, C2, C3 and C4. The sensing sensitivity can be improved by the dual routing structure. In an embodiment, the second traces 425-1, 425-2, 425-3 and 425-4 are connected to the upper or lower sides of the second sensing lines C1, C2, C3 and C4. According to an embodiment, the settings of the first traces 415-1, 415-2, 415-3, 415-4 and 415-5 and the second traces 425-1, 425-2, 425-3 and 425-4 can be configured depending on the shape and size of the display area DA or the sensing method of the input sensing layer 40, etc.

[0222] The capping layer 730 and the conductive sector group 800 may be located in the middle area MA.

[0223] refer to Fig. 20 , the sector group 800 may include a plurality of sectors, for example, first to seventh sectors 810, 820, 830, 840, 850, 860, and 870. Fig. 20 Seven sectors are shown, but the number of sectors may be configured depending on the embodiment.

[0224] A plurality of sectors (e.g., first to seventh sectors 810, 820, 830, 840, 850, 860, and 870) may be arranged in the middle area MA in a circumferential direction around the first area OA. A plurality of sectors (e.g., first to seventh sectors 810, 820, 830, 840, 850, 860, and 870) may be spaced apart from each other.

[0225] The area of ​​the first sensing electrode SP1 and the second sensing electrode SP2 adjacent to the first area OA may be smaller than the area of ​​the other first sensing electrodes SP1 and the second sensing electrodes SP2. At least one of the sectors (e.g., the first to seventh sectors 810, 820, 830, 840, 850, 860, and 870) may be electrically connected to the first sensing electrode SP1 or the second sensing electrode SP2. With the above connection structure, the sensing sensitivity of the first sensing electrode SP1 or the second sensing electrode SP2 having a relatively small area around the first area OA may be compensated, some of the first sensing electrodes SP1 around the first area OA may be electrically connected to each other through one or more of the sectors, and / or some of the second sensing electrodes SP2 around the first area OA may be electrically connected to each other through one or more of the sectors.

[0226] For example, the second sensing electrodes SP2 respectively disposed at opposite sides (upper and lower sides) of the first area OA may be electrically connected through the first sub-connection electrode 421A and the second sub-connection electrode 421B. The first sub-connection electrode 421A and the second sub-connection electrode 421B may be electrically connected to sectors located on a layer different from the layer where the first sub-connection electrode 421A and the second sub-connection electrode 421B are located. In an embodiment, as Fig. 22 As shown in , the first sub-connection electrode 421A may be located on the lower insulating layer 401, and the first sector 810 may be located on the intermediate insulating layer 403. The first sector 810 may be connected to the first portion 421Aa and the second portion 421Ab of the first sub-connection electrode 421A through a contact hole formed in the intermediate insulating layer 403. Similarly, the second sub-connection electrode 421B may be located on the lower insulating layer 401, the sixth sector 860 may be located on the intermediate insulating layer 403, and the sixth sector 860 may be connected to the first portion 421Ba and the second portion 421Bb of the second sub-connection electrode 421B through a contact hole formed in the intermediate insulating layer 403.

[0227] like Fig. 20 As shown in , adjacent first sensing electrodes SP1 respectively disposed on the upper right side and the upper left side of the first area OA may be electrically connected through the first connection electrode CP1. Adjacent first sensing electrodes SP1 respectively disposed on the lower right side and the lower left side of the first area OA may be electrically connected through the third sub-connection electrode 411A and the fourth sub-connection electrode 411B and the fifth sector 850. In an embodiment, the first sensing electrode SP1, the third sub-connection electrode 411A and the fourth sub-connection electrode 411B and the fifth sector 850 may be located on the same layer and formed as a whole. Alternatively, some of the first sensing electrode SP1, the third sub-connection electrode 411A and the fourth sub-connection electrode 411B and the fifth sector 850 may be disposed on different layers and connected through at least one contact hole formed in the insulating layer.

[0228] At least one of the first to seventh sectors 810 , 820 , 830 , 840 , 850 , 860 , and 870 may be electrically connected to the first sensing electrode SP1 or the second sensing electrode SP2 . Fig. 20 The first sector 810 and the sixth sector 860 are shown to be connected to the second sensing electrode SP2, and the second sector 820, the third sector 830, and the fifth sector 850 are shown to be connected to the first sensing electrode SP1. Alternatively, in another embodiment, as the first sector 810 and the sixth sector 860 are connected to the first sensing electrode SP1 and the second sector 820, the third sector 830, and the fifth sector 850 are connected to the second sensing electrode SP2, the sectors may be electrically connected to sensing electrodes that are adjacent to each other or not adjacent to each other. Some of the sectors (for example, the fourth sector 840 and the seventh sector 870) may not be connected to any of the sensing electrodes.

[0229] The cover layer 730 may be closer to the first area OA than the sector group 800. Fig.21 As shown in FIG. 7 , the first end 730E1 of the cover layer 730 may be spaced apart from the sector by a predetermined interval. The cover layer 730 covers the first end 720E1 of the planarization layer 720 .

[0230] The cover layer 730 may be located on a layer different from the layer on which the sector group 800 is disposed. For example, the first to seventh sectors 810, 820, 830, 840, 850, 860, and 870 may be located on the second conductive layer 420 (see Fig.12 ) is disposed on the same layer thereon, and the cover layer 730 may be located on the first conductive layer 410 of the input sensing layer 40 (see Fig.12 ) is disposed on the same layer thereon. In an embodiment, as Fig.23 As shown in the figure, the covering layer 730 can be located on the second insulating layer 740 (the second insulating layer 740 includes the same material as the second sub-lower insulating layer 401b), and the first sector 810 can be located on the intermediate insulating layer 403 (the intermediate insulating layer 403 includes the same material as the third insulating layer 750).

[0231] The capping layer 730 may include a metal layer. For example, the capping layer 730 may include a metal multilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked.

[0232] Unlike at least one sector in the sector group 800 being electrically connected to the first sensing electrode SP1 or the second sensing electrode SP2, the cover layer 730 may be in a floating state (i.e., not electrically connected to other conductors). For example, the cover layer 730 may include / be a floating electrode. In an embodiment, the cover layer 730 may have a predetermined voltage level (e.g., a constant voltage). For example, the cover layer 730 may be electrically connected to an electrode or line located in the display area DA or the external area PA.

[0233] Fig.24 is a plan view of a first area OA of a display device 1 according to an embodiment and the vicinity of the first area OA, Fig.25 yes Fig.24 A part of the floor plan, Fig.26 is along Fig.25 A cross-sectional view taken along line XXVI-XXVI', and Fig. 27 is a plan view of a first area OA of the display apparatus 1 according to an embodiment and the vicinity of the first area OA.

[0234] refer to Fig.24 , except for the cover layer 730' and the wiring 900, the other components are the same as those in the above reference Figure 20 to Figure 23 One or more of the elements described in the description are similar or substantially the same. The differences are mainly described.

[0235] refer to Figure 20 to Figure 23 The capping layer 730 is described to have a ring shape surrounding the first area OA. Fig.24 The cover layer 730' shown in the figure may have a C shape, wherein at least one side of the cover layer 730' is open. The cover layer 730' may have a width defined by the first end 730E1' and the second end 730E2'. The cover layer 730' may partially surround the first area OA. In a plan view, both ends of the cover layer 730' may be spaced apart from each other by a predetermined interval at the opening portion 731'. A portion of the first end 720E1 of the planarization layer 720 corresponding to the opening portion 731' is not covered by the cover layer 730', as shown in FIG. Fig.25 as shown in .

[0236] The wiring 900 may be disposed in the middle area MA. The wiring 900 includes a first portion 900A and a third portion 900C located in the opening portion 731', and includes a second portion 900B connected between the first portion 900A and the third portion 900C. In an embodiment, the second portion 900B may be located on the same layer on which the first portion 900A is disposed, and may be formed integrally with the first portion 900A. The second portion 900B may not be located on the layer on which the third portion 900C is disposed, and may be connected to the wiring 900B through the contact hole CNT (see Fig.25 ) is electrically connected to the third part 900C.

[0237] In an embodiment, the first portion 900A and the second portion 900B of the wiring 900 may be located on the same layer on which the sector group 800 (the sector group 800 includes the first sector 810) is disposed, and the third portion 900C may be located on the same layer on which the cover layer 730' is disposed. The first portion 900A and the second portion 900B of the wiring 900 may be located on the same layer on which the second conductive layer 420 of the input sensing layer 40 is disposed, and the third portion 900C of the wiring 900 may be located on the same layer on which the first conductive layer 410 of the input sensing layer 40 is disposed. For example, Fig.26 As shown in , the first portion 900A of the wiring 900 may be located on the third insulating layer 750, and the third portion 900C of the wiring 900 may be located on the second insulating layer 740. In an embodiment, the first portion 900A and the second portion 900B of the wiring 900 may be located on the same layer (e.g., the second insulating layer 740) on which the first conductive layer 410 of the input sensing layer 40 is disposed, and the third portion 900C may be located on the same layer (e.g., the third insulating layer 750) on which the second conductive layer 420 of the input sensing layer 40 is disposed.

[0238] Fig.24 and Fig.25 The second portion 900B of the wiring 900 is shown to be formed integrally with the first portion 900A, and the third portion 900C is located on a layer different from the layer on which the first portion 900A and the second portion 900B are disposed. Fig. 27 As shown in , the second portion 900B of the wiring 900 may be located on a layer different from the layer on which the first portion 900A is disposed. The second portion 900B may be located on the same layer on which the third portion 900C is disposed, and may be formed as one body with the third portion 900C. In an embodiment, the second portion 900B may be electrically connected to the first portion 900A through a contact hole CNT formed in the intermediate insulating layer 403.

[0239] A signal applied through the first portion 900A of the wiring 900 may pass through the second portion 900B and may be output through the third portion 900C. When a crack occurs around the first area OA and a portion of the wiring 900 is disconnected, the signal may not be output through the third portion 900C. In this way, the wiring 900 may be used to check whether a crack occurs around the first area OA.

[0240] Fig.28 1 is a plan view of an opening region of the display device 1 according to the embodiment and the vicinity of the opening region.

[0241] exist Fig.28The structure of the wiring 900' and the structure of the cover layer 730' shown in the example are similar to those in the above reference Figure 24 to Figure 27 The structures described are different. The other elements except the wiring 900' and the cover layer 730" are the same as those in the above reference Figure 20 to Figure 23 One or more of the elements described in the description are similar or substantially the same. The differences are mainly described.

[0242] The first portion 900A' of the wiring 900' may be located in the first opening portion 731' of the covering layer 730', and the third portion 900C' may not be located in the first opening portion 731' of the covering layer 730'. The second portion 900B' may connect the first portion 900A' and the third portion 900C', may extend along the inner edge of the covering layer 730', and may extend to the outer edge of the covering layer 730'. The outer edge of the covering layer 730' may represent the first end 730E1' of the covering layer 730', and the inner edge of the covering layer 730' (between the first area OA and the outer edge of the covering layer 730') may represent the second end 730E2' of the covering layer 730'.

[0243] In an embodiment, the second opening portion 732" may be provided at Fig.28 In the embodiment, the number of the second opening portions 732" may be two or more, and thus the second portion 900B' of the wiring 900' may extend repeatedly along the inner edge of the cover layer 730" and the outer edge of the cover layer 730". According to the number of the second opening portions 732", the cover layer 730" may include two segments 730-1" and 730-2" (such as Fig.28 Segments 730-1" and 730-2" may substantially conform to the circumference of the first area OA.

[0244] Fig.29 is a cross-sectional view of a portion of the display device 1 according to the embodiment.

[0245] refer to Fig.29 , the position of the cover layer 730 is the same as that of the above reference Fig.12 The cover layer 730 may be located directly on Fig.29 On the planarization layer 720 shown in .

[0246] The first end of the cover layer 730 may extend toward the display area DA beyond the first end 720E1 of the planarization layer 720. A first portion of the cover layer 730 extending toward the display area DA beyond the first end 720E1 of the planarization layer 720 may directly contact the top surface of the first insulating layer 710. A second end of the cover layer 730 may extend toward the first area OA on the planarization layer 720, and thus a second portion of the cover layer 730 including the second end 730E2 may directly contact the top surface of the planarization layer 720.

[0247] refer to Fig.12 The capping layer 730 described above is disposed on the second insulating layer 740. Fig.29 , the cover layer 730 may be disposed under the second insulating layer 740. In an embodiment, the second insulating layer 740 may include the same material as the first sub-intermediate insulating layer 403a of the intermediate insulating layer 403 included in the input sensing layer 40, and may be formed as one body with the first sub-intermediate insulating layer 403a. The third insulating layer 750 may include the same material as the second sub-intermediate insulating layer 403b of the intermediate insulating layer 403 included in the input sensing layer 40, and may be formed as one body with the second sub-intermediate insulating layer 403b. The first insulating layer 710 may include the same material as the lower insulating layer 401 included in the input sensing layer 40, and may be formed as one body with the lower insulating layer 401. The fourth insulating layer 760 may include the same material as the upper insulating layer 405 included in the input sensing layer 40, and may be formed as one body with the upper insulating layer 405.

[0248] The cover layer 730 may be located on the same layer on which a conductive layer (eg, the first conductive layer 410 included in the input sensing layer 40) is disposed, and may include the same material as that of the first conductive layer 410. Fig.29 The characteristics of the described embodiments apply to the above referenced Figures 15 to 28 One or more of the described embodiments and / or related embodiments.

[0249] Fig.30 is a plan view of a portion of a display device 1 ′ according to the embodiment, and Fig.31 is a plan view of a cover layer 730 of a display device 1 ′ according to an embodiment.

[0250] like Fig.30 As shown in , in the display device 1 ', the first area OA may be partially surrounded by the display area DA. For example, in a plan view, the pixel P may not be provided to the upper side of the first area OA. The middle area MA and the outer area PA between the first area OA and the display area DA may be connected to each other.

[0251] refer to Fig.31 , the cover layer 730 may have a ring shape at least partially surrounding the first area OA. The configuration of the cover layer 730 and the vicinity is similar to that of the above reference Figures 12 to 23 In an embodiment, the cover layer 730 may include the configuration similar to or substantially the same as one or more of the configurations described in Figure 24 to Figure 28 at least one opening portion of one or more of the descriptions.

[0252] Embodiments may prevent defects such as floating or separation of a layer around an opening region from occurring.

[0253] Although example embodiments have been described with reference to the accompanying drawings, various changes may be made in form and details without departing from the scope defined by the appended claims and equivalents.

Claims

1. A display device, comprising: a substrate including an aperture and a display area surrounding the aperture; A pixel electrode located in the display area; a counter electrode disposed on the pixel electrode, the counter electrode overlapping the pixel electrode in the display area; an intermediate layer disposed in the display area between the pixel electrode and the counter electrode; an encapsulation layer disposed on the counter electrode, the encapsulation layer comprising at least one inorganic encapsulation layer and at least one organic encapsulation layer; an input sensing layer disposed on the encapsulation layer, wherein the input sensing layer includes a plurality of touch electrodes in the display area; a planarization layer disposed on the substrate and located in an intermediate region between the hole and the display region, wherein the planarization layer does not overlap with the pixel electrode and a first edge of the planarization layer is located between the display region and a second edge of the planarization layer; and A covering layer at least partially covers the first edge of the planarization layer and exposes the second edge of the planarization layer, wherein the covering layer and at least one of the touch electrodes are arranged in a same layer.

2. The display device according to claim 1, wherein: The cover layer includes a metal material.

3. The display device according to claim 1, wherein: The input sensing layer comprises: a lower insulating layer disposed on the encapsulation layer; a first conductive layer disposed on the lower insulating layer; a second conductive layer disposed on the first conductive layer; and an intermediate insulating layer disposed between the first conductive layer and the second conductive layer, wherein: At least one conductive layer selected from the first conductive layer and the second conductive layer includes a plurality of touch electrodes, and the cover layer includes a same material as that of the at least one conductive layer selected from the first conductive layer and the second conductive layer.

4. The display device according to claim 3, wherein: The lower insulating layer comprises: a first lower sub-insulating layer; and A second lower sub-insulating layer is arranged on the first lower sub-insulating layer, wherein: In the display area, a first portion of the first sub-lower insulating layer and a first portion of the second sub-lower insulating layer are in direct contact with each other, and In the middle region, the second portion of the first sub-lower insulation layer and the second portion of the second sub-lower insulation layer are spaced apart from each other, and a portion of the planarization layer is disposed between the second portion of the first sub-lower insulation layer and the second portion of the second sub-lower insulation layer.

5. The display device according to claim 4, wherein: The encapsulation layer comprises: A first encapsulation layer; a second encapsulation layer disposed on the first encapsulation layer; and An organic encapsulation layer is disposed between the first encapsulation layer and the second encapsulation layer.

6. The display device according to claim 5, further comprising: A partition wall is located in the middle area, wherein a portion of the organic encapsulation layer and the portion of the planarization layer overlap each other in a region between the partition wall and the display area.

7. The display device according to claim 5, wherein: The first lower sub-insulating layer is in direct contact with an upper surface of the second encapsulation layer.

8. The display device according to claim 1, wherein: The cover layer includes a first edge overlapping the planarization layer and a second edge opposite to the first edge of the cover layer, and the first edge of the planarization layer is located between the first edge and the second edge of the cover layer.

9. The display device according to claim 8, wherein: A first width from the first edge of the cover layer to the first edge of the planarization layer is greater than a second width from the second edge of the cover layer to the first edge of the planarization layer.

10. A display device, comprising: a substrate including a hole; a display area surrounding the aperture, wherein a plurality of display elements are disposed in the display area; An encapsulation layer covering the display area, the encapsulation layer comprising an organic encapsulation layer and at least one inorganic encapsulation layer; an input sensing layer overlapping the encapsulation layer; wherein the input sensing layer comprises a plurality of touch electrodes in the display area; a planarization layer located in an intermediate area between the hole and the display area, wherein the planarization layer includes a first edge and a second edge opposite to the first edge, wherein the first edge of the planarization layer is adjacent to the hole of the substrate, and the second edge of the planarization layer is located between the first edge of the planarization layer and the display area; and A covering layer is located in the middle region and at least partially covers the second edge of the planarization layer.

11. The display device according to claim 10, wherein: The cover layer includes a metal material.

12. The display device according to claim 10, wherein: The cover layer includes a first edge and a second edge that are opposite to each other and located between the first edge of the planarization layer and the display area.

13. The display device according to claim 12, wherein: The first edge of the cover layer overlaps the planarization layer, and the second edge of the planarization layer is located between the first edge and the second edge of the cover layer.

14. The display device according to claim 13, wherein: A first width from the first edge of the cover layer to the second edge of the planarization layer is greater than a second width from the second edge of the cover layer to the second edge of the planarization layer.

15. The display device according to claim 10, wherein: In plan view, the cover layer at least partially surrounds the hole in the substrate.

16. The display device according to claim 10, wherein: The input sensing layer further comprises a first insulating layer and a second insulating layer arranged between the encapsulation layer and the plurality of contact electrodes, wherein: A first portion of the first insulating layer and a first portion of the second insulating layer are in direct contact with each other in the display area, and In the middle region, the second portion of the first insulating layer and the second portion of the second insulating layer are spaced apart from each other, and a portion of the planarization layer is between the second portion of the first insulating layer and the second portion of the second insulating layer.

17. The display device according to claim 16, wherein: The at least one inorganic encapsulation layer of the encapsulation layer comprises: a first inorganic encapsulation layer; and A second inorganic encapsulating layer is disposed on the first inorganic encapsulating layer, and the organic encapsulating layer is disposed between the first inorganic encapsulating layer and the second inorganic encapsulating layer.

18. The display device according to claim 17, wherein: The first inorganic encapsulating layer directly contacts the second inorganic encapsulating layer.

19. The display device according to claim 16, wherein: The first inorganic encapsulating layer and the second inorganic encapsulating layer include inorganic insulating materials, respectively.

20. The display device according to claim 10, further comprising: A partition wall is located in the middle area, wherein a portion of the organic encapsulation layer and a portion of the planarization layer overlap each other in a region between the partition wall and the display area.

21. A display panel, comprising: a substrate including a first surface and a second surface opposite to the first surface, the substrate having an opening penetrating from the first surface to the second surface; a plurality of light emitting diodes on the first surface of the substrate and disposed in a display area surrounding the opening in the substrate; a partition wall in a non-display area between the opening in the substrate and the display area and surrounding the opening in the substrate; an encapsulation layer on the plurality of light emitting diodes, the encapsulation layer comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer on the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer; an input sensing layer on the encapsulation layer, the input sensing layer comprising a first insulating layer, a first conductive layer on the first insulating layer, a second conductive layer on the first conductive layer, and an intermediate insulating layer between the first conductive layer and the second conductive layer, wherein each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the first insulating layer extends to the non-display area; a planarization layer interposed between the second inorganic encapsulation layer and the first insulating layer in the non-display area, the planarization layer including a first edge adjacent to the opening in the substrate and a second edge opposite to the first edge; and A conductive layer overlapped with the second edge of the planarization layer, wherein the conductive layer is arranged on the same layer as one conductive layer selected from the first conductive layer and the second conductive layer.

22. The display panel according to claim 21, wherein: The conductive layer and the first conductive layer include the same material and are in direct contact with upper surfaces of the first insulating layer, respectively.

23. The display panel according to claim 21, wherein: At least one conductive layer selected from the first conductive layer and the second conductive layer of the input sensing layer includes a plurality of touch electrodes disposed in the display area, and Wherein, in a plan view, the plurality of touch electrodes include a first touch electrode closest to the opening in the substrate, and the conductive layer is located between the first touch electrode and the opening in the substrate and has a shape that at least partially surrounds the opening in the substrate.

24. The display panel according to claim 23, further comprising: a plurality of sectors spaced apart from each other in the non-display area and in a circumferential direction around the opening in the substrate in a plan view, Wherein, the plurality of sectors comprise conductive material.

25. The display panel according to claim 24, wherein: One of the plurality of sectors is located between the first touch electrode and the conductive layer and is electrically connected to one of the plurality of touch electrodes.

26. The display panel according to claim 24, wherein: The plurality of sectors are arranged at a different layer from the conductive layer.

27. The display panel according to claim 26, wherein: The plurality of sectors are arranged at the same layer as the first conductive layer or the second conductive layer.

28. The display panel according to claim 21, wherein: The organic encapsulation layer extends in the non-display area, and the second edge of the planarization layer overlaps the organic encapsulation layer.

29. The display panel according to claim 28, wherein: The conductive layer comprises a first edge and a second edge opposite to the first edge of the conductive layer; the first edge faces the opening in the substrate and overlaps the planarization layer; and Wherein, a first distance from the second edge of the planarization layer to the first edge of the conductive layer is greater than a second distance from the second edge of the planarization layer to the second edge of the conductive layer.

30. The display panel according to claim 21, wherein: The conductive layer has a shape that at least partially surrounds the opening in the substrate; and The display panel further comprises a wiring, and in a plan view, a portion of the wiring is located between the conductive layer and the opening in the substrate.

31. An electronic device comprising: The display panel comprises an opening area, a display area surrounding the opening area, and a non-display area between the opening area and the display area; as well as a component overlapping the opening area of ​​the display panel; Wherein, the display panel comprises: a substrate including a first surface and a second surface opposite to the first surface, the substrate having an opening penetrating from the first surface to the second surface and corresponding to the opening area; a plurality of light emitting diodes, disposed on the first surface of the substrate and in the display area; an encapsulation layer on the plurality of light emitting diodes, the encapsulation layer comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer on the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer, wherein each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends to the non-display area; an input sensing layer on the packaging layer, the input sensing layer comprising a first conductive layer, a second conductive layer on the first conductive layer, and an intermediate insulating layer between the first conductive layer and the second conductive layer; a planarization layer disposed on the second inorganic encapsulation layer in the non-display area, the planarization layer including a first edge adjacent to the opening in the substrate and a second edge opposite to the first edge; and A conductive layer overlapped with the second edge of the planarization layer, wherein the conductive layer is arranged on the same layer as one conductive layer selected from the first conductive layer and the second conductive layer.

32. The electronic device according to claim 31, wherein: The input sensing layer further includes a first insulating layer opposite to the middle insulating layer, the first conductive layer is between the first insulating layer and the middle insulating layer, and The conductive layer and the first conductive layer include the same material and are arranged on an upper surface of the first insulating layer.

33. The electronic device according to claim 31, wherein: At least one conductive layer selected from the first conductive layer and the second conductive layer of the input sensing layer includes a plurality of touch electrodes disposed in the display area, and Wherein, in a plan view, the plurality of touch electrodes include a first touch electrode closest to the opening in the substrate, and the conductive layer is located between the first touch electrode and the opening in the substrate and has a shape that at least partially surrounds the opening in the substrate.

34. The electronic device according to claim 33, wherein: The display panel further comprises: a plurality of sectors spaced apart from each other in the non-display area and in a circumferential direction around the opening in the substrate in a plan view, Wherein, the plurality of sectors comprise conductive material.

35. The electronic device according to claim 34, wherein: One of the plurality of sectors is located between the first touch electrode and the conductive layer and is electrically connected to one of the plurality of touch electrodes.

36. The electronic device according to claim 34, wherein: The plurality of sectors are arranged at a different layer from the conductive layer.

37. The electronic device according to claim 31, wherein: The organic encapsulation layer extends in the non-display area, and the second edge of the planarization layer overlaps the organic encapsulation layer, and The conductive layer includes a first edge and a second edge opposite to the first edge of the conductive layer; the first edge faces the opening in the substrate and overlaps with the planarization layer.

38. The electronic device according to claim 37, wherein: A first distance from the second edge of the planarization layer to the first edge of the conductive layer is greater than a second distance from the second edge of the planarization layer to the second edge of the conductive layer.

39. The electronic device according to claim 31, wherein: The conductive layer has a shape that at least partially surrounds the opening in the substrate; and The display panel further comprises a wiring, and in a plan view, a portion of the wiring is located between the conductive layer and the opening in the substrate.

40. The electronic device according to claim 31, wherein: The components include sensors or cameras.

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