Display device

Abstract

A display device is provided. The display device includes: a base layer having a display area and a non-display area defined therein; a circuit layer on the base layer; and an element layer on the circuit layer, the element layer including a light emitting element and a light receiving element positionally corresponding to the display area. The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a data line connected to the pixel driving circuit; a readout wiring connected to the sensor driving circuit; a shield electrode overlapping the readout wiring and the sensor driving circuit in a plan view, the shield electrode on the data line; and a pixel connection electrode connecting the pixel driving circuit to the light emitting element, the pixel connection electrode and the shield electrode being on the same layer.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure described herein relate to a display device having a biometric information recognition function. Background Art

[0002] The display device provides various functions that enable the user to interact with the display device. For example, the display device can display an image to provide information to the user, or can sense user input. Recent display devices include a function for sensing biometric information of the user.

[0003] Biometric information may be recognized by using a capacitive sensing technology for sensing a change in capacitance between electrodes, a light sensing technology for sensing incident light using an optical sensor, or an ultrasonic sensing technology for sensing vibration using a piezoelectric element.

[0004] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure relate to a display device with improved biometric information recognition performance.

[0006] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate layer having a display area and a non-display area defined therein; a circuit layer on the substrate layer; and an element layer on the circuit layer, the element layer comprising a light-emitting element and a light-receiving element corresponding in position to the display area. The circuit layer comprises: a pixel driving circuit connected to the light-emitting element; a sensor driving circuit connected to the light-receiving element; a data line connected to the pixel driving circuit; a readout wiring connected to the sensor driving circuit; a shielding electrode overlapping the readout wiring and the sensor driving circuit in a plan view, the shielding electrode being on the data line; and a pixel connecting electrode connecting the pixel driving circuit to the light-emitting element, the pixel connecting electrode being on the same layer as the shielding electrode.

[0007] In some embodiments, each of the light-emitting elements includes a pixel anode electrode, wherein the pixel anode electrode is connected to a corresponding pixel driving circuit among the pixel driving circuits through a corresponding pixel connecting electrode among the pixel connecting electrodes, and the pixel anode electrode and the corresponding pixel connecting electrode are in different layers.

[0008] In some embodiments, a first pixel anode electrode of a first light-emitting element among the light-emitting elements is on a first side of a first readout wiring adjacent to the first pixel anode electrode, and a first pixel driving circuit corresponding to the first light-emitting element among the pixel driving circuits is on a second side of the first readout wiring, and a first pixel connecting electrode among the pixel connecting electrodes connects the first pixel anode electrode and the first pixel driving circuit and overlaps with the first readout wiring in a plan view.

[0009] In some embodiments, two or more sequentially stacked insulating layers are between the first readout wiring and the first pixel connection electrode.

[0010] In some embodiments, the first readout wiring includes: a first readout line portion, on a first intermediate insulating layer; and a second readout line portion, on a second intermediate insulating layer covering the first readout line portion, the second readout line portion being connected to the first readout line portion, and a first pixel connection electrode being on a third intermediate insulating layer covering the second readout line portion and crossing the first readout line portion in a plan view.

[0011] In some embodiments, the first readout wiring includes: a first readout line portion, on a first intermediate insulating layer; and a second readout line portion, on a second intermediate insulating layer covering the first readout line portion, the second readout line portion being connected to the first readout line portion, and a first pixel connection electrode being on a third intermediate insulating layer covering the second readout line portion and crossing the second readout line portion in a plan view.

[0012] In some embodiments, the light receiving elements include: first light receiving elements in a first row; and second light receiving elements in a second row, wherein each of the first light receiving elements overlaps with a corresponding first sensor driving circuit among the sensor driving circuits in a plan view, and each of the second light receiving elements does not overlap with a corresponding second sensor driving circuit among the sensor driving circuits in a plan view.

[0013] In some embodiments, each of the second light receiving elements includes: a second sensor anode electrode; and a sensor connection electrode extending from the second sensor anode electrode and overlapping with the second sensor driving circuit, and the second sensor anode electrode and the sensor connection electrode are on the same layer.

[0014] In some embodiments, each of the first light receiving elements includes: a first sensor anode electrode; and a dummy connecting electrode extending from the first sensor anode electrode, and wherein the first sensor anode electrode overlaps with the first sensor driving circuit and is connected to the second sensor driving circuit.

[0015] In some embodiments, the sum of the area of ​​the dummy connection electrode and the area of ​​the first sensor anode electrode is equal to the sum of the area of ​​the sensor connection electrode and the area of ​​the second sensor anode electrode.

[0016] In some embodiments, the shielding electrode includes: a plurality of main shielding electrodes overlapping with the sensor driving circuit and the readout wiring in a plan view; a first branch shielding electrode extending from at least one of the main shielding electrodes and partially overlapping with the dummy connection electrode in a plan view; and a second branch shielding electrode extending from at least one of the main shielding electrodes and partially overlapping with the sensor connection electrode in a plan view.

[0017] In some embodiments, the main shielding electrodes are spaced apart from each other in an extension direction of each of the readout wirings, and the first pixel connection electrode passes through a separation space between the main shielding electrodes in a direction crossing the extension direction.

[0018] In some embodiments, the data lines include: a first data line, connected to a first group of pixel driving circuits among the pixel driving circuits; and a second data line, separated from the first data line in a first direction and connected to a second group of pixel driving circuits among the pixel driving circuits, wherein the circuit layer also includes data connection lines, which are electrically connected to the second data lines in the display area, respectively.

[0019] In some embodiments, the data connection lines include: a plurality of vertical data connection lines extending along the first data lines; and a plurality of horizontal data connection lines extending in a first direction, wherein the plurality of horizontal data connection lines electrically connect the plurality of vertical data connection lines to the second data lines.

[0020] In some embodiments, a portion of the readout wiring is on a first intermediate insulating layer, a first data line and a second data line and a vertical data connection line are on a second intermediate insulating layer, the second intermediate insulating layer covers a portion of the readout wiring and the first intermediate insulating layer, and a shielding electrode and a pixel connection electrode are on a third intermediate insulating layer, the third intermediate insulating layer covers the first data line and the second data line, the vertical data connection line and the second intermediate insulating layer.

[0021] In some embodiments, each of the light-emitting elements includes a pixel anode electrode, which is connected to a corresponding pixel driving circuit among the pixel driving circuits through a corresponding pixel connecting electrode among the pixel connecting electrodes, and the pixel anode electrode is on a fourth intermediate insulating layer, and the fourth intermediate insulating layer covers the shielding electrode and the pixel connecting electrode.

[0022] In some embodiments, the circuit layer further includes: a first driving voltage line connected to the pixel driving circuit; a second driving voltage line connected to the light emitting element and the light receiving element; and a reset voltage line connected to the sensor driving circuit.

[0023] In some embodiments, the shielding electrode is electrically connected to a reset voltage line.

[0024] In some embodiments, each sensor driving circuit in the sensor driving circuit includes: a reset transistor, including a first electrode for receiving a reset voltage, a second electrode connected to a first sensing node, and a third electrode for receiving a reset control signal; an amplification transistor, including a first electrode for receiving a sensor driving voltage, a second electrode connected to the first sensing node, and a third electrode connected to a second sensing node; and an output transistor, including a first electrode connected to the second sensing node, a second electrode connected to a corresponding readout wiring, and a third electrode for receiving an output control signal.

[0025] In some embodiments, the reset voltage line is electrically connected to the shielding electrode and the first electrode of the reset transistor, and supplies a reset voltage to the shielding electrode and the first electrode of the reset transistor.

[0026] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate layer having a display area and a non-display area defined therein; a circuit layer on the substrate layer; and an element layer on the circuit layer, the element layer comprising a light emitting element and a light receiving element corresponding to the display area. The light receiving element comprises a first light receiving element in a first row and a second light receiving element in a second row. The circuit layer comprises: a pixel driving circuit, connected to the light emitting element, respectively; a first sensor driving circuit, overlapping with the first light receiving element when viewed from above the plane, the first sensor driving circuit being connected to the first light receiving element; and a second sensor driving circuit, connected to the second light receiving element, the second sensor driving circuit being configured not to overlap with the second light receiving element in a plan view. The second light receiving element comprises a sensor connecting electrode, the sensor connecting electrode extending from the second sensor anode electrode toward the second sensor driving circuit and connecting the second sensor anode electrode and the second sensor driving circuit, and the first light receiving element comprises a dummy connecting electrode, the dummy connecting electrode extending from the first sensor anode electrode in a direction opposite to the sensor connecting electrode.

[0027] In some embodiments, the circuit layer further includes: a readout wiring connected to the first sensor driving circuit and the second sensor driving circuit; and a shielding electrode overlapping the readout wiring in a plan view, and the sensor connection electrode and the dummy connection electrode are on an intermediate insulating layer covering the shielding electrode.

[0028] In some embodiments, the shielding electrode includes: a plurality of main shielding electrodes overlapping with the first sensor driving circuit and the second sensor driving circuit in a plan view; a first branch shielding electrode extending from one of the main shielding electrodes and partially overlapping with the dummy connecting electrode in a plan view; and a second branch shielding electrode extending from one of the main shielding electrodes and partially overlapping with the sensor connecting electrode in a plan view.

[0029] In some embodiments, the circuit layer further includes pixel connection electrodes, which connect the pixel driving circuits to the light-emitting elements respectively, and the pixel connection electrodes and the shielding electrodes are on the same layer.

[0030] In some embodiments, the circuit layer further includes: a first driving voltage line connected to the pixel driving circuit; a second driving voltage line connected to the light emitting element and the light receiving element; and a reset voltage line connected to the first sensor driving circuit and the second sensor driving circuit.

[0031] In some embodiments, the shielding electrode is electrically connected to a reset voltage line.

[0032] In some embodiments, the sum of the area of ​​the dummy connection electrode and the area of ​​the first sensor anode electrode is equal to the sum of the area of ​​the sensor connection electrode and the area of ​​the second sensor anode electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects and features of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0034] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0035] Figure 2A is an exploded perspective view of a display device according to some embodiments of the present disclosure.

[0036] Figure 2B is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0037] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0038] Figure 4A is a circuit diagram showing pixels and sensors according to some embodiments of the present disclosure.

[0039] Figure 4B It is used to explain some embodiments of the present disclosure. Figure 4A The waveform diagram of the operation of the pixel and sensor is shown in FIG.

[0040] Figure 5is an enlarged plan view showing a partial area of ​​a display panel according to some embodiments of the present disclosure.

[0041] Fig. 6A is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of the connection structure of a red light emitting element and a red pixel driving circuit shown in FIG.

[0042] Figure 6B is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of a connection structure of a second light receiving element and a second sensor driving circuit shown in FIG.

[0043] Figure 7 is a plan view of a display panel according to some embodiments of the present disclosure.

[0044] FIG. 8A to FIG. 8K is a plan view illustrating a process of stacking a circuit layer and a component layer according to some embodiments of the present disclosure.

[0045] Fig. 9 According to some embodiments of the present disclosure, Figure 8K A cross-sectional view taken along line II' shown in FIG.

[0046] Fig. 10A and Fig. 10B is a plan view showing a portion of a display panel according to some embodiments of the present disclosure.

[0047] Fig. 10C According to some embodiments of the present disclosure, Fig. 10B A cross-sectional view taken along line II-II' shown in FIG.

[0048] Fig.11 is a plan view showing a portion of a display panel according to some embodiments of the present disclosure.

[0049] Fig. 12A and Fig. 12B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to some embodiments of the present disclosure.

[0050] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Throughout the drawings and written descriptions, unless otherwise stated, the same reference numerals indicate the same elements, and therefore, their redundant descriptions may not be repeated.

[0052] When some embodiments can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0053] In the accompanying drawings, for clarity, the relative size, thickness and ratio of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below ... ", "below ... ", "lower part", "below ... ", "above ... " and "upper part" can be used here to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device in use or in operation. For example, if the device in the accompanying drawings is turned over, the element described as "below" or "below" or "below" of other elements or features will then be oriented to "above" other elements or features. Therefore, the example terms "below ... " and "below ... " can cover both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used here should be interpreted accordingly.

[0054] In the drawings, directions DR1, DR2, and DR3 are not limited to the three axes of the rectangular coordinate system (e.g., the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, directions DR1, DR2, and DR3 may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0055] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0056] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, it can be directly on, directly connected to, or directly bound to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element and / or can be indirectly electrically connected using one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0057] The term used here is for the purpose of describing a particular embodiment, and is not intended to limit the present disclosure. As used here, unless the context clearly states otherwise, the singular "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when the terms "include", "comprise", "have", "have" and variations thereof are used in this specification, the stated features, integral bodies, steps, operations, elements and / or components are specified to exist, but one or more other features, integral bodies, steps, operations, elements, components and / or combinations thereof are not excluded from existence or addition. As used here, the term "and / or" includes any combination and all combinations of one or more of the related listed items. For example, the expression "A and / or B" indicates A, B or A and B. When the expression such as "at least one (kind / person) in ... " is after a column of elements, the entire column of elements is modified, rather than the listed individual elements. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0058] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0059] The electronic device or electrical device and / or any other related device or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads that execute computer program instructions and interact with other system components for performing the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). The computer program instructions can also be stored in other non-temporary computer-readable media (such as a CD-ROM or a flash drive, etc. as an example). In addition, it should be appreciated by those skilled in the art that, without departing from the spirit and scope of the exemplary embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed on one or more other computing devices.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0061] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0062] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure. Figure 2A is an exploded perspective view of a display device according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0063] Reference Figure 1 , Figure 2A and Figure 2B According to some embodiments of the present disclosure, the display device DD may have a rectangular shape having short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 crossing the first direction DR1. However, not limited thereto, the display device DD may have various shapes such as a circular shape and a polygonal shape.

[0064] The display device DD may be a device activated by an electrical signal. The display device DD may include various embodiments. For example, the display device DD may be applied to an electronic device such as a smart watch, a tablet computer, a notebook computer, a computer, or a smart TV.

[0065] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The expression "when viewed from above a plane" used herein may mean viewing in the third direction DR3.

[0066] An upper surface of the display device DD may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface IS.

[0067] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which the image IM is displayed. The user visually recognizes the image IM through the transmission area TA. In some embodiments, the transmission area TA is shown in a rounded quadrilateral shape. However, this is illustrative, and the transmission area TA may have various suitable shapes and is not limited to any one embodiment.

[0068] The border area BZA may be adjacent to the transmission area TA. The border area BZA may have a preset color. The border area BZA may surround the transmission area TA (e.g., around the transmission area TA). Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is illustrative, and the border area BZA may be set to be adjacent to only one side of the transmission area TA, or may be omitted.

[0069] The display device DD can sense external input applied from the outside. The external input may include various suitable types of input provided from outside the display device DD. For example, the external input may include not only contact with a part of the user's body (e.g., the user's hand US_F) or contact with a separate device (e.g., an active pen or a digitizer), but also external input applied near the display device DD or applied adjacent to the display device DD at a preset distance (e.g., hovering). In addition, the external input may have various suitable forms (e.g., various suitable kinds) such as force, pressure, temperature, and light.

[0070] The display device DD may sense biometric information of a user applied from the outside. A biometric information sensing area capable of sensing the biometric information of the user may be provided on the display surface IS of the display device DD. The biometric information sensing area may be provided in the entire area of ​​the transmission area TA, or may be provided in a partial area of ​​the transmission area TA. Figure 1 An example is shown in which the entire transmission area TA is used as the biometric information sensing area.

[0071] The display device DD may include a window WM, a display module DM, and a case EDC. In some embodiments, the window WM and the case EDC may be combined with each other to form a housing of the display device DD.

[0072] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded by an adhesive, or may include a glass substrate and a plastic film bonded by an adhesive.

[0073] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image IM according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various suitable forms.

[0074] The display panel DP according to some embodiments of the present disclosure may be an emissive display panel, but is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material, and the emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, in the embodiments discussed, the display panel DP will be an organic light-emitting display panel.

[0075] Reference Figure 2B, the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded about a folding axis, or may be a rigid display panel.

[0076] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material of the synthetic resin layer is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, or the like.

[0077] The circuit layer DP_CL may be disposed on (e.g., above) the base layer BL. The circuit layer DP_CL may be disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL may include at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer may include at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit and a sensor driving circuit, the pixel driving circuit being included in each of a plurality of pixels for displaying an image, and the sensor driving circuit being included in each of a plurality of sensors for identifying external information. The external information may be biometric information. In some embodiments of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, or an illumination sensor, etc. In some examples, the sensor may be an optical sensor for optically identifying biometric information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0078] The element layer DP_ED may include a light emitting element and a light receiving element, the light emitting element being included in each of the pixels and the light receiving element being included in each of the sensors. In some embodiments of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that senses light reflected by a user's fingerprint or reacts to light reflected by a user's fingerprint. Figures 6A to 8K The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0079] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer, but is not particularly limited. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0080] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to some embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a continuous process. That is, when the input sensing layer ISL is directly disposed on the display panel DP, no adhesive film is disposed between the input sensing layer ISL and the encapsulation layer TFE. In some examples, an adhesive film may be disposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured together with the display panel DP by a continuous process, and may be manufactured separately from the display panel DP, and then fixed to the upper surface of the display panel DP by an adhesive film.

[0081] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed external input into a preset input signal, and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input in a capacitive type (e.g., sensing the external input by detecting a change in capacitance). The display panel DP may receive an input signal from the input sensing layer ISL, and may generate an image corresponding to the input signal.

[0082] The display module DM may further include a color filter layer CFL. In some embodiments of the present disclosure, the color filter layer CFL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. The color filter layer CFL may be disposed between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0083] The structures of the input sensing layer ISL and the color filter layer CFL will be described in detail below.

[0084] The display device DD according to some embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the input sensing layer ISL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, a pressure sensitive adhesive (PSA), or the like.

[0085] The display module DM may further include a driver chip DIC and sensor chips SIC1 and SIC2. In some embodiments of the present disclosure, the driver chip DIC and the sensor chips SIC1 and SIC2 may be mounted on the display panel DP. The driver chip DIC and the sensor chips SIC1 and SIC2 may be disposed adjacent to (e.g., disposed on) one end portion (hereinafter, referred to as a first end portion) of the display panel DP. Although Figure 2AThe structure in which the driver chip DIC and the sensor chips SIC1 and SIC2 are arranged adjacent to the first end of the display panel DP is shown, but the present disclosure is not limited thereto. For example, the driver chip DIC may be arranged adjacent to the first end of the display panel DP, and the sensor chips SIC1 and SIC2 may be arranged adjacent to the second end opposite to the first end of the display panel DP.

[0086] In some embodiments of the present disclosure, the sensor chips SIC1 and SIC2 may include a first sensor chip SIC1 disposed on one side (hereinafter, referred to as the first side) of the driver chip DIC and a second sensor chip SIC2 disposed on a second side of the driver chip DIC different from the first side. However, in some examples, the first sensor chip SIC1 and the second sensor chip SIC2 may be integrated into one sensor chip, and the one sensor chip may be disposed adjacent to the driver chip DIC. In the present disclosure, the number of sensor chips SIC1 and SIC2 and the number of driver chips DIC are not particularly limited.

[0087] The housing EDC may be combined with the window WM. The housing EDC may be combined with the window WM and provide a preset internal space. The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, and / or metal, etc., or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. A battery module for supplying power for the overall operation of the display device DD may be provided between the display module DM and the housing EDC.

[0088] Figure 3 is a block diagram of a display device according to some embodiments of the present disclosure.

[0089] Reference Figure 3 , the display device DD may include a display panel DP, a panel driver, and a driving controller 100. In some embodiments of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400, and a readout circuit 500.

[0090] The driving controller 100 may receive the image signal RGB and the control signal CTRL. The driving controller 100 may generate the image data DATA by converting the data format of the image signal RGB according to the specification of the interface with the data driver 200. The driving controller 100 may output the first control signal SCS, the second control signal ECS, the third control signal DCS, and the fourth control signal RCS.

[0091] The data driver 200 may receive the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 may convert the image data DATA into a data signal and output the data signal to a plurality of data lines DL1 and DL2 to DLm, which will be described below. The data signal may be an analog voltage corresponding to a grayscale value of the image data DATA. In some embodiments of the present disclosure, the data driver 200 may be embedded in Figure 2A The driver chip shown in DIC.

[0092] The scan driver 300 may receive a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS.

[0093] The voltage generator 400 may generate voltages for operation of the display panel DP. In some embodiments, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, a bias voltage Vbias, and a reset voltage Vrst.

[0094] The display panel DP may include a plurality of areas TA (eg, Figure 1 ) and the display area DA corresponding to the frame area BZA (for example, Figure 1 ) corresponds to the non-display area NDA.

[0095] The display panel DP may include a plurality of pixels PX disposed in the display area DA and a plurality of sensors FX disposed in the display area DA. In some embodiments of the present disclosure, each of the plurality of sensors FX may be disposed between two pixels PX. The plurality of pixels PX and the plurality of sensors FX may be alternately disposed in the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. That is, two or more pixels PX may be disposed between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be disposed between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0096] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 and RL2 to RLh. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn may extend in the first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn may be arranged in the second direction DR2 to be spaced apart from each other. The data lines DL1 to DLm and the readout lines RL1 to RLh may extend in the second direction DR2 and may be arranged in the first direction DR1 to be spaced apart from each other. Here, “n”, “m”, and “h” are natural numbers of 1 or more.

[0097] The plurality of pixels PX may be electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, this is not limited thereto, and the number of scan lines connected to each pixel PX may be changed.

[0098] The plurality of sensors FX may be electrically connected to the write scan lines SWL1 to SWLn and the readout lines RL1 to RLh, respectively. Each of the plurality of sensors FX may be electrically connected to one scan line. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may vary. In some embodiments of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 4, or 1 / 8 of the number of data lines DL1 to DLm.

[0099] The scan driver 300 may be disposed in a non-display area NDA of the display panel DP. The scan driver 300 may receive a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, and output a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, in response to the first control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn, and may output a black scan signal to the black scan lines SBL1 to SBLn. In some examples, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0100] The emission driver 350 may be disposed in the non-display area NDA of the display panel DP. The emission driver 350 may receive the second control signal ECS from the drive controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. In some examples, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0101] The readout circuit 500 may receive a fourth control signal RCS from the drive controller 100. In response to the fourth control signal RCS, the readout circuit 500 may receive a detection signal from the readout lines RL1 to RLh. The readout circuit 500 may process the detection signal received from the readout lines RL1 to RLh, and may provide the processed detection signal S_FS to the drive controller 100. The drive controller 100 may identify the biometric information based on the detection signal S_FS. In some embodiments of the present disclosure, the readout circuit 500 may be embedded in Figure 2A The sensor chips SIC1 and SIC2 are shown in FIG.

[0102] Figure 4A is a circuit diagram showing pixels and sensors according to some embodiments of the present disclosure, Figure 4B It is used to explain some embodiments of the present disclosure. Figure 4A The waveform diagram of the pixel and sensor operation is shown in FIG.

[0103] exist Figure 4A In the Figure 31 is an equivalent circuit diagram of one pixel PXij among the plurality of pixels PX shown in . Since the plurality of pixels PX have the same circuit structure, the description of the circuit structure of the pixel PXij can be applied to the remaining pixels, and the detailed description of the remaining pixels will be omitted. Figure 4A In the Figure 3 An equivalent circuit diagram of one sensor FXdj among the plurality of sensors FX is shown in . Since the plurality of sensors FX have the same circuit structure, the description of the circuit structure of the sensor FXdj can be applied to the remaining sensors, and a detailed description of the remaining sensors will be omitted.

[0104] Reference Figure 4A , the pixel PXij can be connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0105] The pixel PXij includes a light emitting element ED and a pixel driving circuit P_PD. The light emitting element ED may be a light emitting diode. In some embodiments of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer.

[0106] The pixel driving circuit P_PD may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8 and a capacitor Cst. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the eighth transistor T8 may be P-type transistors, and the other transistors may be N-type transistors. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be LTPS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0107] The configuration of the pixel driving circuit P_PD according to the present disclosure is not limited to Figure 4A The embodiment shown in . Figure 4AThe pixel driving circuit P_PD shown in FIG. 1 is only an example, and various suitable changes and modifications may be made to the configuration of the pixel driving circuit P_PD. For example, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may all be P-type transistors or N-type transistors.

[0108] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi can transmit the i-th data signal Di to the pixel PXij. The i-th data signal Di can have a certain value that is different from the value input to the display device DD (for example, referring to Figure 3 ) of the image signal RGB (for example, refer to Figure 3 ) corresponds to the voltage level.

[0109] In some embodiments of the present disclosure, the pixel PXij may be connected to a first driving voltage line VL1 and a second driving voltage line VL2, a first initialization voltage line VIL and a second initialization voltage line VAIL, and a bias voltage line VBL. The first driving voltage line VL1 may transmit a first driving voltage ELVDD to the pixel PXij, and the second driving voltage line VL2 may transmit a second driving voltage ELVSS to the pixel PXij. In addition, the first initialization voltage line VIL may transmit a first initialization voltage Vint to the pixel PXij, and the second initialization voltage line VAIL may transmit a second initialization voltage Vaint to the pixel PXij. The bias voltage line VBL may transmit a bias voltage Vbias to the pixel PXij.

[0110] The first transistor T1 may be connected between the light emitting element ED and a first driving voltage line VL1 receiving a first driving voltage ELVDD. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to an anode electrode of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 may receive an i-th data signal Di transmitted by an i-th data line DLi according to a switching operation of the second transistor T2, and may supply a driving current Id to the light emitting element ED.

[0111] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on according to the j-th write scan signal SWj transmitted through the j-th write scan line SWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0112] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and may diode-connect the first transistor T1 by connecting the third electrode and the second electrode of the first transistor T1.

[0113] The fourth transistor T4 may be connected between the first node N1 and the first initialization voltage line VIL to which the first initialization voltage Vint is applied. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VIL to which the first initialization voltage Vint is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 may be turned on according to the jth initialization scan signal SIj transmitted through the jth initialization scan line SILj. The turned-on fourth transistor T4 initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage Vint to the first node N1.

[0114] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0115] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode electrode of the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the jth emission control line EMLj.

[0116] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and thereafter may be transmitted to the light emitting element ED.

[0117] The seventh transistor T7 may include a first electrode connected to a second initialization voltage line VAIL to which a second initialization voltage Vaint is transmitted, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The second initialization voltage Vaint may have a voltage level lower than or equal to a voltage level of the first initialization voltage Vint.

[0118] The eighth transistor T8 may include a first electrode connected to the bias voltage line VBL transmitted with the bias voltage Vbias, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th black scan line SBLj.

[0119] The seventh transistor T7 and the eighth transistor T8 may be turned on simultaneously according to the jth black scan signal SBj transmitted through the jth black scan line SBLj. The second initialization voltage Vaint applied by the turned-on seventh transistor T7 may be transmitted to the anode electrode of the light emitting element ED. Therefore, the anode electrode of the light emitting element ED may be initialized to the second initialization voltage Vaint. The bias voltage Vbias applied by the turned-on eighth transistor T8 may be transmitted to the first electrode of the first transistor T1. Therefore, the bias voltage Vbias may be periodically applied to the first electrode of the first transistor T1. As a result, the degradation of the display quality caused by the potential difference between the first electrode and the second electrode of the first transistor T1 increasing to a preset level or higher due to hysteresis may be prevented or reduced.

[0120] As described above, one end of the capacitor Cst may be connected to the third electrode of the first transistor T1, and the opposite end of the capacitor Cst may be connected to the first driving voltage line VL1. The cathode electrode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD. In some embodiments of the present disclosure, the second driving voltage ELVSS may have a voltage level lower than the first initialization voltage Vint and the second initialization voltage Vaint.

[0121] Reference Figure 4A and Figure 4B, the j-th emission control signal EMj may have a high level during the non-emission period NEP. During the non-emission period NEP, the j-th initialization scan signal SIj may be activated. When the j-th initialization scan signal SIj having a high level is provided through the j-th initialization scan line SILj during the effective period AP1 (hereinafter, referred to as the first effective period) of the j-th initialization scan signal SIj, the fourth transistor T4 may be turned on in response to the j-th initialization scan signal SIj having a high level. The first initialization voltage Vint may be transmitted to the third electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 may be initialized to the first initialization voltage Vint. Therefore, the first effective period AP1 may be defined as the initialization period of the pixel PXij.

[0122] Next, when the jth compensation scan signal SCj may be activated and the jth compensation scan signal SCj having a high level is supplied through the jth compensation scan line SCLj during an effective period AP2 (hereinafter, referred to as a second effective period) of the jth compensation scan signal SCj, the third transistor T3 may be turned on in response to the jth compensation scan signal SCj having a high level. The first transistor T1 may be diode-connected and forward biased by the turned-on third transistor T3. The first effective period AP1 may not overlap with the second effective period AP2.

[0123] During the second effective period AP2, the j-th write scan signal SWj may be activated. The j-th write scan signal SWj has a low level during the effective period AP4 (hereinafter, referred to as the fourth effective period). During the fourth effective period AP4, the second transistor T2 may be turned on by the j-th write scan signal SWj having a low level. Then, the compensation voltage "Di-Vth" (for example, Di minus Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the i-th data signal Di supplied by the i-th data line DLi may be applied to the third electrode of the first transistor T1. That is, the potential of the third electrode of the first transistor T1 may be the compensation voltage "Di-Vth". The fourth effective period AP4 may overlap with the second effective period AP2. The duration of the second effective period AP2 may be greater than the duration of the fourth effective period AP4.

[0124] The first driving voltage ELVDD and the compensation voltage "Di-Vth" may be applied to opposite ends of the capacitor Cst, and charges corresponding to the difference between the voltages at the opposite ends of the capacitor Cst may be stored in the capacitor Cst. Here, the period during which the j-th compensation scan signal SCj has a high level may be referred to as a compensation period of the pixel PXij.

[0125] The jth black scan signal SBj may be activated within the second effective period AP2 of the jth compensation scan signal SCj. The jth black scan signal SBj may have a low level during an effective period AP3 (hereinafter, referred to as the third effective period). During the third effective period AP3, the seventh transistor T7 may be turned on by receiving the jth black scan signal SBj having a low level via the jth black scan line SBLj. A portion of the drive current Id may escape as a bypass current Ibp through the seventh transistor T7. The third effective period AP3 may overlap with the second effective period AP2. The duration of the second effective period AP2 may be greater than the duration of the third effective period AP3. The third effective period AP3 may be before the fourth effective period AP4 and may not overlap with the fourth effective period AP4.

[0126] When the pixel PXij displays a black image, if the light-emitting element ED emits light, then even if the minimum driving current of the first transistor T1 flows as the driving current Id, the pixel PXij cannot display the black image normally. Therefore, according to the seventh transistor T7 in the pixel PXij of some embodiments of the present disclosure, a part of the minimum driving current of the first transistor T1 can be allocated as a bypass current Ibp to a current path other than the current path toward the light-emitting element ED. Here, the minimum driving current of the first transistor T1 represents the current that flows to the first transistor T1 and turns off the first transistor T1 under the condition that the gate-source voltage (Vgs) of the first transistor T1 is lower than the threshold voltage (Vth). Under the condition that the first transistor T1 is turned off, the minimum driving current (for example, a current of 10pA or less) flowing to the first transistor T1 can be transmitted to the light-emitting element ED, and a black grayscale image is displayed. When the pixel PXij displays a black image, the bypass current Ibp has a relatively large effect on the minimum driving current, while when the pixel PXij displays an image such as a regular image or a white image, the bypass current Ibp has little effect on the driving current Id. Therefore, when the pixel PXij displays a black image, the current obtained by subtracting the bypass current Ibp escaped by the seventh transistor T7 from the driving current Id (i.e., the light emission current Ied) can be provided to the light emitting element ED, so that the pixel PXij clearly expresses the black image. Therefore, the pixel PXij can use the seventh transistor T7 to achieve an accurate black grayscale image, thereby improving (e.g., increasing) the contrast.

[0127] Thereafter, the j-th emission control signal EMj supplied from the j-th emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EMj having a low level. Then, a driving current Id is generated, which depends on the difference between the voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD. The driving current Id may be supplied to the light emitting element ED through the sixth transistor T6, and the light emission current Ied may flow through the light emitting element ED.

[0128] Refer again Figure 4A According to some embodiments of the present disclosure, the sensor FXdj may be connected to the dth readout line RLd, the jth write scan line SWLj, and the reset control line SRL among the readout lines RL1 to RLh.

[0129] The sensor FXdj may include a light receiving element OPD and a sensor driving circuit O_SD. In some embodiments of the present disclosure, the light receiving element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. Figure 4A A structure in which the sensor FXdj includes one light receiving element OPD is shown, but the present disclosure is not limited thereto. For example, the sensor FXdj may include a plurality of light receiving elements OPD connected in parallel.

[0130] The anode electrode of the light receiving element OPD may be connected to the first sensing node SN1, and the cathode electrode of the light receiving element OPD may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The cathode electrode of the light receiving element OPD may be electrically connected to the cathode electrode of the light emitting element ED. In some embodiments of the present disclosure, the cathode electrode of the light receiving element OPD may be integrally formed with the cathode electrode of the light emitting element ED to form a common cathode electrode.

[0131] The sensor driving circuit O_SD may include three transistors ST1, ST2 and ST3. The three transistors ST1, ST2 and ST3 may be a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifying transistor ST2 and the output transistor ST3 may be an oxide semiconductor transistor. In some embodiments of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, it is not limited thereto, and at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0132] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the remaining transistors may be N-type transistors. In some embodiments of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be PMOS transistors, and the reset transistor ST1 may be an NMOS transistor. However, it is not limited thereto, and the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors or P-type transistors.

[0133] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (e.g., the reset transistor ST1) may be transistors of the same type as the third transistor T3 and the fourth transistor T4 of the pixel PXij. The amplifying transistor ST2 and the output transistor ST3 may be transistors of the same type as the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 of the pixel PXij.

[0134] The circuit configuration of the sensor driving circuit O_SD according to the present disclosure is not limited to Figure 4A The circuit configuration shown in . Figure 4A The sensor driving circuit O_SD shown in FIG. 1 is merely illustrative, and various suitable changes and modifications may be made to the configuration of the sensor driving circuit O_SD.

[0135] The reset transistor ST1 may include a first electrode receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal SR. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR may be a signal provided by a reset control line SRL. However, the present disclosure is not limited thereto. In some examples, the reset control signal SR may be a jth compensation scan signal SCj supplied by a jth compensation scan line SCLj. That is, the reset transistor ST1 may receive the jth compensation scan signal SCj supplied from the jth compensation scan line SCLj as the reset control signal SR. In some embodiments of the present disclosure, at least during the effective period of the reset control signal SR, the reset voltage Vrst may have a voltage level lower than the second drive voltage ELVSS. The reset voltage Vrst may be transmitted to the sensor FXdj through the reset voltage line VRL. The reset voltage Vrst may be a DC voltage maintained at a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0136] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter, referred to as the first sub-reset transistor and the second sub-reset transistor). In this case, the third electrode of the first sub-reset transistor and the third electrode of the second sub-reset transistor may be connected to the reset control line SRL. In addition, the second electrode of the first sub-reset transistor and the first electrode of the second sub-reset transistor may be electrically connected to each other. In addition, the reset voltage Vrst may be applied to the first electrode of the first sub-reset transistor, and the second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto and may be modified in various suitable ways.

[0137] The amplifier transistor ST2 may include a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 may be turned on according to the potential of the first sensing node SN1, and the sensing drive voltage SLVD may be applied to the second sensing node SN2. In some embodiments of the present disclosure, the sensing drive voltage SLVD may be one of a first driving voltage ELVDD, a first initialization voltage Vint, and a second initialization voltage Vaint. When the sensing drive voltage SLVD is the first driving voltage ELVDD, the first electrode of the amplifier transistor ST2 may be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 may be electrically connected to the first initialization voltage line VIL, and when the sensing drive voltage SLVD is the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 may be electrically connected to the second initialization voltage line VAIL.

[0138] The output transistor ST3 may include a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. In response to the output control signal, the output transistor ST3 may transmit the detection signal FSd to the dth readout line RLd. The output control signal may be a jth write scan signal SWj supplied through the jth write scan line SWLj. That is, the output transistor ST3 may receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0139] The light receiving element OPD of the sensor FXdj may be exposed to light during the light emission period of the light emitting element ED. The light may be light output from the light emitting element ED.

[0140] If the user's hand US_F (for example, refer to Figure 1) touches the display surface IS (see, for example, Figure 1 ), then the light receiving element OPD may generate a photocharge corresponding to the light reflected by the ridges of the fingerprint or the valleys between the ridges. The amount of current flowing through the light receiving element OPD varies according to the photocharge generated. When the light receiving element OPD receives the light reflected by the ridges of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a first current, and when the light receiving element OPD receives the light reflected by the valleys of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a second current. The amount of light reflected by the ridges of the fingerprint and the amount of light reflected by the valleys of the fingerprint are different from each other, and the difference between the amounts of light is presented as a difference between the first current and the second current. When the first current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a first potential, and when the second current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a second potential. In some embodiments of the present disclosure, the first current may be greater than the second current. In this case, the first potential may be lower than the second potential.

[0141] The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode.

[0142] During the fourth effective period AP4, the jth write scan signal SWj having a low level may be supplied to the output transistor ST3 through the jth write scan line SWLj. When the output transistor ST3 is turned on in response to the jth write scan signal SWj having a low level, the detection signal FSd corresponding to the current flowing through the amplifying transistor ST2 may be output to the dth readout line RLd.

[0143] When a reset control signal SR having a high level is supplied through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period can be defined as an effective period (i.e., a high level period) of the reset control signal SR. In some examples, when the reset transistor ST1 is implemented with a P-type transistor, a reset control signal SR having a low level can be supplied to the reset control line SRL during the reset period. The first sensing node SN1 can be reset to a potential corresponding to the reset voltage Vrst during the reset period. In some embodiments of the present disclosure, the reset voltage Vrst may have a voltage level lower than the second drive voltage ELVSS.

[0144] When the reset period ends, the light receiving element OPD may generate photo charges corresponding to the received light, and the generated photo charges may be accumulated in the first sensing node SN1.

[0145] Figure 5is an enlarged plan view showing a partial area of ​​a display panel according to some embodiments of the present disclosure.

[0146] Reference Figure 5 According to some embodiments of the present disclosure, the display panel DP may include a plurality of pixels PXR, PXG1, PXG2, and PXB and a plurality of sensors FX1 and FX2.

[0147] A plurality of pixels PXR, PXG1, PXG2, and PXB may be grouped into a plurality of reference pixel units RPU. In some embodiments of the present disclosure, each of the reference pixel units RPU may include four pixels, namely, a first pixel PXB (hereinafter referred to as a blue pixel), a second pixel PXR (hereinafter referred to as a red pixel), and two third pixels PXG1 and PXG2 (hereinafter referred to as a first green pixel and a second green pixel). However, the number of pixels included in each reference pixel unit RPU is not limited thereto. In some examples, each reference pixel unit RPU may include three pixels, namely, a blue pixel PXB, a red pixel PXR, and a green pixel (one of the first green pixel PXG1 and the second green pixel PXG2).

[0148] The blue pixel PXB may include a first light-emitting element ED_B (hereinafter, referred to as a blue light-emitting element), the red pixel PXR may include a second light-emitting element ED_R (hereinafter, referred to as a red light-emitting element), and the first green pixel PXG1 and the second green pixel PXG2 include a third light-emitting element ED_G1 and a fourth light-emitting element ED_G2 (hereinafter, referred to as a first green light-emitting element and a second green light-emitting element), respectively. In some embodiments of the present disclosure, the blue light-emitting element ED_B outputs a first color light (e.g., blue light), and the red light-emitting element ED_R outputs a second color light (e.g., red light) different from the first color light. Each of the first green light-emitting element ED_G1 and the second green light-emitting element ED_G2 outputs a third color light (e.g., green light) different from the first color light and the second color light. The green light output from the first green light-emitting element ED_G1 and the green light output from the second green light-emitting element ED_G2 may have the same wavelength band.

[0149] The red light emitting element ED_R and the blue light emitting element ED_B may be arranged alternately and repeatedly in the first direction DR1 and the second direction DR2. The first green light emitting element ED_G1 and the second green light emitting element ED_G2 may be arranged alternately and repeatedly in the first direction DR1, and alternately and repeatedly in the second direction DR2. In a first row (e.g., an odd row) parallel to the first direction DR1, the light emitting elements ED_R, ED_G1, ED_G2, and ED_B may be arranged in the order of the red light emitting element ED_R, the first green light emitting element ED_G1, the blue light emitting element ED_B, and the second green light emitting element ED_G2. In a second row (e.g., an even row) parallel to the first direction DR1, the light emitting elements ED_R, ED_G1, ED_G2, and ED_B may be arranged in the order of the blue light emitting element ED_B, the second green light emitting element ED_G2, the red light emitting element ED_R, and the first green light emitting element ED_G1.

[0150] In some embodiments of the present disclosure, the red light emitting element ED_R may have a size larger than the first green light emitting element ED_G1 and the second green light emitting element ED_G2. In addition, the blue light emitting element ED_B may have a size greater than or equal to the size of the red light emitting element ED_R. The sizes of the light emitting elements ED_R, ED_G1, ED_G2, and ED_B are not limited thereto and may be modified in various suitable ways. For example, in some embodiments of the present disclosure, the light emitting elements ED_R, ED_G1, ED_G2, and ED_B may have the same size.

[0151] The first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have the same shape as the red light emitting element ED_R and the blue light emitting element ED_B. In some embodiments of the present disclosure, each of the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have a circular shape. In some examples, each of the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have a polygonal shape (e.g., one of an octagonal shape, a square shape, and a rectangular shape). However, the present disclosure is not limited thereto, and the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have different shapes.

[0152] The blue light emitting element ED_B may be electrically connected to a blue pixel driving circuit B_PD (or a first pixel driving circuit). Specifically, the blue light emitting element ED_B may include a blue anode electrode B_AE (or a first pixel anode electrode) and a blue emission layer B_EL, and the blue anode electrode B_AE may be electrically connected to the blue pixel driving circuit B_PD through a blue pixel connecting electrode B_CNE (or a first pixel connecting electrode). The blue pixel connecting electrode B_CNE may be connected to the blue anode electrode B_AE and the blue pixel driving circuit B_PD through a blue contact hole B_CH.

[0153] The red light emitting element ED_R may be electrically connected to a red pixel driving circuit R_PD (or a second pixel driving circuit). Specifically, the red light emitting element ED_R may include a red anode electrode R_AE (or a second pixel anode electrode) and a red emission layer R_EL, and the red anode electrode R_AE may be electrically connected to the red pixel driving circuit R_PD through a red pixel connecting electrode R_CNE (or a second pixel connecting electrode). The red pixel connecting electrode R_CNE may be connected to the red anode electrode R_AE and the red pixel driving circuit R_PD through a red contact hole R_CH.

[0154] The first green light emitting element ED_G1 may be electrically connected to the first green pixel driving circuit G1_PD (or the third pixel driving circuit). Specifically, the first green light emitting element ED_G1 may include a first green anode electrode G1_AE (or the third pixel anode electrode) and a first green emission layer G1_EL, and the first green anode electrode G1_AE may be electrically connected to the first green pixel driving circuit G1_PD through a first green pixel connecting electrode G1_CNE (or the third pixel connecting electrode). The first green pixel connecting electrode G1_CNE may be connected to the first green anode electrode G1_AE and the first green pixel driving circuit G1_PD through a first green contact hole G1_CH. The second green light emitting element ED_G2 may be electrically connected to the second green pixel driving circuit G2_PD (or the fourth pixel driving circuit). Specifically, the second green light emitting element ED_G2 may include a second green anode electrode G2_AE (or a fourth pixel anode electrode) and a second green emission layer G2_EL, and the second green anode electrode G2_AE may be electrically connected to the second green pixel driving circuit G2_PD through a second green pixel connecting electrode G2_CNE (or a fourth pixel connecting electrode). The second green pixel connecting electrode G2_CNE may be connected to the second green anode electrode G2_AE and the second green pixel driving circuit G2_PD through a second green contact hole G2_CH.

[0155] The first green emission layer G1_EL and the second green emission layer G2_EL may have the same size and the same shape. However, the present disclosure may not be limited thereto. For example, the first green emission layer G1_EL and the second green emission layer G2_EL may have the same size (or area), but may have different shapes. In some examples, the first green anode electrode G1_AE and the second green anode electrode G2_AE may have different sizes (or areas) and different shapes.

[0156] In the first row (e.g., odd-numbered row), the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD may be arranged in the order of a blue pixel driving circuit B_PD, a second green pixel driving circuit G2_PD, a red pixel driving circuit R_PD, and a first green pixel driving circuit G1_PD. In the second row (e.g., even-numbered row), the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD may be arranged in the order of a blue pixel driving circuit B_PD, a first green pixel driving circuit G1_PD, a red pixel driving circuit R_PD, and a second green pixel driving circuit G2_PD. The first row and the second row may be repeated in the second direction DR2.

[0157] In some embodiments of the present disclosure, the blue pixel driving circuit B_PD may be arranged in a first column parallel to the second direction DR2, the first green pixel driving circuit G1_PD and the second green pixel driving circuit G2_PD may be alternately arranged in a second column parallel to the second direction DR2. The red pixel driving circuit R_PD may be arranged in a third column, and the second green pixel driving circuit G2_PD and the first green pixel driving circuit G1_PD may be alternately arranged in a fourth column.

[0158] Each of the sensors FX1 and FX2 may include a light receiving element OPD1 or OPD2 and a sensor driving circuit O_SD1 or O_SD2. In some embodiments of the present disclosure, one light receiving element OPD1 or OPD2 may be set to correspond to one reference pixel unit RPU. However, the number of light receiving elements set to correspond to each reference pixel unit RPU is not limited thereto. For example, two light receiving elements may be set to correspond to each reference pixel unit RPU.

[0159] A plurality of light receiving elements OPD1 and OPD2 may be arranged in a first direction DR1 and a second direction DR2 in the display panel DP. When the first direction DR1 may be defined as a row direction and the second direction DR2 may be defined as a column direction, a light receiving element disposed in a first row (e.g., an odd row) among the light receiving elements OPD1 and OPD2 is referred to as a first light receiving element OPD1, and a light receiving element disposed in a second row (e.g., an even row) is referred to as a second light receiving element OPD2.

[0160] Each of the first light receiving element OPD1 and the second light receiving element OPD2 may be disposed between the red light emitting element ED_R and the blue light emitting element ED_B in the first direction DR1. The first light receiving element OPD1 may be disposed between the first green light emitting element ED_G1 and the second green light emitting element ED_G2 adjacent to each other in the second direction DR2, and the second light receiving element OPD2 may be disposed between the first green light emitting element ED_G1 and the second green light emitting element ED_G2 adjacent to each other in the second direction DR2.

[0161] The sensor driving circuits O_SD1 and O_SD2 may be arranged in the display panel DP in the first direction DR1 and the second direction DR2. Each of the sensor driving circuits O_SD1 and O_SD2 may have the same length as the red pixel driving circuit R_PD and the blue pixel driving circuit B_PD and the first green pixel driving circuit G1_PD and the second green pixel driving circuit G2_PD in the second direction DR2. Among the sensor driving circuits O_SD1 and O_SD2, the sensor driving circuit disposed in the first row (e.g., odd-numbered row) is referred to as the first sensor driving circuit O_SD1, and the sensor driving circuit disposed in the second row (e.g., even-numbered row) is referred to as the second sensor driving circuit O_SD2. The first sensor driving circuit O_SD1 and the second sensor driving circuit O_SD2 may be alternately disposed in the second direction DR2 in a fifth column parallel to the second direction DR2. The fifth column may be adjacent to the fourth column, and the first to fifth columns may be repeated in the second direction DR2.

[0162] The first light receiving element OPD1 may be connected to the first sensor driving circuit O_SD1, and the second light receiving element OPD2 may be connected to the second sensor driving circuit O_SD2. In some embodiments of the present disclosure, when viewed from above a plane (e.g., in a plan view), the first light receiving element OPD1 may be disposed in a position overlapping with the first sensor driving circuit O_SD1, and when viewed from above a plane (e.g., in a plan view), the second light receiving element OPD2 may be disposed in a position not overlapping with the second sensor driving circuit O_SD2.

[0163] The first light receiving element OPD1 may include a first sensor anode electrode O_AE1 (or a first row anode electrode) and a first photoelectric conversion layer O_RL1, and the second light receiving element OPD2 may include a second sensor anode electrode O_AE2 (or a second row anode electrode) and a second photoelectric conversion layer O_RL2. The first sensor anode electrode O_AE1 may be disposed in a position overlapping with the first sensor driving circuit O_SD1. The first sensor anode electrode O_AE1 may be directly connected to the first sensor driving circuit O_SD1 through the first sensor contact hole O_CH1. The second sensor anode electrode O_AE2 may be disposed in a position not overlapping with the second sensor driving circuit O_SD2. The second light receiving element OPD2 may further include a sensor connection electrode O_CNE2 extending from the second sensor anode electrode O_AE2 in the first direction DR1 to overlap with the second sensor driving circuit O_SD2. That is, the sensor connection electrode O_CNE2 may have an integral shape with the second sensor anode electrode O_AE2 (eg, the sensor connection electrode O_CNE2 may be integrally formed with the second sensor anode electrode O_AE2). The sensor connection electrode O_CNE2 may be directly connected to the second sensor driving circuit O_SD2 through the second sensor contact hole O_CH2.

[0164] In some embodiments of the present disclosure, the first light receiving element OPD1 may further include a dummy connection electrode D_CNE1 extending from the first sensor anode electrode O_AE1 in the first direction DR1. That is, the dummy connection electrode D_CNE1 has an integral shape with the first sensor anode electrode O_AE1. The sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 may be approximately equal to the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2.

[0165] In some embodiments of the present disclosure, the first light receiving element OPD1 and the second light receiving element OPD2 may have the same shape as the light emitting elements ED_G1, ED_G2, ED_R, and ED_B. For example, the first light receiving element OPD1 and the second light receiving element OPD2 may have a circular shape. However, the shapes of the first light receiving element OPD1 and the second light receiving element OPD2 are not limited thereto. For example, the first light receiving element OPD1 and the second light receiving element OPD2 may have a polygonal shape (e.g., an octagonal shape, a square shape, or a rectangular shape). In some examples, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a shape different from at least one of the light emitting elements ED_G1, ED_G2, ED_R, and ED_B.

[0166] The first and second light receiving elements OPD1 and OPD2 may have a size smaller than or equal to that of the first and second green light emitting elements ED_G1 and ED_G2. However, the sizes of the first and second light receiving elements OPD1 and OPD2 are not particularly limited and may be modified in various suitable ways.

[0167] The first sensor anode electrode O_AE1 and the second sensor anode electrode O_AE2, the sensor connection electrode O_CNE2, and the dummy connection electrode D_CNE1 may be disposed at the same layer (e.g., on or in the same layer) as the pixel anode electrodes R_AE, G1_AE, G2_AE, and B_AE. In this case, the first sensor anode electrode O_AE1 and the second sensor anode electrode O_AE2, the sensor connection electrode O_CNE2, and the dummy connection electrode D_CNE1 may include the same material as the pixel anode electrodes R_AE, G1_AE, G2_AE, and B_AE, and may be disposed at the same layer (e.g., on or in the same layer) as the pixel anode electrodes R_AE, G1_AE, G2_AE, and B_AE through the same process.

[0168] The first and second green pixel connection electrodes G1_CNE and G2_CNE, the red and blue pixel connection electrodes R_CNE and B_CNE may be disposed at different layers from the pixel anode electrodes R_AE, G1_AE, G2_AE and B_AE, the first and second sensor anode electrodes O_AE1 and O_AE2, the sensor connection electrode O_CNE2 and the dummy connection electrode D_CNE1.

[0169] The pixel anode electrodes R_AE, G1_AE, G2_AE and B_AE, the first and second sensor anode electrodes O_AE1 and O_AE2, the sensor connection electrode O_CNE2 and the dummy connection electrode D_CNE1 may be included in the element layer DP_ED (eg, refer to Fig. 6A and Figure 6B ), and the first green pixel connection electrode G1_CNE and the second green pixel connection electrode G2_CNE, the red pixel connection electrode R_CNE and the blue pixel connection electrode B_CNE may be included in the circuit layer DP_CL (eg, refer to Fig. 6A and Figure 6B )middle.

[0170] The circuit layer DP_CL may further include a shielding electrode RSE overlapped with the first sensor driving circuit O_SD1 and the second sensor driving circuit O_SD2. In some embodiments of the present disclosure, the first green pixel connection electrode G1_CNE and the second green pixel connection electrode G2_CNE, the red pixel connection electrode R_CNE, and the blue pixel connection electrode B_CNE may include the same material as the shielding electrode RSE, and may be disposed in the same layer (e.g., on or in the same layer) as the shielding electrode RSE through the same process.

[0171] Fig. 6A is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of the connection structure of the red light emitting element and the red pixel driving circuit shown in FIG. Figure 6B is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of a connection structure of a second light receiving element and a second sensor driving circuit shown in FIG.

[0172] Reference Fig. 6A and Figure 6B According to some embodiments of the present disclosure, the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0173] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0174] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers.

[0175] The circuit layer DP_CL may be disposed on the base layer BL. Fig. 6A In the Figure 5 The first transistor T1, the fourth transistor T4 and the sixth transistor T6 of the red pixel driving circuit R_PD shown in FIG. Fig. 6A, the shielding layer BML may be disposed on the base layer BL. The shielding layer BML may overlap the first transistor T1. The shielding layer BML may include metal and may receive a constant voltage. When the constant voltage is applied to the shielding layer BML, the threshold voltage (Vth) of the first transistor T1 disposed above the shielding layer BML may remain unchanged.

[0176] In addition, the shielding layer BML may block light incident to the first transistor T1 from below the shielding layer BML. For example, the shielding layer BML may include a reflective metal. In some embodiments of the present disclosure, the shielding layer BML may be omitted.

[0177] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may include an inorganic layer. The buffer layer BFL may cover the shielding layer BML. The semiconductor layer SCP1 (or semiconductor pattern region, hereinafter, referred to as the first semiconductor layer) of the first transistor T1 and the semiconductor layer SCP6 (or semiconductor pattern region, hereinafter, referred to as the sixth semiconductor layer) of the sixth transistor T6 may be disposed on the buffer layer BFL. The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include polycrystalline silicon. However, not limited thereto, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include amorphous silicon.

[0178] The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be formed by the same process, and partial regions of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be doped with N-type dopants or P-type dopants. Each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include a heavily doped region and a lightly doped region. The heavily doped region has a higher conductivity than the lightly doped region. The heavily doped region may substantially correspond to the source and drain of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to the active (or channel) region of the first transistor T1 and the sixth transistor T6.

[0179] The heavily doped region of the first semiconductor layer SCP1 may include a first source region S1 and a first drain region D1. The lightly doped region of the first semiconductor layer SCP1 may be defined as a first channel region C1 and may be disposed between the first source region S1 and the first drain region D1. The sixth semiconductor layer SCP6 may include a sixth source region S6, a sixth channel region C6, and a sixth drain region D6. The first source region S1 is defined as a first electrode of the first transistor T1, and the first drain region D1 is defined as a second electrode of the first transistor T1. The sixth source region S6 is defined as a first electrode of the sixth transistor T6, and the sixth drain region D6 is defined as a second electrode of the sixth transistor T6.

[0180] Although the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 Fig. 6A, but when viewed from above a plane (e.g., in a plan view), the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may have an integral shape (e.g., the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be integrally formed). In other words, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be different parts or different regions of one semiconductor pattern.

[0181] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6. The third electrodes (or gate electrodes) of the first transistor T1 and the sixth transistor T6 may be disposed on the first insulating layer INS1. The gate electrodes of the first transistor T1 and the sixth transistor T6 may be formed by the same process. Hereinafter, the gate electrode of the first transistor T1 is defined as the first gate electrode G1, and the gate electrode of the sixth transistor T6 is defined as the sixth gate electrode G6.

[0182] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The upper gate electrode UGE may be disposed on the second insulating layer INS2. The upper gate electrode UGE may be disposed above the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from above a plane. The upper gate electrode UGE together with the first gate electrode G1 may form Figure 4A In other words, the first gate electrode G1 corresponds to one electrode of the capacitor Cst, and the upper gate electrode UGE corresponds to the other electrode of the capacitor Cst.

[0183] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the upper gate electrode UGE. The semiconductor layer SCP4 (or semiconductor pattern region, hereinafter, referred to as the fourth semiconductor layer) of the fourth transistor T4 may be disposed on the third insulating layer INS3. The fourth semiconductor layer SCP4 may include an oxide semiconductor including a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0184] The fourth semiconductor layer SCP4 may include a plurality of regions that are distinguished from each other according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may substantially correspond to the source and drain of the fourth transistor T4. The non-reduction region may substantially correspond to the active (or channel) region of the fourth transistor T4.

[0185] The reduction region of the fourth semiconductor layer SCP4 may include a fourth source region S4 and a fourth drain region D4. A fourth channel region C4 may be disposed between the fourth source region S4 and the fourth drain region D4. The fourth source region S4 is defined as a first electrode of a fourth transistor T4, and the fourth drain region D4 is defined as a second electrode of the fourth transistor T4.

[0186] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the fourth semiconductor layer SCP4. The third electrode (ie, the fourth gate electrode G4) of the fourth transistor T4 may be disposed on the fourth insulating layer INS4.

[0187] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer.

[0188] The circuit connection electrodes CNE1, CNE2, and CNE3 and the red pixel connection electrode R_CNE may be disposed between the sixth transistor T6 and the red light emitting element ED_R. The circuit connection electrodes CNE1, CNE2, and CNE3 and the red pixel connection electrode R_CNE may electrically connect the sixth transistor T6 and the red light emitting element ED_R. In some embodiments of the present disclosure, the circuit connection electrodes CNE1, CNE2, and CNE3 may include a first circuit connection electrode CNE1, a second circuit connection electrode CNE2 disposed on the first circuit connection electrode CNE1, and a third circuit connection electrode CNE3 disposed on the second circuit connection electrode CNE2.

[0189] The first circuit connection electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first circuit connection electrode CNE1. The second connection electrode CNE2 may be disposed on the sixth insulating layer INS6. The second circuit connection electrode CNE2 may be connected to the first circuit connection electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6. The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second circuit connection electrode CNE2.

[0190] The third circuit connection electrode CNE3 may be disposed on the seventh insulating layer INS7. The third circuit connection electrode CNE3 may be connected to the second circuit connection electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7.

[0191] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 to cover the third circuit connection electrode CNE3. The red pixel connection electrode R_CNE may be disposed on the eighth insulating layer INS8. When viewed from above a plane, the red pixel connection electrode R_CNE may overlap the circuit connection electrodes CNE1, CNE2, and CNE3 and the red anode electrode R_AE.

[0192] The red pixel connection electrode R_CNE may be connected to the third circuit connection electrode CNE3 through the first red contact hole R_CH1 defined in the eighth insulating layer INS8. The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8. The sixth insulating layer INS6 to the ninth insulating layer INS9 may include an inorganic layer or an organic layer. In this embodiment, each of the sixth insulating layer INS6 to the ninth insulating layer INS9 may include an organic layer.

[0193] The red light emitting element ED_R may be disposed on the ninth insulating layer INS9. The red light emitting element ED_R may include a red anode electrode R_AE, a red cathode electrode R_CE, and a red emission layer R_EL. The red cathode electrode R_CE may be disposed above the red anode electrode R_AE, and the red emission layer R_EL may be disposed between the red anode electrode R_AE and the red cathode electrode R_CE. In some embodiments of the present disclosure, the hole control layer HCL may be additionally disposed between the red anode electrode R_AE and the red emission layer R_EL, and the electron control layer ECL may be additionally disposed between the red cathode electrode R_CE and the red emission layer R_EL.

[0194] The red anode electrode R_AE may be disposed on the ninth insulating layer INS9 and may be connected to the red pixel connection electrode R_CNE through a second red contact hole R_CH2 defined in the ninth insulating layer INS9 .

[0195] A pixel defining layer PDL exposing a predetermined portion of the red anode electrode R_AE may be disposed on the red anode electrode R_AE and the ninth insulating layer INS9. A pixel opening PDL-OP1 for exposing a predetermined portion of the red anode electrode R_AE may be defined in the pixel defining layer PDL.

[0196] The red emission layer R_EL may include an organic material and / or an inorganic material. The red emission layer R_EL may generate red light.

[0197] The hole control layer HCL and the electron control layer ECL may be provided for each pixel PX (eg, Figure 3 ) are commonly arranged. In addition, the red cathode electrode R_CE can be formed integrally with the cathode electrodes of adjacent light emitting elements to form a common cathode electrode.

[0198] The layers from the buffer layer BFL to the ninth insulating layer INS9 may be defined as a circuit layer DP_CL. The layer in which the red light emitting element ED_R is disposed may be defined as an element layer DP_ED.

[0199] The encapsulation layer TFE may be disposed on the element layer DP_ED. The encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer sequentially stacked on each other. The inorganic layer may include an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0200] Reference Figure 6B The semiconductor layer SCP1' (hereinafter, referred to as the first sensing semiconductor layer) of the amplifying transistor ST2 can be connected to Fig. 6A The semiconductor layer SCP2' of the reset transistor ST1 (hereinafter, referred to as the second sensing semiconductor layer) can be formed by the same process as the first semiconductor layer SCP1 of the reset transistor ST1. Fig. 6A The fourth semiconductor layer SCP4 is formed by the same process. The first sensing semiconductor layer SCP1' may include a first source region S1', a first drain region D1' and a first channel region C1'. The second sensing semiconductor layer SCP2' may include a second source region S2', a second drain region D2' and a second channel region C2'. The first source region S1' is defined as a first electrode of the amplifying transistor ST2, and the first drain region D1' is defined as a second electrode of the amplifying transistor ST2. The second source region S2' is defined as a first electrode of the reset transistor ST1, and the second drain region D2' is defined as a second electrode of the reset transistor ST1.

[0201] The stacked structure of the amplifier transistor ST2 can be Fig. 6A The stack structure of the first transistor T1 shown in FIG. 1 is substantially the same as that of the reset transistor ST1. Fig. 6A The stack structure of the fourth transistor T4 shown in FIG. 1 is substantially the same as that of the output transistor ST3 . The stack structure of the output transistor ST3 may be substantially the same as that of the amplifying transistor ST2 .

[0202] The circuit connection electrodes CNE1', CNE2' and CNE3' may include a fourth circuit connection electrode CNE1', a fifth circuit connection electrode CNE2' and a sixth circuit connection electrode CNE3'. The fourth circuit connection electrode CNE1' may be connected to Fig. 6AThe first circuit connection electrode CNE1 shown in FIG. 1 is disposed in the same layer (e.g., on or in the same layer) and may be connected to the third electrode (i.e., the first gate electrode G1') of the amplifying transistor ST2 through the fourth contact hole CH1'. Hereinafter, the first gate electrode G1' is defined as a first sensor gate electrode G1' to be distinguished from the above-mentioned first gate electrode G1.

[0203] The fifth circuit connection electrode CNE2' can be connected to Fig. 6A The second circuit connection electrode CNE2 shown in FIG. 1 is disposed in the same layer (eg, in or on the same layer) and may be connected to the fourth circuit connection electrode CNE1′ through a fifth contact hole CH2′ defined in the sixth insulating layer INS6. The sixth circuit connection electrode CNE3′ may be connected to the fourth circuit connection electrode CNE1′. Fig. 6A The third circuit connection electrode CNE3 shown in FIG. 1 is disposed at the same layer (eg, in or on the same layer) and may be connected to the fifth circuit connection electrode CNE2 ′ through a sixth contact hole CH3 ′.

[0204] The second sensor anode electrode O_AE2 and the sensor connection electrode O_CNE2 may be disposed on the ninth insulating layer INS9. A sensor opening PDL-OP2 for exposing a preset portion of the second sensor anode electrode O_AE2 may be defined in the pixel defining layer PDL. The sensor connection electrode O_CNE2 may extend from the second sensor anode electrode O_AE2 and may overlap with the fourth circuit connection electrode CNE1', the fifth circuit connection electrode CNE2', and the sixth circuit connection electrode CNE3' when viewed from above the plane. The sensor connection electrode O_CNE2 may be connected to the sixth circuit connection electrode CNE3' through a second sensor contact hole O_CH2 defined in the eighth insulating layer INS8 and the ninth insulating layer INS9.

[0205] The second light receiving element OPD2 may include a second sensor anode electrode O_AE2, a second sensor cathode electrode O_CE2, and a second photoelectric conversion layer O_RL2. Fig. 6A The second sensor cathode electrode O_CE2 can be formed by the same process as the red anode electrode R_AE shown in FIG. Fig. 6A The red cathode electrode R_CE shown in FIG. 1 has an integral shape (eg, the second sensor cathode electrode O_CE2 may be Fig. 6A The red cathode electrode R_CE shown in FIG. 1 is formed integrally). That is, Figure 6B The second sensor cathode electrode O_CE2 and Fig. 6A The red cathode electrode R_CE may be a different region of the common cathode electrode. The common cathode electrode may be deposited through an open mask to have an integral shape.

[0206] The hole control layer HCL' may be disposed between the second sensor anode electrode O_AE2 and the second photoelectric conversion layer O_RL2, and the electron control layer ECL' may be disposed between the second sensor cathode electrode O_CE2 and the second photoelectric conversion layer O_RL2. The hole control layer HCL' and the electron control layer ECL' may be respectively Fig. 6A The hole control layer HCL and the electron control layer ECL are extended layers.

[0207] Figure 7 is a plan view of a display panel according to some embodiments of the present disclosure.

[0208] Reference Figure 7 According to some embodiments of the present disclosure, the display panel DP may include a display area DA (see, for example, Figure 3 ) and non-display area NDA (see, e.g., Figure 3 ). A plurality of pixels PX (for example, referring to Figure 3 ) and multiple sensors FX (for example, refer to Figure 3 ) may be disposed in the display area DA. The driver chip DIC and the sensor chips SIC1 and SIC2 may be mounted in the non-display area NDA.

[0209] Data lines DL1 to DLm (for example, see Figure 3 ) can be connected to a plurality of pixels PX in the display area DA, and connected to a driver chip DIC in the non-display area NDA. Figure 3 ) can be connected to the multiple sensors FX in the display area DA, and connected to the sensor chips SIC1 and SIC2 in the non-display area NDA.

[0210] The data lines DL1 to DLm may be divided into a first group and a second group. The first group includes a plurality of first data lines DL_G1, and the second group includes a plurality of second data lines DL_G2. The plurality of first data lines DL_G1 may be arranged in a first direction DR1, and the plurality of second data lines DL_G2 may be arranged in the first direction DR1. The plurality of first data lines DL_G1 may be spaced apart from the plurality of second data lines DL_G2 in the first direction DR1.

[0211] The plurality of first data lines DL_G1 may be connected to a pixel driving circuit P_PD of a first group of pixels among the plurality of pixels PX (see, for example, Figure 4A ), the plurality of second data lines DL_G2 may be connected to the pixel driving circuit P_PD of the second group of pixels among the plurality of pixels PX (see, for example, Figure 4A). The first group of pixels and the first data line DL_G1 may be disposed in the first area A1, and the second group of pixels and the second data line DL_G2 may be disposed in the second area A2. The first area A1 may include a first-first area A1-1 defined on a first side of a center line parallel to the second direction DR2 of the display panel DP and a first-second area A1-2 defined on a second side relative to the center line. The second area A2 may include a second-first area A2-1 disposed between the first-first area A1-1 and the non-display area NDA and a second-second area A2-2 disposed between the first-second area A1-2 and the non-display area NDA.

[0212] The plurality of first data lines DL_G1 may include a first-first data line DL1-1 disposed in the first-first area A1-1 and a first-second data line DL1-2 disposed in the first-second area A1-2. The plurality of second data lines DL_G2 may include a second-first data line DL2-1 disposed in the second-first area A2-1 and a second-second data line DL2-2 disposed in the second-second area A2-2.

[0213] The first-first data line DL1-1 and the first-second data line DL1-2 may be connected to the driver chip DIC. Figure 7 An example is shown in which the first-first data line DL1-1 and the first-second data line DL1-2 are connected to the same driver chip DIC, but the present disclosure is not limited thereto. For example, the first-first data line DL1-1 and the first-second data line DL1-2 may be connected to different driver chips, respectively.

[0214] The display panel DP may further include data link lines connecting the second data lines DL_G2 to the driver chip DIC. The data link lines may include a plurality of vertical data link lines V_DCL extending along the first data lines DL_G1 and a plurality of horizontal data link lines H_DCL extending in the first direction DR1.

[0215] The plurality of horizontal data connection lines H_DCL may include first horizontal data connection lines H_DCL1 (i.e., H_DCL11 to H_DCL13) and second horizontal data connection lines H_DCL2 (i.e., H_DCL21 to H_DCL23). The first horizontal data connection lines H_DCL11 to H_DCL13 may be connected to the second-first data lines DL2-1, and the second horizontal data connection lines H_DCL21 to H_DCL23 may be connected to the second-second data lines DL2-2. The plurality of vertical data connection lines V_DCL may include first vertical data connection lines V_DCL1 and second vertical data connection lines V_DCL2. The first vertical data connection lines V_DCL1 may be connected to the first horizontal data connection lines H_DCL11 to H_DCL13, and the second vertical data connection lines V_DCL2 may be connected to the second horizontal data connection lines H_DCL21 to H_DCL23.

[0216] Therefore, the first vertical data link line V_DCL1 may be electrically connected to the second-first data line DL2-1 through the first horizontal data link lines H_DCL11 to H_DCL13. The second vertical data link line V_DCL2 may be electrically connected to the second-second data line DL2-2 through the second horizontal data link lines H_DCL21 to H_DCL23.

[0217] The first vertical data link lines V_DCL1 may alternate with the first-first data lines DL1-1 in the first direction DR1 in the first-first area A1-1. The second vertical data link lines V_DCL2 may alternate with the first-second data lines DL1-2 in the first direction DR1 in the first-second area A1-2.

[0218] A portion of the vertical data connection line V_DCL and a plurality of horizontal data connection lines H_DCL may be disposed in the display area DA. For example, a portion of the data connection line for connecting the second data line DL_G2 and the driver chip DIC may be disposed in the display area DA. Therefore, the area of ​​the area occupied by the data connection line in the non-display area NDA may be reduced, and thus the area of ​​the dead zone of the display panel DP may be reduced.

[0219] The readout lines RL1 to RLh may be divided into a first group and a second group. The first group includes a plurality of first readout lines RL_G1, and the second group includes a plurality of second readout lines RL_G2. The plurality of first readout lines RL_G1 may be arranged in a first direction DR1, and the plurality of second readout lines RL_G2 may be arranged in the first direction DR1. The plurality of first readout lines RL_G1 may be spaced apart from the plurality of second readout lines RL_G2 in the first direction DR1.

[0220] The plurality of first readout lines RL_G1 may be connected to a sensor driving circuit O_SD of a first group of sensors among the plurality of sensors FX (eg, see Figure 4A ), the plurality of second readout lines RL_G2 may be connected to the sensor driving circuit O_SD of the second group of sensors among the plurality of sensors FX (eg, referring to Figure 4A ). The first group of sensors and the first readout line RL_G1 may be disposed in the second area A2, and the second group of sensors and the second readout line RL_G2 may be disposed in the first area A1.

[0221] The plurality of first readout lines RL_G1 may include first-first readout lines RL1-11 to RL1-13 and first-second readout lines RL1-21 to RL1-23. The first-first readout lines RL1-11 to RL1-13 may be disposed in the second-first area A2-1 and connected to the first sensor chip SIC1. The first-second readout lines RL1-21 to RL1-23 may be disposed in the second-second area A2-2 and connected to the second sensor chip SIC2.

[0222] The plurality of second readout lines RL_G2 may include second-first readout lines RL2-11 to RL2-13 and second-second readout lines RL2-21 to RL2-23. The second-first readout lines RL2-11 to RL2-13 may be disposed in the first-first area A1-1 and electrically connected to the first sensor chip SIC1. The second-second readout lines RL2-21 to RL2-23 may be disposed in the first-second area A1-2 and electrically connected to the second sensor chip SIC2. The plurality of second readout lines RL_G2 may be disposed between the first-first readout lines RL1-11 to RL1-13 and the first-second readout lines RL1-21 to RL1-23 in the first direction DR1.

[0223] The display panel DP may further include connection lines electrically connected to the second readout lines RL_G2. The connection lines may include a plurality of vertical connection lines V_RL extending along the first readout lines RL_G1 (e.g., in the second direction DR2) and a plurality of horizontal connection lines H_RL extending in the first direction DR1. The vertical connection lines V_RL may include a first vertical connection line V_RL1 electrically connected to the first sensor chip SIC1 and a second vertical connection line V_RL2 electrically connected to the second sensor chip SIC2.

[0224] The first vertical connection lines V_RL1 may alternate with the first-first readout lines RL1-11 to RL1-13 in the first direction DR1. The second vertical connection lines V_RL2 may alternate with the first-second readout lines RL1-21 to RL1-23 in the first direction DR1.

[0225] The horizontal connection line H_RL may electrically connect the vertical connection line V_RL to the second readout line RL_G2. The horizontal connection line H_RL may include a first horizontal connection line H_RL1 connecting the first vertical connection line V_RL1 to the second-first readout lines RL2-11 to RL2-13, respectively, and a second horizontal connection line H_RL2 connecting the second vertical connection line V_RL2 to the second-second readout lines RL2-21 to RL2-23, respectively.

[0226] A portion of the vertical connection line V_RL and a plurality of horizontal connection lines H_RL may be disposed in the display area DA. For example, a portion of the connection line for connecting the second readout line RL_G2 with the first sensor chip SIC1 and the second sensor chip SIC2 may be disposed in the display area DA. Therefore, the area of ​​the area occupied by the connection lines in the non-display area NDA may be reduced, and thus the area of ​​the dead zone of the display panel DP may be reduced.

[0227] Even if the first sensor chip SIC1 or the second sensor chip SIC2 may be disposed adjacent to the driver chip DIC, when the second readout line RL_G2 is connected to the first sensor chip SIC1 or the second sensor chip SIC2 through the connection line and the second data line DL_G2 is connected to the driver chip DIC through the data connection line, the readout line and the data line may not cross each other in the non-display area NDA. Therefore, the coupling capacitance between the readout line and the data line may be reduced, and thus the sensing accuracy of the sensor FX may be improved (e.g., increased).

[0228] FIG. 8A to FIG. 8K is a plan view illustrating a process of stacking a circuit layer and a component layer according to some embodiments of the present disclosure. Fig. 9 According to some embodiments of the present disclosure, Figure 8K A cross-sectional view taken along line II' shown in FIG.

[0229] Reference FIG. 8A to FIG. 8K , conductive patterns and semiconductor patterns can be repeatedly arranged on a plane according to preset rules. FIG. 8A to FIG. 8K FIG. 2 shows a pixel driving circuit P_PD (eg, referring to FIG. 2 ) that may be provided in the first row ODD_R according to some embodiments of the present disclosure. Figure 4A ) and a portion of the sensor drive circuit O_SD (for example, see Figure 4A) and a portion of a pixel driving circuit P_PD and a portion of a sensor driving circuit O_SD that may be provided in the second row EVEN_R. The first row ODD_R and the second row EVEN_R may be adjacent to each other in the second direction DR2. Eight first circuit areas (or pixel circuit areas) P_PA corresponding to eight pixel driving circuits P_PD adjacent to each other in the first direction DR1 and a second circuit area (or sensor circuit area) O_SA corresponding to one sensor driving circuit O_SD are defined in the first row ODD_R. Eight first circuit areas P_PA corresponding to eight pixel driving circuits P_PD adjacent to each other in the first direction DR1 and a second circuit area O_SA corresponding to one sensor driving circuit O_SD are defined in the second row EVEN_R. FIG. 8A to FIG. 8K In FIG. 1 , a boundary between the first circuit area P_PA and the second circuit area O_SA is shown by a dotted line.

[0230] Reference Fig. 8A According to some embodiments of the present disclosure, a shielding layer BML may be formed on the buffer layer BFL. The shielding layer BML may be a conductive pattern having a light blocking function. The shielding layer BML may be disposed between the transistors T1 to T8 (eg, referring to Figure 4A ) and can block light from being incident on the transistors T1 to T8 from the outside.

[0231] Reference Fig. 8A and Figure 8B According to some embodiments of the present disclosure, a first semiconductor pattern layer ACT1 may be disposed on the shielding layer BML and the buffer layer BFL. The first semiconductor pattern layer ACT1 may overlap the shielding layer BML on the buffer layer BFL. The first semiconductor pattern layer ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern layer ACT1 may include low temperature polycrystalline silicon (LTPS).

[0232] The first semiconductor pattern layer ACT1 may include a first semiconductor pattern P_ACT1 disposed in each of the first circuit areas P_PA and a second semiconductor pattern S_ACT1 disposed in each of the second circuit areas O_SA.

[0233] Reference Figure 8CAccording to some embodiments of the present disclosure, a first gate pattern layer GAT1 may be disposed on the first insulating layer INS1. The first gate pattern layer GAT1 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material. For example, the first gate pattern layer GAT1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), and / or indium zinc oxide (IZO), but is not particularly limited thereto.

[0234] The first gate pattern layer GAT1 may include a first gate wiring SBL, a second gate wiring EML, a third gate wiring SWL, a first gate electrode G1, and a first sensor gate electrode G1'.

[0235] Each of the first gate wiring SBL, the second gate wiring EML, and the third gate wiring SWL may extend in the first direction DR1. The first gate wiring SBL may correspond to Figure 4A For example, the j-th black scan signal SBj (for example, refer to Figure 4A ) may be provided to the first gate wiring SBL. The first gate wiring SBL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The seventh transistor T7.

[0236] The second gate wiring EML may correspond to Figure 4A For example, the j-th emission control signal EMj (for example, referring to Figure 4A ) may be provided to the second gate wiring EML. The second gate wiring EML may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The fifth transistor T5 and the sixth transistor T6.

[0237] The third gate wiring SWL may correspond to Figure 4A For example, the j-th write scan signal SWj (for example, refer to Figure 4A ) may be provided to the third gate wiring SWL. The third gate wiring SWL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The second transistor T2 and the second semiconductor pattern S_ACT1 may constitute Figure 4A The output transistor ST3.

[0238] The first gate electrode G1 and the first sensor gate electrode G1' may be provided in an island shape. The first gate electrode G1 may constitute a first semiconductor pattern P_ACT1 together with the first semiconductor pattern P_ACT1. Figure 4A The first gate electrode G1 may correspond to the first transistor T1. Fig. 6A The first gate electrode G1 of the first transistor T1 shown in FIG. The first sensor gate electrode G1′ may constitute a first gate electrode G1′ with the second semiconductor pattern S_ACT1. Figure 4A Amplifying transistor ST2.

[0239] Reference Figure 8C and Fig.8D The second insulating layer INS2 may cover the first gate pattern layer GAT1 and may be disposed on the first insulating layer INS1. The second gate pattern layer GAT2 may be disposed on the second insulating layer INS2. The second gate pattern layer GAT2 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0240] The second gate pattern layer GAT2 may include a fourth gate wiring G2_SRL, a fifth gate wiring G2_SCL, a sixth gate wiring G2_SIL, and an upper gate electrode UGE.

[0241] The fourth gate wiring G2_SRL, the fifth gate wiring G2_SCL, and the sixth gate wiring G2_SIL may extend in the first direction DR1. The fourth gate wiring G2_SRL may correspond to the reset control line SRL (eg, referring to Figure 4A ) (or included in the reset control line SRL (for example, refer to Figure 4A )). The fifth gate wiring G2_SCL may correspond to the j-th compensation scan line SCLj (eg, referring to Figure 4A ) (or may include in the jth compensation scan line SCLj (for example, referring to Figure 4A )). The sixth gate wiring G2_SIL may correspond to the jth initialization scan line SILj (eg, referring to Figure 4A ) (or may include in the jth initialization scan line SILj (for example, refer to Figure 4A )middle).

[0242] The upper gate electrode UGE may overlap the first gate electrode G1 and may be provided in an island shape. For example, the upper gate electrode UGE may constitute a capacitor Cst together with the first gate electrode G1 (eg, referring to Figure 4A ). The upper gate electrode UGE may correspond to Fig. 6A The upper gate electrode UGE shown in FIG. An opening UGE_OP may be formed through the upper gate electrode UGE, and the first gate electrode G1 (see, for example, Fig. 6A ) can be partially exposed through the opening UGE_OP.

[0243] Reference Fig.8D and Fig. 8E, the third insulating layer INS3 may cover the second gate pattern layer GAT2 and may be disposed on the second insulating layer INS2. A second semiconductor pattern layer ACT2 may be disposed on the third insulating layer INS3. The second semiconductor pattern layer ACT2 may include an oxide semiconductor. The second semiconductor pattern layer ACT2 may be disposed at a different layer from the first semiconductor pattern layer ACT1 and may not overlap the first semiconductor pattern layer ACT1.

[0244] The second semiconductor pattern layer ACT2 may include a third semiconductor pattern P_ACT2 disposed in each of the first circuit areas P_PA and a fourth semiconductor pattern S_ACT2 disposed in each of the second circuit areas O_SA.

[0245] Reference Fig. 8E and Figure 8F The fourth insulating layer INS4 may cover the second semiconductor pattern layer ACT2 and may be disposed on the third insulating layer INS3. A third gate pattern layer GAT3 may be disposed on the fourth insulating layer INS4. The third gate pattern layer GAT3 may include metal, alloy, conductive metal oxide and / or transparent conductive material.

[0246] The third gate pattern layer GAT3 may include a seventh gate wiring G3_SRL, an eighth gate wiring G3_SCL, a ninth gate wiring G3_SIL, a second-first horizontal initialization voltage line H_VAIL1, a second-second horizontal initialization voltage line H_VAIL2, and a first horizontal reset voltage line G3_VRL. The second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2 may be referred to as a second horizontal initialization voltage line.

[0247] The seventh gate wiring G3_SRL, the eighth gate wiring G3_SCL, and the ninth gate wiring G3_SIL may extend in the first direction DR1. The seventh gate wiring G3_SRL may overlap the fourth semiconductor pattern S_ACT2. The seventh gate wiring G3_SRL may constitute a semiconductor pattern S_ACT2 together with the fourth semiconductor pattern S_ACT2. Figure 4A The seventh gate wiring G3_SRL can be connected to the reset transistor ST1. Fig.8D The fourth gate wiring G2_SRL shown in FIG. 1 is electrically connected to the gate wiring G2_SRL.

[0248] The eighth gate wiring G3_SCL may overlap the fifth gate wiring G2_SCL and the third semiconductor pattern P_ACT2. In some embodiments, the eighth gate wiring G3_SCL may contact the fifth gate wiring G2_SCL through a contact portion (e.g., contact or directly contact the fifth gate wiring G2_SCL). Therefore, the j-th compensation scan signal SCj applied to the fifth gate wiring G2_SCL may be provided to the eighth gate wiring G3_SCL. The fifth gate wiring G2_SCL, the third semiconductor pattern P_ACT2, and the eighth gate wiring G3_SCL may constitute Figure 4A The third transistor T3.

[0249] The ninth gate wiring G3_SIL may overlap the sixth gate wiring G2_SIL and the third semiconductor pattern P_ACT2. The ninth gate wiring G3_SIL may be electrically connected to the sixth gate wiring G2_SIL. The j-th initialization scan signal SIj may be provided to the ninth gate wiring G3_SIL through the sixth gate wiring G2_SIL. The sixth gate wiring G2_SIL, the third semiconductor pattern P_ACT2, and the ninth gate wiring G3_SIL may constitute Figure 4A The fourth transistor T4.

[0250] The second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2 may be included in the second initialization voltage line VAIL (eg, refer to Figure 4A ) components in the second-first horizontal initialization voltage line H_VAIL1 can be connected to Figure 3 The first color pixel (e.g., red pixel) among the multiple pixels PX shown in the figure, the second-second horizontal initialization voltage line H_VAIL2 can be connected to the second color pixel or the third color pixel (e.g., blue pixel or green pixel) different from the first color pixel among the multiple pixels PX.

[0251] The second-first horizontal initialization voltage line H_VAIL1 can use the second-first initialization voltage as the second initialization voltage Vaint (eg, refer to Figure 4A ) is applied to the first color pixel, the second-second horizontal initialization voltage line H_VAIL2 can apply the second-second initialization voltage as the second initialization voltage Vaint to the second color pixel or the third color pixel. The second-second initialization voltage can have a voltage level different from that of the second-first initialization voltage.

[0252] The first horizontal reset voltage line G3_VRL may be included in Figure 4A The reset voltage Vrst (for example, referring to Figure 4A) may be provided to the first horizontal reset voltage line G3_VRL. The first horizontal reset voltage line G3_VRL may be electrically connected to the reset transistor ST1. The reset transistor ST1 may receive the reset voltage Vrst through the first horizontal reset voltage line G3_VRL.

[0253] Reference Figure 8F and Figure 8G , the fifth insulating layer INS5 may cover at least a portion of the third gate pattern layer GAT3 and may be disposed on the fourth insulating layer INS4. The first data pattern layer SD1 may be disposed on the fifth insulating layer INS5. The first data pattern layer SD1 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material. Hereinafter, for ease of description, Figure 8G Only some of the components included in the first data pattern layer SD1 are shown in FIG.

[0254] The first data pattern layer SD1 may include a second horizontal reset voltage line D1_VRL, a bias voltage line D1_VBL, a first horizontal initialization voltage line H_VIL, and a plurality of first connection electrode patterns C_CNE1.

[0255] The second horizontal reset voltage line D1_VRL, the bias voltage line D1_VBL, and the first horizontal initialization voltage line H_VIL may extend in the first direction DR1. The second horizontal reset voltage line D1_VRL, the bias voltage line D1_VBL, and the first horizontal initialization voltage line H_VIL may be spaced apart from each other in the second direction DR2.

[0256] The second horizontal reset voltage line D1_VRL may be included in Figure 4A The reset voltage Vrst (for example, referring to Figure 4A ) may be provided to the second horizontal reset voltage line D1_VRL. The second horizontal reset voltage line D1_VRL may be electrically connected to the first horizontal reset voltage line G3_VRL. The bias voltage line D1_VBL may correspond to Figure 4A The bias voltage Vbias (for example, referring to Figure 4A ) may be provided to the bias voltage line D1_VBL. The bias voltage line D1_VBL may be connected to the eighth transistor T8 through a contact portion. The eighth transistor T8 may receive the bias voltage Vbias through the bias voltage line D1_VBL.

[0257] The first horizontal initialization voltage line H_VIL may be included in Figure 4A The first initialization voltage Vint (for example, referring to Figure 4A) can be provided to the first horizontal initialization voltage line H_VIL. The first horizontal initialization voltage line H_VIL can be connected to the fourth transistor T4 through the contact portion. The fourth transistor T4 can receive the first initialization voltage Vint through the first horizontal initialization voltage line H_VIL.

[0258] The plurality of first connection electrode patterns C_CNE1 may contact one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 (e.g., contact or directly contact one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2). The plurality of first connection electrode patterns C_CNE1 may perform a function of electrically connecting one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 to other wirings or lines. The plurality of first connection electrode patterns C_CNE1 may be connected to one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 through a contact portion. The plurality of first connection electrode patterns C_CNE1 may include Fig. 6A and Figure 6B The first circuit connection electrode CNE1 and the fourth circuit connection electrode CNE1 ′ are shown in FIG.

[0259] The first data pattern layer SD1 may further include a horizontal connection wiring D1_HCL. The horizontal connection wiring D1_HCL may extend in the first direction DR1. The horizontal connection wiring D1_HCL may be used as Figure 7 The components of the horizontal data connection line H_DCL shown in or Figure 7 Components of the horizontal connecting line H_RL shown in .

[0260] Reference Figure 8G and Figure 8H The sixth insulating layer INS6 may cover at least a portion of the first data pattern layer SD1 and may be disposed on the fifth insulating layer INS5. The second data pattern layer SD2 may be disposed on the sixth insulating layer INS6. The second data pattern layer SD2 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0261] The second data pattern layer SD2 may include a first readout line portion RL_P1 , a vertical reset voltage line V_VRL, a first driving voltage line VL1 , and a plurality of voltage connection patterns.

[0262] The first readout line portion RL_P1 may extend in the second direction DR2 in each of the second circuit regions O_SA. That is, the first readout line portion RL_P1 may overlap one corresponding second circuit region O_SA. The first readout line portion RL_P1 may be Figure 3 A portion of each of the readout lines RL1 to RLh shown in FIG. Fig.8I ) can be connected to Figure 4A The sensor drive circuit O_SD (particularly, the output transistor ST3) shown in FIG.

[0263] The vertical reset voltage lines V_VRL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The vertical reset voltage lines V_VRL may be included in Figure 4A The vertical reset voltage line V_VRL may be connected to the first horizontal reset voltage line G3_VRL (see, for example, Figure 8F ) and a second horizontal reset voltage line D1_VRL (see, for example, Figure 8G The reset voltage line VRL may have a mesh form by combining the vertical reset voltage line V_VRL with the first horizontal reset voltage line G3_VRL and the second horizontal reset voltage line D1_VRL.

[0264] The first driving voltage line VL1 may overlap the first circuit region P_PA. The first driving voltage line VL1 may correspond to Figure 4A The first driving voltage ELVDD (for example, refer to Figure 4A ) can be provided to the first driving voltage line VL1. The first driving voltage line VL1 may be arranged in a grid form in the display area DA of the display panel DP (eg, referring to Figure 3 ). The first driving voltage line VL1 can be connected to Figure 4A The fifth transistor T5 shown in FIG. 1 is connected to the capacitor Cst.

[0265] The plurality of voltage connection patterns C_VP may be connected with vertical voltage lines V_VL to be described below.

[0266] The second data pattern layer SD2 may further include a plurality of second connection electrode patterns C_CNE2. The plurality of second connection electrode patterns C_CNE2 may include Fig. 6A and Figure 6B The second circuit connection electrode CNE2 and the fifth circuit connection electrode CNE2' are shown in FIG.

[0267] Reference Figure 8H and Fig.8IThe seventh insulating layer INS7 may cover at least a portion of the second data pattern layer SD2 and may be disposed on the sixth insulating layer INS6. A third data pattern layer SD3 may be disposed on the seventh insulating layer INS7. The third data pattern layer SD3 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0268] The third data pattern layer SD3 may include a data wiring DL, a second readout line portion RL_P2 , a vertical connection wiring D3_VCL, a vertical voltage line V_VL, a dummy vertical reset voltage line D3_VRL, and a plurality of third connection electrode patterns C_CNE3 .

[0269] The data wiring DL, the vertical connection wiring D3_VCL, and the vertical voltage line V_VL may extend in the second direction DR2. The data wiring DL, the vertical connection wiring D3_VCL, and the vertical voltage line V_VL may be spaced apart from each other in the first direction DR1.

[0270] The data wiring DL may correspond to Figure 3 The data wiring DL can be connected to the data lines DL1 to DLm shown in FIG. Figure 4A The pixel driving circuit P_PD (particularly, the second transistor T2) shown in FIG. 1 may be a vertical connection wiring D3_VCL used as Figure 7 The components of the vertical data connection line V_DCL shown in Figure 7 The vertical connection wiring D3_VCL can be connected to the vertical connection wiring V_RL shown in FIG. Figure 8G The horizontal connection wiring D1_HCL shown in FIG. 1 is electrically connected.

[0271] The second readout line portion RL_P2 may overlap two second circuit regions O_SA adjacent to each other. The second readout line portion RL_P2 may be connected to two first readout line portions RL_P1 adjacent to each other. Therefore, one readout wiring RL may include a plurality of first readout line portions RL_P1 and second readout line portions RL_P2. The readout wiring RL may correspond to Figure 3 One of the readout lines RL1 to RLh shown in FIG.

[0272] One of the vertical voltage lines V_VL can be connected through a corresponding voltage connection pattern C_VP (eg, see Figure 8H ) is electrically connected to Figure 8F The second-first horizontal initialization voltage line H_VAIL1 shown in FIG. 1 may be electrically connected to the vertical voltage line V_VL through a corresponding voltage connection pattern C_VP. Figure 8F In other words, a portion of the vertical voltage line V_VL can be used as the second initialization voltage line VAIL (eg, referring to Figure 4A ). In addition, another one of the vertical voltage lines V_VL may be connected via a corresponding voltage connection pattern C_VP (eg, referring to Figure 8H ) is electrically connected to Figure 8G , and may be used as a first horizontal initialization voltage line H_VIL (eg, referring to Figure 4A ).

[0273] The other of the vertical voltage lines V_VL can be used as Figure 4A As described above, the vertical voltage line V_VL can be used as a second driving voltage line VL2 connected to the pixel PX (for example, referring to Figure 3 ) and sensor FX (for example, see Figure 3 ) and can relieve the drop of the voltage applied to the corresponding voltage line. The dummy vertical reset voltage lines D3_VRL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The dummy vertical reset voltage lines D3_VRL may be included in Figure 4A The dummy vertical reset voltage line D3_VRL may be connected to the first horizontal reset voltage line G3_VRL and the second horizontal reset voltage line D1_VRL (see, for example, Figure 8F and Figure 8G ) and a vertical reset voltage line V_VRL.

[0274] The plurality of third connection electrode patterns C_CNE3 may include Fig. 6A and Figure 6B The third circuit connection electrode CNE3 and the sixth circuit connection electrode CNE3 ′ are shown in FIG.

[0275] Reference Fig.8I and Figure 8J , the eighth insulating layer INS8 may cover at least a portion of the third data pattern layer SD3 and may be disposed on the seventh insulating layer INS7. A conductive pattern TCO may be disposed on the eighth insulating layer INS8. The conductive pattern TCO may include a transparent conductive oxide. For example, the conductive pattern TCO may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0276] The conductive pattern TCO may include a plurality of shielding electrodes RSE and a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE. When viewed from above a plane (e.g., in a plan view), the plurality of shielding electrodes RSE may overlap with the readout wiring RL. Each of the plurality of shielding electrodes RSE may contact (e.g., contact or directly contact) the vertical reset voltage line V_VRL through a contact portion. Therefore, the reset voltage Vrst (e.g., referring to the vertical reset voltage line V_VRL) applied to the vertical reset voltage line V_VRL may be increased. Figure 4A ) can be applied to the shielding electrode RSE.

[0277] The plurality of shielding electrodes RSE may be disposed to partially cover the sensor driving circuit O_SD in the second circuit area O_SA (see, for example, Figure 4A ). In particular, each of the shielding electrodes RSE may be arranged to cover the reset transistor ST1 (eg, refer to Figure 4A ), amplifying transistor ST2 (for example, see Figure 4A ) and output transistor ST3 (for example, refer to Figure 4A ) in whole or in part.

[0278] Each shield electrode RSE may perform a shielding function so that a detection signal output from the readout wiring RL is not coupled by a data signal applied to the data wiring DL.

[0279] In some embodiments of the present disclosure, a plurality of shielding electrodes RSE may be spaced apart from each other in the second direction DR2. In the first row ODD_R, a plurality of shielding electrodes RSE may be spaced apart from each other in the second direction DR2 at a first interval d1, and in the second row EVEN_R, a plurality of shielding electrodes RSE may be spaced apart from each other in the second direction DR2 at a second interval d2. In some embodiments of the present disclosure, the first interval d1 may be different from the second interval d2. For example, the second interval d2 may be larger than the first interval d1.

[0280] The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may include first and second green pixel connection electrodes G1_CNE and G2_CNE, a red pixel connection electrode R_CNE, and a blue pixel connection electrode B_CNE.

[0281] The first green pixel connection electrode G1_CNE may be connected to the first green pixel driving circuit G1_PD (eg, refer to Figure 5The second green pixel connection electrode G2_CNE may be connected to the second green pixel driving circuit G2_PD (eg, refer to Figure 5 The red pixel connection electrode R_CNE may be connected to the red pixel driving circuit R_PD (eg, refer to Figure 5 ), the blue pixel connection electrode B_CNE may be connected to the blue pixel driving circuit B_PD (eg, referring to Figure 5 ).

[0282] In some embodiments of the present disclosure, in the second row EVEN_R, the blue pixel connection electrode B_CNE may pass through the separation space RSE_OPa (or the opening portion) between the shielding electrodes RSE in the first direction DR1 .

[0283] Multiple shielding electrodes RSE and pixel connection electrodes G1_CNE, G2_CNE, R_CNE and B_CNE may be disposed in (eg, on or in) the same layer (ie, on the eighth insulating layer INS8) and may not overlap each other when viewed from above a plane (eg, in a plan view).

[0284] Reference Figure 8J and Figure 8K The ninth insulating layer INS9 may cover at least a portion of the conductive pattern TCO and may be disposed on the eighth insulating layer INS8. The anode pattern AEP may be disposed on the ninth insulating layer INS9. The anode pattern AEP may include metal, alloy, conductive metal oxide and / or transparent conductive material.

[0285] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2. The plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE may include first and second green anode electrodes G1_AE and G2_AE, a red anode electrode R_AE, and a blue anode electrode B_AE. The plurality of sensor anode electrodes O_AE1 and O_AE2 may include a first sensor anode electrode O_AE1 disposed in a first row ODD_R and a second sensor anode electrode O_AE2 disposed in a second row EVEN_R.

[0286] The first green anode electrode G1_AE may be connected to the first green pixel connection electrode G1_CNE through the first-second green contact hole G1_CH2 defined in the ninth insulating layer INS9. The second green anode electrode G2_AE may be connected to the second green pixel connection electrode G2_CNE through the second-second green contact hole G2_CH2 defined in the ninth insulating layer INS9. The red anode electrode R_AE may be connected to the red pixel connection electrode R_CNE through the second red contact hole R_CH2 defined in the ninth insulating layer INS9, and the blue anode electrode B_AE may be connected to the blue pixel connection electrode B_CNE through the second blue contact hole B_CH2 defined in the ninth insulating layer INS9.

[0287] As described above, the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may be disposed in the same layer (e.g., on or in the same layer) as the shielding electrode RSE (i.e., disposed on the eighth insulating layer INS8), and the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE may be connected to the corresponding pixel driving circuits. Figure 3 )'s resolution is increased, and the degree of freedom in arrangement of the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE can also be improved (eg, increased).

[0288] The blue anode electrode B_AE can be set to be adjacent to the first side (e.g., the left side) of the readout wiring RL (or the first readout wiring), and the blue pixel driving circuit B_PD (i.e., the first pixel driving circuit) corresponding to the blue anode electrode B_AE (i.e., the blue light-emitting element ED_B) can be set to be adjacent to the second side (e.g., the right side) of the adjacent readout wiring RL.

[0289] Reference Figure 8K and Fig. 9 , in the second row EVEN_R, the blue pixel connection electrode B_CNE may cross the readout wiring RL. In particular, the blue pixel connection electrode B_CNE may cross the first readout line portion RL_P1 and may not cross the second readout line portion RL_P2. Two sequentially stacked insulating layers (i.e., the seventh insulating layer INS7 and the eighth insulating layer INS8) may be provided between the first readout line portion RL_P1 and the blue pixel connection electrode B_CNE.

[0290] The first readout line portion RL_P1 may be disposed on the sixth insulating layer INS6 (or the first intermediate insulating layer), and the second readout line portion RL_P2 (see, for example, Figure 8K) may be disposed on the seventh insulating layer INS7 (or the second intermediate insulating layer). The blue pixel connection electrode B_CNE may be disposed on an eighth insulating layer INS8 (or the third intermediate insulating layer) covering the second readout line portion RL_P2.

[0291] When the blue pixel connection electrode B_CNE is disposed to cross the first readout line portion RL_P1 in the second row EVEN_R, a gap between the blue pixel connection electrode B_CNE and the first readout line portion RL_P1 in the third direction DR3 can be sufficiently ensured by the seventh insulating layer INS7 and the eighth insulating layer INS8. Therefore, the coupling capacitance between the blue pixel connection electrode B_CNE and the readout wiring RL can be reduced, and thus the sensing accuracy of the sensor FX can be improved (e.g., increased).

[0292] In some examples, when the blue pixel connection electrode B_CNE crosses the second readout line portion RL_P2 in the second row EVEN_R, only one insulating layer (ie, the seventh insulating layer INS7 ) may be disposed between the blue pixel connection electrode B_CNE and the second readout line portion RL_P2 .

[0293] The first and second green anode electrodes G1_AE and G2_AE, the red anode electrode R_AE, the blue anode electrode B_AE, and the first and second sensor anode electrodes O_AE1 and O_AE2 may be disposed on the ninth insulating layer INS9 (or the fourth intermediate insulating layer).

[0294] The first sensor anode electrode O_AE1 may be disposed to overlap the sensor circuit area O_SA, and the second sensor anode electrode O_AE2 may be disposed not to overlap the sensor circuit area O_SA. The second sensor anode electrode O_AE2 may overlap the pixel circuit area P_PA. The first sensor anode electrode O_AE1 may be connected to the corresponding sensor driving circuit through the first sensor contact hole O_CH1.

[0295] In some embodiments of the present disclosure, the anode pattern AEP may further include a sensor connection electrode O_CNE2 and a dummy connection electrode D_CNE1. The sensor connection electrode O_CNE2 may extend from the second sensor anode electrode O_AE2 and may partially overlap with the sensor circuit area O_SA. The sensor connection electrode O_CNE2 may be integrally formed with the second sensor anode electrode O_AE2. The sensor connection electrode O_CNE2 may be connected to the corresponding sensor drive circuit through the second sensor contact hole O_CH2. The second sensor anode electrode O_AE2 may be electrically connected to the corresponding sensor drive circuit through the sensor connection electrode O_CNE2.

[0296] The dummy connection electrode D_CNE1 may extend from the first sensor anode electrode O_AE1 and may overlap the pixel circuit area P_PA. In some embodiments of the present disclosure, the dummy connection electrode D_CNE1 may have a shape similar to that of the sensor connection electrode O_CNE2. The sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 may be substantially the same as the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2.

[0297] When the first light receiving element OPD1 (for example, referring to Figure 5 ) and the second light receiving element OPD2 (for example, refer to Figure 5 ) are different from each other, the coupling capacitance acting on the first light receiving element OPD1 (for example, refer to Figure 5 ) and the second light receiving element OPD2 (for example, refer to Figure 5 ) may be different in size from each other. In this case, the detection signals of the corresponding rows may be biased. However, when a design is performed so that the sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 is substantially the same as the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2, the deviation of the detection signals of the corresponding rows can be reduced, thereby improving (e.g., increasing) the sensing uniformity and the sensing accuracy.

[0298] In addition, the data wiring DL (for example, Fig.8I ) and vertical connection wiring D3_VCL (for example, Fig.8I ) may be substantially the same as the number of data wirings DL and vertical connection wirings D3_VCL crossing the dummy connection electrode D_CNE1. Thus, the size of the coupling capacitance acted on the sensor connection electrode O_CNE2 by the data wirings DL and the vertical connection wirings D3_VCL may be the same or substantially the same as the size of the coupling capacitance acted on the dummy connection electrode D_CNE1 by the data wirings DL and the vertical connection wirings D3_VCL. Therefore, the difference between the coupling capacitance acted on the first light receiving element OPD1 disposed in the first row ODD_R and the coupling capacitance acted on the second light receiving element OPD2 disposed in the second row EVEN_R may be reduced.

[0299] Fig. 10A and Fig. 10B is a plan view showing a portion of a display panel according to some embodiments of the present disclosure. Fig. 10C According to some embodiments of the present disclosure, Fig. 10B A cross-sectional view taken along line II-II' shown in FIG.

[0300] Reference Fig. 10A , Fig. 10B and Fig. 10C According to some embodiments of the present disclosure, the conductive pattern TCOa may include a plurality of shielding electrodes RSEa and a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa. When viewed from above a plane (e.g., in a plan view), the plurality of shielding electrodes RSEa may overlap with the readout wiring RL. Each of the plurality of shielding electrodes RSEa may be connected to a vertical reset voltage line V_VRL (see, for example, Figure 8H ) or a dummy vertical reset voltage line D3_VRL (see, for example, Fig.8I ) contacts (eg, contacts or directly contacts) the vertical reset voltage line V_VRL or the dummy vertical reset voltage line D3_VRL. Therefore, the reset voltage Vrst (eg, referring to Figure 4A ) can be applied to the shielding electrode RSEa.

[0301] In some embodiments of the present disclosure, a plurality of shielding electrodes RSEa may be spaced apart from each other in the second direction DR2. A plurality of shielding electrodes RSEa may be spaced apart from each other in the second direction DR2 in the first row ODD_R to provide an opening portion RSE_OPb. In the second row EVEN_R, the opening portion RSE_OPb may not be provided.

[0302] The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa may include first and second green pixel connection electrodes G1_CNE and G2_CNE, a red pixel connection electrode R_CNE, and a blue pixel connection electrode B_CNEa.

[0303] The blue pixel connection electrode B_CNEa may be connected to the blue pixel driving circuit B_PD (eg, refer to FIG. 1 ) through a first blue contact hole B_CH1 defined in the eighth insulating layer INS8. Figure 5 ). In some embodiments of the present disclosure, the blue pixel connection electrode B_CNEa may pass through the opening portion RSE_OPb in the first row ODD_R.

[0304] The plurality of shielding electrodes RSEa and the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa may be arranged at (eg, in or on) the same layer (ie, on the eighth insulating layer INS8 ), and may not overlap each other when viewed from above a plane.

[0305] The anode pattern AEP may be disposed on the ninth insulating layer INS9. The anode pattern AEP may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0306] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2. The plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE may include first and second green anode electrodes G1_AE and G2_AE, a red anode electrode R_AE, and a blue anode electrode B_AE. The plurality of sensor anode electrodes O_AE1 and O_AE2 may include a first sensor anode electrode O_AE1 disposed in a first row ODD_R and a second sensor anode electrode O_AE2 disposed in a second row EVEN_R. The anode pattern AEP may further include a sensor connection electrode O_CNE2 and a dummy connection electrode D_CNE1.

[0307] The first green anode electrode G1_AE may be connected to the first green pixel connection electrode G1_CNE through the first-second green contact hole G1_CH2 defined in the ninth insulating layer INS9. The second green anode electrode G2_AE may be connected to the second green pixel connection electrode G2_CNE through the second-second green contact hole G2_CH2 defined in the ninth insulating layer INS9. The red anode electrode R_AE may be connected to the red pixel connection electrode R_CNE through the second red contact hole R_CH2 defined in the ninth insulating layer INS9, and the blue anode electrode B_AE may be connected to the blue pixel connection electrode B_CNEa through the second blue contact hole B_CH2 defined in the ninth insulating layer INS9.

[0308] Reference Fig. 10A , Fig. 10B and Fig. 10C According to some embodiments of the present disclosure, the blue pixel connection electrode B_CNEa may cross the readout wiring RL. In particular, in the first row ODD_R, the blue pixel connection electrode B_CNEa may cross the second readout line portion RL_P2 and may not cross the first readout line portion RL_P1. An insulating layer (i.e., the eighth insulating layer INS8) may be disposed between the second readout line portion RL_P2 and the blue pixel connection electrode B_CNEa. However, the present disclosure is not limited thereto. In the first row ODD_R, the blue pixel connection electrode B_CNEa may cross the first readout line portion RL_P1 and may not cross the second readout line portion RL_P2. In this case, two insulating layers (i.e., the seventh insulating layer INS7 and the eighth insulating layer INS8) may be disposed between the first readout line portion RL_P1 and the blue pixel connection electrode B_CNEa.

[0309] like Fig. 10C As shown in , the first readout line portion RL_P1 may be disposed on the sixth insulating layer INS6, and the second readout line portion RL_P2 may be disposed on the seventh insulating layer INS7. When the blue pixel connection electrode B_CNEa crosses the second readout line portion RL_P2, the eighth insulating layer INS8 may be disposed between the blue pixel connection electrode B_CNEa and the second readout line portion RL_P2. Even if the eighth insulating layer INS8 is disposed between the blue pixel connection electrode B_CNEa and the second readout line portion RL_P2 as described above, by making the thickness of the seventh insulating layer INS7 sufficiently large, the coupling capacitance between the blue pixel connection electrode B_CNEa and the readout wiring RL may be reduced.

[0310] For example, even in the first row ODD_R, the blue pixel connection electrode B_CNEa may be arranged to cross the first readout line portion RL_P1. In this case, the gap between the blue pixel connection electrode B_CNEa and the first readout line portion RL_P1 in the third direction DR3 may be sufficiently ensured by the seventh insulating layer INS7 and the eighth insulating layer INS8, thereby reducing the coupling capacitance between the blue pixel connection electrode B_CNEa and the readout wiring RL.

[0311] Fig.11 is a plan view showing a portion of a display panel according to some embodiments of the present disclosure.

[0312] Reference Fig.11 According to some embodiments of the present disclosure, the conductive pattern TCOb may include a main shielding electrode RSE_M, a first branch shielding electrode RSE_S1, and a second branch shielding electrode RSE_S2. When viewed from above a plane (eg, in a plan view), the main shielding electrode RSE_M may overlap with the readout wiring RL (see, for example, Fig. 10B ). The main shielding electrode RSE_M may be connected to a vertical reset voltage line V_VRL (see, for example, Figure 8H ) contacts (eg, contacts or directly contacts) the vertical reset voltage line V_VRL. Therefore, the reset voltage Vrst (eg, reference voltage Vrst) applied to the vertical reset voltage line V_VRL is Figure 4A ) can be applied to the main shielding electrode RSE_M.

[0313] The main shielding electrode RSE_M may be disposed to partially cover the sensor driving circuit O_SD in each of the second circuit areas O_SA (see, for example, Figure 4A ). In particular, the main shielding electrode RSE_M may be arranged to cover the reset transistor ST1 (eg, refer to Figure 4A ), amplifying transistor ST2 (for example, see Figure 4A ) and output transistor ST3 (for example, refer to Figure 4A ) in whole or in part.

[0314] The main shielding electrode RSE_M may perform a shielding function so that the detection signal output from the readout wiring RL is not applied to the data wiring DL (see, for example, Fig.8I In other words, the main shielding electrode RSE_M physically separates the readout wiring RL from the data wiring DL.

[0315] The first branch shielding electrode RSE_S1 may extend from a first side of the main shielding electrode RSE_M in a first direction DR1. The first side may be a side parallel to the second direction DR2. The first branch shielding electrode RSE_S1 may overlap the first sensor anode electrode O_AE1 and the dummy connection electrode D_CNE1 in the first row ODD_R. The second branch shielding electrode RSE_S2 may extend from a second side of the main shielding electrode RSE_M in a direction opposite to the first direction DR1. The second side may be a side parallel to the first side. The second branch shielding electrode RSE_S2 may overlap the second sensor anode electrode O_AE2 and the sensor connection electrode O_CNE2 in the second row EVEN_R.

[0316] The first branch shielding electrode RSE_S1 can reduce the coupling capacitance acting on the dummy connection electrode D_CNE1 by shielding the dummy connection electrode D_CNE1 from the influence of the data wiring DL. In addition, the second branch shielding electrode RSE_S2 can reduce the coupling capacitance acting on the second sensor anode electrode O_AE2 and the sensor connection electrode O_CNE2 by shielding the second sensor anode electrode O_AE2 and the sensor connection electrode O_CNE2 from the influence of the data wiring DL. In other words, the first branch shielding electrode RSE_S1 and the second branch shielding electrode RSE_S2 create a physical separation from the data wiring DL. Therefore, the degradation of the sensing accuracy of each sensor FX caused by the coupling capacitance generated when the dummy connection electrode D_CNE1, the second sensor anode electrode O_AE2 and / or the sensor connection electrode O_CNE2 cross the data wiring DL can be substantially reduced or prevented and / or eliminated.

[0317] The conductive pattern TCOb may further include a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE. The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may include a first green pixel connection electrode G1_CNE and a second green pixel connection electrode G2_CNE, a red pixel connection electrode R_CNE, and a blue pixel connection electrode B_CNE. In some embodiments of the present disclosure, in the second row EVEN_R, the blue pixel connection electrode B_CNE may pass through the separation space RSE_OPc (or opening) between the main shielding electrodes RSE_M.

[0318] Fig. 12A and Fig. 12B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to some embodiments of the present disclosure.

[0319] Reference Fig. 12A and Fig. 12B According to some embodiments of the present disclosure, the first electrode layer may be disposed on the circuit layer DP_CL. The pixel defining layer PDL may be formed on the first electrode layer. The first electrode layer may include a red anode electrode R_AE, a green anode electrode G_AE, and a blue anode electrode B_AE. The first light emitting opening OP1_1, the second light emitting opening OP1_2, and the third light emitting opening OP1_3 of the pixel defining layer PDL may expose at least part of the red anode electrode R_AE, the green anode electrode G_AE, and the blue anode electrode B_AE, respectively. In some embodiments of the present disclosure, the pixel defining layer PDL may further include a black material. The pixel defining layer PDL may further include a black organic dye / pigment, such as carbon black or aniline black. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repellent organic material.

[0320] like Fig. 12AAs shown in , the display panel DP may include a first emission area PXA-R, a second emission area PXA-G, and a third emission area PXA-B, and a first non-emission area NPXA-R, a second non-emission area NPXA-G, and a third non-emission area NPXA-B adjacent to the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B. The non-emission areas NPXA-R, NPXA-G, and NPXA-B may surround the corresponding emission areas PXA-R, PXA-G, and PXA-B, respectively. In some embodiments, the first emission area PXA-R may be defined to correspond to a partial area of ​​the red anode electrode R_AE exposed by the first light emitting opening OP1_1. The second emission area PXA-G may be defined to correspond to a partial area of ​​the green anode electrode G_AE exposed by the second light emitting opening OP1_2. The third emission area PXA-B may be defined to correspond to a partial area of ​​the blue anode electrode B_AE exposed by the third light emitting opening OP1_3. The non-pixel area NPA may be defined between the first non-emission area NPXA-R, the second non-emission area NPXA-G, and the third non-emission area NPXA-B.

[0321] The emission layer may be disposed on the first electrode layer. The emission layer may include a red emission layer R_EL, a green emission layer G_EL, and a blue emission layer B_EL. The red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may be disposed in regions corresponding to the first light-emitting opening OP1_1, the second light-emitting opening OP1_2, and the third light-emitting opening OP1_3, respectively. The red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may be formed to be separated from each other. Each of the red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may include an organic material and / or an inorganic material. The red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may generate light of a preset color. For example, the red emission layer R_EL may generate red light, the green emission layer G_EL may generate green light, and the blue emission layer B_EL may generate blue light.

[0322] Although the patterned red emission layer R_EL, green emission layer G_EL, and blue emission layer B_EL are shown in this embodiment, one emission layer may be commonly disposed in the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B. In this case, the emission layer may generate white light or blue light. In addition, the emission layer may have a multilayer structure called a series connection.

[0323] Each of the red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may include a low molecular weight organic material or a high molecular weight organic material as a light-emitting material. In some examples, each of the red emission layer R_EL, the green emission layer G_EL, and the blue emission layer B_EL may include a quantum dot material as a light-emitting material. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, IV-VI group compounds, IV group elements, IV group compounds, and / or combinations thereof.

[0324] The second electrode layer may be arranged on the red emission layer R_EL, the green emission layer G_EL and the blue emission layer B_EL. The second electrode layer may include a red cathode electrode R_CE, a green cathode electrode G_CE and a blue cathode electrode B_CE. The red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may be electrically connected to each other. In some embodiments of the present disclosure, the red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may have an integral shape (for example, the red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may be formed integrally). In this case, the red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may be commonly arranged in the first emission region PXA-R, the second emission region PXA-G, the third emission region PXA-B, the first non-emission region NPXA-R, the second non-emission region NPXA-G and the third non-emission region NPXA-B and the non-pixel region NPA.

[0325] The element layer DP_ED may further include a light receiving element OPD. The light receiving element OPD may be a photodiode. The pixel defining layer PDL may further include a light receiving opening OP2 disposed to correspond to the light receiving element OPD.

[0326] The light receiving element OPD may include a sensor anode electrode O_AE, a photoelectric conversion layer O_RL, and a sensor cathode electrode O_CE. The sensor anode electrode O_AE may be disposed in the same layer as the first electrode layer (e.g., in or on the same layer). That is, the sensor anode electrode O_AE may be disposed on the circuit layer DP_CL and may be formed simultaneously by the same process as the red anode electrode R_AE, the green anode electrode G_AE, and the blue anode electrode B_AE.

[0327] The light receiving opening OP2 of the pixel defining layer PDL may expose at least a portion of the sensor anode electrode O_AE. The photoelectric conversion layer O_RL may be disposed on the sensor anode electrode O_AE exposed by the light receiving opening OP2. The photoelectric conversion layer O_RL may include an organic light sensing material. The sensor cathode electrode O_CE may be disposed on the photoelectric conversion layer O_RL. The sensor cathode electrode O_CE may be formed simultaneously with the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE by the same process. In some embodiments of the present disclosure, the sensor cathode electrode O_CE may be formed integrally with the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE to form a common cathode electrode.

[0328] The encapsulation layer TFE may be disposed on the element layer DP_ED. The encapsulation layer TFE may include at least an inorganic layer and / or an organic layer. In some embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In some embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked with each other.

[0329] The inorganic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from moisture / oxygen, and the organic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0330] The display device DD may include an input sensing layer ISL disposed on the display panel DP and a color filter layer CFL disposed on the input sensing layer ISL.

[0331] The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. The input sensing layer ISL may include a first conductive layer ICL1, an insulating layer IL, a second conductive layer ICL2, and a protective layer PL. The first conductive layer ICL1 may be disposed on the encapsulation layer TFE. Fig. 12A and Fig. 12BA structure in which the first conductive layer ICL1 is directly disposed on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto. The input sensing layer ISL may further include a base insulating layer disposed between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the base insulating layer, and the first conductive layer ICL1 may be disposed on the base insulating layer. In some embodiments of the present disclosure, the base insulating layer may include an inorganic insulating material.

[0332] The insulating layer IL may cover the first conductive layer ICL1. The second conductive layer ICL2 may be disposed on the insulating layer IL. Fig. 12A and Fig. 12B A structure in which the input sensing layer ISL includes the first conductive layer ICL1 and the second conductive layer ICL2 is shown, but the present disclosure is not limited thereto. For example, the input sensing layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0333] The protective layer PL may be disposed on the second conductive layer ICL2. The protective layer PL may include an organic insulating material. The protective layer PL may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from moisture / oxygen and may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from foreign matter such as dust particles.

[0334] The color filter layer CFL may be disposed on the input sensing layer ISL. The color filter layer CFL may be disposed directly on the protection layer PL. The color filter layer CFL may include a first color filter CF_R, a second color filter CF_G, and a third color filter CF_B. The first color filter CF_R has a first color, the second color filter CF_G has a second color, and the third color filter CF_B has a third color. In some embodiments of the present disclosure, the first color may be red, the second color may be green, and the third color may be blue.

[0335] The color filter layer CFL may further include a dummy color filter DCF. In some embodiments of the present disclosure, when the area in which the photoelectric conversion layer O_RL is disposed is defined as a sensing area SA and the area around the sensing area SA is defined as a non-sensing area NSA, the dummy color filter DCF may be disposed to correspond to the sensing area SA. The dummy color filter DCF may overlap the sensing area SA and the non-sensing area NSA. In some embodiments of the present disclosure, the dummy color filter DCF may have the same color as one of the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. In some embodiments of the present disclosure, the dummy color filter DCF may have the same green color as the second color filter CF_G.

[0336] The color filter layer CFL may further include a black matrix BM. The black matrix BM may be arranged to correspond to the non-pixel area NPA. The black matrix BM may be arranged to overlap with the first conductive layer ICL1 and the second conductive layer ICL2 in the non-pixel area NPA. In some embodiments of the present disclosure, the black matrix BM may overlap with the non-pixel area NPA and the first non-emission area NPXA-R, the second non-emission area NPXA-G, and the third non-emission area NPXA-B. The black matrix BM may not overlap with the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B.

[0337] The color filter layer CFL may further include an outer coating layer OCL. The outer coating layer OCL may include an organic insulating material. The outer coating layer OCL may have a thickness sufficient to remove the steps between the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. Without any specific restrictions, the outer coating layer OCL may include any material having a preset thickness and capable of flattening the upper surface of the color filter layer CFL. For example, the outer coating layer OCL may include an acrylate organic material.

[0338] Reference Fig. 12B According to some embodiments of the present disclosure, when the display device DD (for example, referring to Figure 1 ) when the red light emitting element ED_R, the green light emitting element ED_G and the blue light emitting element ED_B can output light. The red light emitting element ED_R outputs red light in the red band, the green light emitting element ED_G outputs green light in the green band, and the blue light emitting element ED_B outputs blue light in the blue band.

[0339] In some embodiments of the present disclosure, the light receiving element OPD may receive light from a specific light emitting element (e.g., green light emitting element ED_G) among the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B. That is, the second light Lg1 may be output from the green light emitting element ED_G, and the light receiving element OPD may receive the second reflected light Lg2 obtained by reflecting the second light Lg1 by the fingerprint of the user. The second light Lg1 and the second reflected light Lg2 may be green light in a green band. A dummy color filter DCF may be disposed above the light receiving element OPD. The dummy color filter DCF may be green. Therefore, the second reflected light Lg2 may pass through the dummy color filter DCF and may be incident on the light receiving element OPD.

[0340] The red light and blue light output from the red light emitting element ED_R and the blue light emitting element ED_B may also be reflected by the user's hand US_F. For example, when the light obtained by reflecting the red light Lr1 output from the red light emitting element ED_R by the user's hand US_F is defined as the first reflected light Lr2, the first reflected light Lr2 may not be able to pass through the dummy color filter DCF and will be absorbed by the dummy color filter DCF. Therefore, the first reflected light Lr2 cannot pass through the dummy color filter DCF and cannot be emitted to the light receiving element OPD. Similarly, even if the blue light is reflected by the user's hand US_F, the blue light will be absorbed by the dummy color filter DCF. Therefore, only the second reflected light Lg2 can be provided to the light receiving element OPD.

[0341] As described above, the pixel connection electrode can be arranged in the same layer as the shielding electrode (for example, in or on the same layer), and the pixel anode electrode can be connected to the corresponding pixel driving circuit. Therefore, even if the resolution of the display device is increased, the arrangement freedom of the pixel anode electrode can be improved (for example, increased). In addition, even if at least one of the pixel connection electrodes may cross the readout wiring, the coupling capacitance can be reduced by adjusting the number of intermediate insulating layers and the gaps between the pixel connection electrodes and the readout wiring, thereby improving (for example, increasing) the sensing accuracy of the sensor.

[0342] When the design is performed so that the sum of the area of ​​the first sensor anode electrode and the area of ​​the dummy connecting electrode is substantially the same as the sum of the area of ​​the second sensor anode electrode and the area of ​​the sensor connecting electrode, the deviation of the detection signal of the corresponding row can be reduced, thereby improving the sensing uniformity and sensing accuracy.

[0343] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various suitable modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be clear to those of ordinary skill in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with a particular embodiment can be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the attached claims and their equivalents.

Claims

1. A display device, comprising: A substrate layer having a display area and a non-display area defined therein; A circuit layer, on the substrate layer; as well as an element layer, on the circuit layer, the element layer including a light emitting element and a light receiving element corresponding in position to the display area, Wherein, the circuit layer includes: A pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; A data line connected to the pixel driving circuit; a readout wiring connected to the sensor drive circuit; a shielding electrode overlapping the readout wiring and the sensor driving circuit in a plan view, the shielding electrode being above the data line; and A pixel connection electrode connects the pixel driving circuit to the light emitting element, and the pixel connection electrode and the shielding electrode are in the same layer.

2. The display device according to claim 1, wherein: Each of the light emitting elements comprises a pixel anode electrode, wherein the pixel anode electrode is connected to a corresponding pixel driving circuit among the pixel driving circuits through a corresponding pixel connecting electrode among the pixel connecting electrodes, and Wherein, the pixel anode electrode and the corresponding pixel connecting electrode are in different layers.

3. The display device according to claim 2, wherein: A first pixel anode electrode of a first light emitting element among the light emitting elements is on a first side of a first readout wiring adjacent to the first pixel anode electrode, and a first pixel driving circuit corresponding to the first light emitting element among the pixel driving circuits is on a second side of the first readout wiring, and Among them, a first pixel connection electrode among the pixel connection electrodes connects the first pixel anode electrode and the first pixel driving circuit, and overlaps with the first readout wiring in a plan view.

4. The display device according to claim 3, wherein: Two or more sequentially stacked insulating layers are between the first readout wiring and the first pixel connection electrode.

5. The display device according to claim 4, wherein: The first readout wiring comprises: a first sense line portion on the first intermediate insulating layer; and a second readout line portion on a second intermediate insulating layer covering the first readout line portion, the second readout line portion being connected to the first readout line portion, and The first pixel connection electrode is on a third intermediate insulating layer covering the second readout line portion and intersects the first readout line portion in a plan view.

6. The display device according to claim 3, wherein: The first readout wiring comprises: a first sense line portion on the first intermediate insulating layer; and a second readout line portion on a second intermediate insulating layer covering the first readout line portion, the second readout line portion being connected to the first readout line portion, and The first pixel connection electrode is on a third intermediate insulating layer covering the second readout line portion and intersects the second readout line portion in a plan view.

7. The display device according to claim 3, wherein: The light receiving element comprises: first light receiving elements in a first row; and The second light receiving element, in the second row, wherein each of the first light receiving elements overlaps with a corresponding first sensor driving circuit among the sensor driving circuits in a plan view, and Each of the second light receiving elements does not overlap with a corresponding second sensor driving circuit among the sensor driving circuits in a plan view.

8. The display device according to claim 7, wherein: Each of the second light receiving elements includes: a second sensor anode electrode; and a sensor connection electrode extending from the second sensor anode electrode and overlapping the second sensor drive circuit, and Wherein, the second sensor anode electrode and the sensor connecting electrode are in the same layer.

9. The display device according to claim 8, wherein: Each of the first light receiving elements includes: a first sensor anode electrode; and a dummy connecting electrode extending from the first sensor anode electrode, and The first sensor anode electrode overlaps with the first sensor driving circuit and is connected to the second sensor driving circuit.

10. The display device according to claim 9, wherein: The sum of the area of ​​the dummy connection electrode and the area of ​​the first sensor anode electrode is equal to the sum of the area of ​​the sensor connection electrode and the area of ​​the second sensor anode electrode.

11. The display device according to claim 9, wherein: The shielding electrode comprises: a plurality of main shielding electrodes overlapping the sensor driving circuit and the readout wiring in a plan view; a first branch shielding electrode extending from at least one of the main shielding electrodes and partially overlapping the dummy connecting electrode in a plan view; and A second branch shielding electrode extends from at least one of the main shielding electrodes and partially overlaps the sensor connecting electrode in a plan view.

12. The display device according to claim 11, wherein: The main shielding electrodes are spaced apart from each other in an extending direction of each of the readout wirings, and The first pixel connection electrode passes through the separation space between the main shielding electrodes in a direction intersecting the extending direction.

13. The display device according to claim 11, wherein: The data line comprises: a first data line connected to a first group of pixel driving circuits among the pixel driving circuits; and a second data line spaced apart from the first data line in a first direction and connected to a second group of pixel driving circuits among the pixel driving circuits, and Wherein, the circuit layer further includes data connection lines, and the data connection lines are electrically connected to the second data lines in the display area respectively.

14. The display device according to claim 13, wherein: The data connection line comprises: a plurality of vertical data connection lines extending along the first data lines; and A plurality of horizontal data connection lines extending in the first direction, and The plurality of horizontal data connection lines electrically connect the plurality of vertical data connection lines to the second data lines.

15. The display device according to claim 14, wherein: The portion of the readout wiring is on the first intermediate insulating layer, wherein the first data line, the second data line and the vertical data connection line are on a second intermediate insulating layer, the second intermediate insulating layer covers the portion of the readout wiring and the first intermediate insulating layer, and The shielding electrode and the pixel connecting electrode are on a third intermediate insulating layer, and the third intermediate insulating layer covers the first data line, the second data line, the vertical data connecting line and the second intermediate insulating layer.

16. The display device according to claim 15, in, The pixel anode electrode is on a fourth intermediate insulating layer, and the fourth intermediate insulating layer covers the shielding electrode and the pixel connecting electrode.

17. The display device according to claim 1, wherein: The circuit layer also includes: A first driving voltage line connected to the pixel driving circuit; a second driving voltage line connected to the light emitting element and the light receiving element; and A reset voltage line is connected to the sensor drive circuit.

18. The display device according to claim 17, wherein: The shielding electrode is electrically connected to the reset voltage line.

19. The display device according to claim 17, wherein: Each of the sensor driving circuits comprises: a reset transistor including a first electrode receiving a reset voltage, a second electrode connected to the first sensing node, and a third electrode receiving a reset control signal; an amplifying transistor including a first electrode receiving a sensor driving voltage, a second electrode connected to the first sensing node, and a third electrode connected to a second sensing node; and The output transistor includes a first electrode connected to the second sensing node, a second electrode connected to the corresponding readout wiring, and a third electrode receiving an output control signal.

20. The display device according to claim 19, wherein: The reset voltage line is electrically connected to the shield electrode and the first electrode of the reset transistor, and supplies the reset voltage to the shield electrode and the first electrode of the reset transistor.

21. A display device, comprising: A substrate layer having a display area and a non-display area defined therein; A circuit layer, on the substrate layer; as well as an element layer, on the circuit layer, the element layer including a light emitting element and a light receiving element corresponding to the display area, wherein the light receiving elements include first light receiving elements in a first row and second light receiving elements in a second row, Wherein, the circuit layer includes: Pixel driving circuits, connected to the light emitting elements respectively; a first sensor driving circuit overlapping the first light receiving element when viewed from above in a plane, the first sensor driving circuit being connected to the first light receiving element; and a second sensor driving circuit connected to the second light receiving element, the second sensor driving circuit being configured not to overlap the second light receiving element in a plan view, wherein the second light receiving element includes a sensor connection electrode extending from the second sensor anode electrode toward the second sensor drive circuit and connecting the second sensor anode electrode and the second sensor drive circuit, and The first light receiving element includes a dummy connection electrode extending from the first sensor anode electrode in a direction opposite to the sensor connection electrode.

22. The display device according to claim 21, wherein: The circuit layer also includes: a readout wiring connected to the first sensor driving circuit and the second sensor driving circuit; and a shield electrode overlapping the readout wiring in a plan view, and Wherein, the sensor connecting electrode and the dummy connecting electrode are on an intermediate insulating layer covering the shielding electrode.

23. The display device according to claim 22, wherein: The shielding electrode comprises: a plurality of main shielding electrodes overlapping the first sensor driving circuit and the second sensor driving circuit in a plan view; a first branch shielding electrode extending from one of the main shielding electrodes and partially overlapping the dummy connection electrode in a plan view; and A second branch shielding electrode extends from one of the main shielding electrodes and partially overlaps the sensor connecting electrode in a plan view.

24. The display device according to claim 22, wherein: The circuit layer further includes pixel connection electrodes, which connect the pixel driving circuits to the light emitting elements respectively, and Wherein, the pixel connecting electrode and the shielding electrode are in the same layer.

25. The display device according to claim 24, wherein: The circuit layer also includes: A first driving voltage line connected to the pixel driving circuit; a second driving voltage line connected to the light emitting element and the light receiving element; and A reset voltage line is connected to the first sensor driving circuit and the second sensor driving circuit.

26. The display device according to claim 25, wherein: The shielding electrode is electrically connected to the reset voltage line.

27. The display device according to claim 21, wherein: The sum of the area of ​​the dummy connection electrode and the area of ​​the first sensor anode electrode is equal to the sum of the area of ​​the sensor connection electrode and the area of ​​the second sensor anode electrode.

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