Scalable power transmission system

Abstract

A power transfer system included in a computer system that uses a plurality of power converter circuits to generate respective voltage levels on a plurality of power supply nodes. The power transfer system includes a buck power converter circuit that generates voltage levels for use by a host power converter circuit and a follower power converter circuit. The host power converter circuit generates an external demand current that is shared by the plurality of follower power converter circuits to regulate voltage levels on the plurality of power nodes. By adjusting the number of follower power converter circuits, the power transfer system can be scaled to different platforms of the computer system.

Description

Background Art Technical Field

[0001] The present disclosure relates to power management in computer systems, and more particularly to voltage regulator circuit operation.

[0002] Related technical description

[0003] Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include a processor, or a processor core configured to execute software or program instructions. In addition, circuit blocks may include memory circuits, mixed signal or analog circuits, etc.

[0004] In some computer systems, circuit blocks may be designed to operate using different power supply voltage levels. For example, in some computer systems, a power management integrated circuit (also referred to as a "power management unit") may generate and monitor various power supply signals.

[0005] The power management circuit generally includes one or more power converter circuits configured to generate a regulator voltage level on a corresponding power signal line using the voltage level of an input power signal. Such converter circuits may employ a plurality of reactive circuit elements, such as inductors, capacitors, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of an embodiment of a power delivery system for a computer system is illustrated.

[0007] Figure 2 A block diagram of another embodiment of a power transmission system is illustrated.

[0008] Figure 3 Block diagrams illustrating various embodiments of power transmission systems.

[0009] Figure 4 A block diagram of an implementation of a host power converter circuit is illustrated.

[0010] Figure 5 A block diagram of an implementation of a follower power converter circuit is illustrated.

[0011] Figure 6 A block diagram of an implementation of a phase circuit included in a power converter circuit is illustrated.

[0012] Figure 7 A block diagram of a control circuit for a phase circuit included in a power converter circuit is illustrated.

[0013] Figure 8 A block diagram of an embodiment of a power delivery system for driving multiple regulated power supply nodes is illustrated.

[0014] Fig. 9 A diagram illustrating a possible power delivery system configuration utilizing a power converter circuit capable of driving multiple regulated supply nodes.

[0015] Fig.10 A flow chart depicting an embodiment of a method for operating a power converter system having an initial power converter stage is illustrated.

[0016] Fig.11 A flow chart depicting an embodiment of a method for operating a power converter system without an initial power converter stage is illustrated.

[0017] Fig.12 A block diagram of a computer system including a system on a chip and a plurality of power converter circuits is illustrated.

[0018] Fig.13 It is a block diagram of the system on chip.

[0019] Fig.14 is a block diagram of an embodiment of a computer system.

[0020] Fig.15 An example of a non-transitory computer-readable storage medium storing circuit design information is illustrated.

[0021] Although the embodiments described in the present disclosure may be subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and detailed description of the drawings are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0022] A computer system may include multiple circuit blocks configured to perform specific functions. Such circuit blocks may be fabricated on a common substrate and may employ different power supply voltage levels. A power management unit (commonly referred to as a "PMU") may include multiple power converter circuits or regulator circuits configured to generate regulated voltage levels for various power supply signals. Such regulator circuits may employ both passive circuit elements (e.g., inductors, capacitors, etc.) and active circuit elements (e.g., transistors, diodes, etc.).

[0023] Different types of voltage regulator circuits may be used based on the power requirements of the load circuit, available circuit area, etc. A common type of voltage regulator circuit is a buck converter circuit. Such a converter circuit includes a plurality of switches (also referred to as "power switches") and a switch node, which is coupled to a regulated power supply node via an inductor. One switch is coupled between the input power supply node and the switch node and is referred to as a "high-side switch". The other switch is coupled between the switch node and the ground power supply node and is referred to as a "low-side switch".

[0024] When the high-side switch is closed (known as the “on-time”), energy is applied to the inductor, causing the current through the inductor to increase. During this time, the inductor stores energy in the form of a magnetic field. When the high-side switch is open and the low-side switch is closed (known as the “off-time”), energy is no longer applied to the inductor and the voltage across the inductor reverses, which causes the inductor to act as a current source, where the energy stored in the inductor’s magnetic field supports the current flowing into the load. The process of closing and opening the high-side switch and the low-side switch is performed periodically to maintain the desired voltage level on the power supply node.

[0025] The power converter circuit can use different voltage regulation modes to determine the periodicity and duration of the on-time and off-time. As used herein, the voltage regulation mode refers to a specific method of detecting operating conditions to determine the frequency and duration of the on-time and off-time used by the power converter circuit. For example, the power converter can detect the maximum current flowing through its inductor to determine the end of the on-time period. This type of voltage regulation mode is called "peak current regulation mode". Alternatively, the power converter circuit can detect the minimum current flowing through its inductor to determine the end of the off-time period. This type of voltage regulation mode is called "valley current regulation mode".

[0026] As the level of integration increases, the power converter circuit needs to supply an increased amount of current to the load circuit. For example, in some cases, the power converter circuit needs to be able to supply 100A or more to the load circuit. In some cases, in order to allow for the increase in load current, a higher voltage input power source (e.g., a battery) may be employed, further complicating the design of the power converter circuit to allow for the higher input voltage.

[0027] Existing power converter circuit solutions are limited by thermal budget, packaging requirements, and input voltage. Therefore, the scalability of current power converter circuit designs is limited and inefficient for high current applications. In addition, the efficiency of the power converter circuit must be maintained at smaller loads, and the design of the power converter circuit must be flexible to allow for changes in current requirements at later stages of the design process, as well as to support different numbers of regulated power supply nodes on different platforms (such as tablet computers, laptop computers, etc.).

[0028] The technology described in the present disclosure allows the following power transmission system, which adopts a host power converter circuit that generates a shared demand current used by multiple follower power converter circuits. As computer system design develops, the shared demand current makes it easy to add or subtract follower power converter circuits to adapt to changes in load current. The use of such host power converter circuits and follower power converter circuits allows a single set of power converter circuits to be used to support multiple power transmission platforms. In addition, an initial step-down power converter circuit can be used to adapt to higher input voltage sources in certain power transmission platforms.

[0029] Go to Figure 1 , depicts a block diagram of a power converter system. As shown, the power transmission system 100 includes a power converter circuit 101, a host power converter circuit 102, a follower power converter circuit 103, and inductors 104-106. Note that the power converter circuit 101, the host power converter circuit 102, and the follower power converter circuit 103 may be located on a common integrated circuit. In some cases, inductors 104-106 may also be located on a common integrated circuit. Alternatively, inductors 104-106 may be located on different integrated circuits or mounted on a circuit board or other substrate where the common integrated circuit is located. In some embodiments, one or more of the inductors 104-106 may be mounted on a common integrated circuit, for example as a small chip.

[0030] The power converter circuit 101 is coupled to the converter power node 111 via the inductor 106 and is configured to generate a specific voltage level on the converter power node 111 using the voltage level of the input power node 107. In various embodiments, the specific voltage level is less than the voltage level of the input power node 107. The power converter circuit 101 may be referred to as a "step-down power converter" because it generates a lower voltage for other power converter circuits (such as the host power converter circuit 102 and the follower power converter circuit 103) that cannot adopt the higher voltage level of the input power node 107.

[0031] In various embodiments, the power converter circuit 101 can be implemented as a buck converter circuit with peak current regulation or valley current regulation. Although the power converter circuit 101 is depicted as being coupled to the converter power node 111 via a single inductor, in other embodiments, the power converter circuit 101 can include multiple phase circuits, each of which is coupled to the converter power node 111 via a corresponding inductor.

[0032] Host power converter circuit 102 is coupled to regulated power supply node 108 via inductor 104. In various embodiments, host power converter circuit 102 is configured to generate internal demand current 117 and external demand current 115 using (e.g., based on) the voltage level of regulated power supply node 108 and reference voltage 118. In some embodiments, host power converter circuit 102 is further configured to generate enable signal 116 using the voltage level of regulated power supply node 108 and reference voltage 118. Host power converter circuit 102 is further configured to supply current 112 to regulated power supply node 108 using the voltage level of converter power supply node 111 based on internal demand current 117.

[0033] The follower power converter circuit 103 is coupled to a regulated power supply node 108 via an inductor 105. In various embodiments, the follower power converter circuit 103 is configured to supply a current 113 to the regulated power supply node 108 using a voltage level of a converter power supply node 111 based on an external demand current 115. As described below, the follower power converter circuit 103 is also configured to supply the current 113 to the regulated power supply node 108 based on an enable signal 116, which can be used to activate or deactivate the follower power converter circuit 103 or individual phase circuits included in the follower power converter circuit 103.

[0034] Although in Figure 1 Only a single follower power converter circuit is depicted in the figure, but in other embodiments, multiple follower power converter circuits may be used. In this case, each of the multiple follower power converter circuits shares an external demand current 115, which provides the multiple follower power converter circuits with a desired amount of output current per phase. Sharing the external demand current 115 in this manner allows the power transmission system to be easily scaled by adding or subtracting follower power converter circuits to be able to supply a desired amount of current to a specific regulated power supply node. In some embodiments, a follower power converter circuit (e.g., follower power converter circuit 103) is characterized as a follower power converter circuit because it is configured to receive one or more enable signals (e.g., enable signal 116) and / or receive an external demand current (e.g., external demand current 115) from a host power converter circuit (e.g., host power converter circuit 102).

[0035] In some cases, a follower power converter circuit capable of using a higher input voltage may be included in a power transmission system. Figure 2A block diagram of another embodiment of a power transmission system is depicted in As shown, power transmission system 200 includes power converter circuit 201, host power converter circuit 202, follower power converter circuits 203 and 204, and inductors 205-208.

[0036] The power converter circuit 201 is coupled to the converter power node 216 via the inductor 208 and is configured to generate a specific voltage level on the converter power node 216 using the voltage level of the input power node 107. In various embodiments, the specific voltage level is less than the voltage level of the input power node 107. In some embodiments, the power converter circuit 201 may correspond to Figure 1 The power converter circuit 101 depicted in the embodiment of the present invention.

[0037] Host power converter circuit 202 is coupled to regulated power supply node 108 via inductor 205. In various embodiments, host power converter circuit 202 is configured to use the voltage level of regulated power supply node 108 and a reference voltage (such as described above with respect to Figure 1 The reference voltage 118 described above) is used to generate an internal demand current (such as the reference voltage 118 described above). Figure 1 In some embodiments, host power converter circuit 202 is further configured to generate enable signal 116 using the voltage level of regulated power supply node 108 and the reference voltage. Host power converter circuit 202 is further configured to supply current 212 to regulated power supply node 108 using the voltage level of converter power supply node 216 based on the internal demand current. In various embodiments, host power converter circuit 202 may correspond to Figure 1 The host power converter circuit 102 is depicted in the implementation scheme of FIG.

[0038] The follower power converter circuit 203 is coupled to the regulated power supply node 108 via the inductor 206. In various embodiments, the follower power converter circuit 203 is configured to supply a current 213 to the regulated power supply node 108 using a voltage level of a converter power supply node 216 based at least in part on the external demand current 115. In some embodiments, the follower power converter circuit 203 may correspond to Figure 1 The follower power converter circuit 103 is depicted in the implementation scheme of FIG.

[0039] The follower power converter circuit 204 is coupled to the regulated power supply node 108 via the inductor 207. In various embodiments, the follower power converter circuit 204 is configured to supply a current 214 to the regulated power supply node 108 using the voltage level of the input power supply node 107 based on the external demand current 115. In some embodiments, the follower power converter circuit 204 is also configured to supply the current 214 to the regulated power supply node 108 based on an enable signal 116, which can be used to activate or deactivate the follower power converter circuit 204 or individual phase circuits included in the follower power converter circuit 204.

[0040] Although in Figure 2 Only two follower power converter circuits are depicted, but in other embodiments, more than two follower power converter circuits may be used. The additional power converter circuits may use the voltage level of the input power node 107 or the converter power node 216 to supply a corresponding current to the regulated power node 108.

[0041] In some cases, in a computer system, the host power converter circuit and the follower power converter circuit may have an input power supply of suitable voltage. In this case, a buck power converter circuit is not required to generate a lower voltage level for the host power converter circuit and the follower power converter circuit. Figure 3 , depicts a block diagram of an embodiment of a power transmission system without a buck power converter circuit. As shown, the power transmission system 300 includes a host power converter circuit 301, follower power converter circuits 302 and 303, and inductors 304-306.

[0042] The host power converter circuit 301 is coupled to the regulated power supply node 108 via an inductor 304. In various embodiments, the host power converter circuit 301 is configured to generate the internal demand current 117 and the external demand current 115 using the voltage level of the regulated power supply node 108 and the reference voltage 118. In some embodiments, the host power converter circuit 301 is also configured to generate the enable signal 116 using the voltage level of the regulated power supply node 108 and the reference voltage 118. The host power converter circuit 301 is also configured to supply a current 310 to the regulated power supply node 108 based on the internal demand current 117 using the voltage level of the input power supply node 313. Note that in various embodiments, the voltage level of the input power supply node 313 is less than the voltage level of the external demand current 115. Figure 1 and Figure 2 The voltage level of the input power supply node 107 is shown.

[0043] The follower power converter circuit 302 is coupled to the regulated power supply node 108 via an inductor 305. In various embodiments, the follower power converter circuit 302 is configured to supply a current 311 to the regulated power supply node 108 using a voltage level of an input power supply node 313 based on an external demand current 115. As described below, the follower power converter circuit 302 is also configured to supply the current 311 to the regulated power supply node 108 based on an enable signal 116, which can be used to activate or deactivate the follower power converter circuit 302 or individual phase circuits included in the follower power converter circuit 302.

[0044] The follower power converter circuit 303 is coupled to the regulated power supply node 108 via an inductor 306. In various embodiments, the follower power converter circuit 303 is configured to supply a current 312 to the regulated power supply node 108 using a voltage level of an input power supply node 313 based on an external demand current 115. As described below, the follower power converter circuit 303 is also configured to supply the current 312 to the regulated power supply node 108 based on an enable signal 116, which can be used to activate or deactivate the follower power converter circuit 303 or individual phase circuits included in the follower power converter circuit 303.

[0045] Although in Figure 2 In the embodiment of only depicting two follower power converter circuits, but in other embodiments, any suitable number of follower power converter circuits can be used. In some cases, the number of follower power converter circuits can be based on the maximum load current to be drawn from the regulated power supply node 108.

[0046] Go to Figure 4 , depicts a block diagram of a host power converter circuit. As shown, host power converter circuit 400 includes control circuit 401, phase circuits 402A and 402B, feedback circuit 403, and multiplexing circuit 408. Note that in various embodiments, host power converter circuit 400 may correspond to host power converter circuit 102, host power converter circuit 202, or host power converter circuit 301.

[0047] Both phase circuits 402A and 402B are coupled to a power supply node 405. In various embodiments, power supply node 405 may correspond to input power supply node 107, converter power supply node 111, converter power supply node 216, or input power supply node 313. As described below, phase circuits 402A and 402B may include switching devices configured to couple switch nodes 404A and 404B to power supply node 405 to supply currents 406A and 406B, respectively. Note that in various embodiments, switch nodes 404A and 404B may correspond to any of switch nodes 109, 110, 209-211, or 307-309. Although in Figure 4 Only two phase circuits are depicted in the embodiment of FIG. , but in other embodiments, any suitable number of phase circuits may be used.

[0048] Phase circuit 402A is configured to supply current 406A to switch node 404A based on selected demand current 411 and a particular enable signal in enable signals 116 received, for example, from control circuit 401. In a similar manner, phase circuit 402B is configured to supply current 406B to switch node 404B based on selected demand current 411 and a different enable signal in enable signals 116. In various embodiments, phase circuits 402A and 402B function when their corresponding enable signals 116 are in an active state. In the event that one or both of the corresponding enable signals 116 are in an inactive state, phase circuits 402A and 402B remain in an inactive or standby state.

[0049] The control circuit 401 is configured to generate the internal demand current 117 and the external demand current 115 based on the voltage level of the regulated power supply node 108. In various embodiments, to generate the internal demand current 117 and the external demand current 115, the control circuit 401 is further configured to perform a comparison of the feedback signal 407 with the reference voltage 118; and use the result of the comparison to generate the internal demand current 117 and the external demand current 115. In other embodiments, the control circuit 401 is further configured to generate the enable signal 116 using the result of the comparison. As described below, the control circuit 401 can be implemented using a combination of analog circuits and digital circuits.

[0050] Feedback circuit 403 is configured to generate feedback signal 407 based on the voltage level of regulated power supply node 108. In various embodiments, the voltage level of feedback signal 407 can be less than the voltage level of regulated power supply node 108. By scaling the voltage level of regulated power supply node 108 before comparing it to reference voltage 118, regulated power supply node 108 can be adjusted to a voltage level higher than reference voltage 118. In various embodiments, feedback circuit 403 can be implemented using a resistive voltage divider circuit or any other suitable circuit configured to scale an input voltage level to generate an output voltage level.

[0051] Multiplexing circuit 408 is configured to generate selected demand current 411 by selecting one of alternative demand current 409 or internal demand current 117. In various embodiments, multiplexing circuit 408 is also configured to select one of alternative demand current 409 or internal demand current 117 based on the value of control signal 410. By providing an alternative to internal demand current 117, host power converter circuit 400 can be used as a follower power converter circuit by changing the value of control signal 410. In some embodiments, multiplexing circuit 408 can be implemented using multiple pass gate circuits coupled together in a wired "OR" manner and controlled by control signal 410.

[0052] Go to Figure 5 , depicts a block diagram of a follower power converter circuit. As shown, the follower power converter circuit 500 includes a phase circuit 501 and a phase circuit 502. In various embodiments, the follower power converter circuit 500 may correspond to any of the follower power converter circuits 103, 203, 204, 302, and 303.

[0053] Both phase circuit 501 and phase circuit 502 are coupled to power supply node 503. In some embodiments, as described above, power supply node 503 may correspond to an output node of a power converter circuit or buck converter (e.g., converter power supply node 216 of power converter circuit 201) or an input power node of a system (such as described above with respect to FIG. Figure 3313 as described above). As described below, phase circuits 501 and 502 may include a switching device configured to couple switch nodes 504 and 505 to power node 503 so as to supply currents 509 and 510. Phase circuit 501 is configured to supply current 509 to switch node 504 based on external demand current 506 and enable signal 507. In a similar manner, phase circuit 502 is configured to supply current 510 to switch node 505 based on external demand current 506 and enable signal 508. In various embodiments, phase circuits 501 and 502 function when enable signals 507 and 508 are in an active state. In the event that one or both of enable signals 507 and 508 are in an inactive state, the corresponding phase circuit in phase circuits 501 and 502 remains in an inactive or standby state.

[0054] In various embodiments, phase circuits 501 and 502 may operate in a peak current regulation mode or a valley current regulation mode. In the peak current regulation mode, when the values ​​of currents 509 and 510 match the value of external demand current 506, phase circuits 501 and 502 stop supplying these currents. Alternatively, in the valley current regulation mode, phase circuits 501 and 502 may stop their respective off times based on a comparison of external demand current 506 with currents 509 and 510. For example, in some embodiments, phase circuits 501 and 502 may stop their respective off times in response to determining that currents 509 and 510 are less than external demand current 506.

[0055] Note that although Figure 5 In the embodiment of the present invention, two phase circuits are depicted, but in other embodiments, any suitable number of phase circuits may be employed. In some cases, two of the phase circuits may be coupled to a common regulated power supply node via a set of inductors (referred to as "coupling inductors") that share a common core.

[0056] Go to Figure 6 , depicts a block diagram of an embodiment of a phase circuit. As shown, phase circuit 600 includes a drive circuit 601, a device 608, a device 609, a latch circuit 602, a comparator circuit 606, a slope compensation circuit 605, and a current sensor circuit 603. In various embodiments, phase circuit 600 may correspond to any of phase circuits 402A-B, 501, or 502.

[0057] Device 608 is coupled between input power supply node 610 and switch node 607, and is controlled by control signal 620. In a similar manner, device 609 is coupled between switch node 607 and ground power supply node 611, and is controlled by control signal 621. In various embodiments, switch node 607 may be further coupled to an inductor, which in turn is coupled to a regulated power supply node.

[0058] In response to activation of control signal 620, device 608 is configured to couple input power node 610 to switch node 607, thereby allowing current to flow into the inductor, thereby magnetizing the inductor. In response to activation of control signal 621, device 609 is configured to couple switch node 607 to ground power node 611. When switch node 607 is coupled to ground power node 611, energy is no longer supplied to the inductor, thereby causing the magnetic field of the inductor to collapse. When the magnetic field collapses, the inductor acts as a current source, thereby providing current to the regulated power node.

[0059] In various embodiments, device 608 can be implemented as a p-channel metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a gate all around field effect transistor (GAAFET), or any other suitable transconductance device. In some embodiments, device 609 can be implemented as an n-channel MOSFET, a FinFET, a GAAFET, or any other suitable transconductance device.

[0060] The driver circuit 601 is configured to generate a control signal 620 and a control signal 621 using a control signal 617. In various embodiments, the driver circuit 601 can be configured to activate the control signal 620 and deactivate the control signal 621 in response to activation of the control signal 617. The driver circuit 601 can also be configured to deactivate the control signal 620 and activate the control signal 621 in response to deactivation of the control signal 617. In some embodiments, the driver circuit 601 can include any suitable combination of logic gates, sequential logic circuit elements, MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

[0061] The latch circuit 602 is configured to deactivate the control signal 617 using the reset signal 612, the set signal 618, and the enable signal 622. In some embodiments, the latch circuit 602 is configured to activate the control signal 617 in response to the activation of the set signal 618 when the enable signal 622 is in an active state, and to deactivate the control signal 617 in response to the activation of the reset signal 612 when the enable signal 622 is in an active state. In various embodiments, the reset signal 612 can be a clock signal or other suitable timing reference signal. The latch circuit 602 is configured to deactivate the control signal 617 in response to determining that the enable signal 622 is in an inactive state. In various embodiments, the latch circuit 602 can be implemented as a set-reset (SR) latch circuit including any suitable combination of logic gates.

[0062] The current sensor circuit 603 is configured to generate an inductor current 616. In various embodiments, the current sensor circuit 603 can measure the voltage drop across the device 609 and use the measured voltage drop to generate the inductor current 616. The current sensor circuit 603 can include any suitable combination of reference circuits and amplifier circuits.

[0063] Slope compensation circuit 605 is configured to modify inductor current 616. In various embodiments, slope compensation circuit 605 can be configured to combine a periodic current ramp with inductor current 616 in a process referred to as "slope compensation." Note that slope compensation is used to improve the stability of phase circuit 600 by increasing the frequency at which the regulator feedback loop can operate, thereby reducing the time for phase circuit 600 to recover from transients.

[0064] The comparator circuit 606 is configured to generate a set signal 618 using the demand current 614 and the inductor current 616. Note that the demand current 614 may correspond to the internal demand current 117, the external demand current 115, or any other suitable demand current. In some embodiments, the comparator circuit 606 may be configured to compare the demand current 614 to the inductor current 616 and activate the set signal 618 in response to determining that the demand current 614 is less than the inductor current 616. In various embodiments, the comparator circuit 606 may be implemented using a differential amplifier circuit, a Schmitt trigger circuit, or any other suitable comparator circuit.

[0065] Go to Figure 7 , depicts a block diagram of an embodiment of the control circuit 401. As shown, the control circuit 401 includes an error amplifier 701, a management circuit 702, a current comparison circuit 703, and a logic circuit 711.

[0066] The error amplifier 701 is configured to generate a demand current 705 using a reference voltage 704 and a feedback signal 403. In various embodiments, the value of the feedback signal 403 can be based on the voltage level of the regulated power supply node 108. In various embodiments, the error amplifier 701 can be configured to generate the demand current 705 such that the value of the demand current 705 is proportional to the difference between the reference voltage 704 and the feedback signal 403. In some embodiments, the error amplifier 701 can be implemented using a differential amplifier circuit or any other suitable comparator circuit.

[0067] Management circuit 702 is configured to use demand current 705 to generate external demand current 115 and internal demand current 117. Figure 7 In the embodiment of FIG. 7 , a single external demand current and a single internal demand current are depicted, but in other embodiments, the management circuit 702 can be configured to generate any suitable number of internal demand currents and external demand currents. In some embodiments, the management circuit 702 can be configured to scale the demand current 705 to generate the external demand current 115 and the internal demand current 117. In various embodiments, the management circuit 702 can include any suitable combination of current mirror circuits, amplifier circuits, and bias circuits.

[0068] The current comparison circuit 703 is configured to generate a comparison signal 709 using the sensed current 708 and the current threshold 707. Note that the sensed current 708 may correspond to the current flowing in the inductors 104 and 105. In various embodiments, the current comparison circuit 703 may be configured to compare a given sensed current in the sensed current 708 with a corresponding current threshold in the current threshold 707 to generate a particular comparison signal in the comparison signal 709.

[0069] In various embodiments, the current comparison circuit 703 can be implemented using a plurality of differential amplifier circuits or other comparator circuits with resistors coupled to their respective inputs to convert the current threshold 707 and the sensed current 708 into voltages for comparison. In some embodiments, additional circuitry (e.g., a Schmitt trigger circuit) can be used to convert the output of the differential amplifier circuit into a digital value of the comparison signal 709.

[0070] The logic circuit 711 is configured to generate the enable signal 116 using the comparison signal 709. In various embodiments, the logic circuit 711 may be configured to activate a given one of the enable signals in response to determining that the number of comparison signals 709 has exceeded a threshold. For example, if two enable signals are active and the comparison signals of the two phase circuits coupled to the active enable signals are active, the current limits of the two phase circuits have been reached and the logic circuit 711 may activate a third enable signal to activate the third phase circuit. By generating the enable signal 116 in this manner, an increase or decrease in the load current drawn from the regulated power supply node 108 may result in a corresponding increase or decrease in the number of active phase circuits. Adjusting the number of active phase circuits may ensure that a sufficient number of phase circuits are active to supply the required current and prevent an undesired drop in the voltage level of the regulated power supply node 108.

[0071] In various embodiments, logic circuit 711 may be implemented using any suitable combination of combinatorial logic circuits and sequential logic circuits. In some cases, logic circuit 711 may be implemented as a microcontroller or general purpose processor circuit configured to execute software or program instructions.

[0072] In some cases, a power converter circuit can be used to regulate voltage levels on multiple power supply nodes. To achieve this, the power converter circuit can use the corresponding voltage levels of the multiple power supply nodes to generate multiple internal demand currents. By using a multiplexing circuit, a single power converter circuit can be used in a variety of environments, each environment having a different number of regulated power supply nodes.

[0073] Figure 8 A block diagram of an embodiment of a power transmission system capable of supporting multiple regulated power supply nodes is depicted in FIG. As shown, the power transmission system 800 includes phase circuits 801A-801B, phase circuits 802A-802B, feedback circuits 803 and 804, comparator circuits 805 and 806, memory circuits 807, and multiplexing circuits 808. Note that in some embodiments, the functionality associated with selecting a particular demand current from a plurality of demand currents may be employed in a master power converter circuit or a follower power converter circuit as described above.

[0074] Phase circuits 801A and 801B are coupled to a regulated power supply node 811 via inductors 809A and 809B, respectively. In a similar manner, phase circuits 802A and 802B are coupled to a regulated power supply node 812 via inductors 810A and 810B, respectively. Phase circuits 801A and 801B are configured to supply a corresponding current to regulated power supply node 811 based on a selected current 819 and using a voltage level of a power supply node 813. Phase circuits 802A and 802B are configured to supply a corresponding current to regulated power supply node 812 based on a demand current 818 and using a voltage level of a power supply node 813. In various embodiments, phase circuits 801A, 801B, 802A, and 802B may correspond to the following: Figure 6 The phase circuit 600 depicted in FIG.

[0075] In the illustrated embodiment, because phase circuits 801A and 801B are coupled to a different regulated power supply node than phase circuits 802A and 802B, control bit 820 is selected to cause multiplexing circuit 808 to select demand current 817 as selected current 819. In other embodiments, if phase circuits 801A and 801B are coupled to the same regulated power supply node as phase circuits 802A and 802B, control bit 820 is selected to cause multiplexing circuit 808 to select demand current 818 as selected current 819.

[0076] Feedback circuit 803 is configured to generate feedback signal 815 using the voltage level of regulated power supply node 811. In a similar manner, feedback circuit 804 is configured to generate feedback signal 816 using the voltage level of regulated power supply node 812. In various embodiments, the voltage level of feedback signal 815 may be less than the voltage level of regulated power supply node 811, and the voltage level of feedback signal 816 may be less than the voltage level of regulated power supply node 812. In various embodiments, feedback circuit 803 and feedback circuit 804 may be implemented using a resistive voltage divider circuit or other suitable circuit.

[0077] The comparator circuit 805 is configured to generate the demand current 817 using the feedback signal 815 and the reference voltage 813. In some embodiments, to generate the demand current 817, the comparator circuit 805 is further configured to perform a comparison of the feedback signal 815 with the reference voltage 813 and generate the demand current 817 using the result of the comparison.

[0078] Comparator circuit 806 is configured to generate demand current 818 using feedback signal 816 and reference voltage 814. In some embodiments, to generate demand current 818, comparator circuit 806 is further configured to perform a comparison of feedback signal 816 with reference voltage 814 and generate demand current 818 using the result of the comparison.

[0079] In various embodiments, comparator circuit 805 and comparator circuit 806 may be implemented as operational transconductance amplifier (OTA) circuits or any other suitable comparator circuits. Figure 8 In the embodiment of FIG. 8 , two comparator circuits are depicted, but in other embodiments, any suitable number of comparator circuits may be employed. In some cases, the number of comparator circuits included in power transmission system 800 may be based on the number of regulated power supply nodes that the power transmission system is designed to support.

[0080] Multiplexing circuit 808 is configured to generate selected current 819 by selecting one of demand current 817 or demand current 818 based on control bit 820. In various embodiments, multiplexing circuit 808 can be implemented using a plurality of pass gates coupled together in a wired OR manner and controlled by control bit 820. Figure 8 In the embodiment of FIG. 8 , only a single multiplexing circuit is depicted, but in other embodiments, any suitable number of multiplexing circuits may be employed. In some cases, the number of multiplexing circuits included in the power transmission system 800 may correspond to the number of regulated power supply nodes that the power transmission system 800 can support.

[0081] Memory circuit 807 is configured to store control bits 820. In various implementations, memory circuit 807 may be implemented as a one-time programmable memory circuit, a read-only memory (ROM) circuit, or any other suitable type of non-volatile memory circuit.

[0082] As described above, the power transmission system can be designed to support multiple regulated power supply nodes. By setting control bits (e.g., control bits 820) to route demand current to each regulated power supply node when necessary, such a power transmission system can be deployed on different power transmission platforms, each with a different number of regulated power supply nodes.

[0083] Go to Fig. 9 , the diagram depicts how a power delivery system having a total of N phase circuits (where N is a positive integer) can be used to implement different power delivery platforms having different numbers of regulated power supply nodes.

[0084] Platform 904 utilizes only regulated power supply node 901. In this case, all N phase circuits included in the power transmission system are coupled to regulated power supply node 901 via corresponding inductors. As described above, control bit 820 is selected to route the demand current generated using the voltage level of regulated power supply node 901 to all phase circuits.

[0085] Platform 905 utilizes regulated power supply node 901 and regulated power supply node 902. As shown, A phase circuits are coupled to regulated power supply node 901, and B phase circuits are coupled to regulated power supply node 902. A phase circuit uses a demand current generated using the voltage level of regulated power supply node 901, while B phase circuits use a different demand current generated using the voltage level of regulated power supply node 902. Note that in some embodiments, the total N phase circuits may be evenly distributed between the A phase circuits and the B phase circuits. Alternatively, if the load current for regulated power supply node 901 is greater than the load current for regulated power supply node 902, more phase circuits may be included in the A phase circuits than in the B phase circuits. In some cases, based on the load currents of regulated power supply nodes 901 and 902, some of the total N phase circuits may remain unallocated to either of regulated power supply nodes 901 and 902.

[0086] Platform 906 uses regulated power supply nodes 901-903. D phase circuits are coupled to regulated power supply node 901, E phase circuits are coupled to regulated power supply node 902, and F phase circuits are coupled to regulated power supply node 903. The D phase circuits, the E phase circuits, and the F phase circuits use corresponding demand currents generated using corresponding voltage levels of regulated power supply nodes 901-903. The number of phase circuits included in each of the D phase circuits, the E phase circuits, and the F phase circuits may be based on the load currents of the regulated power supply nodes 901-903, respectively.

[0087] Notice, Fig. 9 The different power transmission platforms depicted in the diagram of are examples only. In other cases, different numbers of regulated power supply nodes and different numbers of phase circuits assigned to different active regulated power supply nodes are possible and contemplated.

[0088] In summary, various embodiments of a power delivery system for a computer system are disclosed. In general, an apparatus is contemplated in which a first power converter circuit can be configured to generate a specific voltage level on a converter power supply using a voltage level of an input power supply node. In various embodiments, the specific voltage level is less than the voltage level of the input power supply node.

[0089] A host power converter circuit coupled to a regulated power supply node via a first inductor can be configured to generate an internal demand current and an external demand current using a voltage level of the regulated power supply node and a reference voltage. The host power converter circuit can also be configured to supply a first current to the regulated power supply node using a voltage level of the converter power supply node based on the internal demand current.

[0090] A first follower power converter circuit coupled to the regulated power supply node via a second inductor can be configured to supply a second current to the regulated power supply node using a voltage level of the converter power supply node based on an external demand current. In other embodiments, a second follower power converter circuit coupled to the regulated power supply node via a third inductor can be configured to supply a third current to the regulated power supply node using a voltage level of the input power supply node based on an external demand current.

[0091] Go to Fig.10 , illustrates a flow chart depicting an embodiment of a method for operating a power transmission system having an initial power converter stage. The method begins in block 1001 and can be applied to a system including: Figure 1 Various power transmission systems are shown, including power transmission system 100.

[0092] The method includes generating, by a step-down power converter circuit, a specific voltage level on a converter power node using a voltage level of an input power node (block 1002). In various implementations, the specific voltage level is less than the voltage level of the input power node.

[0093] The method also includes generating, by a host power converter circuit, an internal demand current and an external demand current using a voltage level of a regulated power supply node and a reference voltage, wherein the host power converter circuit is coupled to the regulated power supply node via a first inductor (block 1003). In some embodiments, the method also includes generating, by the host power converter circuit, a plurality of enable signals using a voltage level of the regulated power supply node and a reference voltage.

[0094] In some embodiments, generating the external demand current and the internal demand current may include: generating a feedback signal by the host power converter circuit using the voltage level of the regulated power supply node; and performing a comparison of the feedback signal with a reference voltage by the host power converter circuit. The method may also include generating the external demand current and the internal demand current by the host power converter circuit using the result of the comparison.

[0095] The method also includes supplying, by a host power converter circuit and based on an internal demand current, a first current to a regulated power node using a voltage level of a converter power node (block 1004).

[0096] The method also includes supplying a second current to a regulated power node using a voltage level of a converter power node through a first follower power converter circuit and based on an external demand current, wherein the first follower power converter circuit is coupled to the regulated power node via a second inductor (box 1005).

[0097] In some embodiments, the first follower power converter circuit includes a first phase circuit and a second phase circuit, the first phase circuit is coupled to the regulated power supply node via a third inductor, and the second phase circuit is coupled to the regulated power supply node via a fourth inductor. In this case, the method may also include supplying a first portion of the second current to the regulated power supply node through the first phase circuit in response to determining that a first enable signal among the plurality of enable signals has been activated. The method may also include supplying a second portion of the second current to the regulated power supply node through the second phase circuit in response to determining that a second enable signal among the plurality of enable signals has been activated.

[0098] In other embodiments, supplying the first portion of the second current to the regulated supply node may include: performing a comparison of the external demand current and the sensed third inductor current; and using the result of the comparison to activate a driver control signal. The method may also include coupling a first terminal of the third inductor to the converter supply node in response to activation of the driver control signal, wherein a second terminal of the third inductor is coupled to the regulated supply node. The method may also include: deactivating the driver control signal in response to activation of the clock signal; and coupling a first terminal of the third inductor to the ground supply node in response to deactivation of the driver control signal.

[0099] In various embodiments, the method may further include supplying a third current to the regulated power supply node using the voltage level of the input power supply node through a second follower power converter circuit and based on the external demand current, wherein the second follower power converter circuit is coupled to the regulated power supply node via a third inductor. The method ends at block 1006.

[0100] Go to Fig.11 , illustrates a flow chart depicting an embodiment of a method for operating a power transmission system that does not include a buck power converter. The method starts in block 1101 and can be applied to a system including Figure 3 Various power transmission systems including power transmission system 300 are shown.

[0101] The method includes generating, by a host power converter circuit, an internal demand current and an external demand current using a voltage level of a regulated power supply node and a reference voltage (block 1102). In various implementations, the host power converter circuit is coupled to the regulated power supply node via a first inductor.

[0102] In some embodiments, generating the external demand current and the internal demand current may include: generating a feedback signal by the host power converter circuit using the voltage level of the regulated power supply node; and performing a comparison of the feedback signal with a reference voltage by the host power converter circuit. The method may also include generating the external demand current and the internal demand current by the host power converter circuit using the result of the comparison.

[0103] The method also includes supplying a first current to a regulated power node using a voltage level of an input power node, by a host power converter circuit and based on an internal demand current (block 1103).

[0104] The method also includes supplying a second current to the regulated power supply node using the voltage level of the input power supply node through the follower power converter circuit and based on the external demand current (block 1104). In various embodiments, the follower power converter circuit is coupled to the regulated power supply node via a second inductor. The method ends in block 1105.

[0105] Go to Fig.12 , depicts a block diagram of a computer system including a system on chip and multiple power converter circuits. As shown, computer system 1200 includes a system on chip 1201 (denoted as "SoC1201"), power converter circuits 1202, 1203A-B and 1204A-C, and inductors 1205, 1206A-B and 1207A-C.

[0106] The power converter circuit 1202 is coupled to the converter power node 1209 via the inductor 1205 and is configured to supply current to the converter power node 1209 using the voltage level of the input power node 1208. In various embodiments, the power converter circuit 1202 may correspond to Figure 1 The power converter circuit 101 depicted in the embodiment of the present invention.

[0107] Power converter circuit 1203A and power converter circuit 1203B are coupled to regulated power supply node 1210 via inductors 1206A and 1206B, respectively. In various embodiments, power converter circuit 1203A is configured to supply a particular current to regulated power supply node 1210 via inductor 1206A, and power converter circuit 1203B is configured to supply a different current to regulated power supply node 1210 via inductor 1206B. In some embodiments, power converter circuit 1203A may correspond to master power converter circuit 102, and power converter circuit 1203B may correspond to follower power converter circuit 103. Note that while two power converter circuits are depicted as supplying current to regulated power supply node 1210, in other embodiments, additional power converter circuits may be employed to supply current to regulated power supply node 1210.

[0108] Power converter circuits 1204A-1204C are coupled to regulated power supply node 1211 via inductors 1207A-1207C, respectively. In various embodiments, power converter circuit 1204A is configured to use the voltage level of input power supply node 1208 to supply a specific current to regulated power supply node 1211. Additionally, power converter circuits 1204B and 1204C are configured to use the voltage level of input power supply node 1208 to supply corresponding currents to regulated power supply node 1211. In some embodiments, power converter circuit 1204A may correspond to host power converter circuit 101, while power converter circuits 1204B and 1204C may correspond to follower power converter circuits 103. Note that while three power converter circuits are depicted as being capable of supplying current to regulated power supply node 1211, in other embodiments, any suitable number of power converter circuits may be employed to supply current to regulated power supply node 1211.

[0109] Although SoC 1201 is depicted as having only two regulated power supply nodes, in other embodiments, SoC 1201 may include any suitable number of regulated power supply nodes. In this case, additional power converter circuits may be employed to regulate the voltage levels on the regulated power supply nodes.

[0110] Fig.13 1300. A block diagram of a system on chip (SoC) is illustrated in FIG. 1300. In the illustrated embodiment, SoC 1300 includes processor circuit 1301, memory circuit 1302, analog / mixed signal circuit 1303, and input / output circuit 1304. Processor circuit 1301 and memory circuit 1302 are coupled to power supply node 1305, while analog / mixed signal circuit 103 and input / output circuit 1304 are coupled to power supply node 1306. The voltage levels on power supply nodes 1305 and 1306 can be generated by different arrangements of power converter circuits, such as the arrangements described above. In various embodiments, SoC 1300 can be configured for use in a desktop computer, a server, or in a mobile computing application, such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0111] In various embodiments, processor circuit 1301 may represent a general purpose processor that performs computing operations. For example, processor circuit 1301 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0112] In various embodiments, memory circuit 1302 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or nonvolatile memory. Fig.13 A single memory circuit is illustrated in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0113] The analog / mixed signal circuit 1303 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed signal circuit 1303 may be configured to perform power management tasks by including an on-chip power supply and voltage regulator.

[0114] Input / output circuitry 1304 may be configured to coordinate data transfers between SoC 1300 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., magnetic or optical media based storage devices, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 1304 may be configured to implement a universal serial bus (USB) protocol or IEEE 1394 The version of the protocol.

[0115] The input / output circuitry 1304 may also be configured to coordinate data transfers between the SoC 1300 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 1300 via a network. In one embodiment, the input / output circuitry 1304 may be configured to perform data processing required to implement an Ethernet (IEEE 802.3) networking standard (such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet), although it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 1304 may be configured to implement multiple discrete network interface ports.

[0116] Now go to Fig.14 , illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. The system or device 1400, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide range of fields. For example, the system or device 1400 may be used as part of the hardware of a system such as a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a cellular or mobile phone 1440, or a television 1450 (or a set-top box coupled to a television).

[0117] Similarly, the disclosed elements can be used in a wearable device 1460, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0118] The system or device 1400 may also be used in various other contexts. For example, the system or device 1400 may be used in the environment of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1470. Further, the system or device 1400 may be implemented in a wide range of dedicated everyday devices, including common devices 1480 in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1400 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1490.

[0119] Fig.14 The applications illustrated in the examples are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0120] Fig.15 15 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 1520 is configured to process design information 1515 stored on non-transitory computer-readable storage medium 1510 and manufacture integrated circuit 1530 based on design information 1515.

[0121] The non-transitory computer-readable storage medium 1510 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1510 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1510 may include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1510 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0122] Design information 1515 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 1515 may be used by semiconductor manufacturing system 1520 to manufacture at least a portion of integrated circuit 1530. The format of design information 1515 may be recognizable by at least one semiconductor manufacturing system, such as, for example, semiconductor manufacturing system 1520. In some embodiments, design information 1515 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1530 may also be included in design information 1515. Such cell libraries may include information indicating device or transistor level netlists, mask design data, characterization data, and the like of cells included in the cell library.

[0123] In various embodiments, integrated circuit 1530 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1515 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0124] Semiconductor manufacturing system 1520 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1520 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0125] In various embodiments, integrated circuit 1530 is configured to operate according to the circuit design specified by design information 1515, which may include performing any of the functions described herein. For example, integrated circuit 1530 may include any of the various elements shown or described herein. In addition, integrated circuit 1530 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0126] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0127] ***

[0128] This disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of this disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0129] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the disclosed form, even if only a single example is described for a particular feature. Therefore, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This patent application is intended to cover such alternatives, modifications, and equivalents, which will be obvious to those skilled in the art having the benefit of this disclosure.

[0130] The specific features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Therefore, the present disclosure is intended to include any feature or combination of such features disclosed herein (explicitly or implicitly), or any generalization thereof. Therefore, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the attached claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any suitable manner rather than just by the specific combinations listed in the attached claims.

[0131] For example, although the appended dependent claims are drafted so that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. It is also contemplated that a claim drafted in one legal type (e.g., apparatus) may inspire a corresponding claim of another legal type (e.g., method), where appropriate.

[0132] ***

[0133] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0134] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not exclude additional instances of that item.

[0135] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0136] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0137] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0138] The expressions "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0139] In this disclosure, various "labels" may precede a noun. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0140] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0141] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function.

[0142] The phrase "configured to" perform one or more tasks in the appended claims is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution, it will use the phrase "means for [performing the function]" to describe the claim element.

[0143] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence a determination. That is, a determination may be based only on specified factors or on specified factors as well as other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0144] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B performing A." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that performing A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

Claims

1. A device, comprising: a first power converter circuit configured to generate a particular voltage level at a converter power node based on a voltage level at an input power node; a host power converter circuit coupled to a regulated power supply node via a first inductor, wherein the host power converter circuit is configured to: generating an internal demand current and an external demand current using the voltage level of the regulated power supply node and a reference voltage; and supplying a first current to the regulated power node using a voltage level of the converter power node; and A first follower power converter circuit is coupled to the regulated power supply node via a second inductor, wherein the follower power converter circuit is configured to supply a second current to the regulated power supply node using the voltage level of the converter power supply node.

2. The device according to claim 1 further includes a second follower power converter circuit, which is coupled to the regulated power supply node via a third inductor, wherein the follower power converter circuit is configured to use the voltage level of the input power supply node to supply a third current to the regulated power supply node. 3 . The apparatus of claim 1 , wherein the host power converter circuit is further configured to generate one or more enable signals using the voltage level of the regulated power supply node and the reference voltage. 4 . The apparatus of claim 3 , wherein the first follower power converter circuit is further configured to supply the second current to the regulated power supply node based on the one or more enable signals.

5. An apparatus according to claim 3, wherein the first follower power converter circuit comprises a plurality of phase circuits, the plurality of phase circuits being coupled to the regulated power supply node via a corresponding plurality of inductors, wherein a given phase circuit among the plurality of phase circuits is configured to supply a portion of the second current to the regulated power supply node based on the external demand current and at least one enable signal among the one or more enable signals.

6. The apparatus of claim 1 , wherein the host power converter circuit is further configured to: generating a feedback signal using the voltage level of the regulated power supply node; performing a comparison of the feedback signal with the reference voltage; and The external demand current and the internal demand current are generated using a result of the comparison.

7. A method comprising: generating an internal demand current and an external demand current using a voltage level of a regulated power supply node and a reference voltage by a host power converter circuit, wherein the host power converter circuit is coupled to the regulated power supply node via a first inductor; supplying a first current to the regulated power node using a voltage level of an input power node through the host power converter circuit and based on the internal demand current; as well as The voltage level of the input power node is used to supply a second current to the regulated power node through a first follower power converter circuit and based on the external demand current, wherein the first follower power converter circuit is coupled to the regulated power node via a second inductor.

8. The method according to claim 7 further includes supplying a third current to the regulated power supply node using a voltage level of a converter power supply node through a second follower power converter circuit and based on the external demand current, wherein the second follower power converter circuit is coupled to the regulated power supply node via a third inductor, and wherein the voltage level of the converter power supply node is less than the voltage level of the input power supply node. 9 . The method of claim 8 , further comprising generating, by the host power converter circuit, a plurality of enable signals using the voltage level of the regulated power supply node and the reference voltage.

10. The method of claim 9, wherein the first follower power converter circuit comprises a first phase circuit and a second phase circuit, the first phase circuit being coupled to the regulated power supply node via a third inductor, the second phase circuit being coupled to the regulated power supply node via a fourth inductor, and the method further comprising: In response to determining that a first enable signal of the plurality of enable signals has been activated, supplying a first portion of the second current to the regulated power supply node through the first phase circuit; as well as In response to determining that a second enable signal of the plurality of enable signals has been activated, a second portion of the second current is supplied to the regulated power supply node through the second phase circuit.

11. The method of claim 10, wherein supplying the first portion of the second current to the regulated power supply node comprises: performing a comparison of the external demand current and the sensed third inductor current; using a result of the comparison to activate a driver control signal; as well as A first terminal of the third inductor is coupled to the converter supply node in response to activation of the driver control signal, wherein a second terminal of the third inductor is coupled to the regulated supply node.

12. The method according to claim 11, further comprising: deactivating the driver control signal in response to activation of a clock signal; as well as The first terminal of the third inductor is coupled to a ground supply node in response to deactivation of the driver control signal.

13. The method of claim 7, wherein generating the external demand current and the internal demand current comprises: generating a feedback signal using the voltage level of the regulated power supply node by the host power converter circuit; performing, by the host power converter circuit, a comparison of the feedback signal with the reference voltage; as well as The external demand current and the internal demand current are generated by the host power converter circuit using a result of the comparison.

14. A device, comprising: A first power converter circuit is coupled to a first regulated power supply node and a second regulated power supply node, wherein the power converter circuit comprises: one or more first phase circuits coupled to the first regulated power supply node through corresponding ones of the one or more first inductors; a plurality of second phase circuits coupled to the second regulated supply node through corresponding inductors of a second plurality of inductors; a first error amplifier circuit configured to generate a first demand current using a first voltage level of the first regulated power supply node and a first reference voltage; a second error amplifier circuit configured to generate a second demand current using a second voltage level of the second regulated power supply node and a second reference voltage; and a multiplexing circuit configured to select the first demand current or the second demand current using one or more control bits to generate a selected demand current; wherein the one or more first phase circuits are configured to supply a corresponding current of the one or more first currents to the first regulated power supply node based on the first demand current and a voltage level of the converter power supply node; and Wherein the plurality of second phase circuits are configured to supply corresponding currents of a plurality of second currents to the second regulated power supply node based on the selected demand current and the voltage level of the converter power supply node.

15. The apparatus of claim 14, further comprising a buck power converter circuit configured to generate a specific voltage level on the converter power node using a voltage level of an input power node, wherein the specific voltage level is less than the voltage level of the input power node.

16. The apparatus of claim 14, wherein the one or more first inductors comprise at least one pair of coupled inductors, wherein a particular phase circuit of the first plurality of phase circuits is coupled to the first regulated power supply node via a first inductor of the at least one pair of coupled inductors, and wherein a different phase circuit of the one or more first phase circuits is coupled to the first regulated power supply node via a second inductor of the at least one pair of coupled inductors.

17. The apparatus according to claim 16, further comprising: a first feedback circuit configured to generate a first feedback signal using the voltage level of the first regulated power supply node; and a second feedback circuit configured to generate a second feedback signal using the voltage level of the second regulated power supply node; wherein in order to generate the first demand current, the first error amplifier circuit is further configured to compare the first feedback signal with the first reference voltage; and In order to generate the second demand current, the second error amplifier circuit is further configured to compare the second feedback signal with the second reference voltage.

18. The apparatus of claim 14, wherein a specific phase circuit of the one or more first phase circuits is coupled to a specific inductor of the one or more first inductors, wherein the specific phase circuit is configured to: performing a comparison of the first demand current and a current sensed in the particular inductor; using the result of the comparison to activate a driver control signal; and A first terminal of the particular inductor is coupled to the converter supply node in response to activation of the driver control signal, wherein a second terminal of the particular inductor is coupled to the first regulated supply node.

19. The apparatus according to claim 18, wherein the specific phase circuit is further configured to: deactivating the driver control signal in response to activation of a clock signal; and The first terminal of the particular inductor is coupled to a ground supply node in response to deactivation of the driver control signal.

20. The apparatus of claim 14, further comprising a memory circuit configured to store the one or more bits.

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