Systems and methods for performing read operations

Abstract

The present disclosure provides a memory device including a memory array having memory cells, a page buffer coupled to the memory array by a bit line. The page buffer includes a latch and a control logic unit coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, based on the first read operation, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state from the memory cells; perform a second read operation on the first plurality of memory cells; select, based on the second read operation, a third plurality of memory cells from the first plurality of memory cells; perform a third read operation on the third plurality of memory cells; and determine a read development time based on the third read operation.

Description

Technical Field

[0001] This specification generally relates to the field of semiconductor technology, and more specifically, to systems and methods for performing read operations in NAND memory. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures, for example, can address the density and performance limitations of planar memory cells.

[0003] In NAND flash memory, many layers of memory cells can be stacked vertically, allowing for a significant increase in storage density per unit area. Vertically stacked memory cells can form memory strings, where channels of the memory cells are connected in each string. Each memory cell can be addressed via word lines and bit lines. Data (i.e., logical state) of memory cells sharing the same word line across an entire memory page can be read or programmed simultaneously. However, due to the drastic scaling, reliability may be a concern for NAND flash memory. Attached Figure Description

[0004] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present disclosure and, together with the specification, further serve to explain the principles of the disclosure and enable those skilled in the art to implement and use the disclosure.

[0005] Figure 1 and Figures 2A-2B A storage system having one or more memory chips is shown according to some embodiments.

[0006] Figure 3 A schematic diagram of a memory device according to some embodiments is shown.

[0007] Figure 4 A schematic diagram of a memory device according to some embodiments is shown.

[0008] Figure 5 A schematic diagram of an exemplary threshold voltage distribution of a memory device according to some embodiments is shown.

[0009] Figure 6A An exemplary schematic circuit diagram of a memory device according to some embodiments is shown.

[0010] Figure 6B An exemplary schematic diagram of a page buffer of a memory device according to some embodiments is shown.

[0011] Figure 7 An illustration according to some embodiments is shown. Figure 6B An exemplary signal waveform of the voltage level of the sensing node in the image.

[0012] Figure 8A An exemplary method 800 for performing a read operation on a memory device according to some embodiments is shown.

[0013] Figure 8B The following are illustrations based on some embodiments. Figure 8A An example of threshold voltage distribution and data structure during the process flow.

[0014] The features and advantages of this disclosure will become more apparent when viewed in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements. In the drawings, similar reference numerals generally indicate the same, functionally similar, and / or structurally similar elements.

[0015] Aspects of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0016] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be applied in a variety of other applications.

[0017] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0018] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0019] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer).

[0020] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0021] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the terms "approximately" or "roughly" indicate the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the terms "approximately" or "roughly" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0022] Currently, in memory devices, especially high-density memory devices, threshold voltage (Vt) distribution offset is a common and critical issue, as it can be affected by many factors, such as charge loss of programmed cells over time, noise, and long NAND service life. After Vt distribution offset, predefined read levels cannot track the Vt distribution, resulting in read failures. Systems and methods for performing read operations in NAND memory are needed to track the Vt distribution.

[0023] Figure 1 A block diagram of an electronic device S1 having a storage system 10 according to some embodiments is shown. In some embodiments, the electronic device S1 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system 10 (e.g., a NAND storage system) may include a memory controller 20 and one or more semiconductor memory devices 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory device 25 (hereinafter referred to as a "memory device") may be a NAND device (e.g., "flash memory", "NAND flash", or "NAND"). The storage system 10 may communicate with a host 15 via the memory controller 20, wherein the memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more storage channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory device 25 may be managed by the memory controller 20 via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n.

[0024] In some embodiments, host 15 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 15 may send data stored in storage system 10 and / or retrieve data from storage system 10.

[0025] In some embodiments, memory controller 20 can process I / O requests received from host 15, ensure data integrity and efficient storage, and manage memory device 25. To perform these tasks, memory controller 20 can run firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller units, CPUs) of memory controller 20. For example, memory controller 20 can run firmware 21 to map logical addresses (e.g., addresses associated with host data utilized by the host) to physical addresses (e.g., the actual location where data is stored) in memory device 25. Memory controller 20 also runs firmware 21 to manage defective blocks of memory in memory device 25, where firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. Memory controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) that can be used to store various metadata used by firmware 21. In some embodiments, memory controller 20 can also perform error recovery via error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors occurring within each memory device 25.

[0026] In some embodiments, the memory channel 30 may provide data and control communication between the memory controller 20 and each memory device 25 via a data bus. The memory controller 20 may select one of the memory devices 25 based on a chip enable signal.

[0027] In some embodiments, Figure 1 Each memory device 25 may include one or more memory devices 100, wherein each memory device may be a NAND memory.

[0028] In some embodiments, the memory controller 20 and one or more memory devices 25 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 10 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 20 and a single memory device 25 can be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a connection between the memory card 26 and a host computer (e.g., Figure 1The host 15) is coupled to the memory card connector 24. In such a way... Figure 2B In another example shown, the memory controller 20 and multiple memory devices 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host (e.g., Figure 1 The host 15) is coupled to the SSD connector 28.

[0029] Figure 3 A top view of a memory device 100 according to some embodiments is shown. Figure 3 The exemplary configurations shown are given as non-limiting examples, and it should be understood that the memory is scalable. In some embodiments, the memory device 100 may include one or more memory planes 101, wherein each memory plane may include a plurality of memory blocks 103. The same and simultaneous operations may occur at each memory plane 101. A memory block 103, which may be megabytes (MB) in size, is the minimum size for performing an erase operation. For example, the memory device 100 may include four memory planes 101. For example, each memory plane 101 may include six memory blocks 103. Each memory block 103 may include a plurality of memory cells, wherein each memory cell may be addressed by interconnects (e.g., bit lines and word lines). Bit lines and word lines may be arranged vertically (e.g., by row and column, respectively), forming an array of metal lines. Figure 3 In this context, the directions of the bit lines and word lines are marked as "BL" and "WL".

[0030] In some embodiments, the memory device 100 may further include a peripheral region 105, i.e., a region surrounding the memory plane 101. The peripheral region 105 may include a number of digital, analog, and / or mixed-signal circuits for supporting the functions of the memory device, such as page buffers, row decoders, column decoders, and sense amplifiers. As will be apparent to those skilled in the art, the peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc.

[0031] In some embodiments, Figure 3 The arrangement of storage planes 101 in the memory device 100 shown and the arrangement of storage blocks 103 in each storage plane 101 are used as examples only and do not limit the scope of this disclosure.

[0032] Figure 4A schematic diagram of a memory device 100 according to some embodiments is shown. In some embodiments, the memory device 100 may include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 may include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. Memory cells 340 sharing the same word line form memory pages 432. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate (“LSG”) 332 and a top select gate (“TSG”) 334, respectively. The lower select gate (“LSG”) may also be referred to as the bottom select gate (“BSG”). The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source (“ACS”) 430. The ACS 430 may be shared by the memory strings 212 throughout the memory block and is also referred to as the common source line.

[0033] In some embodiments, the memory device 100 may further include peripheral circuitry, which may include a number of digital, analog, and / or mixed-signal circuits for supporting the functionality of the memory block 103, such as a page buffer 52, a row decoder / word line driver 40, a column decoder / bit line driver 50, a controller 70, a voltage generator 65, and an input / output buffer 55. The controller 70 may include one or more control circuits. In some aspects, the controller 70 may include one or more registers, buffers, and / or memories to store one or more trim settings described in this disclosure. As will be apparent to those skilled in the art, these circuits may include active semiconductor devices and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc.

[0034] In some embodiments, memory block 103 may be coupled to line decoder / word line driver 40 via word line (“WL”) 333, lower select gate (“LSG”) 332, and top select gate (“TSG”) 334. Memory block 103 may be coupled to page buffer 52 via bit line (“BL”) 341. Line decoder / word line driver 40 may select one of the memory blocks 103 on memory device 100 in response to an X-path control signal provided by controller 70. Line decoder / word line driver 40 may deliver a voltage from voltage generator 65 to word line according to the X-path control signal. During read and program operations, line decoder / word line driver 40 may deliver read voltage V according to the X-path control signal received from controller 70. read and programming voltage V pgm Transmit to the selected word line and apply the turn-on voltage V.pass Send to the unselected word line.

[0035] In some embodiments, the column decoder / bit line driver 50 can suppress the voltage V according to the Y path control signal received from the controller 70. inhibit The data is transmitted to the unselected bit line and the selected bit line is connected to ground. In other words, the column decoder / bit line driver 50 can be configured to select or deselect one or more memory strings 212 according to the Y-path control signal from the controller 70. The page buffer 52 can be configured to read data from the memory block 103 and program (write) data to the memory block 103 according to the Y-path control signal from the controller 70. For example, the page buffer 52 can store data of a page to be programmed into a memory page 432. In another example, the page buffer 52 can perform a verification operation to ensure that data has been properly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer 52 can sense the current flowing through the bit line 341 that reflects the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification.

[0036] In some embodiments, to increase the efficiency of write operations, the column decoder / bit line driver 50 can adjust the bias voltage V based on the Y-path control signal from the controller 70 and the data to be programmed from the page buffer 52. bias Transmit to the selected bit line.

[0037] In some embodiments, the input / output buffer 55 can transfer I / O data from / to the page buffer 52 and transfer address ADDR or command CMD to the controller 70. In some embodiments, the input / output buffer 55 can function as the memory controller 20 on the memory device 25. Figure 1 The function of the interface between the (middle) and the memory device 100.

[0038] In some embodiments, controller 70 may control page buffer 52 and row decoder / word line driver 40 in response to command CMD transmitted by input / output buffer 55. During programming operations, controller 70 may control row decoder / word line driver 40 and page buffer 52 to program selected memory cells. During read operations, controller 70 may control row decoder / word line driver 40 and page buffer 52 to read selected memory cells. X-path control signals and Y-path control signals include row address X-ADDR and column address Y-ADDR, which can be used to locate selected memory cells in memory block 103. Row address X-ADDR may include page index PD, block index BD, and plane index PL to identify memory page 432, memory block 103, and memory plane 101, respectively. Figure 3(In the middle). The column address Y-ADDR can identify a byte or word in the data of page 432.

[0039] In some embodiments, voltage generator 65 can generate voltages to be supplied to word lines and bit lines under the control of controller 70. The voltages generated by voltage generator 65 include the read voltage V. read Programming voltage V pgm , conduction voltage V pass Suppression voltage V inhibit Bit line bias voltage V bias wait.

[0040] Notice, Figure 1 , Figures 2A-2B and Figures 3-4 The arrangement of electronic components in the storage system 10 and memory device 100 is shown as a non-limiting example. In some embodiments, the storage system 10 and memory device 100 may have other layouts and may include additional components. Figure 4 Components on the memory device 100 shown (e.g., controller 70, I / O buffer 55) can also be removed from the memory device 100 as separate electrical components in the storage system 10. Figure 4 Components on the memory device 100 shown (e.g., controller 70, I / O buffer 55) can also be moved to other components in the memory system 10. For example, a portion of controller 70 can be combined with memory controller 20, or vice versa.

[0041] Figure 5 A schematic diagram of an exemplary threshold voltage distribution of a memory device according to some embodiments is shown.

[0042] Back Figure 4 In some embodiments, the memory block 103 may be formed based on floating gate technology. In some embodiments, the memory block 103 may be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. This is expressed in terms of logic states (“states”, for example, the threshold voltage V of memory cell 340). th The amount of stored data depends on the number of charge carriers captured in the storage membrane of storage cell 340.

[0043] In some embodiments, in a NAND flash memory, read and write operations (also known as programming operations) can be performed on storage page 432, and erase operations can be performed on storage block 103.

[0044] In some embodiments, in a NAND memory, memory cell 340 can be in an erase state ER or a programmable state P1. Initially, by implementing a negative voltage difference between the control gate 333 and the channel, memory cell 340 in memory block 103 can be reset to an erase state as logic "1", allowing the charge carriers trapped in the storage film of memory cell 340 to be removed. For example, this can be achieved by setting the control gate 333 of memory cell 340 to ground and applying a high positive voltage (erase voltage V). erase A negative voltage difference is induced by applying a voltage to the ACS 430. In the erase state ER (“State ER”), the threshold voltage V of the memory cell 340 can be... th Reset to the lowest value.

[0045] In some embodiments, during programming (i.e., writing), a programming voltage V can be applied to the control gate 333, for example. pgm (For example, a positive voltage pulse between 10V and 20V) and grounding the corresponding bit line 341 determines the positive voltage difference between the control gate 333 and the channel. Therefore, charge carriers (e.g., electrons) can be injected into the storage film of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. th Therefore, storage unit 340 can be programmed to programming state P1 (“state P1” or logic “0”).

[0046] In some embodiments, the threshold voltage V of the memory cell can be measured or sensed. th To determine the state of the memory cell (e.g., state ER or state P1). During a read operation, a read voltage V can be applied to the control gate 333 of the memory cell. read Furthermore, the current flowing through the memory cell can be measured at bit line 341. A turn-on voltage V can be applied to an unselected word line. pass To connect to the unselected storage unit.

[0047] In some embodiments, NAND flash memory can be configured to operate in Single-Level Cell (SLC) mode. To increase storage capacity, NAND flash memory can also be configured to operate in Multi-Level Cell (MLC) mode, Triple-Level Cell (TLC) mode, Quadruple-Level Cell (QLC) mode, or any combination of these modes. In SLC mode, the memory cell stores 1 bit and has two logical states, logic {1 and 0}, namely states ER and S1. In MLC mode, the memory cell stores 2 bits and has four logical states, logic {11, 10, 01, and 00}, namely states ER, M1, M2, and M3. In TLC mode, the memory cell stores 3 bits and has eight logical states, logic {111, 110, 101, 100, 011, 010, 001, 000}, namely states ER and states T1-T7. In QLC mode, the memory cell stores 4 bits and has 16 logic states: {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000}, i.e., states ER and Q1-Q15. The memory controller 20 of the memory system 10 (see...) Figure 1 Data received from host 15 can be converted into the corresponding logical state of the storage cell on storage device 100, and vice versa.

[0048] In one aspect of QLC mode, states P1-P15 correspond to states Q1-Q15. In other aspects, each state of the memory cell may correspond to a threshold voltage V. th A specific range, where the threshold voltage V for each state th The distribution can be represented by a probability density. In some aspects, incremental step pulse programming (ISPP) schemes can be used to program states other than the erase state ER, where step pulses V can be added. step To incrementally increase the programming voltage V pgm For example, the QLC state can be programmed from state ER with a lower threshold voltage to state Q15 with the highest threshold voltage.

[0049] In some aspects, after programming, during the verification process, states P1-P15 can be verified using one or more predefined read reference voltages. By applying one or more of the predefined read reference voltages to the control gate of the target memory cell, the threshold voltage V of the memory cell can be determined. th The range.

[0050] For example, to verify whether a memory cell is in state ER, a read reference voltage V can be used. R1 If the target memory cell is in state ER, then the threshold voltage V of the target memory cell... th Below the reading reference voltage V R1 The target memory cell can be turned on, and a conductive path is formed in the channel. If the target memory cell is in any of states P1-P15, the threshold voltage V of the target memory cell... th Higher than the predefined read reference voltage V R1 The target memory cell is thus turned off. The threshold voltage V of the target memory cell can be verified by measuring or sensing the current through the target memory cell at the corresponding bit line via page buffer 52. th Or state.

[0051] In some aspects, as shown in Figure 510, in order to determine the states ER and P1-P15 for the QLC mode, (for example) including V R1 V R13 V R14 and V R15 A predefined read reference voltage. For example, in QLC mode, the threshold voltage of the state ER is lower than V. R1 The threshold voltage of state P15 is higher than V. R15 The threshold voltage of state P14 is located at V. R14 With V R15 Between, and the threshold voltage of state P13 is located at V R13 With V R14 between.

[0052] In some aspects, as shown in Figure 520, the threshold voltage V for each state in P1-P15 th The distribution can shift over time. As shown in Figure 520, the change in the threshold voltage distribution of the memory cell can be illustrated depending on the programming state. For example, in the lower programming states P1, P2, and P3, the distribution may tend to shift slightly to the right. Furthermore, in the upper programming states P12, P13, P14, and P15, the distribution may tend to expand slightly to the left. This is achieved by using a predefined read reference voltage (including, for example, V). R1 V R13 V R14 and V R15 One or more predefined read reference voltages are applied to the control gate of the target memory cell, and the threshold voltage V of the memory cell is... thThe range may not be properly defined. In some aspects, a valley may include the intersection between a first threshold voltage distribution of a first state and a second threshold voltage distribution of a second state. The second state may include a state adjacent to or near the first state. For example, valley 530 may include the intersection between the threshold voltage distribution of programming state P14 and the threshold voltage distribution of programming state P15.

[0053] In memory devices, especially high-density memory devices, threshold voltage (Vt) distribution offset is a common and critical issue, as it can be affected by many factors, such as charge loss of programmed cells over time, noise, and long NAND service life. After a Vt distribution offset, the predefined read level cannot track the Vt distribution, resulting in read failures.

[0054] Figure 6A An exemplary schematic circuit diagram 600 of a memory device according to aspects of the present disclosure is shown. The exemplary schematic circuit diagram 600 includes a memory block 604 and peripheral circuitry 602. In some aspects, the exemplary schematic circuit diagram 600 includes a plurality of memory strings 610, 620, and 630, wherein each of the memory strings 610, 620, and 630 has a plurality of memory cells 608. Memory string 610 also includes at least one field-effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate (LSG) 612 and a top select gate (TSG) 614, respectively. The memory cells 608 can be controlled by control gates, wherein the control gates can be connected to word lines 640 of the exemplary schematic circuit diagram 600. The drain terminal of TSG 614 can be connected to bit line 618, and the source terminal of LSG 612 can be connected to an array common source (ACS) 616. ACS 616 can be shared by memory strings 610 throughout the memory block and is also referred to as the common source line. In some examples, storage string 620 may be associated with bit line 628, and storage string 630 may be associated with bit line 638.

[0055] In some aspects, the exemplary schematic circuit diagram 600 can be formed based on floating gate technology. In some aspects, the exemplary schematic circuit diagram 600 can be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. It stores data or logic states (e.g., the threshold voltage V of memory cell 608). th The amount depends on the amount of charge captured in the storage layer. In some aspects, storage block 604 may be a three-dimensional (3D) memory device, and exemplary schematic circuit diagram 600 may be a 3D memory array in which storage cells 608 may be stacked vertically on top of each other.

[0056] In a NAND memory, memory cell 608 can be in an erase state ER or a programmable state P1. Initially, all memory cells 608 in the exemplary schematic diagram 600 can be reset to the erase state ER, which is logic "1", by implementing a negative voltage difference between the control gate and the source terminal (e.g., array common source 616) of the memory cell, so that all trapped electron charge in the storage layer of memory cell 608 can be removed. For example, a negative voltage difference can be induced by setting the control gate of memory cell 608 to ground and applying a high positive voltage to array common source 616. In the erase state ER ("state ER"), the threshold voltage V of memory cell 608 is... th It can be reset to the lowest value and can be measured or sensed at bit line 618.

[0057] During programming (i.e., writing), a programming voltage V can be applied to the control gate. pgm (For example, a positive voltage pulse between 10V and 20V) allows electronic charge (e.g., electrons) to be injected into the storage layer of storage cell 608, thereby increasing the threshold voltage V of storage cell 608. th Therefore, memory cell 608 is programmed to state P1. In some examples, memory cell 608 can be programmed to different states, such as P2-P15 in QLC mode.

[0058] Figure 6B An exemplary schematic diagram of a page buffer of a memory device according to some embodiments is shown. (The remaining text appears to be incomplete and possibly contains errors.) Figure 4 Page buffer 52 and Figures 1-6A To describe the components in Figure 6B However, not all the depicted components may be used, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0059] like Figure 6B As shown, page buffer 52 includes a first page buffer structure 658, a second page buffer structure 668, a third page buffer structure 678, and a latch 680. Latch 680 is connected to the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678 to perform read operations on a memory device (e.g., memory device 100). In some examples, the first page buffer structure 658 can be... Figure 6A Bit line 618 is connected to memory string 610. In some examples, the second page buffer structure 668 can be connected via... Figure 6ABit line 628 is connected to memory string 620. In some examples, the third page buffer structure 678 can be connected via... Figure 6A Bit line 638 is connected to memory string 630.

[0060] like Figure 6B As shown, the first page buffer structure 658 includes a sensing node (SO) 650, a pre-charge path 652, an SO discharge path 654, and a sensing latch 656. The second page buffer structure 668 includes a sensing node (SO) 660, a pre-charge path 662, an SO discharge path 664, and a sensing latch 666. The third page buffer structure 678 includes a sensing node (SO) 670, a pre-charge path 672, an SO discharge path 674, and a sensing latch 676.

[0061] For reference Figure 4 As described, during a read operation, the line decoder / word line driver 40 can adjust the read voltage V based on the X path control signal received from the controller 70. read Data is transmitted to the selected or unselected word line. Page buffer 52 can be configured to read data from and write data to memory block 103 according to a Y-path control signal from controller 70. During a read operation, page buffer 52 can sense the current flowing through bit line 341 that reflects the logic state (i.e., data) of memory cell 340 and amplify the small signal to a measurable amplification.

[0062] During a read operation, the first page buffer structure 658 can be precharged by a control logic unit (e.g., control circuitry 70) via precharge path 652 to the bit line 618, and the selected memory cell can be sensed at SO 650 as to whether it is on or off. The second page buffer structure 668 and the third page buffer structure 678 can precharge the bit lines connected to the second page buffer structure 668 and the third page buffer structure 678 respectively, based on the same procedure as the precharge operation of the first page buffer structure 658 described above.

[0063] During a read operation, bit line 618 and SO 650 can be precharged to a predetermined level during a precharge period. Current can be generated (e.g., in the channel) to flow through bit line 618 into the first page buffer structure 658. During a development period with a development time, when the selected memory cell is in a first state (e.g., an on cell), the charge charged at SO 650 can be discharged through bit line 618 to the array common source (ACS) 616 and through SO discharge path 654 to the channel of the cell string. In this case, because the current flowing to the first page buffer structure 658 is relatively large, the voltage drop at SO 650 may be relatively fast. On the other hand, during a development period with a development time, when the selected memory cell is in a second state (e.g., an off cell), it may be difficult for the charge charged at SO 650 to be discharged through bit line 618 to ACS 616. Therefore, because the current flowing to the first page buffer structure 658 is relatively small, the voltage drop at SO 650 may be relatively slow.

[0064] During the latching period, the state of SO 650 associated with the selected memory cell can be latched to the sense latch 656 as a first state of the selected memory cell with a logic value of 1. Alternatively, the state of SO 650 associated with the selected memory cell can be latched to the sense latch 656 as a second state of the selected memory cell with a logic value of 0. In some examples, the threshold voltage of the selected memory cell in the first state is greater than the read voltage in the read operation, and the threshold voltage of the selected memory cell in the second state is less than the read voltage in the read operation. In some examples, the memory cell is in the first state when it is turned on when the read voltage level is applied, and in the second state when it is turned off when the read voltage level is applied.

[0065] In some examples, the second page buffer structure 668 and the third page buffer structure 678 can discharge the bit lines connected to the second page buffer structure 668 and the third page buffer structure 678 respectively based on the same procedure as the operation of the first page buffer structure 658 described above, and sense the state of the sensing node as the first state or the second state of the selected memory cell.

[0066] After the latching period, latch 680 may store data associated with each of the sensing latches 656, 666, and 676. Latch 680 may perform one or more modifications on the stored data associated with each of the sensing latches 656, 666, and 676. In some examples, latch 680 may modify the logical value of the data associated with each of the sensing latches 656, 666, and 676. For example, latch 680 may modify a logical value of 1 to a logical value of 0. Alternatively, latch 680 may modify a logical value of 0 to a logical value of 1.

[0067] In some examples, during a read operation, the development time during the development phase can be different for each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678. The sensing node, precharge path, SO discharge path, and sensing latch associated with each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678 can be controlled individually in different configurations.

[0068] Figure 7 An illustration according to some embodiments is shown. Figure 6B An exemplary signal waveform of the voltage level of the sensing node in Figure 6. This can be related to page sensing nodes 650, 660, or 670 in Figure 6. Figures 1-6B To describe the components in Figure 7 However, not all of the shown components may be used, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0069] refer to Figure 7 This can be simply illustrated by showing the level change of sensing node SO (e.g., sensing node 650, 660, or 670) according to the threshold voltage level of the memory cell and the latching results according to the development period. The time period 710 from time T0 to time T1 can be referred to as such. Figure 6B The pre-charging period discussed, the time interval 720 from time T1 to time T2, can be referred to as, as in the reference... Figure 6BThe development period under discussion. During the development period, the change in voltage level of the sensing node SO for the strongly conducting cell can be represented by curve C1. Strongly conducting or strongly turning-off cells may not be significantly affected by slight changes in development time. The voltage change of the sensing node SO used to sense the memory cell can be represented by curve C2, and the threshold voltage of each memory cell in the memory cell can be located near the read voltage. Curve C2 shows the development slope of a memory cell with a threshold voltage slightly lower than the read voltage. The time period 730 between time T2 and T3 can be referred to as [reference missing]. Figure 6B The sensing period discussed.

[0070] In some examples, when the memory cell has a threshold voltage relatively higher than the read voltage, the level change of the sensing node SO may be relatively small. When the memory cell has a threshold voltage relatively lower than the read voltage, the level change of the sensing node SO may be relatively large. In some aspects, the memory cell whose threshold voltage distribution is located around a valley (e.g., valley 530) between a first threshold voltage distribution in the first state and a second threshold voltage distribution in the second state may be a memory cell located at the boundary between a conducting cell and a turning-off cell. Therefore, the difference between conducting and turning-off cells with respect to the memory cell can be varied depending on the development time. That is, even if the development time is slightly reduced, each memory cell in the memory cell whose threshold voltage distribution is around the valley can be identified as a "turn-off cell". On the other hand, even if the development time is slightly increased, each memory cell in the memory cell whose threshold voltage distribution is around the valley can be identified as a "conducting cell". That is, in a memory cell having a threshold voltage level similar to the read voltage level to be provided to the word line, the sensing operation can be performed in the same way as the sensing operation using a reading voltage increased by reducing the development time. On the other hand, in a memory cell having a threshold voltage level similar to the read voltage level to be provided to the word line, a sensing operation can be performed in the same way as a sensing operation using a read voltage that is reduced by increasing the development time.

[0071] Therefore, sensing the sensing node SO multiple times at the point in time when the development time is changed can be the same as changing the word line voltage and precharging and sensing the bit line.

[0072] Figure 8A An exemplary method 800 for performing a read operation on a memory device according to some embodiments is shown. (This can be discussed regarding...) Figures 1-7 To describe the components in Figure 8A It can be provided by a storage system (e.g., Figure 1The storage system 10) executes Example 800. It should be understood that process flow 800 is not exhaustive, and other operation steps may be performed before, after, or between any of the operation steps shown. In some embodiments, some operation steps of process flow 800 may be omitted, or other operation steps not described herein may be included for simplicity. In some embodiments, the operation steps of process flow 800 may be performed in a different order, and / or the operation steps of process flow 800 may vary.

[0073] At step 802, a first read operation is performed on a memory cell (e.g., memory cell 608) in the memory device (e.g., memory device 100). In one example, the first operation may include applying a predetermined read voltage (e.g., Figure 5 V in R15 This is used to determine the state of one or more memory cells (e.g., P15). In some aspects, as shown in Figure 520, the threshold voltage V for each state in P1-P15 is... th The distribution can shift over time.

[0074] At step 804, based on the first read operation, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state are selected from the memory cells. In some examples, the threshold voltage of each memory cell in the first plurality of memory cells in the first state may be greater than the read voltage in the first read operation, and the threshold voltage of each memory cell in the second plurality of memory cells in the second state may be less than the read voltage in the first read operation. In some examples, the first state of the memory cell may correspond to a logic value of 1 in a sense latch. In some examples, the second state of the memory cell may correspond to a logic value of 0 in a sense latch. In some examples, one or more bit lines or sense nodes associated with the first plurality of memory cells may be precharged after the first read operation. One or more bit lines or sense nodes associated with the second plurality of memory cells may not be precharged after the first read operation.

[0075] At step 806, a second read operation is performed on the first plurality of memory cells, including steps 816, 826, and 836. At step 816, first data is sensed from the first plurality of memory cells via a first set of bit lines (e.g., bit line 618) during a first development time. In some examples, the first development time may be related to... Figure 7The development and sensing periods discussed are related. At step 826, first data is sensed from the first plurality of memory cells via a second set of bit lines (e.g., bit line 628) during the second development time. At step 836, first data is sensed from the first plurality of memory cells via a third set of bit lines (e.g., bit line 638) during the third development time. In some examples, the first development time may include a time period (e.g., "T"), the second development time may include a time period twice the length of the first development time (e.g., "2T"), and the third development time may include a time period three times the length of the first development time (e.g., "3T"). In some examples, the number of development times may not be limited to three and may include any number. In some examples, the number of development times may be selected based on different numbers of sets of bit lines.

[0076] In some examples, a first discharge path associated with the bit lines of the first group (e.g., SO discharge path 654) may be disabled after a first development time. In some examples, a second discharge path associated with the bit lines of the second group (e.g., SO discharge path 664) may be disabled after a second development time. In some examples, a third discharge path associated with the bit lines of the third group (e.g., SO discharge path 674) may be disabled after a third development time, thereby performing a second read operation on the first plurality of memory cells.

[0077] In some examples, one or more sense latches (e.g., sense latches 656, 666, and 676) latch first data corresponding to each of the first plurality of memory cells to a logic value of one or zero based on a second read operation. The first data may be passed to latch 680 and modified in latch 680. The modified logic value corresponding to each of the first plurality of memory cells may be obtained by latch 680. In some examples, the logic value one may be modified to the logic value zero. Alternatively, the logic value zero may be modified to the logic value one.

[0078] At step 808, a third plurality of storage units are selected from the first plurality of storage units based on the second read operation. In some examples, the third plurality of storage units may be selected from the first plurality of storage units based on a modified logical value. In some examples, the modified logical value corresponding to each storage unit in the third plurality of storage units may be one. In some examples, the modified logical value corresponding to each storage unit in the third plurality of storage units may be a predetermined value.

[0079] At step 810, a third read operation is performed on the third plurality of memory cells, including steps 820 and 830. At step 820, second data is sensed from the third plurality of memory cells via the second set of bit lines during a fourth development time. At step 830, the second data is sensed from the third plurality of memory cells via the third set of bit lines during a fifth development time. In some examples, the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time. In some examples, the first difference between the second development time and the first development time, and the second difference between the third development time and the second development time, may be the same. In some examples, the third difference between the second development time and the fourth development time, and the fourth difference between the third development time and the fifth development time, may be the same. In some examples, the third difference and the fourth difference may be the same as the first development time. In some examples, the fourth development time may be equal to the first development time. In some examples, the fifth development time may be equal to the second development time.

[0080] In some examples, the second discharge path associated with the bit lines of the second group can be disabled after the fourth development time; the third discharge path associated with the bit lines of the third group can be disabled between the fifth development time, thereby performing a third read operation on the third plurality of memory cells.

[0081] In some examples, the second data corresponding to each of the third plurality of memory cells can be latched to a logic value of one or zero based on the third read operation.

[0082] In some examples, a first number of memory cells corresponding to the logic value 1 associated with the bit lines of the first group can be determined. A second number of memory cells corresponding to the logic value 1 associated with the bit lines of the second group can be determined. A third number of memory cells corresponding to the logic value 1 associated with the bit lines of the third group can be determined.

[0083] At step 812, the read development time is determined based on the third read operation.

[0084] In some examples, a first quantity, a second quantity, and a third quantity can be compared to obtain the minimum quantity among the first, second, and third quantities. A set of bit lines from the first group, the second group, and the third group corresponding to the minimum quantity among the first, second, and third quantities can be determined. The development time associated with the determined set of bit lines from the first group, the second group, and the third group can be determined as the read development time. A first group of bit lines corresponding to the minimum quantity among the first, second, and third quantities can be determined. The first development time associated with the bit lines of the first group can be determined as the read development time. The read development time can be the optimal development time for determining a data state (e.g., P15) of the memory device for use in... Figure 5 Predefined read levels (e.g., V) R15 This is used to minimize the impact of the threshold voltage (Vt) distribution offset.

[0085] In some examples, the first group of bit lines may include a first number of bit lines. In some examples, the second group of bit lines may include a second number of bit lines. In some examples, the third group of bit lines may include a third number of bit lines. In some examples, the first, second, and third numbers may be the same.

[0086] In some examples, the fourth development time can be the same as the first development time; and the fifth development time can be the same as the second development time.

[0087] Figure 8B The following are illustrations based on some embodiments. Figure 8A An exemplary threshold voltage distribution and data structure during the process flow. (This can be related to...) Figure 8A and Figures 1-7 To describe Figure 8B However, not all of the shown components may be used, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. Additional, different, or fewer components may be provided.

[0088] Figure 8B It includes the first data structure 892, the second data structure 896, and the third data structure 890.

[0089] In some examples, Figure 8A During the first read operation at step 802, the first data structure 892 may include data associated with a latch (e.g., 680) in a page buffer (e.g., page buffer 52) that is associated with one or more memory cells. For example, the first data structure 892 may be associated with... Figure 6BThe page buffer 52 is associated with the first data structure 892, which may include D_S_g0, D_S_g1, D_S_g2, D_S_g3, and D_S_g4 corresponding to the first bit line group g0, the second bit line group g1, the third bit line group g2, the fourth bit line group g3, and the fifth bit line group g4. Each of D_S_g0, D_S_g1, D_S_g2, D_S_g3, and D_S_g4 may include a logic value of 1 or 0 to indicate a first state or a second state of the memory cell.

[0090] For reference Figure 6B As described, during the latching period, the state of SO 650 associated with the selected memory cell can be latched to sense latch 656 as a first state of the selected memory cell having a logic value of 1. Alternatively, the state of SO 650 associated with the selected memory cell can be latched to sense latch 656 as a second state of the selected memory cell having a logic value of 0. In some examples, the threshold voltage of the selected memory cell in the first state is greater than the read voltage in the read operation, and the threshold voltage of the selected memory cell in the second state is less than the read voltage in the read operation. After the latching period, latch 680 can store data associated with each of sense latches 656, sense latch 666, and sense latch 676 as bit-line associated data, such as the first data structure 892.

[0091] In some examples, during the second read operation at step 806, the second data structure 896 may include data associated with one or more sense latches (e.g., sense latches 656, 666, and 676) and latches (e.g., 680) in a page buffer (e.g., page buffer 52) that are associated with one or more memory cells. As described above, the second read operation is performed on the first plurality of memory cells, including steps 816, 826, and 836. The second data structure 896 may include data associated with five sense latches SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4. Each of SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4 may correspond to a sense latch associated with a first bit line group g0, a second bit line group g1, a third bit line group g2, a fourth bit line group g3, and a fifth bit line group g4. The sense latch can be sense latch 656, 666 and 676 or include sense latch 656, 666 and 676.

[0092] In some examples, the second data structure 896 includes second data structures 896A, 896B, and 896C. Second data structure 896A may include data associated with one or more sense latches associated with the first plurality of memory cells. Second data structure 896A may include data associated with one or more sense latches associated with the first plurality of memory cells. After steps 816, 826, and 836 in step 806, second data structure 896B may include data associated with one or more sense latches associated with the first plurality of memory cells. After steps 816, 826, and 836 in step 806, second data structure 896C may include modified data associated with one or more latches (e.g., 680) associated with the first plurality of memory cells in a page buffer (e.g., page buffer 52). See reference... Figure 6B and Figure 8A As described, the latches in the page buffer can modify the data associated with the sense latches SO_g0, SO_g1, SO_g2, SO_g3, and SO_g4 to change a logic value of 1 to a logic value of 0 and vice versa. The modified data can be provided in a second data structure 896C.

[0093] In some examples, during the third read operation at step 810, the third data structure 890 may include data associated with one or more sense latches (e.g., sense latches 656, 666, and 676) and latches (e.g., 680) that are associated with one or more memory cells in a page buffer (e.g., page buffer 52). The third read operation is performed on the third plurality of memory cells as described above, including steps 820 and 830.

[0094] The third data structure 890 includes third data structures 890A, 890B, and 890C. In some examples, the third data structure 890A may include data associated with one or more sense latches associated with the third plurality of memory cells. In some examples, after steps 820 and 830 in step 810, the third data structure 890B may include data associated with one or more sense latches associated with the third plurality of memory cells. In some examples, after steps 820 and 830 in step 810, the third data structure 890C may include data associated with latches (e.g., 680) associated with the third plurality of memory cells in a page buffer (e.g., page buffer 52).

[0095] In some examples, as described above with reference to step 812, the read development time is determined based on the third data structure 890C.

[0096] In some examples, the number of one or more units associated with the first data structure 892, the second data structure 896, and the third data structure 890 in the first or second state can correspond to Figure 8B One or more regions in the exemplary threshold voltage distribution shown.

[0097] In this disclosure, a read development time is determined based on a third read operation after the first and second read operations. The read development time can be an optimal development time for determining a data state (e.g., P15) of the memory device, in order to use... Figure 5 Predefined read levels (e.g., V) R15 This is used to minimize the impact of the threshold voltage (Vt) distribution offset.

[0098] In addition, two advantages of this disclosure may include: (1) improved read efficiency can be achieved by obtaining the Vt distribution of multiple regions in the threshold voltage distribution at once, which saves not only read sensing time but also cell count time; (2) improved system design can be achieved by using only one latch in the page buffer (e.g., latch 680), thereby improving one or more circuit designs and performance.

[0099] The foregoing description of specific embodiments so fully reveals the general nature of this disclosure that others, by applying knowledge in the art, can readily modify and / or transform various applications of these specific embodiments without excessive experimentation and without departing from the overall concept of this disclosure. Therefore, based on the disclosure and guidance set forth herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It will be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0100] Embodiments of this disclosure have been described above using functional building blocks, which illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined provided that the specific functions and relationships are properly implemented.

[0101] The summary and abstract section may set forth one or more exemplary embodiments of this disclosure conceived by (a plurality of) inventors, but not all exemplary embodiments, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0102] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined only by the following claims and their equivalents.

Claims

1. A NAND memory device, comprising: A storage array having storage units; Page buffers, the page buffers being coupled to the memory array via bit lines, wherein the page buffers include latches; and A control logic unit, coupled to the page buffer, is configured to: Perform a first read operation on the storage unit; Based on the first read operation, select a first plurality of storage units in a first state and a second plurality of storage units in a second state from the storage units; Performing a second read operation on the first plurality of memory cells includes: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time. Based on the second read operation, a third plurality of storage units are selected from the first plurality of storage units; Performing a third read operation on the third plurality of memory cells includes: sensing second data from the third plurality of memory cells via the bit lines of the second set during a fourth development time, and sensing the second data from the third plurality of memory cells via the bit lines of the third set during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and The reading development time is determined based on the third reading operation.

2. The NAND memory device according to claim 1, wherein, In the first state, the threshold voltage of each of the first plurality of storage cells is greater than the read voltage in the first read operation, and in the second state, the threshold voltage of each of the second plurality of storage cells is less than the read voltage in the first read operation.

3. The NAND memory device according to claim 1, wherein, The control logic unit is further configured to: Disable the first discharge path associated with the bit line of the first group after the first development time; After the second development time, disable the second discharge path associated with the bit line of the second group; and After the third development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the second read operation on the first plurality of memory cells.

4. The NAND memory device according to claim 1, wherein, The control logic unit is further configured to: Based on the second read operation, the first data corresponding to each of the first plurality of storage units is latched to a logic value of one or zero; Modifying the latched first data includes: obtaining a modified logical value corresponding to each of the first plurality of memory cells; and The third plurality of storage cells are selected from the first plurality of storage cells, wherein the modified logical value corresponding to each of the third plurality of storage cells is one.

5. The NAND memory device according to claim 1, wherein, The control logic unit is further configured to: The second discharge path associated with the bit lines of the second group is disabled after the fourth development time; and After the fifth development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the third read operation on the third plurality of memory cells.

6. The NAND memory device according to claim 1, wherein, The control logic unit is further configured to: Based on the third read operation, the second data corresponding to each of the third plurality of storage units is latched to a logic value of one or zero; and Determine a first number of memory cells associated with the bit lines of the first group corresponding to the logical value 1, a second number of memory cells associated with the bit lines of the second group corresponding to the logical value 1, and a third number of memory cells associated with the bit lines of the third group corresponding to the logical value 1.

7. The NAND memory device according to claim 6, wherein, The control logic unit is further configured to: The first quantity, the second quantity, and the third quantity are compared to obtain the minimum quantity among the first quantity, the second quantity, and the third quantity; Determine the bit lines of the first group, the second group, and the third group that correspond to the minimum quantity among the first quantity, the second quantity, and the third quantity; and Determine the development time for reading.

8. The NAND memory device according to claim 1, wherein, The first group of bit lines includes a first number of bit lines; the second group of bit lines includes a second number of bit lines; the third group of bit lines includes a third number of bit lines; and the first number, the second number, and the third number are the same.

9. The NAND memory device according to claim 1, further comprising: The first difference between the second development time and the first development time; And a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

10. The NAND memory device according to claim 1, wherein, The fourth development time is the same as the first development time; and the fifth development time is the same as the second development time.

11. The NAND memory device according to claim 4, wherein, The control logic unit is further configured to modify the first data of the latch, including: modifying the first data of the latch having the logic value one to the logic value zero; and modifying the first data of the latch having the logic value zero to the logic value one.

12. A method for operating a memory device, comprising: Perform a first read operation on the memory cell in the memory device; Based on the first read operation, select a first plurality of storage units in a first state and a second plurality of storage units in a second state from the storage units; Performing a second read operation on the first plurality of memory cells includes: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time. Based on the second read operation, a third plurality of storage units are selected from the first plurality of storage units; Performing a third read operation on the third plurality of memory cells includes: sensing second data from the third plurality of memory cells via the bit lines of the second set during a fourth development time, and sensing the second data from the third plurality of memory cells via the bit lines of the third set during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and The reading development time is determined based on the third reading operation.

13. The method according to claim 12, wherein, In the first state, the threshold voltage of each of the first plurality of storage cells is greater than the read voltage in the first read operation, and in the second state, the threshold voltage of each of the second plurality of storage cells is less than the read voltage in the first read operation.

14. The method of claim 12, further comprising: Disable the first discharge path associated with the bit line of the first group after the first development time; Disable the second discharge path associated with the bit line of the second group after the second development time; as well as After the third development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the second read operation on the first plurality of memory cells.

15. The method of claim 12, further comprising: Based on the second read operation, the first data corresponding to each of the first plurality of storage units is latched to a logic value of one or zero; Modifying the latched first data includes: obtaining a modified logical value corresponding to each of the first plurality of memory cells; and The third plurality of storage cells are selected from the first plurality of storage cells, wherein the modified logical value corresponding to each of the third plurality of storage cells is one.

16. The method of claim 12, further comprising: The second discharge path associated with the bit lines of the second group is disabled after the fourth development time. as well as After the fifth development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the third read operation on the third plurality of memory cells.

17. The method of claim 12, further comprising: Based on the third read operation, the second data corresponding to each of the third plurality of storage units is latched to a logic value of one or zero; as well as Determine a first number of memory cells associated with the bit lines of the first group corresponding to the logical value 1, a second number of memory cells associated with the bit lines of the second group corresponding to the logical value 1, and a third number of memory cells associated with the bit lines of the third group corresponding to the logical value 1.

18. The method of claim 17, further comprising: The first quantity, the second quantity, and the third quantity are compared to obtain the minimum quantity among the first quantity, the second quantity, and the third quantity; Determine the bit lines of the first group, the second group, and the third group that correspond to the minimum quantity among the first quantity, the second quantity, and the third quantity; as well as Determine the development time for reading.

19. The method according to claim 12, wherein, The first group of bit lines includes a first number of bit lines; the second group of bit lines includes a second number of bit lines; the third group of bit lines includes a third number of bit lines; and the first number, the second number, and the third number are the same.

20. The method of claim 12, further comprising: The first difference between the second development time and the first development time; And a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

21. The method according to claim 12, wherein, The fourth development time is the same as the first development time; and the fifth development time is the same as the second development time.

22. The method of claim 15, further comprising: Modify the first data of the latch, which has the logical value one, to the logical value zero; as well as The first data of the latch, which has the logic value of zero, is modified to the logic value of one.

23. A memory system, comprising: A storage array having storage cells coupled to one of a plurality of bit lines; Page buffers, the page buffers being coupled to the memory array via the bit lines, wherein the page buffers include latches; and A control logic unit, coupled to the page buffer, is configured to: Perform a first read operation on the storage unit; Based on the first read operation, select a first plurality of storage units in a first state and a second plurality of storage units in a second state from the storage units; Performing a second read operation on the first plurality of memory cells includes: sensing first data from the first plurality of memory cells through a first set of bit lines during a first development time, sensing first data from the first plurality of memory cells through a second set of bit lines during a second development time, and sensing first data from the first plurality of memory cells through a third set of bit lines during a third development time. Based on the second read operation, a third plurality of storage units are selected from the first plurality of storage units; Performing a third read operation on the third plurality of memory cells includes: sensing second data from the third plurality of memory cells via the bit lines of the second set during a fourth development time, and sensing the second data from the third plurality of memory cells via the bit lines of the third set during a fifth development time, wherein the fourth development time is shorter than the second development time, and the fifth development time is shorter than the third development time; and The reading development time is determined based on the third reading operation.

24. The memory system according to claim 23, wherein, In the first state, the threshold voltage of each of the first plurality of storage cells is greater than the read voltage in the first read operation, and in the second state, the threshold voltage of each of the second plurality of storage cells is less than the read voltage in the first read operation.

25. The memory system according to claim 23, wherein, The control logic unit is further configured to: Disable the first discharge path associated with the bit line of the first group after the first development time; After the second development time, disable the second discharge path associated with the bit line of the second group; and After the third development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the second read operation on the first plurality of memory cells.

26. The memory system according to claim 23, wherein, The control logic unit is further configured to: Based on the second read operation, the first data corresponding to each of the first plurality of storage units is latched to a logic value of one or zero; Modifying the latched first data includes: obtaining a modified logical value corresponding to each of the first plurality of memory cells; and The third plurality of storage cells are selected from the first plurality of storage cells, wherein the modified logical value corresponding to each of the third plurality of storage cells is one.

27. The memory system according to claim 23, wherein, The control logic unit is further configured to: The second discharge path associated with the bit lines of the second group is disabled after the fourth development time; and After the fifth development time, the third discharge path associated with the bit lines of the third group is disabled, thereby performing the third read operation on the third plurality of memory cells.

28. The memory system according to claim 23, wherein, The control logic unit is further configured to: Based on the third read operation, the second data corresponding to each of the third plurality of storage units is latched to a logic value of one or zero; and Determine a first number of memory cells associated with the bit lines of the first group corresponding to the logical value 1, a second number of memory cells associated with the bit lines of the second group corresponding to the logical value 1, and a third number of memory cells associated with the bit lines of the third group corresponding to the logical value 1.

29. The memory system according to claim 28, wherein, The control logic unit is further configured to: The first quantity, the second quantity, and the third quantity are compared to obtain the minimum quantity among the first quantity, the second quantity, and the third quantity; Determine the bit lines of the first group, the second group, and the third group that correspond to the minimum quantity among the first quantity, the second quantity, and the third quantity; and Determine the development time for reading.

30. The memory system according to claim 23, wherein, The first group of bit lines includes a first number of bit lines; the second group of bit lines includes a second number of bit lines; the third group of bit lines includes a third number of bit lines; and the first number, the second number, and the third number are the same.

31. The memory system of claim 23, further comprising: The first difference between the second development time and the first development time; And a second difference between the third development time and the second development time, wherein the first difference and the second difference are the same.

32. The memory system according to claim 23, wherein, The fourth development time is the same as the first development time; and the fifth development time is the same as the second development time.

33. The memory system according to claim 26, wherein, The control logic unit is further configured to modify the first data of the latch, including: modifying the first data of the latch having the logic value one to the logic value zero; and modifying the first data of the latch having the logic value zero to the logic value one.

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