Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device including a first heat sink on which a first semiconductor element is mounted, a first electrode plate connected to the first heat sink via an inclined bent portion, a second heat sink on which a second semiconductor element is mounted, and a second electrode plate provided with a height difference from the second heat sink, the first electrode plate is disposed at a position higher than the first heat sink, the second electrode plate is disposed at a position higher than the second heat sink, the first and second electrode plates are disposed at the same height, the first and second heat sinks are disposed at the same height, and the second electrode plate is disposed above the first heat sink. The first electrode plate is disposed above the second heat sink, the first semiconductor element is bonded to the first heat sink and the second electrode plate, and the second semiconductor element is bonded to the second heat sink and the first electrode plate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a direct wire bonding structure in which a semiconductor element and an electrode are directly bonded to each other. Background Art

[0002] In power semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and high-voltage diodes, a semiconductor device module sealed with transfer mold resin using a direct wire bonding (DLB) structure in which a semiconductor element is directly bonded to an electrode.

[0003] For example, Patent Document 1 discloses a DLB structure in which a semiconductor element is bonded to a die pad of a lead frame by a bonding member such as solder, and then an upper surface electrode of the semiconductor element and a DLB frame are bonded by the bonding member. Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2018-081947 Summary of the invention Technical problem to be solved by the invention

[0005] In the prior art, since it is necessary to prepare a lead frame and a DLB frame and perform steps of bonding them to semiconductor elements, there is a problem that the number of parts and the number of manufacturing steps increase, and the manufacturing cost increases.

[0006] The present disclosure is proposed to solve the above-mentioned technical problems, and its object is to provide a semiconductor device that reduces the number of components and the number of manufacturing steps, thereby reducing the manufacturing cost. Technical means for solving technical problems

[0007] The semiconductor device involved in the present disclosure includes: a first heat sink equipped with a first semiconductor element, a first electrode plate connected to the first heat sink by an inclined bending portion, a second heat sink equipped with a second semiconductor element, and a second electrode plate arranged to have a height difference with the second heat sink, the first electrode plate is arranged at a position higher than the first heat sink, the second electrode plate is arranged at a position higher than the second heat sink, the first electrode plate and the second electrode plate are arranged at the same height, the first heat sink and the second heat sink are arranged at the same height, the second electrode plate is arranged above the first heat sink, the first electrode plate is arranged above the second heat sink, the first semiconductor element is bonded to the first heat sink and the second electrode plate, and the second semiconductor element is bonded to the second heat sink and the first electrode plate. Effects of the Invention

[0008] According to the semiconductor device involved in the present invention, by preparing a frame in which the first heat sink and the first electrode plate are provided with a height difference, and a frame in which the second heat sink and the second heat sink are provided with a height difference, a semiconductor device in which the first semiconductor element is bonded to the first heat sink and the second electrode plate, and the second semiconductor element is bonded to the second heat sink and the first electrode plate can be obtained, so that it is not necessary to separately provide a heat sink and an electrode plate, and the number of components can be reduced. In addition, by bonding the first and second semiconductor elements in a state in which the two frames are overlapped, the number of manufacturing processes can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a top view showing the structure of the semiconductor device according to the first embodiment. Figure 2 This is a plan view showing a frame for manufacturing the semiconductor device according to the first embodiment. Figure 3 This is a plan view showing a frame for manufacturing the semiconductor device according to the first embodiment. Figure 4 This is a plan view showing a state in which two frames for manufacturing the semiconductor device according to the first embodiment are combined. Figure 5 This is a cross-sectional view showing a frame for manufacturing the semiconductor device according to the first embodiment. Figure 6 This is a cross-sectional view showing a frame for manufacturing the semiconductor device according to the first embodiment. Figure 7 This is a plan view showing a state where two frames for manufacturing the semiconductor device according to the first embodiment are halfway overlapped. Figure 8 This is a plan view showing a state in which two frames for manufacturing a semiconductor device according to the second embodiment are combined. Fig. 9 This is a cross-sectional view schematically showing a semiconductor device according to a second embodiment. Fig.10 This is a plan view showing a state where two frames for manufacturing a semiconductor device according to the third embodiment are halfway overlapped. Fig.11 It is a top view showing a state in which two frames for manufacturing a semiconductor device according to the third embodiment are combined. Fig.12 This is a top view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. Fig.13 This is a top view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. Fig.14 It is a top view showing a state in which two frames for manufacturing a semiconductor device according to a fourth embodiment are combined. Fig.15 This is a cross-sectional view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. Fig.16 This is a cross-sectional view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. Fig.17 This is a cross-sectional view showing a frame for manufacturing a semiconductor device according to the fifth embodiment. Fig.18 This is a cross-sectional view showing a frame for manufacturing a semiconductor device according to the fifth embodiment. Fig.19 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a sixth embodiment. Fig. 20 It is a top view for explaining the manufacturing process of a semiconductor device. Fig.21 It is a top view for explaining the manufacturing process of a semiconductor device. Fig. 22 It is a top view for explaining the manufacturing process of a semiconductor device. Fig.23 It is a top view for explaining the manufacturing process of a semiconductor device. Fig.24 It is a top view for explaining the manufacturing process of a semiconductor device. Fig.25 It is a top view showing a state where two frames for manufacturing a semiconductor device according to a seventh embodiment are halfway overlapped. Fig.26 It is a top view showing a state in which two frames for manufacturing a semiconductor device according to a seventh embodiment are combined. Fig. 27 This is a plan view showing a state where two frames are halfway overlapped in the method for manufacturing a semiconductor device according to the eighth embodiment. Fig.28This is a top view showing a state where two frames are combined in the method for manufacturing a semiconductor device according to the eighth embodiment. Fig.29 This is a plan view showing a state where two frames are halfway overlapped in the method for manufacturing a semiconductor device according to the ninth embodiment. Fig.30 This is a top view showing a state where two frames are combined in the method for manufacturing a semiconductor device according to the eighth embodiment. Fig.31 It is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a tenth embodiment. Fig.32 It is a top view illustrating the method for manufacturing a semiconductor device according to the tenth embodiment. DETAILED DESCRIPTION

[0010] <Implementation method 1> Figure 1 It is a plan view showing the structure of a single-phase power inverter 100 which is a semiconductor device according to the first embodiment of the present disclosure. Figure 1 The single-phase inverter 100 shown is sealed with a molded resin, but for convenience, the molded resin on the upper surface is omitted, and only the molded resin RG on the lower surface is shown. In addition, for convenience, only the power semiconductor element 1a (first semiconductor element) and the power semiconductor element 1b (second semiconductor element) are shown, but if they are connected as IGBTs or MOSFETs in series, it can be considered as a basic circuit of a single-phase inverter.

[0011] like Figure 1 As shown, in the single-phase inverter 100, the heat sink 4a2 (first heat sink) equipped with power semiconductor elements 1a such as IGBT, MOSFET and high withstand voltage diode is connected to the electrode plate 4a1 (first electrode plate) arranged in parallel in a top view, and is configured to have the same potential. The heat sink 4a2 and the electrode plate 4a1 are connected by a bent portion BP1. The bent portion BP1 has an inclination that becomes higher on the electrode plate 4a1 side and lower on the heat sink 4a2 side. Therefore, there is a height difference between the heat sink 4a2 and the electrode plate 4a1.

[0012] Furthermore, the bent portion BP1 is provided along the entire long side of the heat sink 4a2, so that the electrode plate 4a1 and the heat sink 4a2 are firmly engaged with each other, and the shape of the electrode plate 4a1 can be stabilized.

[0013] In the power semiconductor element 1a, the first main electrode arranged on the lower surface side is joined to the upper surface of the heat sink 4a2 by means of solder or other brazing material (not shown), and the second main electrode arranged on the upper surface side is joined to the lower surface of the electrode plate 4b1 (second electrode plate) arranged above the heat sink 4a2 (second heat sink) by means of solder or other brazing material (not shown).

[0014] In addition, a heat sink 4b2 carrying a power semiconductor element 1b is disposed below the electrode plate 4a1. In the power semiconductor element 1b, a first main electrode disposed on the lower surface side is bonded to the upper surface of the heat sink 4b2 by a brazing material such as solder (not shown), and a second main electrode disposed on the upper surface side is bonded to the lower surface of the electrode plate 4a1 by a brazing material such as solder (not shown).

[0015] The radiator 4a2 and the radiator 4b2 are arranged in parallel when viewed from above, and there is no height difference between the two. On the other hand, the electrode plate 4b1 and the radiator 4b2 are arranged in parallel when viewed from above, but the electrode plate 4b1 is located at a higher position and the radiator 4b2 is located at a lower position, and there is a height difference between the two.

[0016] The electrode plate 4b1 is rectangular in shape when viewed from above, and one end thereof is joined to the main terminal plate T2, and the main terminal plate T2 protrudes to the outside of the molded resin RG. The end to which the main terminal plate T2 is joined is the side opposite to the end of the heat sink 4a2 on which the power semiconductor element 1a is mounted. In addition, a bent portion BP2 is provided at one end of the electrode plate 4b1. The bent portion BP2 has an inclination that becomes higher on the electrode plate 4b1 side and lower on the main terminal plate T2 side. As a result, there is a height difference between the electrode plate 4b1 and the heat sink 4b2.

[0017] The heat sink 4a2 has a rectangular shape in a plan view, and the power semiconductor element 1a is mounted on one end thereof and connected to the relay terminal RT1 via the lead wire WR. The relay terminal RT1 protrudes to the outside of the mold resin RG.

[0018] The heat sink 4b2 is rectangular in shape when viewed from above, and one end of the heat sink 4b2 is joined to a main terminal board T3, which protrudes to the outside of the molded resin RG. The end to which the main terminal board T3 is joined is the same side as the end on which the power semiconductor element 1b is mounted. The power semiconductor element 1b is connected to the relay terminal RT2 via the lead wire WR, and the relay terminal RT2 protrudes to the outside of the molded resin RG.

[0019] The electrode plate 4a1 is rectangular in plan view, and one end thereof is joined to a main terminal plate T1, which protrudes out of the mold resin RG. The end to which the main terminal plate T1 is joined is on the opposite side of the end of the heat sink 4b2 on which the power semiconductor element 1b is mounted.

[0020] As mentioned above, in Figure 1In the single-phase inverter 100 shown, there is a height difference between the heat sink 4a2 and the electrode plate 4a1, and there is a height difference between the electrode plate 4b1 and the heat sink 4b2. By arranging the power semiconductor element 1a between the heat sink 4a2 and the electrode plate 4b1, and arranging the power semiconductor element 1b between the heat sink 4b2 and the electrode plate 4a1, the power semiconductor element 1a and the power semiconductor element 1b can be connected in series.

[0021] Next, use Figure 2 to Figure 6 A method for manufacturing the main parts of the single-phase inverter 100 will be described. Figure 2 and Figure 3 4 are top views respectively showing a frame 4b and a frame 4a used to manufacture a single-phase inverter 100, Figure 4 It is a plan view showing a state where the frame 4a (first frame) and the frame 4b (second frame) are combined.

[0022] like Figure 2 As shown, the frame 4b is composed of a frame body 4b0, an electrode plate 4b1 and a radiator 4b2 having an outline of the frame 4b. The frame body 4b0 is a frame having a rectangular shape when viewed from above, and the electrode plate 4b1 and the radiator 4b2 are extended from one side of the frame body 4b0 toward the inside. The electrode plate 4b1 and the radiator 4b2 are spaced apart from each other and arranged in parallel when viewed from above, but a bent portion BP2 is provided at one end of the electrode plate 4b1. The bent portion BP2 has an inclination that becomes higher on one end side and lowers on the frame body 4b0 side. As a result, there is a height difference between the electrode plate 4b1 and the radiator 4b2.

[0023] The heat sink 4b2 carries the power semiconductor element 1b and the power semiconductor element 11b, and the end portion on the side where the power semiconductor element 1b is carried is partially narrowed and integrated with the frame body 4b0.

[0024] like Figure 3 As shown, the frame 4a is composed of a frame body 4a0 having a defined outline of the frame 4a, an electrode plate 4a1, and a heat sink 4a2. The frame body 4a0 is a frame having a rectangular shape when viewed from above, and the electrode plate 4a1 is extended inward from one side of the frame body 4a0. The electrode plate 4a1 is connected to the heat sink 4a2 arranged in parallel when viewed from above through a bent portion BP1.

[0025] The bent portion BP1 has an inclination that becomes higher on the electrode plate 4a1 side and lower on the heat sink 4a2 side. Therefore, there is a height difference between the heat sink 4a2 and the electrode plate 4a1. The heat sink 4a2 carries the power semiconductor element 1a and the power semiconductor element 11a. The frames 4a and 4b can be formed of aluminum (Al) or copper (Cu).

[0026] like Figure 2 and Figure 3 As shown, one side of the frame body 4b0 extending from the electrode plate 4b1 and the heat sink 4b2 of the frame 4b has a relative positional relationship with one side of the electrode plate 4a1 of the frame 4a. If the frame 4b is overlapped with the frame 4a, it becomes Figure 4 The structure shown.

[0027] Figure 4 express Figure 1 The structure of the region sealed by the mold resin RG of the single-phase inverter 100 shown is such that the power semiconductor elements 1a and 11a are arranged between the heat sink 4a2 and the electrode plate 4b1, and the power semiconductor elements 1b and 11b are arranged between the heat sink 4b2 and the electrode plate 4a1.

[0028] Figure 5 express Figure 4 The sectional view in the direction of the arrow of line AA, Figure 6 The arrow indicates a cross-sectional view along line BB.

[0029] like Figure 5 As shown, the power semiconductor elements 1a and 11a are bonded to the heat sink 4a2 via the solder 2a, and bonded to the upper electrode plate 4b1 via the solder (first solder).

[0030] In addition, if Figure 6 As shown, the power semiconductor elements 1b and 11b are bonded to the heat sink 4b2 via the solder 2b, and bonded to the upper electrode plate 4a1 via the solder 3b (second solder). Solder can be used as the solders 2a, 3a, 2b, and 3b, for example.

[0031] As described above, by arranging the electrode plate 4a1 and the radiator 4a2 on the frame 4a, arranging the electrode plate 4b1 and the radiator 4b2 on the frame 4b, and arranging the frame 4a and the frame 4b in an overlapping manner, it is not necessary to arrange the radiator and the electrode plate separately, and the number of parts can be reduced. In addition, since the solder 3a and 3b are joined in a state where the frame 4a and the frame 4b overlap, the number of manufacturing steps can be reduced.

[0032] In addition, since the frame shape can be freely designed, the degree of freedom in inductor design increases. In addition, heat dissipation can also be improved.

[0033] Furthermore, by making the outer shapes defined by the frame main body 4a0 of the frame 4a and the frame main body 4b0 of the frame 4b have the same dimensions, it becomes easy to align the frames when the two are overlapped, and the alignment accuracy is also improved.

[0034] Here, as the types of the power semiconductor elements 1a and 11a, for example, the power semiconductor element 1a is an IGBT, the power semiconductor element 11a is a high withstand voltage diode, and the power semiconductor element 11a is connected in anti-parallel with the power semiconductor element 1a.

[0035] As the types of the power semiconductor elements 1 b and 11 b , for example, the power semiconductor element 1 b is an IGBT, the power semiconductor element 11 b is a high withstand voltage diode, and the power semiconductor elements 11 b and 1 b are connected in anti-parallel.

[0036] Furthermore, by connecting the power semiconductor element 1 b and the power semiconductor element 1 a in series, an inverter in which the power semiconductor elements 11 b and 11 a operate as free wheeling diodes can be configured.

[0037] <Implementation method 2> Next, use Figure 7 and Figure 8 , embodiment 2 involved in the present disclosure is described. Figure 7 4 is a top view showing a state where the frame 4b and the frame 4a are overlapped. Figure 8 It is a plan view showing a state where the frame 4a and the frame 4b are combined, and shows a main part of the single-phase inverter 200 according to the second embodiment.

[0038] exist Figure 7 In the frame 4b, Figure 2 The embodiment 1 shown in the figure has the same shape, but the bent portion BP1 in the frame 4a for joining the electrode plate 4a1 and the heat sink 4a2 is not arranged along an entire long side of the heat sink 4a2, but is arranged to connect a part of one long side with a part of one long side of the electrode plate 4a1. Therefore, it can be said that the bent portion BP1 is arranged to form a slit between the electrode plate 4a1 and the heat sink 4a2.

[0039] like Figure 8 As shown, by forming a slit between the electrode plate 4a1 and the heat sink 4a2, the gap between the heat sink 4b2 and the heat sink 4a2 can be utilized.

[0040] Fig. 9 Yes Figure 8 The schematic cross-sectional view of the single-phase inverter 200 formed by combining the frame 4a and the frame 4b shown in FIG. Figure 8 Cross-sectional view in the direction of the arrow on line CC.

[0041] exist Figure 8In the embodiment, the cooling fin 6 is mounted on the single-phase inverter 200 sealed with the molding resin RG, but by forming a slit between the electrode plate 4a1 and the heat sink 4a2, a through hole TH penetrating the molding resin RG in the thickness direction can be provided between the electrode plates 4b1 and 4a1, and between the heat sinks 4a2 and 4b2. The single-phase inverter 200 can be mounted on the cooling fin 6 by passing the screw 7 through the through hole TH. In this way, in the single-phase inverter 200, a position for the screw 7 to pass through can be ensured.

[0042] <Implementation method 3> Next, use Fig.10 and Fig.11 , embodiment 3 involved in the present disclosure is described. Fig.10 4 is a top view showing a state where the frame 4b and the frame 4a are overlapped. Fig.11 It is a plan view showing a state where the frame 4a and the frame 4b are combined, and shows a main part of the single-phase inverter 300 according to the second embodiment.

[0043] exist Fig.10 In the frame 4b, Figure 2 The embodiment 1 shown in the figure has the same shape, but the bent portion BP1 in the frame 4a for connecting the electrode plate 4a1 and the heat sink 4a2 is not arranged along an entire long side of the heat sink 4a2, but is arranged to connect two parts on one long side that are far away from each other and two parts on one long side that are far away from each other. Therefore, it can be said that the bent portion BP1 is arranged to form an opening between the electrode plate 4a1 and the heat sink 4a2.

[0044] like Fig.11 As shown, by forming an opening between the electrode plate 4a1 and the heat sink 4a2, the gap between the heat sink 4b2 and the heat sink 4a2 can be utilized.

[0045] As used in implementation 2 Fig. 9 As described above, the method used is the position through which the screws pass when the cooling fins are installed on the single-phase inverter 300. In addition, compared with the case where a slit is formed between the electrode plate 4a1 and the heat sink 4a2, the engagement between the electrode plate 4a1 and the heat sink 4a2 becomes stronger, and the shape of the electrode plate 4a1 can be stabilized.

[0046] <Implementation method 4> Next, use Figure 12 to Figure 16 , embodiment 4 involved in the present disclosure is described. Fig.12 and Fig.13 4 are top views respectively showing a frame 4b and a frame 4a used to manufacture a single-phase inverter 400 according to the fourth embodiment. Fig.144 is a top view showing a state where the frame 4a and the frame 4b are combined, and shows the main parts of the single-phase inverter 400 according to the fourth embodiment. Figure 12 to Figure 16 In the embodiment 1, Figure 2 to Figure 6 The same structures are denoted by the same reference numerals, and repeated descriptions are omitted.

[0047] like Fig.12 As shown, the frame 4b includes a frame body 4b0 defining the outline of the frame 4b, an electrode plate 4b1, a heat sink 4b2, and a relay terminal 4b3 (second relay terminal).

[0048] The frame body 4b0 is a frame having a rectangular shape when viewed from above, and the electrode plate 4b1, the heat sink 4b2 and a plurality of relay terminals 4b3 are arranged to extend inward from one side of the frame body 4b0. A terminal hole 4bh is provided at one end of the electrode plate 4b1 at a position closer to the frame body 4b0 than the bent portion BP2. In addition, in the heat sink 4b2, the end on the side where the power semiconductor element 1b is mounted is locally narrowed in width and becomes one with the frame body 4b0, and a terminal hole 4bh is provided at a position on one side of the frame body 4b0. The portion provided with the terminal hole 4bh functions as the main terminal of the so-called single-phase inverter 400, and the terminal hole 4bh functions as a mounting hole for connecting to external wiring. A plurality of relay terminals 4b3 extend to the vicinity of the power semiconductor element 1b on the heat sink 4b2 when viewed from above.

[0049] like Fig.13 As shown, the frame 4a includes a frame body 4a0 defining the outline of the frame 4a, an electrode plate 4a1, a heat sink 4a2, and a plurality of relay terminals 4a3 (first relay terminals).

[0050] The frame body 4a0 is a frame having a rectangular shape when viewed from above, and the electrode plate 4a1 and a plurality of relay terminals 4a3 are arranged to extend inward from one side of the frame body 4a0. A terminal hole 4ah is provided at one end of the electrode plate 4a1, at a position on one side of the frame body 4a0. The portion provided with the terminal hole 4ah functions as a main terminal of the so-called single-phase inverter 400, and the terminal hole 4ah functions as a mounting hole for connecting to external wiring. The plurality of relay terminals 4b3 extend to the vicinity of the power semiconductor element 1a on the heat sink 4a2 when viewed from above. The plurality of relay terminals 4a3 function as terminals for lead connection to the control terminal on the upper surface of the power semiconductor element 1a.

[0051] like Fig.12 and Fig.13As shown, one side of the frame body 4b0 from which the electrode plate 4b1, the heat sink 4b2 and the plurality of relay terminals 4b3 of the frame 4b extend has a relative positional relationship with one side from which the electrode plate 4a1 and the plurality of relay terminals 4a3 of the frame 4a extend. If the frame 4b is overlapped with the frame 4a, it becomes Fig.14 The structure shown.

[0052] Fig.14 express Figure 1 The structure of the region sealed by the mold resin RG of the single-phase inverter 100 shown is such that the power semiconductor elements 1a and 11a are arranged between the heat sink 4a2 and the electrode plate 4b1, and the power semiconductor elements 1b and 11b are arranged between the heat sink 4b2 and the electrode plate 4a1.

[0053] Fig.15 express Fig.14 The sectional view in the direction of the arrow of line AA, Fig.16 The arrow indicates a cross-sectional view along line BB.

[0054] like Fig.15 As shown, the power semiconductor elements 1a and 11a are bonded to the heat sink 4a2 via the solder 2a, and bonded to the upper electrode plate 4b1 via the solder 3a.

[0055] In addition, if Fig.16 As shown, the power semiconductor elements 1b and 11b are bonded to the heat sink 4b2 via the solder 2b, and bonded to the upper electrode plate 4a1 via the solder 3b.

[0056] As described above, by providing multiple relay terminals 4a3 and portions functioning as main terminals on the frame 4a, and providing multiple relay terminals 4b3 and portions functioning as main terminals on the frame 4b, the number of components required for assembling the single-phase inverter 400 can be reduced, thereby improving productivity.

[0057] In addition, if Fig.12 As shown, a structure is shown in which a plurality of relay terminals 4b3 of the frame 4b extend to the vicinity of the power semiconductor element 1b on the heat sink 4b2 in a plan view. In this case, by using the power semiconductor element 1b near the plurality of relay terminals 4b3 as an IGBT or MOSFET, and using the plurality of relay terminals 4b3 as terminals for wire bonding with the control terminals of the IGBT or MOSFET, wire bonding becomes easy, thereby improving productivity. The power semiconductor element 11b becomes a high withstand voltage diode.

[0058] Likewise, Fig.13As shown, a structure is shown in which a plurality of relay terminals 4a3 of the frame 4a extend to the vicinity of the power semiconductor element 1a on the heat sink 4a2 in a plan view. In this case, by using the power semiconductor element 1a near the plurality of relay terminals 4a3 as an IGBT or MOSFET, and using the plurality of relay terminals 4a3 as terminals for wire bonding to the control terminals of the IGBT or MOSFET, wire bonding becomes easy, thereby improving productivity. The power semiconductor element 11b becomes a high withstand voltage diode.

[0059] <Implementation method 5> Next, use Fig.17 and Fig.18 , embodiment 5 involved in the present disclosure is described. Fig.17 1 is a cross-sectional view showing a cross-sectional structure of a heat sink 4a2 constituting a single-phase inverter 500 according to the fifth embodiment. A groove GR (first groove) for positioning the power semiconductor elements 1a and 11a is provided on the semiconductor element mounting surface of the heat sink 4a2.

[0060] The groove GR is formed to a depth and size that prevents the power semiconductor elements 1a and 11a disposed on the solder 2a from deviating from the solder 2a. The groove GR is provided in a direction orthogonal to the arrangement direction of the power semiconductor elements 1a and 11a, and has a depth that can accommodate the solder 2a and also accommodate a portion of the power semiconductor elements 1a and 11a.

[0061] By providing the groove GR, it is possible to improve the positioning accuracy when the power semiconductor elements 1a and 11a are arranged on the solder 2a, and prevent the power semiconductor elements 1a and 11a from being displaced from the solder 2a.

[0062] exist Fig.17 , an example of providing a groove GR on the heat sink 4a2 is shown, but a groove GR (second groove) may be provided on the heat sink 4b2 to improve the positioning accuracy of the power semiconductor elements 1b and 11b and prevent the deviation of the power semiconductor elements 1b and 11b.

[0063] Fig.18 4a2 is a cross-sectional view showing a structure in which a protrusion PJ is provided on the semiconductor element mounting surface of the heat sink 4a2 instead of the groove GR. Fig.18 As shown in FIG. 1 , the protrusion PJ is formed to prevent the power semiconductor elements 1a and 11a disposed on the solder 2a from deviating from the solder 2a. In a plan view, the protrusion PJ is provided on the outside of each of the power semiconductor elements 1a and 11a, and its height exceeds the thickness of the solder 2a and reaches a part of the thickness of the power semiconductor elements 1a and 11a. Fig.18In the embodiment, the protrusions PJ are provided at the front and rear of each of the power semiconductor elements 1a and 11a, but may be provided at the left and right of each of the power semiconductor elements 1a and 11a, or may be provided at both the front and rear and the left and right.

[0064] Providing the protrusions PJ can improve the positioning accuracy when the power semiconductor elements 1a and 11a are arranged on the solder 2a, and can prevent the power semiconductor elements 1a and 11a from being displaced from the solder 2a.

[0065] exist Fig.18 , an example in which the protrusions PJ are provided on the heat sink 4a2 is shown, but the protrusions PJ may also be provided on the heat sink 4b2 to improve the positioning accuracy of the power semiconductor elements 1b and 11b and prevent the power semiconductor elements 1b and 11b from deviating.

[0066] <Implementation method 6> Next, as Embodiment 6 of the present disclosure, refer to Fig.19 The flowchart shown in Figure 20 to Figure 24 illustrate Figure 1 The manufacturing method of the single-phase inverter 100 is shown.

[0067] exist Fig.19 In step S1 shown in the figure, the frame is formed. Fig. 20 As shown, this is a process of preparing the frames 4a and 4b, and the frames 4a and 4b are formed by punching and bending. Fig. 20 The frames 4a and 4b shown are respectively Figure 3 The frame 4a and Figure 2 The frame 4b is shown in a state before a power semiconductor element is mounted.

[0068] Next, in step S2, the power semiconductor element is bonded to the heat sink using solder. Fig.21 As shown, this is a process of joining the power semiconductor elements 1a and 11a to the heat sink 4a of the frame 4a via the solder 2a (not shown), and joining the power semiconductor elements 1b and 11b to the heat sink 4b2 of the frame 4b via the solder 2b (not shown), and is a process of melting the solder. Fig.21 The frames 4a and 4b shown are Figure 3 The frame 4a and Figure 2 In the state of the frame 4b shown, solder 3a is placed on the power semiconductor elements 1a and 11a, and solder 3b is placed on the power semiconductor elements 1b and 11b for the next step.

[0069] Next, in step S3, the two frames are overlapped and the electrode plates are joined using the solder on the power semiconductor element. Fig. 22As shown, this is a process of overlapping the frame 4a and the frame 4b, joining the solder 3a (not shown) on the power semiconductor elements 1a and 11a of the frame 4a to the electrode plate 4b1 of the frame 4b, and joining the solder 3b (not shown) on the power semiconductor elements 1b and 11b of the frame 4b to the electrode plate 4a1 of the frame 4a, which is a process of melting the solder. Fig. 22 The overlapping state of the frame 4a and the frame 4b shown is equivalent to Figure 4 Status shown.

[0070] Next, in step S4, the main terminal board is joined to the external connection frame provided with the relay terminal. Fig.23 As shown in FIG. 1 , this is a step of bonding the external frame OF to the frames 4 a and 4 b in a state where the power semiconductor element and the electrode plate have already been bonded.

[0071] The external frame OF is joined to the already overlapped frames 4a and 4b so as to be further overlapped, and is constituted by a frame body OF0 defining the outline of the external frame OF, main terminal plates T1, T2 and T3, and relay terminals RT1 and RT2.

[0072] The frame body OF0 is a rectangular frame in a plan view, and the main terminal board T1 and the relay terminal RT1 are provided extending inward from one side of the frame body OF0. The main terminal board T1 is provided at a position joined to the end of the electrode plate 4a1, and the relay terminal RT1 is provided at a position opposite to the power semiconductor element 1a.

[0073] In addition, the main terminal plates T2, T3 and the relay terminal RT2 are provided to extend inward from a side of the frame body OF0 opposite to a side from which the main terminal plate T1 and the relay terminal RT1 extend. The main terminal plate T2 is provided at a position joined to the end of the electrode plate 4b1, the main terminal plate T3 is provided at a position joined to the end of the heat sink 4b2, and the relay terminal RT2 is provided at a position opposite to the power semiconductor element 1b.

[0074] Ultrasonic (US) bonding can be used to bond the external frame OF to the frames 4a and 4b. Alternatively, bonding via brazing material may be used.

[0075] Next, in step S5, the relay terminal and the power semiconductor element are connected by wire bonding. Fig.24 As shown, this is a step of connecting the relay terminal RT1 and the control terminal of the power semiconductor element 1a through the lead wire WR, and connecting the relay terminal RT2 and the control terminal of the power semiconductor element 1b through the lead wire WR.

[0076] Then, unnecessary parts of the frame body OF0, frame bodies 4a0 and 4b0 are cut off, and the main part of the single-phase inverter 100 is sealed with a molding resin RG to obtain a Figure 1 A single-phase inverter 100 is shown.

[0077] <Implementation method 7> Next, use Fig.25 and Fig.26 , embodiment 7 involved in the present disclosure is described. Fig.25 4 is a top view showing a state where the frame 4b and the frame 4a are overlapped. Fig.26 It is a plan view showing a state where the frame 4a and the frame 4b are combined, and shows a main part of the single-phase inverter 600 according to the seventh embodiment.

[0078] exist Fig.25 In the frame 4b is with Figure 2 The frame 4a has the same shape as the embodiment 1 shown, but the frame 4a has a cutout portion NP where a part of the frame body 4a is cut out. The cutout portion NP is provided at a position where the end of the electrode plate 4b1 of the frame 4b engages with the frame body 4a0 when the frame 4a and the frame 4b are combined. Therefore, when the frame 4a and the frame 4b are overlapped and joined, the end of the frame body 4a0 and the electrode plate 4b1 do not overlap and can be easily joined.

[0079] <Implementation method 8> Next, use Fig. 27 and Fig.28 , embodiment 8 involved in the present disclosure is described. Fig. 27 4 is a top view showing a state where the frame 4b and the frame 4a are overlapped. Fig.28 It is a plan view showing a state where the frame 4a and the frame 4b are combined.

[0080] like Fig. 27 As shown, the frame body 4b0 of the frame 4b has convex portions CV on both sides in the left-right direction parallel to the arrangement of the electrode plates 4b1 and the heat sink 4b2. The convex portions CV are provided at four corners of the frame body 4b0 and protrude toward the side where the frame 4a is overlapped.

[0081] On the other hand, Fig. 27 As shown in FIG. 1 , the frame body 4a0 of the frame 4a has openings OP on both sides in the left-right direction parallel to the arrangement of the electrode plate 4a1 and the heat sink 4a2. The openings OP are provided at four corners of the frame body 4a0, such as Fig.28 As shown in FIG. 1 , the convex portion CV is arranged at a position where the convex portion CV is inserted into the opening OP when the frame 4a is overlapped on the frame 4b. Therefore, the positioning accuracy when the frame 4a and the frame 4b are overlapped is improved.

[0082] <Implementation method 9> Next, use Fig.29 and Fig.30 , embodiment 9 involved in the present disclosure is described. Fig.29 4 is a top view showing a state where the frame 4b and the frame 4a are overlapped. Fig.30 It is a plan view showing a state where the frame 4a and the frame 4b are combined.

[0083] like Fig.29 As shown, the frame body 4b0 of the frame 4b has a plurality of dimples DP2 (second dimples) on both sides in the left-right direction parallel to the arrangement of the electrode plate 4b1 and the heat sink 4b2. The plurality of dimples DP2 are arranged in a row along the extending direction of each side on both sides in the left-right direction.

[0084] Similarly, the frame body 4a0 of the frame 4a also has a plurality of dimples DP1 (first dimples) on both sides in the left-right direction parallel to the arrangement of the electrode plate 4a and the heat sink 4a. The plurality of dimples DP1 are arranged in a row along the extending direction of each side on both sides in the left-right direction.

[0085] like Fig.30 As shown, the plurality of recesses DP1 and DP2 of the frames 4a and 4b are arranged to be recessed in the same direction at the overlapping positions when the frame 4a is overlapped on the frame 4b. Therefore, the positioning accuracy when the frame 4a and the frame 4b are overlapped is improved.

[0086] <Implementation method 10> Next, use Fig.31 and Fig.32 , embodiment 10 involved in the present disclosure is described. Fig.31 This is a cross-sectional view showing a state where the frame 4a and the frame 4b are overlapped and the electrode plates are bonded with solder on the power semiconductor element, which is similar to that described in the first embodiment. Figure 5 The corresponding cross-sectional view is to illustrate the embodiment 6 Fig.19 FIG. 1 is a diagram of the process in step S3 of the flowchart shown.

[0087] like Fig.31 As shown in FIG. 1 , the process of melting the brazing material is performed while the overlapping frames 4a and 4b are fixed by the fixing jig JG. The fixing jig JG is composed of a lower fixing jig JD disposed on the lower side of the overlapping frames 4a and 4b, i.e., on the side of the heat sink 4a, and an upper fixing jig JU disposed on the upper side of the overlapping frames 4a and 4b, i.e., on the side of the electrode plate 4b1.

[0088] like Fig.31 As shown, the overlapping frames 4a and 4b are clamped by the lower fixing jig JD and the upper fixing jig JU, thereby preventing the frames 4a and 4b from shifting when the brazing material melts and improving the positioning accuracy of the electrode plate.

[0089] exist Fig.31 , the structure in which the entire overlapping frames 4a and 4b are clamped by the fixing jig JG is shown, but the present invention is not limited to this, and a structure in which only a part of the frame is clamped may be used.

[0090] Fig.32 FIG. 1 is a top view showing the fixing fixture JG clamping only a portion of the frame. Fig.32 , the structure in which the left and right frame bodies of the overlapping frames 4a and 4b are clamped by the lower fixing jig JD and the upper fixing jig JU is shown. The upper fixing jig JU is only arranged on the left and right frame bodies of the overlapping frames 4a and 4b. When such a fixing jig JG is used, the next wire bonding process can also be carried out in a state where the overlapping frames 4a and 4b are clamped by the fixing jig JG.

[0091] Examples of the material of the fixing jig JG include carbon which can withstand the temperature when the brazing material is melted and is less deformed.

[0092] <Semiconductor materials for power semiconductor devices> The power semiconductor elements 1a, 1b, 11a and 11b are not limited to silicon semiconductor elements using silicon (Si), but may be wide bandgap semiconductor elements such as silicon carbide semiconductor elements using silicon carbide (SiC) and gallium nitride semiconductor elements using gallium nitride (GaN). Compared with silicon semiconductor elements, wide bandgap semiconductor elements can be miniaturized, have excellent voltage resistance, allow a higher current density, and have higher heat resistance, so they can also operate at high temperatures and achieve high efficiency.

[0093] <Modification> In the above-described embodiments 1 to 10, the present disclosure is applied to a single-phase inverter, but is not limited thereto and may be applied to a three-phase inverter in which a single-phase inverter is combined into three phases, or to a converter for power regeneration.

[0094] The present disclosure can freely combine the various embodiments within the scope of the disclosure, or can appropriately modify or omit the various embodiments.

[0095] The present disclosure has been described in detail, but the above description is only an example in all aspects, and the present disclosure is not limited thereto. It should be understood that countless modifications not shown in the examples are conceivable without departing from the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first heat sink equipped with a first semiconductor element; a first electrode plate connected to the first heat sink via an inclined bent portion; a second heat sink equipped with a second semiconductor element; as well as a second electrode plate provided with a height difference with the second radiator, The first electrode plate is arranged at a position higher than the first heat sink, The second electrode plate is arranged at a position higher than the second radiator. The first electrode plate and the second electrode plate are arranged at the same height, The first radiator and the second radiator are arranged at the same height, The second electrode plate is arranged above the first radiator. The first electrode plate is arranged above the second radiator. The first semiconductor element is bonded to the first heat sink and the second electrode plate, and the second semiconductor element is bonded to the second heat sink and the first electrode plate.

2. The semiconductor device according to claim 1, wherein The first heat sink and the first electrode plate are in a side-by-side position relationship in a plan view, The bent portion is disposed along an entire side of the first heat sink opposite to the first electrode plate.

3. The semiconductor device according to claim 1, wherein The first heat sink and the first electrode plate are in a side-by-side position relationship in a plan view, The bent portion is provided at a portion of a side of the first heat sink opposite to the first electrode plate, and a slit is formed between the first heat sink and the first electrode plate.

4. The semiconductor device according to claim 1, wherein: The first heat sink and the first electrode plate are in a side-by-side position relationship in a plan view, The bent portion is provided at a first portion and a second portion of the first heat sink that are opposite to the first electrode plate and are spaced apart from each other, and an opening is formed between the first heat sink and the first electrode plate.

5. The semiconductor device according to claim 1, wherein: The first heat sink and the first electrode plate are in a side-by-side position relationship in a plan view, The semiconductor device further includes a plurality of first relay terminals arranged side by side with the first heat sink in a plan view, The first semiconductor element is arranged on the first heat sink at a position close to the plurality of first relay terminals. The second heat sink and the second electrode plate are in a side-by-side position relationship in a plan view. The semiconductor device further includes a plurality of second relay terminals arranged side by side with the second heat sink in a plan view, The second semiconductor element is arranged on the second heat sink at a position close to the plurality of second relay terminals.

6. The semiconductor device according to claim 5, wherein: The first semiconductor element and the second semiconductor element are IGBTs or MOSFETs.

7. The semiconductor device according to claim 1, wherein The first heat sink has a first groove matching the size of the first semiconductor element in a plan view at a portion where the first semiconductor element is mounted. The second heat sink has a second groove matching the size of the second semiconductor element in a plan view at a portion where the second semiconductor element is mounted.

8. The semiconductor device according to claim 1, wherein The first heat sink has a plurality of first protrusions at a portion where the first semiconductor element is mounted, and the plurality of first protrusions are provided at positions outside the first semiconductor element in a plan view. The second heat sink has a plurality of second protrusions at a portion where the second semiconductor element is mounted, and the plurality of second protrusions are provided at positions located outside the first semiconductor element in a plan view.

9. The semiconductor device according to claim 1, wherein: The first semiconductor element is a silicon carbide semiconductor element.

10. A method for manufacturing a semiconductor device, characterized in that: Using the first and second frames, The first frame has a first heat sink to which a first semiconductor element is bonded, and a first electrode plate connected to the first heat sink via an inclined bent portion. The second frame includes a second heat sink to which a second semiconductor element is bonded, and a second electrode plate provided with a height difference with the second heat sink. The first electrode plate is arranged at a position higher than the first heat sink, The second electrode plate is arranged at a position higher than the second radiator. The first electrode plate and the second electrode plate are arranged at the same height, The first radiator and the second radiator are arranged at the same height, The second electrode plate is arranged above the first radiator. The first electrode plate is arranged above the second radiator. The method for manufacturing a semiconductor device comprises: (a) overlapping the first frame and the second frame so that the first semiconductor element is sandwiched between the first heat sink and the second electrode plate, and the second semiconductor element is sandwiched between the second heat sink and the first electrode plate; and (b) A step of melting a first solder disposed between the first semiconductor element and the second electrode plate and a second solder disposed between the second semiconductor element and the first electrode plate to bond the first semiconductor element to the second electrode plate and to bond the second semiconductor element to the first electrode plate.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The first frame has a cutout portion at a portion that contacts the second electrode plate when the first frame and the second frame are overlapped.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The second frame has a plurality of protrusions. The first frame has a plurality of openings provided at positions corresponding to the plurality of protrusions of the second frame. The step (a) is to overlap the first frame and the second frame so that the plurality of protrusions are inserted into the plurality of openings.

13. The method for manufacturing a semiconductor device according to claim 10, wherein: The second frame has a plurality of second recesses, The first frame has a plurality of first recesses disposed at positions corresponding to the plurality of second recesses of the second frame, The step (a) overlaps the first frame and the second frame in such a manner that the plurality of first recesses overlap the plurality of second recesses.

14. The method for manufacturing a semiconductor device according to claim 10, wherein: The step (b) includes a step of pressing the first frame and the second frame stacked together vertically using a fixing jig.

15. The method for manufacturing a semiconductor device according to claim 10, wherein: The first frame and the second frame have the same outer dimensions.

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