Semiconductor device, electronic apparatus, and method for manufacturing semiconductor device

Abstract

A semiconductor device according to one embodiment of the present disclosure includes: a semiconductor substrate having a first insulating layer and a plurality of first terminals provided in the first insulating layer; and semiconductor elements stacked on the semiconductor substrate, each of the semiconductor elements having a second insulating layer and a plurality of second terminals provided in the second insulating layer and connected to the plurality of first terminals, respectively. The first insulating layer or the second insulating layer has a third insulating layer formed of a material different from a material of the first insulating layer and joining the semiconductor substrate and the semiconductor element.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device. Background Art

[0002] In various semiconductor devices such as solid-state imaging devices, light-emitting devices, and storage devices, chip-on-wafer (CoW) technology is used (for example, Patent Document 1). In this CoW technology, chips are laminated and bonded on a wafer. The chip has a plurality of pads (for example, Cu pads), each of which serves as a terminal. Chips are undergoing miniaturization, and due to the influence of chip miniaturization, the pitch of each pad is narrowed. Prior art literature Patent Literature

[0003] [Patent Document 1] International Publication No. 2019 / 087764 Summary of the invention Technical problem to be solved by the invention

[0004] When the bonding strength on the bonding surface between the chip and the wafer is insufficient, bonding failure, film elevation, etc. may occur during the heating process of the subsequent process. The pad area and the insulating area are mixed on the bonding surface, and the bonding strength tends to be insufficient at the portion where the insulating area occupies a large area. For example, when the chip is small, the bonding strength tends to decrease compared to the case where the chip is large.

[0005] Therefore, the present disclosure provides a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device capable of improving bonding strength. Technical means to solve technical problems

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate, which includes a first insulating layer and a plurality of first terminals arranged on the first insulating layer; and a semiconductor element stacked on the semiconductor substrate, the semiconductor element including a second insulating layer and a plurality of second terminals arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein the first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from the material of the first insulating layer and bonding the semiconductor substrate and the semiconductor element.

[0007] An electronic device according to one aspect of the present disclosure includes a semiconductor device, which includes: a semiconductor substrate, which includes a first insulating layer and a plurality of first terminals arranged on the first insulating layer; and a semiconductor element stacked on the semiconductor substrate, the semiconductor element including a second insulating layer and a plurality of second terminals arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein the first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from the material of the first insulating layer and bonding the semiconductor substrate and the semiconductor element.

[0008] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes: stacking a semiconductor element having a second insulating layer and a plurality of second terminals on a semiconductor substrate having a first insulating layer and a plurality of first terminals arranged on the first insulating layer, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein stacking the semiconductor element on the semiconductor substrate includes joining the semiconductor substrate and the semiconductor element through a third insulating layer, the third insulating layer being formed of a material different from the first insulating layer and being contained in the first insulating layer or the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment. Figure 2 is a plan view showing a configuration example of the semiconductor device according to the first embodiment. Figure 3 is a diagram showing stress relaxation of the joining surface materials according to the first embodiment. Figure 4 1 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. Figure 5 1 is a diagram showing a manufacturing process of the semiconductor element according to the first embodiment. Figure 6 is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment. Figure 7 2 is a diagram showing a manufacturing process of a semiconductor device according to the second embodiment. Figure 8 is a diagram showing a manufacturing process of a semiconductor element according to the second embodiment. Fig. 9 is a cross-sectional view showing a configuration example of a semiconductor device according to a third embodiment. Fig.10 2 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment. Fig.11 2 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment. Fig.12 is a cross-sectional view showing a configuration example of a semiconductor device according to a fourth embodiment. Fig.13 2 is a diagram showing a manufacturing process of a semiconductor device according to a fourth embodiment. Fig.14 is a cross-sectional view showing a configuration example of a semiconductor device according to a fifth embodiment. Fig.15 is a plan view showing a configuration example of a semiconductor device according to a fifth embodiment. Fig.16 1 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. Fig.17 1 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. Fig.18 is a cross-sectional view showing a configuration example of a semiconductor device according to a sixth embodiment. Fig.19 is a plan view showing a configuration example of a semiconductor device according to a sixth embodiment. Fig. 20 2 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. Fig.21 2 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment. Fig. 22 is a perspective view showing a configuration example of a semiconductor device according to a seventh embodiment. Fig.23 is a cross-sectional view showing a configuration example of a semiconductor device according to a seventh embodiment. Fig.24 is a cross-sectional view showing a circuit example of a semiconductor device according to a seventh embodiment. Fig.25 is a diagram showing a circuit example of a comparator according to the seventh embodiment. Fig.26 is a diagram showing an output example of a comparator according to the seventh embodiment. Fig. 27 is a perspective view showing a configuration example of a semiconductor device according to an eighth embodiment. Fig.28 is a cross-sectional view showing a configuration example of a semiconductor device according to an eighth embodiment. Fig.29 is a perspective view showing exemplary areas of a pixel region and a connection region of a semiconductor device according to an eighth embodiment. Fig.30is a plan view showing a configuration example of wiring of a semiconductor device according to an eighth embodiment. Fig.31 is a diagram showing a circuit example of a semiconductor device according to an eighth embodiment. Fig.32 is a diagram showing another circuit example of the semiconductor device according to the eighth embodiment. Fig.33 : are diagrams showing application examples using the semiconductor device according to each embodiment. Fig.34 is a diagram showing a configuration example of an image pickup device according to an application example. Fig.35 : is a diagram showing a configuration example of a distance measuring device according to an application example. DETAILED DESCRIPTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the apparatus, device, method, etc. according to the present disclosure are not limited to the embodiments. In the following embodiments, the same parts are basically given the same reference numerals to omit redundant descriptions.

[0011] In the following description, one or more embodiments (including examples and variations) may be implemented independently. On the other hand, at least some of the multiple embodiments described below may be appropriately combined with at least some of the other embodiments. Multiple embodiments may include novel features that are different from each other. Therefore, multiple embodiments can help solve different objects or problems and can exhibit different effects. Note that the effects in each embodiment are merely exemplary and not limiting, and other effects may be provided.

[0012] In addition, the drawings cited in the following description are drawings for the purpose of facilitating the description and understanding of the embodiments of the present disclosure, and for the sake of clarity, the shapes, sizes, ratios, etc. shown in the drawings may be different from the actual ones. In addition, the elements and the like shown in the drawings may be appropriately modified in design in consideration of the following description and known technologies. In addition, in the following description, the vertical direction of the stacked structure of the elements and the like corresponds to the relative direction when, for example, the surface of the substrate on which the elements are disposed faces upward, and may be different from the vertical direction according to the actual gravitational acceleration.

[0013] The present disclosure will be described in the following order. 1. First Embodiment 1-1. Example of semiconductor device configuration 1-2. Method for manufacturing semiconductor device 1-3. Method for manufacturing semiconductor element 2. Second Embodiment 2-1. Example of semiconductor device configuration 2-2. Method for manufacturing semiconductor device 2-3. Method for manufacturing semiconductor element 3. Third embodiment 3-1. Example of semiconductor device configuration 3-2. Method for manufacturing semiconductor device 4. Fourth embodiment 4-1. Example of semiconductor device configuration 4-2. Method for manufacturing semiconductor device 5. Fifth embodiment 5-1. Example of semiconductor device configuration 5-2. Method for manufacturing semiconductor device 6. Sixth embodiment 6-1. Example of semiconductor device configuration 6-2. Method for manufacturing semiconductor device 7. Seventh embodiment 7-1. Example of semiconductor device configuration 8. Eighth Embodiment 8-1. Example of semiconductor device configuration 9. Functions and effects according to various embodiments 10. Application Examples 11. Electronic devices according to application examples 11-1. Camera device 11-2. Distance measuring device 12. Other embodiments 13. Appendix

[0014] <1. First Embodiment> <1-1. Example of configuration of semiconductor device> Will refer to Figures 1 to 3 A configuration example of a semiconductor device 1A according to the present embodiment will be described. Figure 1 is a cross-sectional view showing a configuration example of a semiconductor device 1A according to the present embodiment. Figure 2 1 is a plan view showing a configuration example of a semiconductor device 1A according to the present embodiment. Figure 3 is a diagram showing stress relaxation of bonding surface materials between adjacent chips.

[0015] like Figure 1 As shown, the semiconductor device 1A according to the present embodiment includes a semiconductor substrate 10 and a plurality of semiconductor elements (semiconductor substrates) 20. Examples of the semiconductor device 1A include various semiconductor devices such as a solid-state imaging device, a light-emitting device, and a storage device. Note that Figure 1 is an example, and in Figure 1 The semiconductor device 1A shown is provided with necessary components in order to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0016] The semiconductor substrate 10 includes a substrate 11, a plurality of circuit elements 12, a plurality of terminals (first terminals) 13, and an insulating layer (first insulating layer) 14. Each circuit element 12 is implemented by, for example, various elements (such as transistors and wiring) constituting a circuit. These circuit elements 12 are provided on the substrate 11. Each terminal 13 is implemented by a pad such as a Cu pad. These terminals 13 are connected to the corresponding circuit elements 12 and provided on the substrate 11, and the end surface of the terminal 13 (the surface on one side of the semiconductor element 20) is exposed from the insulating layer 14. The insulating layer 14 is provided to be stacked on the substrate 11 to ensure the insulation of each circuit element 12 and the terminal 13.

[0017] The insulating layer 14 includes two insulating layers 14a and 14b. The insulating layers 14a and 14b are stacked on the substrate 11 and are formed of the same material. For example, SiO2 is used as the material of these insulating layers 14a and 14b. The insulating layer 14b is located on the surface (bonding surface) of the insulating layer 14 on the semiconductor element 20 side and serves as an adhesive layer that bonds the semiconductor substrate 10 and the semiconductor element 20 together.

[0018] In the semiconductor substrate 10 described above, there are portions where the pitch (separation distance) of the terminals 13 is wide and portions where the pitch is narrow. Figure 1 In the example of FIG. 1 , the pitch (bonding pitch) of the terminals 13 decreases from left to right in the plane direction of the semiconductor substrate 10 . The pitch is set according to the semiconductor element 20 .

[0019] Each semiconductor element 20 includes a substrate 21, a plurality of circuit elements 22, a plurality of terminals (second terminals) 23, and an insulating layer (second insulating layer) 24. The circuit elements 22 are implemented by, for example, various elements (such as transistors and wiring) constituting a circuit. These circuit elements 22 are provided on the substrate 21. Each terminal 23 is implemented by a pad such as a Cu pad. These terminals 23 are connected to the corresponding circuit elements 22 and provided on the substrate 21, and the end faces (surfaces located on one side of the semiconductor substrate 10) of the terminals 23 are exposed from the insulating layer 24. The insulating layer 24 is provided to be stacked on the substrate 21 to ensure insulation of the circuit elements 22 and the terminals 23.

[0020] The semiconductor element 20 includes a plurality of semiconductor elements (20A, 20B, and 20C) having different sizes, pitches of terminals 23, etc. Figure 1 In the example of FIG. 2 , in the semiconductor element 20 , the pitch of the terminals 23 becomes narrower from left to right in the plane direction of the semiconductor substrate 10 . Figure 2As shown, the semiconductor element 20 having the largest planar size and pitch is defined as a first semiconductor element 20A, the element 20 having the second largest planar size and pitch is defined as a second semiconductor element 20B, and the semiconductor element 20 having the third largest planar size and pitch (the smallest planar size and spacing) is defined as a third semiconductor element 20C. For example, the semiconductor elements 20A, 20B, and 20C are semiconductor elements including logic circuits or memory circuits.

[0021] The insulating layer 24 of the first semiconductor element 20A includes two insulating layers 24a and 24b. Each of the insulating layers 24a and 24b is stacked on the substrate 21 and is formed of the same material. For example, SiO2 is used as the material of these insulating layers 24a and 24b. The insulating layer 24b is located on the surface (bonding surface) of the insulating layer 24 on the semiconductor substrate 10 side and serves as a bonding layer for bonding the semiconductor substrate 10 and the first semiconductor element 20A.

[0022] The insulating layer 24 of the second semiconductor element 20B and the third semiconductor element 20C includes three insulating layers 24a, 24b and 24c, respectively. These insulating layers 24a, 24b and 24c are stacked on the substrate 21. The insulating layers 24a and 24b are formed of the same material, and the insulating layer (third insulating layer) 24c is formed of a material different from the insulating layers 24a and 24b. In other words, a material different from the insulating layer 14b of the semiconductor substrate 10 is used. For example, SiO2 is used as the material of the insulating layers 24a and 24b. As the material of the insulating layer 24c, for example, SiN or SiCN is used. The insulating layer 24c is located on the surface (bonding surface) of the insulating layer 24 on the semiconductor substrate 10 side, and serves as a bonding layer for bonding the semiconductor substrate 10 and the semiconductor elements 20 (20B and 20C) together.

[0023] Here, since the insulating layer 24c is formed of at least a material different from the insulating layer 14b of the semiconductor substrate 10, the second semiconductor element 20B is bonded to the semiconductor substrate 10 by materials different from each other. Similarly, the third semiconductor element 20C is bonded to the semiconductor substrate 10 by materials different from each other. The insulating layer 24c of the second semiconductor element 20B and the insulating layer 24c of the third semiconductor element 20C may be made of the same material or different materials. Figure 1 In the example shown, the insulating layer 24b of the first semiconductor element 20A is made of the same material (eg, SiO2) as the insulating layer 14b of the semiconductor substrate 10. Therefore, the first semiconductor element 20A and the semiconductor substrate 10 are bonded by the same material.

[0024] In addition to SiN and SiCN, the material of the insulating layer 24c may also include SiO2, Si3N4, SiNxOy, SiOC, GeO2, Ge3N4, SnO2, B2O3, BN, SeO2, TeO2, TeO3, MgO, Mg3N2, Al2O3, AlN, TiO2, TiN, V2O5, MnO, MnO2, Mn2O3, Mn2O7, Mn3O4, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, Ni2O3, CuO, Cu2O, Cu3N, ZnO, CrN, Cr23C6, Cr3C, Cr7C3, Cr3C2, Mo3C2, TiC, Nb4C3 and Ta4C3, ZrC, HfC, V4C3, VC, W2C, WC, Fe3C, Fe7C3 or Fe2C.

[0025] Generally, when the bonding strength on the bonding surface where Cu (terminal material) and SiO2 (insulating material) coexist is insufficient, bonding failure or film bulging may occur during the heating process in the subsequent step. According to the size (chip size) of the semiconductor elements 20B and 20C and the density (pad density) of the terminals 23, the occurrence of blistering during heating can be suppressed by using a bonding film such as SiN or SiCN having a higher bonding strength than SiO2 for the insulating layer 24c. For example, the material of the insulating layer 24c is determined so that as the size of the semiconductor elements 20 (20A, 20B, 20C) or the pitch of the terminals 23 decreases, the bonding strength between the semiconductor substrate 10 and the semiconductor elements 20 (20A, 20B, and 20C) caused by the insulating layer 24c increases. For the first semiconductor element 20A having a larger size and a larger number of terminals 23 than the semiconductor elements 20B and 20C, that is, the first semiconductor element 20A having no problem in bonding strength, the insulating film 24b of the SiO2 layer having a lower wiring capacitance and superior production cost is directly used as the bonding surface. Experiments and the like have confirmed that, compared with the case of using SiO 2 , by using SiN, SiCN, or the like for the insulating layer 24 c of the semiconductor elements 20B and 20C, it is possible to approximately double the bonding strength and reduce the blistering area from about 30 mm to about 0.2 mm.

[0026] In addition, when SiO2 is used for insulation of the terminals 23 (narrow pitch pads) with narrow pitch, the withstand voltage between the terminals 23 (between pads and pads) may be insufficient. For example, in the CoW of each semiconductor element 20B and 20C having each terminal 23 with narrow pitch, such as advanced logic, in view of the concern of reduced reliability due to insufficient withstand voltage between each terminal 23, a bonding film (such as SiN and SiCN) corresponding to the required withstand voltage is used as the insulating layer 24c. In addition, the withstand voltage between the terminals 23 can be adjusted by changing the film thickness (length in the direction orthogonal to the plane) of the insulating layer 24c. For example, the film thickness of the insulating layer 24c is determined so that the insulation resistance between the terminals 23 increases as the pitch of the terminals 23 decreases. Since the first semiconductor element 20A has terminals 23 with wide pitch, there is no problem with withstand voltage, so the insulating film 24b of the SiO2 layer with low wiring capacitance and superior production cost is directly used as the bonding surface.

[0027] Furthermore, when the adjacent semiconductor elements 20 (chips) have the same bonding material, deformation caused by the difference in the coefficient of thermal expansion (CTE) of each element material of the different elements cannot be controlled. Therefore, the deformation caused by the above CTE can be mitigated by changing the film type, film thickness, etc. of the insulating layer 24c with respect to the CTE, size, and layout of the semiconductor elements 20B and 20C.

[0028] For example, Figure 3 As shown in the left figure of , each chip A1 (semiconductor element 20) manufactured according to the normal process is bonded to the semiconductor element substrate 10 and then covered with an oxide film B1 (e.g. SiO). Due to the temperature increase (about 350°C) when the oxide film B1 is formed, each chip A1 expands due to the CTE of the chip A1 itself, and is fixed by the oxide film B1 in this state. Figure 3 As shown in the left figure, the expanded chip A1 tends to shrink when cooled at room temperature, but because the chip A1 is fixed by the oxide film B1, Figure 3 The stress in the arrow direction in the left figure remains in the chip A1. The magnitude of the stress is different. The above strain due to the residual stress is transmitted to the semiconductor substrate 10 side bonded to the chip A1, and OCL deviation (an example of an additional member) and fluctuation of transistor characteristics (an example of the circuit element 22) may occur. Therefore, as Figure 3 As shown in the right figure, in the chip A2 having the insulating layer 24c as described above, the above-mentioned residual stress can be reduced by changing the film type, film thickness, etc. of the insulating layer 24c (for example, making the stress of chip A1 and the stress of chip A2 offset each other), thereby reducing the distortion of adjacent chips A1 and A2.

[0029] <1-2. Method for manufacturing semiconductor device> Will refer to Figure 4 A method for manufacturing the semiconductor device 1A according to the present embodiment will be described. Figure 4 1A is a diagram showing a manufacturing process of the semiconductor device 1A according to the present embodiment.

[0030] like Figure 4 As shown, a semiconductor substrate 10 is prepared, and a first semiconductor element 20A, a second semiconductor element 20B, and a third semiconductor element 20C are prepared. The semiconductor substrate 10 is, for example, a wafer, and is formed based on a general manufacturing process. Figure 4 The example in FIG. 1 is a part of a wafer, namely, the semiconductor substrate 10. In addition, the first semiconductor element 20A is cut out and singulated from the wafer W1, the second semiconductor element 20B is cut out and singulated from the wafer W2, and the third semiconductor element 20C is cut out and singulated from the wafer W3.

[0031] The first semiconductor element 20A, the second semiconductor element 20B, and the third semiconductor element 20C are bonded to the semiconductor substrate 10 by the chip on wafer (CoW) technology (CoW bonding). At this point, the semiconductor device 1A is completed. Specifically, a plurality of first semiconductor elements 20A, a plurality of second semiconductor elements 20B, and a plurality of third semiconductor elements 20C are bonded to a wafer as the semiconductor substrate 10, and a plurality of semiconductor devices 1A are cut out from the wafer and singulated. Note that before or after the semiconductor device 1A is cut into individual pieces, necessary components are provided in the semiconductor device 1A to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device. For example, in a solid-state imaging device, necessary components such as an on-chip lens, an on-chip color filter, and a supporting substrate are provided in the semiconductor device 1A. For example, the bonding between the terminal 13 of the semiconductor substrate 10 and the terminal 23 of the semiconductor element 20 (20A, 20B, 20C) is achieved by Cu-Cu thermal diffusion bonding.

[0032] In the above-mentioned CoW bonding, the second semiconductor element 20B and the third semiconductor element 20C are bonded to the semiconductor substrate 10 through different materials. Specifically, the corresponding insulating layers 24c of the second semiconductor element 20B and the third semiconductor element 20C are bonded to the insulating layer 14b of the semiconductor substrate 10. These insulating layers 24c and the insulating layer 14b are formed of different materials. As a result, compared with the case where the insulating layer 24c and the insulating layer 14b are formed of the same material as in the usual case, the bonding strength can be improved, and the withstand voltage can be improved and the deformation can be suppressed. For example, the material of the insulating layer 24c can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc.

[0033] <1-3. Method for manufacturing semiconductor element> Reference Figure 5 The manufacturing process of the second semiconductor element 20B, that is, the wafer W2 including a plurality of second semiconductor elements 20B, will be described. Figure 5 is a diagram showing a manufacturing process of the second semiconductor element 20B according to the present embodiment. Figure 5 In the example of FIG. 2 , one second semiconductor element 20B is shown. Since the manufacturing process of the third semiconductor element 20C is similar to the manufacturing process of the second semiconductor element 20B, the description thereof will be omitted.

[0034] like Figure 5 As shown, an insulating layer 24a is stacked on a substrate 21, and a plurality of circuit elements 22 are provided on the insulating layer 24a. Next, an insulating layer 24b is stacked on the insulating layer 24a and the plurality of circuit elements 22, and an insulating layer 24c is stacked on the insulating layer 24b. Next, a photoresist layer (mask layer) 51 is stacked on the insulating layer 24c by photolithography, and the insulating layer 24c and the insulating layer 24b are processed by dry etching. Then, a photoresist layer (mask layer) 52 is stacked on the insulating layer 24c and the insulating layer 24b by photolithography, and a portion of each of the insulating layer 24b and the plurality of circuit elements 22 is processed by dry etching. Finally, these processed portions are filled with metal to form the terminal 23. In this way, a wafer W2 containing a plurality of second semiconductor elements 20B is completed, and the second semiconductor element 20B is cut out from the wafer W2. Thus, the second semiconductor element 20B is completed.

[0035] <2. Second Embodiment> <2-1. Example of configuration of semiconductor device> Will refer to Figure 6 A configuration example of the semiconductor device 1B according to the present embodiment will be described. Figure 6 1 is a cross-sectional view showing a configuration example of a semiconductor device 1B according to the present embodiment. In the present embodiment, a portion that is basically different from the first embodiment will be described.

[0036] like Figure 6As shown, in the semiconductor device 1B according to the present embodiment, the configurations of the second semiconductor element 20B and the third semiconductor element 20C are different from those of the first embodiment. In the second semiconductor element 20B and the third semiconductor element 20C according to the present embodiment, the insulating layer 24 includes two insulating layers 24a and 24c. For example, by increasing the thickness of the insulating layer (third insulating layer) 24c compared to the first embodiment, the deformation caused by the above-mentioned CTE can be reliably suppressed. Generally, since the plane size of the semiconductor element 20 is determined by a standard or the like, it is difficult to change the size, but the thickness of the insulating layer 24c can be changed relatively freely. Therefore, the thickness of the insulating layer 24c can be appropriately adjusted to reliably suppress the deformation caused by the above-mentioned CTE.

[0037] <2-2. Method for manufacturing semiconductor device> Will refer to Figure 7 A method for manufacturing the semiconductor device 1B according to the present embodiment will be described. Figure 7 1 is a diagram showing a manufacturing process of the semiconductor device 1B according to the present embodiment.

[0038] like Figure 7 As shown, similar to the first embodiment, a semiconductor substrate 10 is prepared, and a first semiconductor element 20A, a second semiconductor element 20B, and a third semiconductor element 20C are prepared. For example, the semiconductor substrate 10 is a wafer and is formed based on a general manufacturing process. Figure 7 In the example of FIG. 1 , a portion of a wafer, namely, a semiconductor substrate 10 is shown. In addition, a first semiconductor element 20A is cut out from a wafer W1 and singulated, a second semiconductor element 20B is cut out from a wafer W2 and singulated, and a third semiconductor element 20C is cut out from a wafer W3 and singulated.

[0039] As in the first embodiment, the first semiconductor element 20A, the second semiconductor element 20B, and the third semiconductor element 20C are bonded to the semiconductor substrate 10 by the CoW technology (CoW bonding). At this point, the semiconductor device 1B is completed. Specifically, a plurality of first semiconductor elements 20A, a plurality of second semiconductor elements 20B, and a plurality of third semiconductor elements 20C are bonded to a wafer as the semiconductor substrate 10, and the wafer is cut and singulated into a plurality of semiconductor devices 1B. Note that before or after the semiconductor device 1B is cut into a plurality of pieces, necessary components are provided in the semiconductor device 1B to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0040] In the above-mentioned CoW bonding, as in the first embodiment, the second semiconductor element 20B and the third semiconductor element 20C are bonded to the semiconductor substrate 10 through different materials. Specifically, the respective insulating layers 24c of the second semiconductor element 20B and the third semiconductor element 20C are bonded to the insulating layer 14b of the semiconductor substrate 10. These insulating layers 24c and the insulating layer 14b are formed of different materials. As a result, compared with the case where the insulating layer 24c and the insulating layer 14b are formed of the same material as in the usual case, the bonding strength can be improved, and further, the withstand voltage can be improved and the deformation can be suppressed. For example, the material of the insulating layer 24c can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc.

[0041] <2-3. Method for manufacturing semiconductor element> Will refer to Figure 8 The manufacturing process of the second semiconductor element 20B, that is, the wafer W2 including a plurality of second semiconductor elements 20B, will be described. Figure 8 is a diagram showing a manufacturing process of the second semiconductor element 20B according to the present embodiment. Figure 8 In the example of FIG. 2 , one second semiconductor element 20B is shown. Since the manufacturing process of the third semiconductor element 20C is similar to the manufacturing process of the second semiconductor element 20B, the description thereof will be omitted.

[0042] like Figure 8 As shown, an insulating layer 24a is stacked on a substrate 21, a plurality of circuit elements 22 are arranged on the insulating layer 24a, and an insulating layer 24c is stacked on the insulating layer 24a and the circuit elements 22. Next, a photoresist layer (mask layer) 61 is stacked on the insulating layer 24c by photolithography, and the insulating layer 24c is processed by dry etching. Next, a photoresist layer (mask layer) 62 is stacked on the insulating layer 24c by photolithography, and a portion of the insulating layer 24c and each circuit element 22 is processed by dry etching. Finally, these processed portions are filled with metal to form the terminal 23. In this way, a wafer W2 containing a plurality of second semiconductor elements 20B is completed, and the second semiconductor element 20B is cut out from the wafer W2. Thus, the second semiconductor element 20B is completed.

[0043] <3. Third Embodiment> <3-1. Example of configuration of semiconductor device> Will refer to Fig. 9 A configuration example of a semiconductor device 1C according to the present embodiment will be described. Fig. 9 1 is a cross-sectional view showing a configuration example of a semiconductor device 1C according to the present embodiment. In the present embodiment, a portion that is basically different from the first embodiment will be described.

[0044] like Fig. 9As shown, in the semiconductor device 1C according to the present embodiment, the configurations of the semiconductor substrate 10, the second semiconductor element 20B, and the third semiconductor element 20C are different from those of the first embodiment. The semiconductor substrate 10 according to the present embodiment includes two insulating layers (third insulating layers) 14c and 14d. These insulating layers 14c and 14d are formed of a material different from that of the insulating layers 14a and 14b, and are formed of, for example, the same material as the insulating layer 24c according to the first embodiment. In addition, the second semiconductor element 20B and the third semiconductor element 20C according to the present embodiment have the same configuration as the first semiconductor element 20A according to the first embodiment, and the insulating layer 24 includes two insulating layers 24a and 24b.

[0045] <3-2. Method for manufacturing semiconductor device> Will refer to Fig.10 and Fig.11 A method for manufacturing the semiconductor device 1C according to the present embodiment will be described. Fig.10 and Fig.11 1 is a diagram showing a manufacturing process of the semiconductor device 1C according to the present embodiment.

[0046] like Fig.10 As shown, an insulating layer 14a is stacked on the substrate 11, a plurality of circuit elements 12 are arranged on the insulating layer 24a, and an insulating layer 14b is stacked on the insulating layer 14a and the circuit elements 12. Next, a photoresist layer (mask layer) 71 is stacked on the insulating layer 14b by photolithography, and the insulating layer 14b is processed by dry etching. This processing position is the position where the insulating layer 14c is set. Next, a material (such as SiCN) 72 for forming the insulating layer 14c is stacked (deposited) on the insulating layer 14b and planarized by chemical mechanical polishing (CMP) technology. Then, a photoresist layer (mask layer) 73 is stacked on the insulating layer 14b and the insulating layer 14c by photolithography, and the insulating layer 14b is processed by dry etching. This processing position is the position where the insulating layer 14d is set. Next, a material (such as SiN) 74 for forming the insulating layer 14d is stacked (deposited) on the insulating layer 14b and planarized by CMP technology. Next, if Fig.11 As shown, the terminal 13 is formed by processing. Thus, the semiconductor substrate 10 including the two insulating layers 14c and 14d is completed.

[0047] Thus, the semiconductor substrate 10 is prepared. For example, the semiconductor substrate 10 is a wafer, and Fig.10 and Fig.11In the example in FIG. 1 , a portion of a wafer, namely, a semiconductor substrate 10 is shown. A first semiconductor element 20A, a second semiconductor element 20B, and a third semiconductor element 20C are also prepared. The first semiconductor element 20A, the second semiconductor element 20B, and the third semiconductor element 20C may be cut out from the same wafer W4 and singulated, or may be cut out from a plurality of different wafers W4 and singulated.

[0048] As in the first embodiment, the first semiconductor element 20A, the second semiconductor element 20B, and the third semiconductor element 20C are bonded to the semiconductor substrate 10 by the CoW technology (CoW bonding). At this point, the semiconductor device 1C is completed. Specifically, a plurality of first semiconductor elements 20A, a plurality of second semiconductor elements 20B, and a plurality of third semiconductor elements 20C are bonded to a wafer as the semiconductor substrate 10, and the wafer is cut and divided into a plurality of semiconductor devices 1C. Note that before or after the semiconductor device 1C is cut into individual pieces, necessary components are provided in the semiconductor device 1C to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0049] In the above-mentioned CoW bonding, similar to the first embodiment, the semiconductor substrate 10, the second semiconductor element 20B and the third semiconductor element 20C are bonded by different materials. Specifically, the insulating layer 14c of the semiconductor substrate 10 is bonded to the insulating layer 24b of the second semiconductor element 20B, and the insulating layer 14d of the semiconductor substrate 10 is bonded to the insulating layer 24b of the third semiconductor element 20c. These insulating layers 14c and 14d are formed of a different material from the insulating layer 24b. Therefore, compared with the case where the insulating layers 14c and 14d are formed of the same material as the insulating layer 24b as is usually the case, the bonding strength can be improved, and in addition, the withstand voltage can be improved and the deformation can be suppressed. For example, the materials of the insulating layers 14c and 14d can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc.

[0050] <4. Fourth embodiment> <4-1. Example of configuration of semiconductor device> Will refer to Fig.12 A configuration example of a semiconductor device 1D according to the present embodiment will be described. Fig.12 1 is a cross-sectional view showing a configuration example of a semiconductor device 1D according to the present embodiment. In the present embodiment, a portion that is basically different from the third embodiment will be described.

[0051] like Fig.12As shown, in the semiconductor device 1D according to the present embodiment, the configurations of the second semiconductor element 20B and the third semiconductor element 20C are different from those of the third embodiment. The configurations of the second semiconductor element 20B and the third semiconductor element 20C according to the present embodiment are the same as those of the first embodiment.

[0052] <4-2. Method for manufacturing semiconductor device> Will refer to Fig.13 A method for manufacturing the semiconductor device 1D according to the present embodiment will be described. Fig.13 1 is a diagram showing a manufacturing process of the semiconductor device 1D according to the present embodiment.

[0053] like Fig.13 As shown, a semiconductor substrate 10 according to the third embodiment is prepared (the manufacturing process of the semiconductor substrate 10 is the same as that of the third embodiment). For example, the semiconductor substrate 10 is a wafer, and Fig.13 In the example of FIG. 1 , a portion of a wafer as a semiconductor substrate 10 is shown. In addition, a first semiconductor element 20A, a second semiconductor element 20B, and a third semiconductor element 20C according to the first embodiment are prepared. The first semiconductor element 20A is cut out from the wafer W1 and singulated, the second semiconductor element 20B is cut out from the wafer W2 and singulated, and the third semiconductor element 20C is cut out from the wafer W3 and singulated.

[0054] As in the first embodiment, the first semiconductor element 20A, the second semiconductor element 20B, and the third semiconductor element 20C are bonded to the semiconductor substrate 10 by the CoW technology (CoW bonding). Thus, the semiconductor device 1D is completed. Specifically, a plurality of first semiconductor elements 20A, a plurality of second semiconductor elements 20B, and a plurality of third semiconductor elements 20C are bonded to a wafer as the semiconductor substrate 10, and the wafer is cut and divided into a plurality of semiconductor devices 1D. Note that before or after the semiconductor device 1D is divided into individual chips, necessary components are provided for the semiconductor device 1D to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0055] In the above-mentioned CoW bonding, the semiconductor substrate 10, the second semiconductor element 20B and the third semiconductor element 20C are bonded to each other by materials different from the insulating layers 14a, 14b, 24a and 24b. Specifically, the insulating layer 24c of the second semiconductor element 20B is bonded to the insulating layer 14c of the semiconductor substrate 10, and the insulating layer 24c of the third semiconductor element 20C is bonded to the insulating layer 14d of the semiconductor substrate 10. These insulating layers 14c, 14d and 24c are formed of materials different from the insulating layers 14a, 14b, 24a and 24b. As a result, compared with the case where the insulating layers 14c, 14d and 24c are formed of the same material as the insulating layers 14a, 14b, 24a and 24b, the bonding strength can be improved, and in addition, the withstand voltage can be improved and the deformation can be suppressed. For example, the material of the insulating layer 24c can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc. The materials of the insulating layers 14c, 14d and 24c can be the same or different.

[0056] <5. Fifth embodiment> <5-1. Example of configuration of semiconductor device> Will refer to Fig.14 and Fig.15 A configuration example of a semiconductor device 1E according to the present embodiment will be described. Fig.14 is a cross-sectional view showing a configuration example of a semiconductor device 1E according to the present embodiment. Fig.15 1 is a plan view showing a configuration example of a semiconductor device 1E according to the present embodiment. In the present embodiment, a portion basically different from the first embodiment will be described.

[0057] like Fig.14 and Fig.15 As shown, in the semiconductor device 1E according to the present embodiment, the configuration of the first semiconductor element 20A is different from that of the first embodiment. According to the first embodiment, the semiconductor device 1E does not include the second semiconductor element 20B and the third semiconductor element 20C.

[0058] The first semiconductor element 20A according to the present embodiment has a dense region R1 in which the pitch of the terminals 23 is narrow, and a sparse region R2 in which the pitch of the terminals 23 is wide. Figure 1 In the example, in the surface direction of the semiconductor substrate 10, the left region is a dense region R1 where the pitch of the terminals 23 is narrow, and the right region is a sparse region R2 where the pitch of the terminals 23 is wide. For example, the terminals 23 in the left region are arranged at a first pitch, and the terminals 23 in the right region are arranged at a second pitch wider than the first pitch.

[0059] In addition, the first semiconductor element 20A according to the present embodiment includes the insulating layer 24c according to the first embodiment. The insulating layer 24c is provided in the sparse region R2 where the pitch of the terminals 23 is wide. The insulating layer 24c is located on the surface of the insulating layer 24 on the semiconductor substrate 10 side and serves as a bonding layer for bonding the semiconductor substrate 10 and the first semiconductor element 20A.

[0060] Note that the insulating layer 24c is provided only in the sparse region R2, but is not limited thereto. For example, the insulating layer 24c may be provided only in the dense region R1, or may be provided in both the sparse region R2 and the dense region R1. In addition, although the insulating layer 24c is provided only on the first semiconductor element 20A, for example, the insulating layer 24c may be provided only on the semiconductor substrate 10 on the side facing the sparse region R2 of the first semiconductor element 20A, or may be provided on both the first semiconductor element 20A and the semiconductor substrate 10.

[0061] <5-2. Method for manufacturing semiconductor device> Will refer to Fig.16 and Fig.17 A method for manufacturing the semiconductor device 1E according to the present embodiment is described. Fig.16 and Fig.17 1 is a diagram showing a manufacturing process of the semiconductor device 1E according to the present embodiment.

[0062] like Fig.16 As shown, an insulating layer 24a is stacked on a substrate 21, a plurality of circuit elements 22 are provided, and an insulating layer 24b is stacked on the insulating layer 24a and the circuit elements 22. Next, a photoresist layer (mask layer) 81 is stacked on the insulating layer 24b by photolithography, and the insulating layer 24b is processed by dry etching. The processing position is the position where the insulating layer 24c is provided. Next, a material (e.g., SiN) 82 for forming the insulating layer 24c is stacked (deposited) on the insulating layer 24b and planarized by CMP technology. Then, the terminal 13 is formed by processing. Thus, the first semiconductor element 20A including the insulating layer 24c is completed.

[0063] In this way, the first semiconductor element 20A is prepared. Fig.17 As shown, a wafer W5 having a plurality of first semiconductor elements 20A is prepared, and a plurality of first semiconductor elements 20A are cut out from the wafer W5 and singulated to prepare the first semiconductor elements 20A. In addition, a semiconductor substrate 10 is also prepared. For example, the semiconductor substrate 10 is a wafer formed based on a normal manufacturing process. Fig.17 In the example of FIG. 1 , a portion of a wafer serving as a semiconductor substrate 10 is shown.

[0064] The first semiconductor element 20A is bonded to the semiconductor substrate 10 by the CoW technology (CoW bonding). Thus, the semiconductor device 1E is completed. Specifically, a plurality of first semiconductor elements 20A are bonded to a wafer as the semiconductor substrate 10, and the wafer is cut and divided into a plurality of semiconductor devices 1E. Note that before or after the semiconductor device 1E is divided into individual chips, necessary components are provided in the semiconductor device 1E to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0065] In the above-mentioned CoW bonding, the semiconductor substrate 10 and the sparse region R2 of the first semiconductor element 20A are bonded by different materials. Specifically, the insulating layer 14b of the semiconductor substrate 10 and the insulating layer 24c of the first semiconductor element 20A are bonded together. These insulating layers 14b and 24c are made of different materials. As a result, compared with the case where the insulating layers 14b and 24c are formed of the same material as in the usual case, the bonding strength can be improved, and in addition, the withstand voltage can be improved and the deformation can be suppressed. For example, the material of the insulating layer 24c can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc.

[0066] <6. Sixth embodiment> <6-1. Example of configuration of semiconductor device> Will refer to Fig.18 and Fig.19 A configuration example of a semiconductor device 1F according to the present embodiment will be described. Fig.18 is a cross-sectional view showing a configuration example of a semiconductor device 1F according to the present embodiment. Fig.19 1F is a plan view showing a configuration example of a semiconductor device 1F according to the present embodiment. In the present embodiment, a portion basically different from the first embodiment will be described.

[0067] like Fig.18 and 19 As shown, in the semiconductor device 1F according to the present embodiment, the configuration of the first semiconductor element 20A is different from that of the first embodiment. The semiconductor device 1F does not include the second semiconductor element 20B and the third semiconductor element 20C according to the first embodiment.

[0068] The first semiconductor element 20A according to the present embodiment has the terminal 23 according to the first embodiment in the central region R3, and has the insulating layer 24c according to the third embodiment in the peripheral region R4. Fig.19 As shown, in the outer peripheral region R4 of the first semiconductor element 20A on the surface on the semiconductor substrate 10 side, the insulating layer 24c is formed into a rectangular ring shape. The insulating layer 24c is located on the surface of the insulating layer 24 on the semiconductor substrate 10 side, and serves as a bonding layer for bonding the semiconductor substrate 10 and the first semiconductor element 20A.

[0069] The insulating layer 24c is continuously provided in a rectangular ring shape in the peripheral region R4, but is not limited thereto. For example, the insulating layer 24c may be provided in a discontinuous dot shape, or may be provided in other shapes. The ring-shaped insulating layer 24c is provided only on the first semiconductor element 20A. However, for example, the insulating layer 24c may be provided only on one side of the semiconductor substrate 10 facing the peripheral region R4 of the first semiconductor element 20A, or may be provided on both the first semiconductor element 20A and the semiconductor substrate 10.

[0070] <6-2. Method for manufacturing semiconductor device> Will refer to Fig. 20 and Fig.21 A method for manufacturing the semiconductor device 1F according to the present embodiment is described. Fig. 20 and Fig.21 1 is a diagram showing a manufacturing process of the semiconductor device 1F according to the present embodiment.

[0071] like Fig. 20 As shown, an insulating layer 24a is stacked on a substrate 21, a plurality of circuit elements 22 are provided, and an insulating layer 24b is stacked on the insulating layer 24a and the circuit elements 22. Next, a photoresist layer (mask layer) 91 is stacked on the insulating layer 24b by photolithography, and the insulating layer 24b is processed by dry etching. The processing position is the position where the insulating layer 24c is provided. Next, a material (e.g., SiN) for forming the insulating layer 24c is stacked (deposited) on the insulating layer 24b and planarized by CMP technology. Then, each terminal 13 is formed by processing. Thus, the first semiconductor element 20A including the insulating layer 24c is completed.

[0072] In this way, the first semiconductor element 20A is prepared. Specifically, Fig.21 As shown, a wafer W6 having a plurality of first semiconductor elements 20A is prepared, and a plurality of first semiconductor elements 20A are cut out from the wafer W6 and singulated to prepare the first semiconductor elements 20A. In addition, a semiconductor substrate 10 is also prepared. For example, the semiconductor substrate 10 is a wafer formed based on a normal manufacturing process. Fig.21 In the example of FIG. 1 , a portion of a wafer serving as a semiconductor substrate 10 is shown.

[0073] The first semiconductor element 20A is bonded to the semiconductor substrate 10 by the CoW technology (CoW bonding). At this point, the semiconductor device 1F is completed. Specifically, a plurality of first semiconductor elements 20A are bonded to a wafer as the semiconductor substrate 10, and the wafer is cut and singulated into a plurality of semiconductor devices 1F. Note that before or after the semiconductor device 1F is cut into individual pieces, necessary components are provided in the semiconductor device 1F to complete, for example, a solid-state imaging device, a light-emitting device, or a storage device.

[0074] In the above-mentioned CoW bonding, the semiconductor substrate 10 and the peripheral region R4 of the first semiconductor element 20A are bonded by different materials. Specifically, the insulating layer 14b of the semiconductor substrate 10 and the insulating layer 24c of the first semiconductor element 20A are bonded together. These insulating layers 14b and 24c are made of different materials. As a result, compared with the case where the insulating layers 14b and 24c are formed of the same material as in the usual case, the bonding strength can be improved, and in addition, the withstand voltage can be improved and the deformation can be suppressed. For example, the material of the insulating layer 24c can be appropriately changed according to the required bonding strength, the required withstand voltage, the allowed deformation, etc.

[0075] <7. Seventh Embodiment> <7-1. Example of configuration of semiconductor device> Will refer to Figure 22 to Figure 26 A configuration example of a semiconductor device 1G according to the present embodiment will be described. Fig. 22 1 is a perspective view showing a configuration example of a semiconductor device 1G according to the present embodiment. Fig.23 is a cross-sectional view showing a configuration example of a semiconductor device 1G according to the present embodiment. Fig.24 is a diagram showing a circuit example of a semiconductor device 1G according to the present embodiment. Fig.25 is a diagram showing a circuit example of the comparator 72 according to the present embodiment. Fig.26 : is a diagram showing an output example of the comparator 72 according to the present embodiment. In the present embodiment, a portion basically different from the fourth embodiment will be described.

[0076] like Fig. 22 As shown, in the semiconductor device 1G according to the present embodiment, for example, the semiconductor substrate 10 is a pixel chip including a plurality of pixels 100. Each of the two semiconductor elements 20A is a circuit chip including a plurality of drivers 110. The semiconductor element 20B is a circuit chip including an analog-to-digital converter (ADC) 120. These pixel chips and circuit chips, etc. may include other elements, circuits, etc.

[0077] For example, each pixel 100 of the semiconductor substrate 10 includes a transistor 100a and a photodiode (which will be described in detail later). A horizontal signal line (drive wiring) 101 and a vertical signal line 102 are connected to each pixel 100. The horizontal signal line 101 is arranged, for example, in each row of a two-dimensional matrix, and is commonly connected to a plurality of pixels 100 arranged in a row. The vertical signal line 102 is arranged, for example, in each column of a two-dimensional matrix, and is commonly connected to a plurality of pixels 100 arranged in one column. The pixel 100 is controlled by a control signal transmitted through the horizontal signal line 101 to generate an image signal, and outputs the generated image signal to the ADC 120 of the semiconductor element 20B or the like through the vertical signal line 102.

[0078] Here, for example, there is a layout method in which a wiring layer (for example, a layer including an insulating layer 14c and an insulating layer 24c) used at a bonding interface between the semiconductor substrate 10 and the semiconductor elements 20A and 20B is used. Fig.23 )), and the wiring layer is used as a circuit wiring node instead of an electrical junction between chips. When this method is used, depending on the wiring (wiring node), there are wirings such as drive wirings that are expected to reduce parasitic capacitance, and there are wirings such as phase compensation capacitance and charge retention capacitance (pixel internal capacitance) that are expected to increase capacitance as much as possible. For example, since the coupling capacitance between wiring layers (for example, between Cu wiring layers) contributes to the above capacitance, the dielectric constant of the wiring layer will be a design parameter.

[0079] For example, the wiring layer (eg, such as the insulating layer 14c and the insulating layer 24c ( Fig.23 ) to control the capacitance value: when it is necessary to increase the capacitance associated with the wiring (wiring node capacitance), the wiring layer is formed using an insulating film material with a high dielectric constant; when it is necessary to reduce the capacitance associated with the wiring, the wiring layer is formed using an insulating film material with a low dielectric constant. In the pixel chip of the semiconductor substrate 10, for example, it is sometimes desired to reduce the parasitic capacitance C1 of the horizontal signal line (drive wiring) 101. For example, in the circuit chip of the semiconductor element 20B, it is sometimes desired to increase the phase compensation capacitance C2 of the ADC 120 in a narrow area. Note that, for example, the phase compensation capacitance C2 of the horizontal signal line 101 and the ADC 120 is formed in the Cu-Cu connecting wiring layer.

[0080] like Fig.23As shown, the insulating layer 14c of the semiconductor substrate 10 is formed of, for example, an insulating film material having a lower dielectric constant than the insulating layer 14a, the insulating layer 14b, etc. As a result, the parasitic capacitance C1 between the horizontal signal lines 101 can be reduced. Therefore, for example, it is possible to achieve a reduction in the capacitance of the drive wiring required to be driven at high speeds such as indirect time of flight (iToF) and an increase in the driving speed. As an insulating film material having a low dielectric constant, for example, SiO2 having a relative dielectric constant of 3.8 can be used.

[0081] In addition, the insulating layer 24c of the semiconductor element 20B is formed of an insulating film material having a higher dielectric constant than the insulating layer 24a, the insulating layer 24b, etc. As a result, for example, the phase compensation capacitor C2 between the wirings 121 can be increased. Therefore, a large capacitance of the phase compensation capacitor C2 can be achieved. In addition, for example, the cutoff frequency of the low-pass filter can be reduced or the capacitance area can be reduced. As an insulating film material with a high dielectric constant, for example, SiN with a relative dielectric constant of 7.8 or SiCN with a relative dielectric constant of 8.0 can be used.

[0082] like Fig.24 As shown, the pixel 100 may include, for example, a photodiode 100b and a plurality of transistors 100a. Each transistor 100a includes a transfer transistor, a reset transistor, an amplifying transistor, a selection transistor, etc. Each transistor 100a constitutes a pixel circuit. The photodiode 100b is an example of a photoelectric conversion element that generates an amount of charge corresponding to the amount of light received and accumulates the generated charge therein.

[0083] ADC 120 may include a load current source 120a, a comparator 120b, and a counter 120c. A reference voltage generating section 120d is connected to the comparator 120b. The reference voltage generating section 120d applies a reference voltage to the comparator 120b. Fig.24 In the example of FIG. 1 , a bonding interface M1 between the pixel chip of the semiconductor substrate 10 and the circuit chip of the semiconductor element 20B is shown.

[0084] like Fig.25 As shown, the comparator 120b may include a plurality of transistors 122 and a phase compensation capacitor C2. In other words, the phase compensation capacitor C2 in the ADC 120 may be a capacitor in the comparator 120b. The plurality of transistors 122 include, for example, P-channel and N-channel transistors.

[0085] like Fig.26 As shown, the comparator 120b compares the pixel signal (eg, voltage waveform) input from the vertical signal line 102 with the reference voltage provided from the reference voltage generating section 120d and generates a pulse signal. The counter 120c performs, for example, P-phase counting or D-phase counting and measures the pulse width of the pulse signal.

[0086] According to the present embodiment, the dielectric constant of the insulating layer 14c of the semiconductor substrate 10 is different from the dielectric constant of the insulating layer 14a, the insulating layer 14b, etc. For example, the dielectric constant of the insulating layer 14c of the semiconductor substrate 10 is lower than the dielectric constant of the insulating layer 14a, the insulating layer 14b, etc. In addition, the dielectric constant of the insulating layer 24c of the semiconductor element 20B is different from the dielectric constant of the insulating layer 24a, the insulating layer 24b, etc. For example, the dielectric constant of the insulating layer 24c of the semiconductor element 20B is higher than the dielectric constant of the insulating layer 24a, the insulating layer 24b, etc. This makes it possible to adjust the capacitance such as the parasitic capacitance C1 and the phase compensation capacitance C2 while improving the bonding strength. For example, the parasitic capacitance C1 can be reduced, and the phase compensation capacitance C2 can be increased. For example, the dielectric constants of the insulating layer 14a, the insulating layer 14b, the insulating layer 24a, and the insulating layer 24b are the same, but can also be different.

[0087] In the above description, the present embodiment is applied to the fourth embodiment, but it can also be applied to other embodiments, such as the first and second embodiments. For example, the construction of the present embodiment is applied to semiconductor elements 20B and 20C according to other embodiments (such as the first and second embodiments). In the present embodiment, an insulating layer (for example, insulating layer 14c, insulating layer 24c, etc.) for improving bonding strength and adjusting capacitance is provided, but an insulating layer for improving bonding strength and an insulating layer for adjusting capacitance can also be stacked and provided. In this case, for example, the dielectric constant of the insulating layer for adjusting capacitance is different from the dielectric constant of other insulating layers (for example, insulating layer 14a, insulating layer 14b, insulating layer 24a, insulating layer 24b, etc.). In addition, for example, the insulating layer for improving bonding strength is closer to the semiconductor substrate 10 than the insulating layer for adjusting capacitance.

[0088] <8. Eighth Embodiment> <8-1. Example of configuration of semiconductor device> Will refer to Figures 27 to 32 A configuration example of the semiconductor device 1H according to the present embodiment will be described. Fig. 27 1 is a perspective view showing a configuration example of a semiconductor device 1H according to the present embodiment. Fig.28 is a cross-sectional view showing a configuration example of a semiconductor device 1H according to the present embodiment. Fig.29 1 is a perspective view showing exemplary areas of the pixel region R11 and the connection region R12 of the semiconductor device 1H according to the present embodiment. Fig.30 1 is a plan view showing a configuration example of wiring of the semiconductor device 1H according to the present embodiment. Fig.31 is a diagram showing a circuit example of a semiconductor device 1H according to the present embodiment. Fig.321 is a diagram showing another circuit example of the semiconductor device 1H according to the present embodiment. In the present embodiment, parts that are basically different from the third and eighth embodiments will be described.

[0089] like Fig. 27 As shown, in the semiconductor device 1H according to the present embodiment, as in the eighth embodiment, for example, the semiconductor substrate 10 is a pixel chip including a plurality of pixels 100. Each of the two semiconductor elements 20A is a circuit chip including a plurality of drivers 110. The semiconductor element 20B is a circuit chip including an ADC 120. These pixel chips and circuit chips, etc. may include other elements, circuits, etc. Note that in Fig.28 In the example of FIG. 1 , a plurality of in-pixel wirings 103 and 104 and a plurality of power supply wirings 105 and 106 are shown.

[0090] Here, for example, as in the eighth embodiment, the wiring layer (for example, such as the insulating layer 14c and the insulating layer 14e ( Fig.28 ) to control the capacitance value: when it is necessary to increase the capacitance associated with the wiring (wiring node capacitance), the wiring layer is formed using an insulating film material with a high dielectric constant; when it is necessary to reduce the capacitance associated with the wiring, the wiring layer is formed using an insulating film material with a low dielectric constant. For example, there is a case where it is desired to increase the in-pixel capacitance C3 having a narrow area and reduce the parasitic capacitance C4 of the vertical signal line 102. Note that, for example, the in-pixel capacitance C3 is formed in the Cu-Cu connecting wiring layer.

[0091] like Fig.28 and 29 As shown, in the pixel region R11 ( Fig.29 ) is provided with an insulating layer 14c of the semiconductor substrate 10. The insulating layer 14c is formed of, for example, an insulating film material (e.g., SiN or SiCN) having a higher dielectric constant than the insulating layers 14a and 14b. This makes it possible to increase the in-pixel capacitance C3. Therefore, a large capacitance of the in-pixel capacitance C3 can be achieved. In other words, the charge holding capacitance of the pixel 100 can be increased.

[0092] In the connection region R12 ( Fig.29 ) is provided with an insulating layer 14e of the semiconductor substrate 10. The insulating layer 14e is formed of, for example, an insulating film material (eg, SiO2) having a lower dielectric constant than the insulating layers 14a and 14b. As a result, the parasitic capacitance C4 of the vertical signal line 102 can be reduced.

[0093] like Fig.30As shown, in the pixel region R11, for example, each of the in-pixel wirings 103 and 104 and each of the power supply wirings 105 and 106 can be formed in a comb shape, and each of the comb-shaped in-pixel wirings 103 and 104 and each of the comb-shaped power supply wirings 105 and 106 can be arranged in combination with each other. This makes it possible to increase the in-pixel capacitance C3. Note that the in-pixel wiring 103 is an upper layer wiring, the in-pixel wiring 104 is a lower layer wiring, the power supply wiring 105 is an upper layer wiring, and the power supply wiring 106 is a lower layer wiring (refer to Fig.29 ).

[0094] The comb-shaped intra-pixel wirings 103 and 104 and the comb-shaped power supply wirings 105 and 106 are arranged to avoid the plurality of connection points 107. In other words, as a wiring layout (e.g., a wiring shape in a plan view) in the pixel region R11, a wiring layout having a comb shape or the like that avoids the connection points 107 is effective. Fig.30 In the example of FIG. 1 , four connection points 107 are shown. Each connection point 107 is, for example, a Cu-Cu connection point. The connection point 107 may include, for example, a dummy connection point (dummy layout).

[0095] Each of the comb-shaped pixel wirings 103 and 104 is connected through a plurality of vias V1. Each of the comb-shaped power wirings 105 and 106 is also connected through a plurality of vias V2. Each via V1 is a via that connects the comb-shaped pixel wirings 103 and 104. Each via V2 is a via that connects the comb-shaped power wirings 105 and 106.

[0096] like Fig.31 As shown, the in-pixel capacitor C3 may be, for example, an in-pixel charge holding capacitor for receiving overflowing charges from the photodiode 100 b. As the capacitance increases, a larger light quantity signal can be read.

[0097] In addition, if Fig.32 As shown, the in-pixel capacitor C3 may be, for example, an in-pixel charge holding capacitor that collectively transfers and holds the charge of the photodiodes 100b in all rows in a voltage domain global shutter (VDGS). VDGS is an imaging method that collectively transfers and holds the charge of the photodiodes 100b in all rows. The larger the capacitance that holds such a charge, the smaller the influence of leakage during the holding period.

[0098] According to the present embodiment, the dielectric constant of the insulating layer 14c of the semiconductor substrate 10 is different from the dielectric constant of the insulating layer 14a and the insulating layer 14b, etc. For example, the dielectric constant of the insulating layer 14c of the semiconductor substrate 10 is higher than the dielectric constant of the insulating layer 14a and the insulating layer 14b, etc. In addition, the dielectric constant of the insulating layer 14e of the semiconductor substrate 10 is different from the dielectric constant of the insulating layer 14a and the insulating layer 14b, etc. For example, the dielectric constant of the insulating layer 14e of the semiconductor substrate 10 is lower than the dielectric constant of the insulating layer 14a and the insulating layer 14b, etc. This makes it possible to adjust the capacitance such as the in-pixel capacitance C3 and the parasitic capacitance C4, etc. while improving the bonding strength. For example, it is possible to increase the capacitance of the in-pixel capacitance C3 and reduce the parasitic capacitance C4.

[0099] In the above description, the present embodiment is applied to the third embodiment, but it can also be applied to other embodiments such as the first and second embodiments. For example, the configuration of the present embodiment is applied to the semiconductor elements 20B and 20C according to other embodiments such as the first and second embodiments. Also in the present embodiment, similar to the eighth embodiment, an insulating layer for improving the bonding strength and adjusting the capacitance (for example, the insulating layer 14c and the insulating layer 14e) is provided, but an insulating layer for improving the bonding strength and an insulating layer for adjusting the capacitance may be stacked and provided.

[0100] <9. Functions and Effects According to Each Embodiment> As described above, according to the embodiment, a semiconductor device (for example, any one of the semiconductor devices 1A to 1H) includes a semiconductor substrate 10 including a first insulating layer 14 and a plurality of first terminals 13 provided on the first insulating layer 14, and a semiconductor element 20 which is stacked on the semiconductor substrate 10 and includes a second insulating layer 24 and a plurality of second terminals 23 provided on the second insulating layer 24 and connected to the plurality of first terminals 13. The first insulating layer 14 or the second insulating layer 24 has a third insulating layer (for example, insulating layer 24c, insulating layer 14c, and insulating layer 14d) which is made of a material different from that of the first insulating layer 14 and which bonds the semiconductor substrate 10 and the semiconductor element 20. Therefore, when bonding the semiconductor substrate 10 and the semiconductor element 20, the first insulating layer 14 or the second insulating layer 24 and the third insulating layer are bonded, and the bonding strength can be improved compared to the case where the first insulating layer 14 and the second insulating layer 24 are directly bonded in a normal case. For example, the material of the third insulating layer can be appropriately changed according to the required bonding strength.

[0101] Furthermore, the second insulating layer 24 may include a third insulating layer (eg, insulating layer 24 c ). Even with this structure, the bonding strength can be improved.

[0102] In addition, the third insulating layer can be formed in the entire region of the surface of the semiconductor element 20 on the semiconductor substrate 10 side while avoiding the plurality of second terminals 23. This makes it possible to reliably improve the bonding strength.

[0103] In addition, the semiconductor element 20 may have a first region (e.g., a dense region R1) in which a portion of the plurality of second terminals 23 are arranged at a first pitch, and a second region (e.g., a sparse region R2) in which a portion of the plurality of second terminals 23 are arranged at a second pitch wider than the first pitch, and a third insulating layer may be formed in the second region. This makes it possible to reliably improve the bonding strength.

[0104] In addition, the third insulating layer can be formed in the peripheral region R4 of the surface of the semiconductor element 20 located on the semiconductor substrate 10 side. This makes it possible to reliably improve the bonding strength. For example, since peeling that is likely to occur in the peripheral region R4 of the semiconductor element 20 can be suppressed, the bonding strength can be reliably improved.

[0105] The first insulating layer 14 may include a third insulating layer (eg, insulating layer 14 c and insulating layer 14 d ). Even with such a structure, the bonding strength can be improved.

[0106] Furthermore, the third insulating layer may be formed in a region facing the semiconductor element 20, that is, a region of the surface of the semiconductor substrate 10 on the semiconductor element side. This makes it possible to reliably improve the bonding strength.

[0107] In addition, the semiconductor element 20 may have a first region (e.g., a dense region R1) in which a portion of the plurality of second terminals 23 are arranged at a first pitch, and a second region (e.g., a sparse region R2) in which a portion of the second terminals 23 are arranged at a second pitch wider than the first pitch. The third insulating layer may be formed in a region facing the second region, which is a region of the surface of the semiconductor substrate 10 on the side of the semiconductor element 20. This makes it possible to reliably improve the bonding strength.

[0108] In addition, the third insulating layer may be formed in a region opposite to the peripheral region R4 of the surface of the semiconductor element 20 located on the semiconductor element 10 side, which is a region of the surface of the semiconductor substrate 10 located on the semiconductor element 20 side. This makes it possible to reliably improve the bonding strength. For example, since peeling that is likely to occur in the peripheral region R4 of the semiconductor element 20 can be suppressed, the bonding strength can be reliably improved.

[0109] The dielectric constant of the third insulating layer (e.g., insulating layer 14c, insulating layer 14e, and insulating layer 24c) may be different from the dielectric constant of the first insulating layer 14 or the second insulating layer 24. Therefore, for example, various capacitances such as parasitic capacitance C1, phase compensation capacitance C2, in-pixel capacitance C3, and parasitic capacitance C4 can be adjusted.

[0110] Furthermore, each of the first insulating layer 14 and the second insulating layer 24 may have a third insulating layer (eg, the insulating layer 14 c , the insulating layer 14 d , and the insulating layer 24 c ). Even with such a configuration, the bonding strength can be improved.

[0111] Furthermore, a plurality of third insulating layers may be provided at positions facing each other. This makes it possible to reliably improve the bonding strength.

[0112] In addition, the dielectric constant of the third insulating layer (e.g., insulating layer 14c) included in the first insulating layer 14 may be different from the dielectric constant of the first insulating layer 14, and the dielectric constant of the third insulating layer (e.g., insulating layer 24c) included in the second insulating layer 24 may be different from the dielectric constant of the second insulating layer 24. Therefore, for example, various capacitances such as the parasitic capacitance C1, the phase compensation capacitance C2, the in-pixel capacitance C3, and the parasitic capacitance C4 can be adjusted.

[0113] In addition, the material of the third insulating layer can be determined so that the bonding strength of the third insulating layer between the semiconductor substrate 10 and the semiconductor element 20 increases as the size of the semiconductor element 20 decreases. This makes it possible to reliably improve the bonding strength.

[0114] Furthermore, the material or thickness of the third insulating layer may be determined so that the withstand voltage between the plurality of second terminals 23 due to the third insulating layer increases as the intervals between the plurality of second terminals 23 narrow. As a result, the withstand voltage can be improved.

[0115] In addition, a plurality of semiconductor elements 20 may be provided, and a third insulating layer may be provided for each semiconductor element 20. Therefore, in each semiconductor element 20, the bonding strength can be improved.

[0116] Furthermore, the material of the third insulating layer of each semiconductor element 20 may be different for each semiconductor element 20. Therefore, in each semiconductor element 20, the bonding strength can be reliably improved.

[0117] In addition, the material of the third insulating layer of each semiconductor element 20 can be determined to suppress deformation caused by CTE differences between the plurality of semiconductor elements 20. This makes it possible to suppress deformation in a semiconductor device (eg, any of the semiconductor devices 1A to 1H) including the plurality of semiconductor elements 20.

[0118] <10. Application examples> Next, application examples of the semiconductor devices 1A to 1H according to the embodiments will be explained. Fig.33 1A to 1H are diagrams showing usage examples of the semiconductor devices 1A to 1H according to the embodiments.

[0119] The semiconductor devices 1A to 1H described above can be used in various situations where light such as visible light, infrared light, ultraviolet light, and X-rays are sensed, for example, as described below. Fig.33 As shown, the semiconductor devices 1A to 1H are used for "devices for capturing images for viewing, such as digital cameras or portable devices with camera functions", "devices for traffic, such as on-board sensors for capturing the front, back, surroundings, interior, etc. of a car for purposes such as automatic parking and recognition of the driver's status, monitoring cameras for monitoring moving vehicles and roads, and ranging sensors for measuring the distance between vehicles", "devices for home appliances such as televisions, refrigerators, and air conditioners for capturing images of user gestures and performing device operations that conform to the gestures", "devices for medical or health care, such as endoscopes or devices for performing angiography by receiving infrared light", "devices for security, such as monitoring cameras for crime prevention or cameras for identity verification of persons", "devices for beauty care, such as skin measuring instruments for skin imaging or microscopes for scalp imaging", "devices for sports, such as sports cameras or wearable cameras for sports", "devices for agriculture, such as cameras for monitoring the conditions of farmland and crops", and the like.

[0120] Note that the technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device (e.g., electronic device) installed on any type of mobile body, such as an automobile, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). For example, the technology according to the present disclosure can be implemented as a device (e.g., electronic device) installed on an endoscopic surgery system, a microsurgery system, etc.

[0121] <11. Electronic devices according to application examples> As an electronic device to which any one of the semiconductor devices 1A to 1H described above is applied, reference will be made to Fig.34 and 35 The imaging device 300 and the distance measuring device 400 will be described.

[0122] <11-1. Camera device> Will refer to Fig.34 An imaging device 300 according to an application example will be described. Fig.341 is a diagram showing an example of a schematic configuration of an imaging device 300 according to an application example. The imaging device 300 is an example of an electronic device to which any one of the above-described semiconductor devices 1A to 1H is applied. Examples of the imaging device 300 include electronic devices such as a digital camera, a video camera, a smartphone with an imaging function, and a mobile phone.

[0123] like Fig.34 As shown, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture still images and moving images.

[0124] The optical system 301 includes one or more lenses. The optical system 301 guides light (incident light) from a subject to the imaging element 303 , and forms an image on a light receiving surface of the imaging element 303 .

[0125] The shutter device 302 is provided between the optical system 301 and the image pickup element 303. The shutter device 302 controls a light irradiation period and a light shielding period of the image pickup element 303 according to control of the control circuit 304.

[0126] The imaging element 303 accumulates signal charges for a certain period of time according to light formed on a light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the imaging element 303 are transferred according to a drive signal (timing signal) supplied from the control circuit 304.

[0127] The control circuit 304 outputs a drive signal for controlling the transfer operation of the imaging element 303 and the shutter operation of the shutter device 302 to drive the imaging element 303 and the shutter device 302 .

[0128] The signal processing circuit 305 performs various types of signal processing on the signal charge output from the image pickup element 303. An image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to the monitor 306 and also supplied to the memory 307.

[0129] The monitor 306 displays a moving image or a still image captured by the imaging element 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel is used.

[0130] The memory 307 stores the image data supplied from the signal processing circuit 305 , that is, image data of a moving image or a still image captured by the imaging element 303 .

[0131] In the imaging device 300 configured in this manner, by applying any of the semiconductor devices 1A to 1H to each portion such as the imaging element 303 , the signal processing circuit 305 , and the memory 307 , it is possible to increase the bonding strength, that is, improve the quality.

[0132] <11-2. Distance measuring device> Will refer to Fig.35 A distance measuring device 400 according to an application example will be described. Fig.35 1A is a diagram showing an example of a schematic configuration of a distance measuring device 400 according to an application example. The distance measuring device 400 is an example of an electronic device to which any one of the above-described semiconductor devices 1A to 1H is applied.

[0133] like Fig.35 As shown, the distance measuring device (distance image sensor) 400 includes a light source section 401, an optical system 402, an imaging element (solid-state imaging device) 403, a control circuit (driving circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 can acquire a distance image according to the distance to the subject by projecting light from the light source section 401 toward the subject and receiving light (modulated light or pulse light) reflected from the surface of the subject.

[0134] The light source section 401 projects light toward the subject. As the light source section 401, for example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source or a laser diode array in which laser diodes are arranged in a row is used. Note that the laser diode array is supported by a predetermined driving unit (not shown) and scans in a direction perpendicular to the array direction of the laser diodes.

[0135] The optical system 402 includes one or more lenses. The optical system 402 guides light (incident light) from a subject to the imaging element 403 to form an image on a light receiving surface (sensor portion) of the imaging element 403 .

[0136] The imaging element 403 stores signal charge according to light of an image formed on a light receiving surface via the optical system 402. A distance signal indicating a distance obtained from a light receiving signal (APD OUT) output from the imaging element 403 is supplied to a signal processing circuit 405. As the imaging element 403, for example, a solid-state imaging element such as an image sensor is used.

[0137] The control circuit 404 outputs a drive signal (control signal) for controlling the operation of the light source section 401 , the imaging element 403 , and the like, to drive the light source section 401 , the imaging element 403 , and the like.

[0138] The signal processing circuit 405 performs various types of signal processing on the distance signal supplied from the imaging element 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) for constructing a distance image based on the distance signal. An image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to the monitor 406, and is also supplied to the memory 407.

[0139] The monitor 406 displays the distance image captured by the imaging element 303 based on the image data supplied from the signal processing circuit 405. As the monitor 406, for example, a panel type display device such as a liquid crystal panel or an organic EL panel is used.

[0140] The memory 407 stores the image data supplied from the signal processing circuit 405 , that is, the image data of the distance image captured by the imaging element 303 .

[0141] In the distance measuring device 400 configured in this manner, by applying any of the semiconductor devices 1A to 1H to various portions such as the imaging element 403 , the signal processing circuit 405 , and the memory 407 , the bonding strength, that is, the quality can be improved.

[0142] Note that the semiconductor devices 1A to 1H described above can be mounted on various electronic devices as described above. For example, in addition to the camera device 300 and the distance measuring device 400, the semiconductor devices 1A to 1H can be mounted on various electronic devices such as hard disk drives (HDDs), notebook computers (PCs), mobile devices (e.g., smartphones, tablet computers, etc.), personal digital assistants (PDAs), wearable devices, game devices, and music devices.

[0143] <12. Other embodiments> The configuration according to the above-described embodiment can be implemented in various different forms other than the above-described embodiment. For example, the configuration is not limited to the above-described example and can be implemented in various modes. In addition, for example, unless otherwise specified, the configuration, processing steps, specific names, and information including various data and parameters shown in the above-described documents and drawings can be arbitrarily changed.

[0144] Furthermore, the individual components of the devices shown in the drawings are conceptual in function and are not necessarily physically constructed as shown in the drawings. In other words, the specific forms of distribution and integration of the devices are not limited to those shown, and all or part of them may be functionally or physically distributed and integrated in arbitrary units according to various loads and usage conditions, etc.

[0145] Furthermore, the above-described embodiments (or modified examples) can be appropriately combined within the range that the processing contents are not contradictory. Note that the effects described in this specification are merely examples and are not limited, and other effects may be provided.

[0146] <13. Appendix> The present technology may also have the following configurations. (1) A semiconductor device comprising: a semiconductor substrate including a first insulating layer and a plurality of first terminals disposed on the first insulating layer; and A semiconductor element stacked on the semiconductor substrate, the semiconductor element comprising a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein The first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from that of the first insulating layer and bonding the semiconductor substrate and the semiconductor element. (2) The semiconductor device according to (1), wherein: The second insulating layer includes the third insulating layer. (3) A semiconductor device according to (2), wherein: The third insulating layer is formed over the entire region of the surface of the semiconductor element on the semiconductor substrate side, and the third insulating layer is formed to avoid the plurality of second terminals. (4) A semiconductor device according to (2), wherein: The semiconductor element has a first region and a second region, in which a part of the plurality of second terminals are arranged at a first pitch, and in which a part of the plurality of second terminals are arranged at a second pitch wider than the first pitch. The third insulating layer is formed in the second region. (5) A semiconductor device according to (2), wherein: The third insulating layer is formed in an outer peripheral region of a surface of the semiconductor element on the semiconductor substrate side. (6) The semiconductor device according to (1), wherein: The first insulating layer includes the third insulating layer. (7) A semiconductor device according to (6), wherein: The third insulating layer is formed in a region of the surface of the semiconductor substrate on the side of the semiconductor element, the region facing the semiconductor element. (8) A semiconductor device according to (6), wherein: The semiconductor element has a first region and a second region, in which a part of the plurality of second terminals are arranged at a first pitch, and in which a part of the plurality of second terminals are arranged at a second pitch wider than the first pitch. The third insulating layer is formed in a region of the surface of the semiconductor substrate on the side of the semiconductor element, the region facing the second region. (9) A semiconductor device according to (6), wherein: The third insulating layer is formed in a region of the surface of the semiconductor substrate on the semiconductor element side, the region facing an outer peripheral region of the surface of the semiconductor element on the semiconductor substrate side. (10) The semiconductor device according to any one of (1) to (9), wherein: The third insulating layer has a dielectric constant different from a dielectric constant of the first insulating layer or the second insulating layer. (11) The semiconductor device according to (1), wherein: The first insulating layer and the second insulating layer both include the third insulating layer. (12) A semiconductor device according to (11), wherein: The plurality of third insulating layers are disposed at positions facing each other. (13) The semiconductor device according to (11) or (12), wherein: The third insulating layer included in the first insulating layer has a dielectric constant different from that of the first insulating layer, and The third insulating layer included in the second insulating layer has a dielectric constant different from that of the second insulating layer. (14) The semiconductor device according to any one of (1) to (13), wherein: The material of the third insulating layer is determined so that the bonding strength of the third insulating layer between the semiconductor substrate and the semiconductor element increases as the size of the semiconductor element decreases. (15) The semiconductor device according to any one of (1) to (13), wherein: The material or thickness of the third insulating layer is determined so that a withstand voltage of the third insulating layer between the plurality of second terminals becomes higher as a pitch of the plurality of second terminals becomes narrower. (16) The semiconductor device according to (1), wherein: The semiconductor element is provided in plurality, and The third insulating layer is provided for each of the semiconductor elements. (17) A semiconductor device according to (16), wherein: The material of the third insulating layer of each of the semiconductor elements is different for each of the semiconductor elements. (18) A semiconductor device according to (17), wherein: The material of the third insulating layer of each of the semiconductor elements is determined so as to suppress deformation caused by a difference in thermal expansion coefficient among the plurality of semiconductor elements. (19) An electronic device having a semiconductor device, wherein the semiconductor device comprises: a semiconductor substrate including a first insulating layer and a plurality of first terminals disposed on the first insulating layer; and A semiconductor element stacked on the semiconductor substrate, the semiconductor element comprising a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein The first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from that of the first insulating layer and bonding the semiconductor substrate and the semiconductor element. (20) A method for manufacturing a semiconductor device, comprising: A semiconductor element is stacked on a semiconductor substrate having a first insulating layer and a plurality of first terminals arranged on the first insulating layer, the semiconductor element having a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein Stacking the semiconductor element on the semiconductor substrate includes bonding the semiconductor substrate and the semiconductor element via a third insulating layer, the third insulating layer being formed of a material different from that of the first insulating layer and being included in the first insulating layer or the second insulating layer. (twenty one) An electronic device comprising the semiconductor device according to any one of (1) to (18). (twenty two) A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device according to any one of (1) to (18). Description of Reference Numerals

[0147] 1A semiconductor device 1B Semiconductor Device 1C semiconductor device 1D semiconductor device 1E Semiconductor Device 1F semiconductor device 1G semiconductor device 1H semiconductor device 10Semiconductor substrate 11 substrate 12 Circuit Elements 13 terminals 14 Insulation layer 14a Insulation layer 14b Insulation layer 14c insulation layer 14d insulation layer 14e insulation layer 20Semiconductor components 20A first semiconductor element 20B second semiconductor element 20C Third semiconductor element 21 substrate 22 Circuit components 23 terminals 24 Insulation layer 24a insulation layer 24b insulation layer 24c insulation layer 100 pixels 100A transistor 100b Photodiode 101 signal line 102 signal line 103 pixel internal wiring 104 pixel internal wiring 105 power wiring 106 Power wiring 107 Connection Points 110 Drive 120ADC 120A load current source 120b Comparator 120c counter 120d reference voltage generating unit 121 wiring 122 transistors 300 Camera Devices 400 Distance Measuring Device A1 chip A2 Chip C1 parasitic capacitance C2 Phase compensation capacitor C3 pixel internal capacitance C4 parasitic capacitance R1 dense area R2 sparse area R3 Central Area R4 peripheral area R11 pixel area R12 connection area V1 via V2 via W1 chip W2 chip W3 chip W4 chip W5 chip W6 chip

Claims

1. A semiconductor device comprising: A semiconductor substrate comprising a first insulating layer and a plurality of first terminals disposed on the first insulating layer; and A semiconductor element stacked on the semiconductor substrate, the semiconductor element comprising a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein The first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from that of the first insulating layer and bonding the semiconductor substrate and the semiconductor element.

2. The semiconductor device according to claim 1, wherein The second insulating layer includes the third insulating layer.

3. The semiconductor device according to claim 2, wherein: The third insulating layer is formed over the entire region of the surface of the semiconductor element on the semiconductor substrate side, and the third insulating layer is formed to avoid the plurality of second terminals.

4. The semiconductor device according to claim 2, wherein: The semiconductor element has a first region and a second region, in which a part of the plurality of second terminals are arranged at a first pitch, and in which a part of the plurality of second terminals are arranged at a second pitch wider than the first pitch. The third insulating layer is formed in the second region.

5. The semiconductor device according to claim 2, wherein: The third insulating layer is formed in an outer peripheral region of a surface of the semiconductor element on the semiconductor substrate side.

6. The semiconductor device according to claim 1, wherein The first insulating layer includes the third insulating layer.

7. The semiconductor device according to claim 6, wherein: The third insulating layer is formed in a region of the surface of the semiconductor substrate on the side of the semiconductor element, the region facing the semiconductor element.

8. The semiconductor device according to claim 6, wherein: The semiconductor element has a first region and a second region, in which a part of the plurality of second terminals are arranged at a first pitch, and in which a part of the plurality of second terminals are arranged at a second pitch wider than the first pitch. The third insulating layer is formed in a region of the surface of the semiconductor substrate on the side of the semiconductor element, the region facing the second region.

9. The semiconductor device according to claim 6, wherein: The third insulating layer is formed in a region of the surface of the semiconductor substrate on the semiconductor element side, the region facing an outer peripheral region of the surface of the semiconductor element on the semiconductor substrate side.

10. The semiconductor device according to claim 1, wherein The third insulating layer has a dielectric constant different from a dielectric constant of the first insulating layer or the second insulating layer.

11. The semiconductor device according to claim 1, wherein The first insulating layer and the second insulating layer both include the third insulating layer.

12. The semiconductor device according to claim 11, wherein The plurality of third insulating layers are disposed at positions facing each other.

13. The semiconductor device according to claim 11, wherein The third insulating layer included in the first insulating layer has a dielectric constant different from that of the first insulating layer, and The third insulating layer included in the second insulating layer has a dielectric constant different from that of the second insulating layer.

14. The semiconductor device according to claim 1, wherein The material of the third insulating layer is determined so that the bonding strength of the third insulating layer between the semiconductor substrate and the semiconductor element increases as the size of the semiconductor element decreases.

15. The semiconductor device according to claim 1, wherein The material or thickness of the third insulating layer is determined so that a withstand voltage of the third insulating layer between the plurality of second terminals becomes higher as a pitch of the plurality of second terminals becomes narrower.

16. The semiconductor device according to claim 1, wherein The semiconductor element is provided in plurality, and The third insulating layer is provided for each of the semiconductor elements.

17. The semiconductor device according to claim 16, wherein: The material of the third insulating layer of each of the semiconductor elements is different for each of the semiconductor elements.

18. The semiconductor device according to claim 17, wherein: The material of the third insulating layer of each of the semiconductor elements is determined so as to suppress deformation caused by a difference in thermal expansion coefficient among the plurality of semiconductor elements.

19. An electronic device having a semiconductor device, the semiconductor device comprising: A semiconductor substrate comprising a first insulating layer and a plurality of first terminals disposed on the first insulating layer; and A semiconductor element stacked on the semiconductor substrate, the semiconductor element comprising a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein The first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from that of the first insulating layer and bonding the semiconductor substrate and the semiconductor element.

20. A method for manufacturing a semiconductor device, comprising: A semiconductor element is stacked on a semiconductor substrate having a first insulating layer and a plurality of first terminals arranged on the first insulating layer, the semiconductor element having a second insulating layer and a plurality of second terminals, the plurality of second terminals being arranged on the second insulating layer and respectively connected to the plurality of first terminals, wherein Stacking the semiconductor element on the semiconductor substrate includes bonding the semiconductor substrate and the semiconductor element via a third insulating layer, the third insulating layer being formed of a material different from that of the first insulating layer and being included in the first insulating layer or the second insulating layer.

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