Semiconductor device, design method and manufacturing method thereof

Abstract

According to an embodiment, a semiconductor device includes a first cell including a first PMOS transistor, a second PMOS transistor arranged in alignment with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged in alignment with the first NMOS transistor, and a seventh wiring not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, a design method thereof, and a manufacturing method thereof. Background Art

[0002] In the layout design of semiconductor devices, an automatic place and route technology for automatically arranging cells and wiring connections is sometimes used.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2012-043894 Summary of the invention

[0006] Problems to be solved by the invention

[0007] One embodiment of the present invention provides a semiconductor device capable of suppressing an increase in development cost and an extension of development period.

[0008] Means for solving problems

[0009] The semiconductor device of the embodiment includes a first unit, wherein the first unit includes: a first PMOS transistor; a second PMOS transistor arranged in a first direction with the first PMOS transistor, and one end of which is shared with one end of the first PMOS transistor; a first NMOS transistor arranged in a second direction intersecting the first direction with the first PMOS transistor; a second NMOS transistor arranged in the first direction with the first NMOS transistor, and one end of which is shared with one end of the first NMOS transistor; a first wiring electrically connected to the other end of the first PMOS transistor; a second wiring electrically connected to one end of the first PMOS transistor and one end of the second PMOS transistor; a third wiring electrically connected to the other end of the second PMOS transistor; a power supply A voltage wiring extends in the second direction, is arranged above the first wiring, the second wiring and the third wiring, and is electrically connected to the first wiring, the second wiring and the third wiring; a fourth wiring is electrically connected to the other end of the first NMOS transistor; a fifth wiring is electrically connected to one end of the first NMOS transistor and one end of the second NMOS transistor; a sixth wiring is electrically connected to the other end of the second NMOS transistor; a ground voltage wiring extends in the second direction, is arranged above the fourth wiring, the fifth wiring and the sixth wiring, and is electrically connected to the fourth wiring, the fifth wiring and the sixth wiring; and a seventh wiring is arranged on the same layer as the first to sixth wirings, and is not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing the overall structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 This is a circuit diagram of a memory cell array included in the semiconductor device according to the first embodiment.

[0012] Figure 3 It is a cross-sectional view of a PMOS transistor included in the semiconductor device according to the first embodiment.

[0013] Figure 4 It is a cross-sectional view of an NMOS transistor included in the semiconductor device according to the first embodiment.

[0014] Figure 5 It is a plan view of a standard cell of a NAND circuit included in the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a plan view of a standard cell of a NOR circuit included in the semiconductor device according to the first embodiment.

[0016] Figure 7 It is a plan view of a standard cell of the inverter circuit included in the semiconductor device according to the first embodiment.

[0017] Figure 8 It is a plan view of a standard cell of the buffer circuit included in the semiconductor device according to the first embodiment.

[0018] Fig. 9 It is a top view of a transistor of an ECO basic unit included in the semiconductor device of the first embodiment.

[0019] Fig.10 It is a plan view of an ECO basic cell including a decoupling capacitor included in the semiconductor device according to the first embodiment.

[0020] Fig.11 This is an equivalent circuit diagram of an ECO basic cell including a decoupling capacitor included in the semiconductor device of the first embodiment.

[0021] Fig.12 It is a plan view of an ECO basic cell constituting a NAND circuit included in the semiconductor device according to the first embodiment.

[0022] Fig.13 It is a plan view of an ECO basic cell including a NOR circuit included in the semiconductor device according to the first embodiment.

[0023] Fig.14 It is a plan view of an ECO basic cell including an inverter circuit included in the semiconductor device according to the first embodiment.

[0024] Fig.15 It is a plan view of an ECO basic cell constituting a buffer circuit included in the semiconductor device according to the first embodiment.

[0025] Fig.16 It is a plan view of an ECO basic cell including a through cell included in the semiconductor device according to the first embodiment.

[0026] Fig.17 This is an equivalent circuit diagram of an ECO basic cell including a through cell included in the semiconductor device of the first embodiment.

[0027] Fig.18 It is a top view of a filling unit included in the semiconductor device according to the first embodiment.

[0028] Fig.19 It is a plan view showing a specific example of using the through cell in the semiconductor device according to the first embodiment.

[0029] Fig. 20 This is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Fig.21 This is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Fig. 22 This is a diagram showing an example of a planar layout after standard cells are arranged in the layout design of the semiconductor device according to the first embodiment.

[0032] Fig.23 This is a diagram showing an example of a planar layout in which ECO basic cells including decoupling capacitors are arranged in the layout design of the semiconductor device according to the first embodiment.

[0033] Fig.24 This is a diagram showing an example of a planar layout after arranging fill cells in the layout design of the semiconductor device according to the first embodiment.

[0034] Fig.25 This is a diagram showing an example of a planar layout after the ECO logic cell is changed in the layout design of the semiconductor device according to the first embodiment.

[0035] Fig.26 This is a diagram showing an example of a planar layout after a through cell is changed in the layout design of the semiconductor device according to the first embodiment.

[0036] Fig. 27 It is a plan view showing a specific example of using a through cell in a semiconductor device according to a first modification of the first embodiment.

[0037] Fig.28 It is a plan view showing a specific example of using a through cell in a semiconductor device according to a first modification of the first embodiment.

[0038] Fig.29 It is a plan view showing a specific example of using a through cell in a semiconductor device according to a first modification of the first embodiment.

[0039] Fig.30 It is a plan view of a transistor of an ECO basic unit included in a semiconductor device according to a second modification of the first embodiment.

[0040] Fig.31 It is a plan view of a transistor of an ECO basic unit included in a semiconductor device according to a second modification of the first embodiment.

[0041] Fig.32 It is a plan view of an ECO basic cell including a through cell including a decoupling capacitor formed of an NMOS transistor, which is included in a semiconductor device according to a third modification of the first embodiment.

[0042] Fig.33 This is an equivalent circuit diagram of an ECO basic cell including a through cell including a decoupling capacitor formed of an NMOS transistor, which is included in a semiconductor device according to a third modification of the first embodiment.

[0043] Fig.34 It is a plan view of an ECO basic cell including a through cell including a decoupling capacitor formed of a PMOS transistor, which is included in a semiconductor device according to a third modification of the first embodiment.

[0044] Fig.35 This is an equivalent circuit diagram of an ECO basic cell including a through cell including a decoupling capacitor formed of a PMOS transistor, which is included in a semiconductor device according to a third modification of the first embodiment.

[0045] Fig.36 This is a flowchart of a method for manufacturing a semiconductor device according to a fourth modification of the first embodiment.

[0046] Fig.37 This is a flowchart of a method for manufacturing a semiconductor device according to a fourth modification of the first embodiment.

[0047] Fig.38 It is a block diagram showing the overall structure of a semiconductor device according to a second embodiment.

[0048] Fig.39 It is a block diagram showing the overall structure of a semiconductor device according to a third embodiment.

[0049] Fig.40 It is a block diagram showing the overall structure of a semiconductor device according to a fourth embodiment.

[0050] Fig.41 It is a block diagram showing the overall structure of a semiconductor device according to a fifth embodiment.

[0051] Fig.42 This is a circuit diagram of a memory cell array included in a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION

[0052] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, in the following description, the same reference numerals are used to mark the constituent elements having substantially the same function and structure. In the case where repeated description is not necessary, it is sometimes omitted. In addition, each embodiment shown below illustrates an apparatus and method for concretizing the technical idea of ​​the embodiment. The technical idea of ​​the embodiment does not limit the material, shape, structure, configuration, etc. of the constituent parts to the following contents. The technical idea of ​​the embodiment can be subjected to various changes within the scope of the main purpose of the invention. These embodiments and their modifications are included in the invention described in the claims and the scope of their equivalents.

[0053] 1. First Implementation

[0054] The semiconductor device of the first embodiment is described. In this embodiment, the case where the semiconductor device is a NAND flash memory is described. In addition, the semiconductor device 1 may also be a non-volatile semiconductor memory device other than a NAND flash memory. For example, the semiconductor device 1 may be a FeRAM (Ferroelectric Random Access Memory). Furthermore, the semiconductor device 1 may also be a device other than a semiconductor memory device.

[0055] 1.1 Overall structure of semiconductor devices

[0056] First, refer to Figure 1 , an example of the overall structure of the semiconductor device 1 is described. Figure 1 1 is a block diagram showing the overall structure of the semiconductor device 1. Figure 1 In the figure, a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0057] The semiconductor device 1 is, for example, a NAND flash memory, which includes a plurality of nonvolatile memory cell transistors (also referred to as memory cells).

[0058] The semiconductor device 1 is connected to an external controller (not shown) and operates based on a command from the external controller.

[0059] The semiconductor device 1 includes a memory cell array 10 , an input / output circuit 11 , a command register 12 , an address register 13 , a sequencer 14 , a voltage generation circuit 15 , a drive circuit 16 , a row control circuit 17 , and a sense amplifier 18 .

[0060] The memory cell array 10 is a collection of a plurality of memory cell transistors arranged in a row. The memory cell array 10 includes a plurality of blocks BLK. Figure 1 In the example, the memory cell array 10 includes four blocks BLK0, BLK1, BLK2 and BLK3. Block BLK is, for example, a collection of multiple memory cell transistors whose data is uniformly erased. Each memory cell transistor is associated with a row and a column. More specifically, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with, for example, a bit line and a word line. The detailed structure of the memory cell array 10 will be described later.

[0061] The input / output circuit 11 is a circuit for inputting and outputting signals to and from an external controller. That is, the input / output circuit 11 functions as an interface circuit on the semiconductor device 1 side between the semiconductor device 1 and the external controller.

[0062] The input / output circuit 11 transmits and receives the signal DQ and the clock signals DQS and DQSn with the external controller. For example, the signal DQ is data DT, address information ADD or command CMD. For example, the command CMD includes a command for the sequencer 14 to perform a read operation, a write operation and an erase operation. The clock signals DQS and DQSn are clock signals used when inputting and outputting the data DT. The clock signal DQSn is an inverted signal of the clock signal DQS.

[0063] The input-output circuit 11 is connected to the command register 12, the address register 13, and the sense amplifier 18. The input-output circuit 11 sends a command CMD to the command register 12. The input-output circuit 11 sends address information ADD to the address register 13. The input-output circuit 11 sends data DT (write data) to the sense amplifier 18. In addition, the input-output circuit 11 receives data DT (read data) from the sense amplifier 18.

[0064] The input / output circuit 11 receives various control signals from an external controller. For example, the semiconductor device 1 receives a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the external controller. The command latch enable signal CLE is a signal indicating that the signal DQ received from the external controller is a command CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received from the external controller is address information ADD. The write enable signal WEn is a signal that instructs the semiconductor device 1 to input the signal DQ. The read enable signal REn is a signal that instructs the semiconductor device 1 to output the signal DQ.

[0065] The input / output circuit 11 sends a ready / busy signal RBn to the external controller. The ready / busy signal RBn is a signal indicating whether the semiconductor device 1 is in a busy state or a ready state. The busy state is a state in which the semiconductor device 1 cannot receive a DQ signal from the external controller. The ready state is a state in which the semiconductor device 1 can receive a DQ signal from the external controller.

[0066] The input / output circuit 11 has a function as a digital signal control circuit (also referred to as a “logic circuit”) that processes digital signals such as a signal DQ and a control signal received from an external controller, for example.

[0067] The command register 12 temporarily stores the command CMD. The command register 12 is connected to the sequencer 14. The command register 12 sends the command CMD to the sequencer 14.

[0068] The command register 12 functions as a digital signal control circuit that processes a received digital signal (command CMD).

[0069] The address register 13 temporarily stores address information ADD. For example, the address information ADD includes a block address, a page address (word line address), and a column address. The block address, the page address, and the column address are used to select a block BLK, a word line, and a bit line in the memory cell array 10, respectively. The address register 13 is connected to a drive circuit 16, a row control circuit 17, and a sense amplifier 18. For example, the address register 13 sends a page address to the drive circuit 16. The address register 13 sends a block address to the row control circuit 17. The address register 13 sends a column address to the sense amplifier 18. Hereinafter, the block BLK selected based on the block address is described as a selected block BLK. The word line selected based on the page address is described as a selected word line.

[0070] The address register 13 functions as a digital signal control circuit that processes a received digital signal (address information ADD).

[0071] The sequencer 14 controls the overall operation of the semiconductor device 1. For example, the sequencer 14 is connected to the voltage generation circuit 15, the drive circuit 16, the row control circuit 17, and the sense amplifier 18. The sequencer 14 controls the voltage generation circuit 15, the drive circuit 16, the row control circuit 17, and the sense amplifier 18. For example, the sequencer 14 performs a read operation, a write operation, an erase operation, and the like based on the command CMD.

[0072] The sequencer 14 functions as a digital signal control circuit that processes received digital signals (commands CMD and the like).

[0073] The voltage generation circuit 15 generates various voltages based on the control of the sequencer 14. The voltage generation circuit 15 is connected to the drive circuit 16. The voltage generation circuit 15 supplies the generated voltage to the drive circuit 16.

[0074] The voltage generating circuit 15 includes a digital signal control circuit 15a. The digital signal control circuit 15a is a circuit that processes a received digital signal (a control signal received from the sequencer 14).

[0075] The driving circuit 16 is a circuit that supplies voltage to the row control circuit 17 and the sense amplifier 18. The driving circuit 16 is connected to the row control circuit 17 and the sense amplifier 18. More specifically, the driving circuit 16 supplies a plurality of voltages used in a read operation, a write operation, an erase operation, etc. to the row control circuit 17 and the sense amplifier 18 based on the control of the sequencer 14. The driving circuit 16 is connected to the row control circuit 17 via a plurality of wirings CGI. For example, the driving circuit 16 applies a predetermined voltage to each of the plurality of wirings CGI based on a page address.

[0076] The driving circuit 16 includes a digital signal control circuit 16a. The digital signal control circuit 16a is a circuit that processes the received digital signal (address information ADD and the control signal received from the sequencer 14).

[0077] The row control circuit 17 is a circuit that controls the row-direction wiring (word line and selection gate line) of the memory cell array 10. The row control circuit 17 is connected to the memory cell array 10. For example, the row control circuit 17 selects a block BLK in the memory cell array 10 based on the block address. For example, the row control circuit 17 transmits the voltage applied to the wiring CGI corresponding to the selected word line to the selected word line in the selected block BLK.

[0078] The row control circuit 17 includes a digital signal control circuit 17a. The digital signal control circuit 17a is a circuit that processes the received digital signal (address information ADD and the control signal received from the sequencer 14).

[0079] The sense amplifier 18 is a circuit that controls the wiring (bit line) in the column direction of the memory cell array 10. The sense amplifier 18 is connected to the memory cell array 10. The sense amplifier 18 applies a voltage to each bit line of the memory cell array 10 based on the write data DT in the write operation. In addition, the sense amplifier 18 determines the data stored in the memory cell transistor based on the voltage of the bit line in the read operation, and transmits the determination result to the input-output circuit 11 as the read data DT.

[0080] The sense amplifier 18 includes a digital signal control circuit 18a. The digital signal control circuit 18a is a circuit that processes the received digital signal (address information ADD and the control signal received from the sequencer 14).

[0081] 1.2 Circuit structure of memory cell array

[0082] Next, refer to Figure 2 An example of the circuit configuration of the memory cell array 10 will be described. Figure 2 is a circuit diagram of the memory cell array 10. In addition, Figure 2 The example shows the circuit structure of one block BLK.

[0083] like Figure 2 As shown, the block BLK includes a plurality of string units SU. The string unit SU includes a plurality of NAND strings NS. Figure 2 In the example, each block BLK includes four string units SU0 to SU3. The string unit SU is, for example, a set of multiple NAND strings uniformly selected in a write operation or a read operation. In addition, the number of blocks BLK in the memory cell array 10 and the number of string units SU in the block BLK are arbitrary.

[0084] The NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2. Figure 2 In the example of , the NAND string NS includes eight memory cell transistors MC0 to MC7. In addition, the number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0085] The memory cell transistor MC is a memory element that stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage film. The memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer in the charge storage film. The FG type uses a conductor in the charge storage film.

[0086] The selection transistors ST1 and ST2 are switch elements. The selection transistors ST1 and ST2 are used to select the string unit SU in various operations. The number of the selection transistors ST1 and ST2 included in the NAND string NS is arbitrary. As long as the NAND string NS includes more than one selection transistor ST1 and ST2, it will suffice.

[0087] The current path of the selection transistor ST2, memory cell transistors MC0 to MC7, and the selection transistor ST1 in the NAND string NS is connected in series. The drain of the selection transistor ST1 is connected to the bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

[0088] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are connected to the word lines WL0 to WL7 in common. More specifically, the control gates of the plurality of memory cell transistors MC0 in the block BLK are connected to one word line WL0 in common. The same is true for the memory cell transistors MC1 to MC7.

[0089] The gates of the multiple selection transistors ST1 in the string unit SU are commonly connected to a selection gate line SGD. More specifically, the gates of the multiple selection transistors ST1 in the string unit SU0 are commonly connected to the selection gate line SGD0. The gates of the multiple selection transistors ST1 in the string unit SU1 are commonly connected to the selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string unit SU2 are commonly connected to the selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string unit SU3 are commonly connected to the selection gate line SGD3.

[0090] The gates of the plurality of selection transistors ST2 in the block BLK are commonly connected to a selection gate line SGS. In addition, similarly to the selection gate line SGD, a different selection gate line SGS may be provided for each string unit SU.

[0091] The word lines WL0 to WL7 , the selection gate lines SGD0 to SGD3 , and the selection gate line SGS are respectively connected to the row control circuit 17 .

[0092] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address is assigned to a plurality of NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 18.

[0093] The source line SL is shared by, for example, a plurality of blocks BLK.

[0094] A set of a plurality of memory cell transistors MC connected to a common word line WL in one string unit SU is expressed as, for example, a “cell unit CU.” For example, a write operation and a read operation are performed in units of the cell unit CU.

[0095] 1.3 Automatic wiring layout

[0096] Next, the automatic layout and wiring are described. In the present embodiment, the automatic layout and wiring technology of the standard cell method is applied in the layout design of various digital signal control circuits included in the semiconductor device 1. In the automatic layout and wiring of the standard cell method, the layout design is performed by arranging various units (circuit blocks) without gaps on the semiconductor substrate. For example, in some cases, the circuit is corrected after the layout design. In such a case, the operation of correcting the layout by suppressing changes from the original layout data as much as possible is expressed as ECO (Engineering Change Order: engineering modification, engineering change). ECO includes device ECO (Device ECO) (also expressed as pre-mask ECO (Pre-mask ECO)) and metal ECO (Metal ECO) (also expressed as post-mask ECO (Post-mask ECO)). In the device ECO, changes including the layout of various units (transistors / circuit blocks) (hereinafter also expressed as "device layout") are made. In the metal ECO, the device layout is changed as the wiring layout is changed.

[0097] For example, in automatic placement and wiring, standard cells (also referred to as "logic cells"), ECO basic cells, and filling cells are used. Hereinafter, when not limited to any one of the standard cells, ECO basic cells, and filling cells, it is simply referred to as a "cell".

[0098] The standard cell and the ECO basic cell include a plurality of p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) (hereinafter referred to as "PMOS transistors") and n-channel MOSFETs (hereinafter referred to as "NMOS transistors"). Hereinafter, when not limited to either PMOS transistors or NMOS transistors, they are simply referred to as "transistors".

[0099] A plurality of transistors in a cell are interconnected via the bottom M1 wiring. An M2 wiring is provided above the M1 wiring. A power supply voltage VDD or a ground voltage VSS is supplied to the transistor via the M2 wiring. That is, the M2 wiring functions as a power supply voltage wiring or a ground voltage wiring. An M3 wiring is provided above the M2 wiring. An M4 wiring is provided above the M3 wiring. For example, M3 wiring and M4 wiring are used in the connection between cells. In addition, the number of layers of wiring used in the automatic layout wiring is not limited to four. The number of layers of wiring used in the automatic layout wiring can be three or more layers.

[0100] A standard cell is a cell that is pre-configured with a NAND (NAND) circuit, a NOR (exclusive OR) circuit, an inverter circuit, or a buffer circuit. In a standard cell, the configuration of the transistor and the M1 wiring and M2 wiring connected thereto are designed in advance. The type and number of transistors included in the standard cell are based on the configured circuit. The configuration of the standard cell and the M3 wiring and M4 wiring connected to the standard cell are determined by automatic layout wiring.

[0101] The ECO basic cell is a cell corresponding to the metal ECO. The ECO basic cell can change the circuit function by using the metal ECO to change the connection between the transistors configured in the ECO basic cell, that is, the layout of the M1 wiring. In the automatic layout wiring, the ECO basic cell is configured in the gap after the standard cell is configured. For example, in some cases, after the configuration of the cell is completed, the circuit design changes. In such a case, by executing the metal ECO of the ECO basic cell, the change of the circuit design can be coped with without changing the configuration of the cell.

[0102] In the ECO basic cell, the configuration of transistors is predetermined. For example, the ECO basic cell includes two PMOS transistors and two NMOS transistors. By automatically placing and routing, the configuration of the ECO basic cell and the M1 to M4 wirings connected to the transistors of the ECO basic cell are designed.

[0103] The ECO basic unit can constitute a decoupling capacitor, a NAND circuit, a NOR circuit, an inverter circuit, or a buffer circuit according to the layout of the M1 wiring. For example, when the transistor in the ECO basic unit is not used in the circuit structure of the semiconductor device 1, that is, when the metal ECO is not performed, a decoupling capacitor is formed. By forming a decoupling capacitor, the potential of each terminal of the transistor is determined. When the metal ECO is performed, the structure of the ECO basic unit can be changed from a decoupling capacitor to a NAND circuit, a NOR circuit, an inverter circuit, or a buffer circuit. In the following, the ECO basic unit that is constituted by a NAND circuit, a NOR circuit, an inverter circuit, or a buffer circuit is also described as an "ECO logic unit."

[0104] In addition, the ECO basic cell of this embodiment can form a through cell by performing metal ECO. The through cell includes an M1 wiring connected to the transistor in the through cell and an M1 wiring used for connecting two cells adjacent to the through cell. The M1 wiring used for connecting adjacent cells is not connected to the transistor in the through cell.

[0105] The filling cell is a cell arranged in the gap after the standard cell and the ECO basic cell are arranged. The filling cell includes an N-type well region corresponding to the M2 wiring and the PMOS transistor. No transistor is set in the filling cell. For example, in the direction in which the M2 wiring extends, if there is a gap between the cells, the M2 wiring, that is, the power supply voltage wiring and the ground voltage wiring becomes a disconnected state. By inserting the filling cell in the gap, the M2 wiring between adjacent cells is connected. Similarly, by inserting the filling cell, the N-type well region between adjacent cells is connected.

[0106] 1.3.1 Cross-sectional structure of PMOS and NMOS transistors

[0107] Next, refer to Figure 3 and Figure 4 An example of the cross-sectional structure of a PMOS transistor and an NMOS transistor will be described. Figure 3 is a cross-sectional view of a PMOS transistor. Figure 4 is a cross-sectional view of an NMOS transistor. Figure 3 and Figure 4 In the example of , the interlayer insulating film is omitted. In the following description, the direction parallel to the surface of the semiconductor substrate is set as the X direction. The direction parallel to the surface of the semiconductor substrate and intersecting the X direction is set as the Y direction. The direction intersecting the semiconductor substrate and intersecting the X direction and the Y direction is set as the Z direction.

[0108] First, the cross-sectional structure of the PMOS transistor TP is described. Figure 3 As shown, an N-type well region 101 is provided near the surface of the semiconductor substrate 100. The N-type well region 101 is doped with, for example, phosphorus (P). The region of the N-type well region 101 separated by the element isolation region STI functions as an active area (AA: Active Area) 102 of the PMOS transistor TP. The element isolation region STI uses, for example, silicon oxide (SiO).

[0109] Two p + The impurity diffusion region 103. + The impurity diffusion region 103 is doped with, for example, boron (B). + The impurity diffusion regions 103 function as a source and a drain of the PMOS transistor TP.

[0110] For example, two p + The impurity diffusion regions 103 are arranged separately in the X direction. +A gate insulating film 110 is provided between the impurity diffusion regions 103 on the active region 102. The gate insulating film includes, for example, an oxide metal such as silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), or hafnium silicon oxynitride (HfSiON).

[0111] A gate electrode 111 is provided on the gate insulating film. For example, the gate electrode 111 includes a conductive material such as polysilicon, tungsten (W), tungsten silicide (WSi), and titanium nitride (TiN). For example, the gate electrode 111 includes a stack of polysilicon, polysilicon and silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi). For example, the gate electrode 111 includes a stack of silicon nitride (SiN), polysilicon and tungsten (W), and tungsten silicide (WSi). For example, the gate electrode 111 includes aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the gate electrode 111 includes a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), titanium aluminum nitride (AlTiN), titanium aluminum nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN), and titanium nitride (TiN). For example, the gate electrode 111 includes a stack of silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). For example, the gate electrode 111 includes a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). In addition, the stack described here may not include all layers, but only include a part of the layers.

[0112] In p + A contact plug 120 is provided on the impurity diffusion region 103 and the gate electrode 111. For example, the contact plug 120 has a cylindrical shape extending in the Z direction.

[0113] An M1 wiring 130 is provided over the contact plug 120 .

[0114] A contact plug 140 is provided over the M1 wiring 130. For example, the contact plug 140 has a cylindrical shape extending in the Z direction.

[0115] An M2 wiring 150 is provided over the contact plug 140. For example, the M2 wiring 150 extends in the X direction.

[0116] A contact plug 160 is provided on the M2 wiring 150. For example, the contact plug 160 has a cylindrical shape extending in the Z direction.

[0117] An M3 wiring 170 is provided over the contact plug 160. For example, the M3 wiring 170 extends in the Y direction.

[0118] A contact plug 180 is provided on the M3 wiring 170. For example, the contact plug 180 has a cylindrical shape extending in the Z direction.

[0119] An M4 wiring 190 is provided over the contact plug 180. For example, the M4 wiring 190 extends in the X direction.

[0120] The M1 wiring 130 and the M2 wiring 150 include, for example, tungsten (W). The M3 wiring 170 and the M4 wiring 190 include, for example, tungsten (W), copper (Cu), or aluminum (Al). The M1 wiring 130, the M2 wiring 150, the M3 wiring 170, and the M4 wiring 190 include barrier metals such as titanium nitride (TiN), tantalum nitride (TaN), or a stack of tantalum nitride (TaN) and tantalum (Ta).

[0121] Next, the cross-sectional structure of the NMOS transistor TN is described. Figure 4 As shown, a P-type well region is provided in a region surrounded by the device isolation region STI near the surface of the semiconductor substrate 100. The P-type well region functions as an active region 104 of the NMOS transistor TN.

[0122] Two n + The impurity diffusion region 105. + The impurity diffusion region 105 is doped with phosphorus (P), for example. + The impurity diffusion regions 105 function as a source and a drain of the NMOS transistor TN.

[0123] For example, two n + The impurity diffusion regions 105 are arranged separately in the X direction. + A gate insulating film 110 is provided between the impurity diffusion regions 103 and on the active region 104. A gate electrode 111 is provided on the gate insulating film.

[0124] In n + A contact plug 120 is provided on the impurity diffusion region 105 and the gate electrode 111. The structure of the wiring and the contact plug above the contact plug 120 is similar to that of Figure 3 Same description as .

[0125] 1.3.2 Planar structure of standard cell

[0126] Next, an example of a planar structure of a standard cell will be described. Hereinafter, a standard cell of a NAND circuit, a NOR circuit, an inverter circuit, and a buffer circuit will be described.

[0127] 1.3.2.1 NAND Circuit

[0128] First, refer to Figure 5 An example of a planar structure of a standard cell of a NAND circuit will be described. Figure 5 is a top view of a standard cell of a NAND circuit. Figure 5 In the example of , the interlayer insulating film is omitted. In the following description, either the source or the drain of a transistor is referred to as one end of the transistor. In addition, the other either the source or the drain of a transistor is referred to as the other end of the transistor.

[0129] like Figure 5 As shown, for example, the standard cell has a rectangular shape with a long side extending in the Y direction and a short side extending in the X direction. The same is true for the ECO basic cell and the filling cell described later.

[0130] For example, the length of the long side of each cell (standard cell, ECO basic cell and filling cell) is the same because it corresponds to the automatic layout wiring. The length of the short side of each cell is different according to the structure of the cell. In addition, the positions of the M2 wiring 150 and the N-type well region 101 in the Y direction of the standard cell, the ECO basic cell and the filling cell are respectively the same. When the cells are arranged in the Y direction, the M2 wiring 150 and the N-type well region 101 are connected to each other between the cells.

[0131] The standard cell 1001 of the NAND circuit includes an N-type well region 101 , PMOS transistors TP1 and TP2 , NMOS transistors TN1 and TN2 , an M1 wiring 130 , an M2 wiring 150 , and contact plugs 120 and 140 .

[0132] exist Figure 5 In the example of FIG. 1 , an N-type well region 101 is provided on the upper side of the standard cell 1001 of the NAND circuit.

[0133] The PMOS transistors TP1 and TP2 and the NMOS transistors TN1 and TN2 are arranged in the Y direction. The PMOS transistors TP1 and TP2 are provided in the N-type well region 101. In other words, in the N-type well region 101, the active region 102 corresponding to the PMOS transistor TP1 and the active region 102 corresponding to the PMOS transistor TP2 are arranged in the Y direction. In addition, the active region 104 corresponding to the NMOS transistor TN1 and the active region 104 corresponding to the NMOS transistor TN2 are arranged in the Y direction.

[0134] Four M2 wirings 150_1 to 150_4 extending in the X direction are provided in the standard cell 1001. For example, the M2 wirings 150_1 and 150_2 provided above the N-type well region 101 (PMOS transistor TP) function as power supply voltage wirings. The M2 wirings 150_3 and 150_4 provided above the NMOS transistor TN function as ground voltage wirings. In addition, the M2 wirings 150 functioning as power supply voltage wirings and ground voltage wirings may be one or more.

[0135] One ends of the PMOS transistors TP1 and TP2 are commonly connected to M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_1.

[0136] One ends of the NMOS transistors TN1 and TN2 are connected in common via an M1 wiring 130_2.

[0137] The other ends of the PMOS transistors TP1 and TP2 and the other end of the NMOS transistor TN1 are connected together via an M1 wiring 130_3. The M1 wiring 130_3 functions as a signal output wiring (OUT) of the NAND circuit.

[0138] The other end of the NMOS transistor TN2 is connected to the M2 wiring 150_4 (ground voltage wiring) via the M1 wiring 130_4.

[0139] The gate electrode 111 of the PMOS transistor TP1 is connected to the gate electrode 111 of the NMOS transistor TN2 via the M1 wiring 130_5. The M1 wiring 130_5 functions as one signal input wiring (IN1) of the NAND circuit.

[0140] The gate electrode 111 of the PMOS transistor TP2 is connected to the gate electrode 111 of the NMOS transistor TN1 via the M1 wiring 130_6. The M1 wiring 130_6 functions as another signal input wiring (IN2) of the NAND circuit.

[0141] 1.3.2.2NOR Circuit

[0142] Next, refer to Figure 6 An example of a planar structure of a standard cell of a NOR circuit will be described. Figure 6 is a top view of a standard cell of a NOR circuit. Figure 6 In the example, the interlayer insulating film is omitted.

[0143] like Figure 6As shown, a standard cell 1002 of a NOR circuit includes an N-type well region 101 , PMOS transistors TP3 and TP4 , NMOS transistors TN3 and TN4 , an M1 wiring 130 , an M2 wiring 150 , and contact plugs 120 and 140 .

[0144] Similar to the standard cell 1001, the standard cell 1002 is provided with an N-type well region 101 and M2 wirings 150_1 to 150_4. The positions of the N-type well region 101 and M2 wirings 150_1 to 150_4 in the Y direction are the same as those of the standard cell 1001. The four M2 wirings 150_1 to 150_4 extend in the X direction, respectively.

[0145] The PMOS transistors TP3 and TP4 and the NMOS transistors TN3 and TN4 are arranged in the Y direction. The PMOS transistors TP3 and TP4 are provided in the N-type well region 101. In the N-type well region 101, the active region 102 corresponding to the PMOS transistor TP3 and the active region 102 corresponding to the PMOS transistor TP4 are arranged in the Y direction. In addition, the active region 104 corresponding to the NMOS transistor TN3 and the active region 104 corresponding to the NMOS transistor TN4 are arranged in the Y direction.

[0146] One ends of the PMOS transistors TP3 and TP4 are connected in common via an M1 wiring 130_10.

[0147] One ends of the NMOS transistors TN3 and TN4 are commonly connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_11.

[0148] The other end of the PMOS transistor TP3 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_12.

[0149] The other end of the PMOS transistor TP4 and the other ends of the NMOS transistors TN3 and TN4 are commonly connected via an M1 wiring 130_13. The M1 wiring 130_13 functions as a signal output wiring (OUT) of the NOR circuit.

[0150] The gate electrode 111 of the PMOS transistor TP3 is connected to the gate electrode 111 of the NMOS transistor TN4 via the M1 wiring 130_14. The M1 wiring 130_14 functions as one signal input wiring (IN1) of the NOR circuit.

[0151] The gate electrode 111 of the PMOS transistor TP4 is connected to the gate electrode 111 of the NMOS transistor TN3 via the M1 wiring 130_15. The M1 wiring 130_15 functions as another signal input wiring (IN2) of the NOR circuit.

[0152] 1.3.2.3 Inverter Circuit

[0153] Next, refer to Figure 7 An example of a planar structure of a standard cell of an inverter circuit will be described. Figure 7 is a top view of a standard unit cell of an inverter circuit. Figure 7 In the example, the interlayer insulating film is omitted.

[0154] like Figure 7 As shown, the standard cell 1003 of the inverter circuit includes an N-type well region 101 , a PMOS transistor TP5 , an NMOS transistor TN5 , an M1 wiring 130 , an M2 wiring 150 , and contact plugs 120 and 140 .

[0155] Similar to the standard cell 1001, the standard cell 1003 is provided with an N-type well region 101 and M2 wirings 150_1 to 150_4. The positions of the N-type well region 101 and M2 wirings 150_1 to 150_4 in the Y direction are the same as those of the standard cell 1001. The four M2 wirings 150_1 to 150_4 extend in the X direction, respectively.

[0156] The PMOS transistor TP5 and the NMOS transistor TN5 are arranged side by side in the Y direction. The PMOS transistor TP5 is provided in the N-type well region 101. The active region 102 corresponding to the PMOS transistor TP5 and the active region 104 corresponding to the NMOS transistor TN5 are arranged side by side in the Y direction.

[0157] One end of the PMOS transistor TP5 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_20.

[0158] One end of the NMOS transistor TN5 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_21.

[0159] The other end of the PMOS transistor TP5 is connected to the other end of the NMOS transistor TN5 via the M1 wiring 130_22. The M1 wiring 130_22 functions as a signal output wiring (OUT) of the inverter circuit.

[0160] The gate electrode 111 of the PMOS transistor TP5 is connected to the gate electrode 111 of the NMOS transistor TN5 via the M1 wiring 130_23. The M1 wiring 130_23 functions as a signal input wiring (IN) of the inverter circuit.

[0161] 1.3.2.4 Buffer Circuit

[0162] Next, refer to Figure 8 An example of a planar structure of a standard cell of a buffer circuit will be described. Figure 8 is a top view of a standard unit of a buffer circuit. Figure 8 In the example, the interlayer insulating film is omitted.

[0163] like Figure 8 As shown, the standard cell 1004 of the buffer circuit includes an N-type well region 101 , PMOS transistors TP6 and TP7 , NMOS transistors TN6 and TN7 , an M1 wiring 130 , an M2 wiring 150 , and contact plugs 120 and 140 .

[0164] Similar to the standard cell 1001, the standard cell 1004 is provided with an N-type well region 101 and M2 wirings 150_1 to 150_4. The positions of the N-type well region 101 and M2 wirings 150_1 to 150_4 in the Y direction are the same as those of the standard cell 1001. The four M2 wirings 150_1 to 150_4 extend in the X direction, respectively.

[0165] The PMOS transistors TP6 and TP7 are disposed in the N-type well region 101. The PMOS transistors TP6 and TP7 are disposed in an active region 102. The PMOS transistors TP6 and TP7 are arranged in an X direction. The PMOS transistors TP6 and TP7 share a source or a drain.

[0166] The NMOS transistors TN6 and TN7 are disposed in an active region 104. The NMOS transistors TN6 and TN7 are arranged in parallel in the X direction. The NMOS transistors TN6 and TN7 share a source or a drain.

[0167] One end of the PMOS transistor TP6 is connected to one end of the NMOS transistor TN6 via the M1 wiring 130_30. The M1 wiring 130_30 functions as a signal output wiring (OUT) of the buffer circuit.

[0168] One end common to the PMOS transistors TP6 and TP7 (the other ends of the PMOS transistors TP6 and TP7 ) is commonly connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_31 .

[0169] One end common to the NMOS transistors TN6 and TN7 (the other ends of the NMOS transistors TN6 and TN7 ) is commonly connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_32 .

[0170] One end of the PMOS transistor TP7, one end of the NMOS transistor TN7, the gate electrode 111 of the PMOS transistor TP6, and the gate electrode 111 of the NMOS transistor TN6 are commonly connected via the M1 wiring 130_33.

[0171] The gate electrode 111 of the PMOS transistor TP7 and the gate electrode 111 of the NMOS transistor TN7 are connected in common via the M1 wiring 130_34. The M1 wiring 130_34 functions as a signal input wiring (IN) of the buffer circuit.

[0172] 1.3.3 Planar structure of ECO basic unit

[0173] Next, an example of a planar structure of an ECO basic cell will be described. The following description will focus on the differences from the standard cell.

[0174] 1.3.3.1 Planar structure of transistors in the ECO basic unit

[0175] First, refer to Fig. 9 An example of a planar structure of a transistor of an ECO basic unit will be described. Fig. 9 is a top view of the transistor of the ECO basic unit. Fig. 9 In the example of FIG. 1 , the interlayer insulating film, the M1 wiring 130 , the M2 wiring 150 , and the contact plugs 120 and 140 are omitted.

[0176] like Fig. 9 As shown, the ECO basic unit 1010 includes an N-type well region 101 , PMOS transistors TP10 and TP11 , and NMOS transistors TN10 and TN11 .

[0177] Similar to the standard cell 1001, an N-type well region 101 is provided on the upper side of the ECO basic cell 1010. The position of the N-type well region 101 in the Y direction is the same as that of the standard cell 1001. The positions of the M2 wirings 150_1 to 150_4 (not shown) are also the same as those of the standard cell 1001.

[0178] The PMOS transistors TP10 and TP11 are disposed in the N-type well region 101. The PMOS transistors TP10 and TP11 are disposed in an active region 102. The PMOS transistors TP10 and TP11 are arranged in an X direction. The PMOS transistors TP10 and TP11 share a source or a drain.

[0179] The NMOS transistors TN10 and TN11 are disposed in an active region 104. The NMOS transistors TN10 and TN11 are arranged in parallel in the X direction. The NMOS transistors TN10 and TN11 share a source or a drain.

[0180] exist Fig. 9 In the example, at the end of the gate electrode 111 of each transistor, a connection portion 111a is provided to the contact plug 120 (not shown). The width of the connection portion 111a in the X direction is larger than the wiring width (length in the X direction) of the gate electrode 111. More specifically, at the end of the gate electrode 111 extending in the Y direction, the connection portion 111a is provided in a manner that both sides protrude in the X direction. In addition, the shape of the connection portion 111a is arbitrary. The width of the connection portion 111a in the X direction may be the same as the wiring width of the gate electrode 111. In other words, the connection portion 111a may also be removed.

[0181] 1.3.3.2 Decoupling capacitors

[0182] Next, we will refer to Fig.10 and Fig.11 , an example of a planar structure of an ECO basic unit 1010 (ECO_C) having a decoupling capacitor is described. Fig.10 It is a top view of an ECO basic unit 1010 (ECO_C) having a decoupling capacitor. Fig.11 1 is an equivalent circuit diagram of an ECO basic unit 1010 (ECO_C) having a decoupling capacitor. Fig.10 In the example, the interlayer insulating film is omitted.

[0183] like Fig.10 As shown, one end of the PMOS transistor TP10 and the gate electrodes 111 of the NMOS transistors TN10 and TN11 are commonly connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_40.

[0184] One end common to the PMOS transistors TP10 and TP11 (the other ends of the PMOS transistors TP10 and TP11 ) is commonly connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_41 .

[0185] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_42.

[0186] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_43.

[0187] One end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11 ) is commonly connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_44 .

[0188] One end of the NMOS transistor TN11 and the gate electrodes 111 of the PMOS transistors TP10 and TP11 are commonly connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_45 .

[0189] like Fig.11 As shown, the power supply voltage VDD is applied to the source and drain of each of the PMOS transistors TP10 and TP11. The gates of each of the PMOS transistors TP10 and TP11 are grounded (the ground voltage VSS is applied). In addition, the source and drain of each of the NMOS transistors TN10 and TN11 are grounded. The power supply voltage VDD is applied to the gates of each of the NMOS transistors TN10 and TN11. Thus, each transistor functions as a decoupling capacitor between the power supply voltage VDD and the ground voltage VSS.

[0190] 1.3.3.3NAND Circuit

[0191] Next, refer to Fig.12 An example of a planar structure of an ECO basic cell 1010 (ECO_NAND) including a NAND circuit will be described. Fig.12 FIG. 1 is a top view of an ECO basic unit 1010 (ECO_NAND) having a NAND circuit. Fig.12 In the example, the interlayer insulating film is omitted.

[0192] like Fig.12 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_50.

[0193] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_51.

[0194] One end common to the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11) and one end of the NMOS transistor TN11 are connected together via the M1 wiring 130_52. The M1 wiring 130_52 functions as a signal output wiring (OUT) of the NAND circuit.

[0195] One end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11 ) is not connected to the M1 wiring 130 .

[0196] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_53.

[0197] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are connected in common via the M1 wiring 130_54. The M1 wiring 130_54 functions as one signal input wiring (IN1) of the NAND circuit.

[0198] The gate electrode 111 of the PMOS transistor TP11 and the gate electrode 111 of the NMOS transistor TN11 are connected in common via the M1 wiring 130_55. The M1 wiring 130_55 functions as another signal input wiring (IN2) of the NAND circuit.

[0199] 1.3.3.4NOR Circuit

[0200] Next, we will refer to Fig.13 An example of a planar structure of an ECO basic cell 1010 (ECO_NOR) including a NOR circuit will be described. Fig.13 FIG. 1 is a top view of an ECO basic unit 1010 (ECO_NOR) having a NOR circuit. Fig.13 In the example, the interlayer insulating film is omitted.

[0201] like Fig.13 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_60.

[0202] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_61.

[0203] One end common to the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11 ) is not connected to the M1 wiring 130 .

[0204] One end of the PMOS transistor TP11 and one end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11) are connected together via the M1 wiring 130_62. The M1 wiring 130_62 functions as a signal output wiring (OUT) of the NOR circuit.

[0205] One end of the NMOS transistor TN11 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_63.

[0206] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are connected in common via the M1 wiring 130_64. The M1 wiring 130_64 functions as one signal input wiring (IN1) of the NOR circuit.

[0207] The gate electrode 111 of the PMOS transistor TP11 and the gate electrode 111 of the NMOS transistor TN11 are connected in common via the M1 wiring 130_65. The M1 wiring 130_65 functions as another signal input wiring (IN2) of the NOR circuit.

[0208] 1.3.3.5 Inverter Circuit

[0209] Next, refer to Fig.14 An example of a planar structure of an ECO basic unit 1010 (ECO_I) including an inverter circuit will be described. Fig.14 FIG. 1 is a top view of an ECO basic unit 1010 (ECO_I) having an inverter circuit. Fig.14 In the example, the interlayer insulating film is omitted.

[0210] like Fig.14 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_70.

[0211] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_71.

[0212] One end common to the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11) is commonly connected to one end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11) via the M1 wiring 130_72. The M1 wiring 130_72 functions as a signal output wiring (OUT) of the inverter circuit.

[0213] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_73.

[0214] One end of the NMOS transistor TN11 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_74.

[0215] The gate electrodes 111 of the PMOS transistors TP10 and TP11 and the gate electrodes 111 of the NMOS transistors TN10 and TN11 are connected in common via the M1 wiring 130_75. The M1 wiring 130_75 functions as a signal input wiring (IN) of the inverter circuit.

[0216] 1.3.3.6 Buffer Circuit

[0217] Next, refer to Fig.15 An example of a planar structure of an ECO basic cell 1010 (ECO_B) including a buffer circuit will be described. Fig.15 FIG. 1 is a top view of an ECO basic unit 1010 (ECO_B) having a buffer circuit. Fig.15 In the example, the interlayer insulating film is omitted.

[0218] like Fig.15 As shown, one end of the PMOS transistor TP10, one end of the NMOS transistor TN10, a gate electrode 111 of the PMOS transistor TP11, and a gate electrode 111 of the NMOS transistor TN11 are commonly connected via an M1 wiring 130_80.

[0219] One end common to the PMOS transistors TP10 and TP11 (the other ends of the PMOS transistors TP10 and TP11 ) is commonly connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_81 .

[0220] One end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11 ) is connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_82 .

[0221] One end of the PMOS transistor TP11 and one end of the NMOS transistor TN11 are connected together via an M1 wiring 130_83. The M1 wiring 130_83 functions as a signal output wiring (OUT) of the buffer circuit.

[0222] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are connected in common via the M1 wiring 130_84. The M1 wiring 130_84 functions as a signal input wiring (IN) of the buffer circuit.

[0223] 1.3.3.7 Direct-through unit

[0224] Next, refer to Fig.16 and Fig.17 An example of a planar structure of an ECO basic cell 1010 (ECO_T) including a through cell will be described. Fig.16 It is a top view of an ECO basic unit 1010 (ECO_T) that is composed of a through unit. Fig.17 is the equivalent circuit diagram of the through unit. In addition, Fig.16 In the example, the interlayer insulating film is omitted. Fig.16 In the example, the case where two M1 wirings 130a (130a_1 and 130a_2) passing through the through cell in the Y direction are provided will be described. The M1 wiring 130a is not electrically connected to the through cell. Alternatively, there may be only one M1 wiring 130a.

[0225] like Fig.16 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_90.

[0226] One end shared by the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11 ), the gate electrode 111 of the PMOS transistor TP10 , and the gate electrode 111 of the PMOS transistor TP11 are connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_91 .

[0227] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_92.

[0228] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_93.

[0229] One end shared by the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11 ), the gate electrode 111 of the NMOS transistor TN10 , and the gate electrode 111 of the NMOS transistor TN11 are connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_94 .

[0230] One end of the NMOS transistor TN11 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_95.

[0231] Between the M1 wiring 130_90 and the M1 wiring 130_91 and between the M1 wiring 130_93 and the M1 wiring 130_94, an M1 wiring 130a_1 passing through the through cell along the Y direction is arranged. The M1 wiring 130a_1 is not electrically connected to each transistor of the through cell. The M1 wiring 130a_1 passes through the N-type well region 101, the active region 102, the element isolation region STI surrounding the active region 102, the active region 104, the element isolation region STI surrounding the active region 104, the top of the gate electrode 111 of the PMOS transistor TP10, and the top of the gate electrode 111 of the NMOS transistor TN10 in the Y direction.

[0232] Between the M1 wiring 130_91 and the M1 wiring 130_92 and between the M1 wiring 130_94 and the M1 wiring 130_95, an M1 wiring 130a_2 passing through the through cell along the Y direction is arranged. The M1 wiring 130a_2 is not electrically connected to each transistor of the through cell. The wiring 130a_2 passes through the N-type well region 101, the active region 102, the element isolation region STI surrounding the active region 102, the active region 104, the element isolation region STI surrounding the active region 104, the top of the gate electrode 111 of the PMOS transistor TP11, and the top of the gate electrode 111 of the NMOS transistor TN11 in the Y direction.

[0233] like Fig.17 As shown in FIG. 1 , the power supply voltage VDD is applied to the gate, source and drain of each of the PMOS transistors TP10 and TP11. In addition, the gate, source and drain of each of the NMOS transistors TN10 and TN11 are grounded. Thus, the potential of each terminal of the transistor is fixed.

[0234] 1.3.4 Planar structure of filling unit

[0235] Next, refer to Fig.18 An example of a planar structure of a filling unit will be described. Fig.18 This is a top view of a filling unit. The following description will focus on the differences from the standard unit and the ECO basic unit.

[0236] like Fig.18As shown, the filling cell 1020 includes an N-type well region 101 and M2 wirings 150_1 to 105_4. The positions of the N-type well region 101 and the M2 wirings 150_1 to 150_4 in the Y direction are the same as those of the standard cell 1001. The filling cell 1020 does not include a transistor. The N-type well region 101 and the M2 wirings 150_1 to 105_4 of the filling cell 1020 are connected to the N-type well region 101 and the M2 wirings 150_1 to 105_4 of the adjacent cell (not shown) in the X direction.

[0237] 1.3.5 Specific example of using the through unit

[0238] Next, refer to Fig.19 A specific example of using the through unit is described. Fig.19 1 is a top view of a semiconductor device 1 showing a specific example of using a through cell. Fig.19 In the example of FIG. 1 , the interlayer insulating film, the M3 wiring 170 , the M4 wiring 190 , and the contact plugs 160 and 180 are omitted.

[0239] like Fig.19 As shown, for example, by automatic layout and wiring, the standard cell 1004a of the buffer circuit, the ECO basic cells 1010a and 1010b, the filling cell 1020, and the standard cell 1004b of the buffer circuit are arranged adjacently along the X direction. The N-type well regions 101 of each cell arranged along the X direction are connected to each other. Similarly, the M2 wirings 150_1 to 150_4 of each cell arranged along the X direction are connected to each other. In addition, the ECO basic cells 1010c and 1010d are arranged adjacently along the Y direction from the bottom of the paper so as to sandwich the ECO basic cell 1010a.

[0240] When the metal ECO is not used, a decoupling capacitor is formed in the ECO basic cells 1010 a to 1010 d to fix the potential of each terminal of the transistor.

[0241] In the above layout, a case where an OR (logical OR) circuit using the ECO basic cells 1010 a , 1010 c , and 1010 d is formed by metal ECO will be described.

[0242] For example, a through cell is formed in the ECO basic cell 1010a by metal ECO. In the ECO basic cell 1010c, a NOR circuit is formed. In the ECO basic cell 1010d, an inverter circuit is formed. In addition, the M1 wiring 130_62 of the ECO basic cell 1010c (ECO_NOR) and the M1 wiring 130_75 of the ECO basic cell 1010d (ECO_I) are electrically connected via the M1 wiring 130a of the ECO basic cell 1010a (ECO_T) as a through cell. That is, an OR circuit is formed by connecting the signal output wiring of the NOR circuit and the signal input wiring of the inverter circuit.

[0243] 1.4 Method for manufacturing semiconductor device

[0244] Next, refer to Figure 20 to Figure 26 An example of a flow of a method for manufacturing a semiconductor device will be described. Fig. 20 and Fig.21 This is a flow chart of a method for manufacturing a semiconductor device. Fig. 22 This is an example of a planar layout after arranging standard cells. Fig.23 This is an example of a planar layout in which the ECO basic unit 1010 (ECO_C) having a decoupling capacitor is arranged. Fig.24 This is an example of a planar layout after the filling cells 1020 are arranged. Fig.25 This is an example of the floor plan after the ECO logic unit is changed. Fig.26 This is an example of the floor plan after the through unit is changed. Figure 22 to Figure 26 In the example of FIG. 1 , in order to illustrate the configuration position of each cell, a grid block of 5 rows (Y=5)×7 columns (X=7) is shown based on the cell size of the standard cell 1004 of the buffer circuit. The position of each grid block is represented by the coordinates (X, Y). Figure 22 to Figure 26 In the example of FIG. 1 , for simplicity of description, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, and the standard cell 1003 of the inverter circuit are set to the same cell size and are shown with the same hatching. The cell size of the standard cell 1004 of the buffer circuit and the ECO basic cell are shown with the same cell size. Figure 22 to Figure 26 In the example of FIG. 1 , hatching is appropriately added in the top view to facilitate viewing of each unit. The hatching added to the top view has no relation to the materials and characteristics of the hatched components.

[0245] The following description will focus on the steps up to wiring formation in the layout design and manufacturing process of the semiconductor device.

[0246] like Fig. 20As shown, after the circuit design, first, the layout design shown in S1 to S5 is performed. More specifically, first, the standard cells are arranged based on the circuit design data (S1). In addition, this step is equivalent to "Place" in automatic placement and routing (Place and Route).

[0247] like Fig. 22 As shown in FIG. 1 , in the stage S1 where standard cells are arranged, a blank area (an area where no cells are arranged) remains in the planar layout. Fig. 22 In the example, the areas with coordinates (4, 2), (4, 3), (4, 4), (4, 5), (5, 1), (5, 2), and (7, 1) are blank. In addition, part of the areas with coordinates (3, 2), (3, 3), and (7, 3) are blank.

[0248] like Fig. 20 As shown, the standard cells are connected to each other (S2) using the M3 wiring 170 and the M4 wiring 190. This step corresponds to "Route" in the automatic placement and routing (Place and Route).

[0249] In the gap region after the standard cells are arranged, an ECO basic cell 1010 (ECO_C) having a decoupling capacitor is inserted (S3).

[0250] like Fig.23 As shown, through S3, for example, the ECO basic unit 1010 (ECO_C) is arranged in the area of ​​coordinates (4, 2), (4, 3), (4, 4), (4, 5), (5, 1), (5, 2) and (7, 1) on the plane layout. When X=4, four ECO basic units 1010 (ECO_C) are arranged adjacent to each other in the Y direction, when X=5, two are arranged adjacent to each other in the Y direction, and when X=7, a single unit is arranged. In addition, when Y=2, two ECO basic units 1010 (ECO_C) are arranged adjacent to each other in the X direction. That is, two or more ECO basic units 1010 (ECO_C) are arranged adjacent to each other in the X direction or the Y direction.

[0251] like Fig. 20 As shown, the filling cell 1020 is inserted into the gap region after the standard cell and the ECO basic cell 1010 (ECO_C) are arranged (S4).

[0252] like Fig.24 As shown, in S4, for example, the padding cells 1020 are arranged in the blank portions of the regions at the coordinates (3, 2), (3, 3), and (7, 3) on the planar layout.

[0253] like Fig. 20As shown, the device layout is determined (S5). That is, the configuration of each unit (transistor) is determined.

[0254] If the device layout is determined, the manufacturing process of the semiconductor device shown in S6 to S7 is executed. In addition, in this example, the case where the layout design process of S8 to S14 described later is executed after the manufacturing process of the semiconductor device of S6 to S7 is described, but it is not limited to this. The manufacturing process of the semiconductor device of S6 to S7 and the layout design process of S8 to S14 can also be executed in parallel. First, various masks related to the element isolation region and well region (diffusion layer region) of the semiconductor substrate 100 and the photolithography process of the transistor are prepared (hereinafter referred to as "device masks") (S6).

[0255] Based on the device mask, a transistor is manufactured on the semiconductor substrate 100 ( S7 ).

[0256] like Fig.21 As shown, the layout design (metal ECO) shown in S8 to S14 is performed. When the circuit design is changed (S8_Yes), metal ECO is performed. More specifically, the structure of a part of the ECO basic unit 1010 is changed from a decoupling capacitor to an ECO logic unit (S9). That is, the layout of the wiring layer (here, the M1 wiring 130) of the ECO basic unit 1010 is changed.

[0257] like Fig.25 As shown, through S9, for example, the ECO basic cells at the coordinates (4, 5) and (5, 1) are changed to ECO logical cells in the planar layout.

[0258] like Fig.21 As shown, it is confirmed whether the wiring connection of the ECO logic cell can be performed (S10). More specifically, it is confirmed whether there is space for providing M3 wiring 170 and M4 wiring 190 connected to the ECO logic cell in the layout of M2 wiring 150, M3 wiring 170 and M4 wiring 190.

[0259] When the ECO logic cell can be wired (S10_Yes), the ECO logic cell is connected using M2 wiring 150, M3 wiring 170 and M4 wiring 190 (S11). ECO logic cells may be connected to each other or to standard cells.

[0260] A layout check of the wiring is performed ( S12 ). For example, when the congestion of the M3 wiring 170 and the M4 wiring 190 is high, the wiring connected to the ECO logic cell may not satisfy the design rule or the conditions such as the timing of signal transmission.

[0261] When the wiring connection of the ECO logic cell cannot be performed (S10_No), or when the layout check fails (S12_No), metal ECO is performed again. More specifically, near the ECO logic cell that cannot be wired or fails the layout check (NG), an unused ECO basic cell 1010 (ECO_C) that has not been changed to an ECO logic cell is searched. And the structure of the ECO basic cell 1010 (ECO_C) is changed from a decoupling capacitor to a through cell (S13).

[0262] like Fig.26 As shown, through S13, in the plane layout, for example, in order to connect the ECO logic units at coordinates (4, 5) and (5, 1), the ECO basic units in the areas of coordinates (4, 2), (4, 3), (4, 4) and (5, 2) are changed to through cells. For example, the through cells are adjacent to the ECO logic units in the Y direction.

[0263] like Fig.21 As shown, after the through cell is changed, it enters S10 to confirm whether the wiring connection of the ECO logic cell can be performed. If the wiring connection can be performed (S10_Yes), the M1 wiring 130a passing through the through cell is used to connect the wiring to the ECO logic cell where the wiring connection fails (NG). Fig.26 In the planar layout shown, the ECO logic cells at coordinates (4, 5) and (5, 1) are connected via through cells at coordinates (4, 2), (4, 3), (4, 4) and (5, 2).

[0264] If there is no change in the circuit design (S8_Yes), or if the layout check is passed (S12_Yes), the wiring layout is determined (S14). Thus, the layout design is completed.

[0265] When the wiring layout is determined, the manufacturing process of the semiconductor device shown in S15 to S16 is executed. First, various masks related to the photolithography process of forming wiring (hereinafter referred to as "wiring mask") are prepared (S15).

[0266] Various wirings are manufactured based on the wiring mask ( S16 ) More specifically, for example, contact plug 120 , M1 wiring 130 , contact plug 140 , M2 wiring 150 , contact plug 160 , M3 wiring 170 , contact plug 180 , and M4 wiring 190 are sequentially formed.

[0267] 1.5 Effects of this Implementation

[0268] According to the structure of this embodiment, it is possible to suppress the increase of development cost and the extension of development period. This effect will be described in detail.

[0269] For example, there may be a case where the circuit design is changed after the mask of the semiconductor device 1 is produced. In such a case, if the layout of the transistor is re-produced, the re-production of the device mask will increase the development cost and extend the development period.

[0270] In contrast, according to the structure of this embodiment, in the automatic layout wiring, the ECO basic cell can be arranged in the free space where the standard cell is arranged. The ECO basic cell can change the circuit function by changing the layout of the M1 wiring based on the metal ECO. Therefore, even if the circuit design is changed after the device mask is made, the circuit design can be handled by performing metal ECO without changing the configuration of the cell (transistor).

[0271] However, even if the ECO basic cell is changed to an ECO logic cell, it is sometimes impossible to connect the ECO logic cell by wiring. In addition, even if it is possible to connect by wiring, if the wiring congestion caused by the increase of wiring accompanying the addition of the ECO logic cell is high, it is sometimes impossible to pass the judgment of the layout check.

[0272] In contrast, according to the structure of the present embodiment, a through cell can be formed in an ECO basic cell. In the through cell, an M1 wiring that is not connected to the transistor in the through cell and connects the cells adjacent to the through cell can be set. By setting it as a through cell, the layout resources of the M1 wiring can be increased. As a result, wiring congestion can be alleviated and metal ECO can be performed. Therefore, by setting the through cell, the wiring connection of the ECO logic cell can be made easier. Therefore, without changing the device mask corresponding to the semiconductor formation process including the transistor, only by changing the wiring mask of the wiring process, it is possible to cope with the change of the circuit design. Therefore, the increase in development cost and the extension of the development period can be suppressed.

[0273] Furthermore, since the terminal of the transistor in the through cell is connected to the power supply voltage wiring or the ground voltage wiring, charge is not accumulated at the terminal of the transistor, which contributes to stable operation.

[0274] 1.6 Modification of the First Embodiment

[0275] Next, a modification of the first embodiment will be described. Hereinafter, the description will be mainly focused on the differences from the first embodiment.

[0276] 1.6.1 First Modification

[0277] First, a first modification of the first embodiment will be described. In the first modification, a case where an M1 wiring 130a passing through two through cells arranged adjacent to each other in the X direction is provided will be described. Figure 27 to Figure 29 1 is a top view of a semiconductor device 1 showing a specific example of using a through cell. Figure 27 to Figure 29 In the example of , the layout of M1 wiring 130a is different. Figure 27 to Figure 29 In the example of FIG. 1 , the interlayer insulating film, the M3 wiring 170 , the M4 wiring 190 , and the contact plugs 160 and 180 are omitted.

[0278] like Fig. 27 As shown, for example, by automatic routing, the standard cell 1004a of the buffer circuit, the ECO basic cells 1010a and 1010b, the filling cell 1020, and the standard cell 1004b of the buffer circuit are arranged adjacent to each other along the X direction. The ECO basic cell 1010c is arranged adjacent to the lower side of the ECO basic cell 1010a on the paper surface. The ECO basic cell 1010d is arranged adjacent to the upper side of the ECO basic cell 1010b on the paper surface.

[0279] In the above layout, for example, through cells are formed in ECO basic cells 1010a and 1010b by metal ECO. In ECO basic cell 1010c, a NOR circuit is formed. In ECO basic cell 1010d, an inverter circuit is formed. And, via M1 wiring 130a passing through ECO basic cells 1010a (ECO_T) and 1010b (ECO_T) as through cells, M1 wiring 130_62 of ECO basic cell 1010c (ECO_NOR) is electrically connected to M1 wiring 130_75 of ECO basic cell 1010d (ECO_I). More specifically, M1 wiring 130a passes through N-type well region 101, active region 102, element isolation region STI surrounding active region 102, and above gate electrode 111 of PMOS transistor TP10 of ECO basic cell 1010b (ECO_T) in the Y direction. The M1 wiring 130a that passes through the active region 102 along the Y direction is bent in the X direction on the left side of the paper. Then, in the ECO basic unit 1010b (ECO_T), the M1 wiring 130a is bent in the Y direction on the lower side of the paper and extends. Before reaching the active region 104 of the ECO basic unit 1010b (ECO_T), the M1 wiring 130a extending in the Y direction is bent in the X direction on the left side of the paper and extends into the ECO basic unit 1010a (ECO_T). Further, the M1 wiring 130a is bent in the Y direction on the lower side of the paper, and passes through the active region 104 of the ECO basic unit 1010a (ECO_T), the element isolation region STI surrounding the active region 104, and above the gate electrode 111 of the NMOS transistor TN11 in the Y direction.

[0280] In addition, the layout of the M1 wiring 130a is not limited to the above-mentioned layout. Two examples are shown with respect to different layouts of the M1 wiring 130a.

[0281] like Fig.28 As shown, for example, the M1 wiring 130a that passes through the active region 102 of the ECO basic unit 1010b (ECO_T) along the Y direction is bent in the X direction on the left side of the paper and extends toward the ECO basic unit 1010a (ECO_T). Then, in the ECO basic unit 1010a (ECO_T), the M1 wiring 130a is bent and extended in the Y direction on the lower side of the paper. The M1 wiring 130a extending in the Y direction is bent in the X direction on the left side of the paper before reaching the active region 104 of the ECO basic unit 1010a (ECO_T). Then, the M1 wiring 130a is bent in the Y direction on the lower side of the paper and extends in the Y direction above the gate electrode 111 of the NMOS transistor TN11.

[0282] like Fig.29 As shown, a portion of the M1 wiring 130a may also be branched into two. For example, the M1 wiring 130a passing through the active region 102 of the ECO basic unit 1010b (ECO_T) along the Y direction is bent toward the X direction on the left side of the paper. The M1 wiring 130a extending along the X direction is branched into two.

[0283] On the other hand, if you use Fig. 27 As described above, the M1 wiring 130a is bent and extended in the Y direction on the lower side of the paper in the ECO basic unit 1010b (ECO_T). The M1 wiring 130a extending in the Y direction is bent in the X direction on the left side of the paper before reaching the active region 104 of the ECO basic unit 1010b (ECO_T) and extends into the ECO basic unit 1010b (ECO_T).

[0284] On the other hand, if you use Fig.28 As described above, the M1 wiring 130a extends into the ECO basic unit 1010a (ECO_T). Then, in the ECO basic unit 1010a (ECO_T), the M1 wiring 130a bends and extends in the Y direction at the lower side of the paper. The M1 wiring 130a extending in the Y direction merges with one of the branched M1 wirings 130a before reaching the active region 104 of the ECO basic unit 1010a (ECO_T).

[0285] 1.6.2 Second Modification

[0286] Next, a second modification of the first embodiment will be described. In the second modification, two examples of the structure of the connection portion 111 a of the gate electrode 111 that is different from that of the first embodiment will be described. Fig.30 and Fig.31is a top view of the transistors of the ECO basic unit 1010. Fig.30 and Fig.31 In the example of FIG. 1 , the interlayer insulating film, the M1 wiring 130 , the M2 wiring 150 , and the contact plugs 120 and 140 are omitted.

[0287] like Fig.30 As shown, the structure of each transistor of the ECO basic unit 1010 is the same as that of the first embodiment. Fig. 9 same.

[0288] exist Fig.30 In the example of FIG. 1 , a connection portion 111 a is provided at the end of the gate electrode 111 of each transistor. The width of the connection portion 111 a in the X direction is larger than the wiring width of the gate electrode 111. Fig.30 In the example of FIG. 1 , a connection portion 111 a is provided from the gate electrode 111 so as to protrude in one X direction.

[0289] like Fig.31 As shown, the structure of each transistor of the ECO basic unit 1010 is the same as that of the first embodiment. Fig. 9 same.

[0290] exist Fig.31 In the example of FIG. 1 , the connection portion 111 a is removed. In other words, at the end of the gate electrode 111 , a connection portion 111 a having the same length as the wiring width of the gate electrode 111 is provided.

[0291] In addition, in this modification, the connection portion 111 a of the gate electrode 111 of the ECO basic cell is described, but the gate electrode of the standard cell may also have the same structure.

[0292] 1.6.3 Third Modification

[0293] Next, a third modification of the first embodiment will be described. In the third modification, two examples of the structure of the through unit different from that of the first embodiment will be described.

[0294] 1.6.3.1 First example of a direct-through unit

[0295] First, refer to Fig.32 and Fig.33 , an example of a planar structure of an ECO basic cell 1010 (ECO_T) including a through cell including a decoupling capacitor formed of an NMOS transistor is described. Fig.32 FIG. 1 is a top view of an ECO basic cell 1010 (ECO_T) including a through cell including a decoupling capacitor formed of an NMOS transistor. Fig.33 is an equivalent circuit diagram of a through cell including a decoupling capacitor formed by an NMOS transistor. Fig.32 In the example, the interlayer insulating film is omitted. Fig.32 In the example, the case where two M1 wirings 130a (130a_1 and 130a_2) are provided passing through the through cell in the Y direction is described. The M1 wiring 130a is not electrically connected to each transistor of the through cell. Alternatively, there may be only one M1 wiring 130a.

[0296] like Fig.32 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_100.

[0297] One end shared by the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11), the gate electrode 111 of the PMOS transistor TP10, the gate electrode 111 of the PMOS transistor TP11, the gate electrode 111 of the NMOS transistor TN10, and the gate electrode 111 of the NMOS transistor TN11 are connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_101.

[0298] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_102.

[0299] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_103.

[0300] One end common to the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11 ) is connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_104 .

[0301] One end of the NMOS transistor TN11 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_105.

[0302] Between the M1 wiring 130_100 and the M1 wiring 130_101 and between the M1 wiring 130_103 and the M1 wiring 130_104, an M1 wiring 130a_1 passing through the through cell in the Y direction is arranged. The M1 wiring 130a_1 is not electrically connected to each transistor of the through cell.

[0303] Between the M1 wiring 130_101 and the M1 wiring 130_102 and between the M1 wiring 130_104 and the M1 wiring 130_105, an M1 wiring 130a_2 passing through the through cell in the Y direction is arranged. The M1 wiring 130a_2 is not electrically connected to each transistor of the through cell.

[0304] like Fig.33 As shown, the power supply voltage VDD is applied to the gate, source and drain of each of the PMOS transistors TP10 and TP11. The power supply voltage VDD is applied to the gate of each of the NMOS transistors TN10 and TN11. The source and drain of each of the NMOS transistors TN10 and TN11 are grounded. Thus, the potential of each terminal of the transistor is fixed. The NMOS transistors TN10 and TN11 function as decoupling capacitors between the power supply voltage VDD and the ground voltage VSS.

[0305] 1.6.3.2 Second example of direct-through unit

[0306] First, refer to Fig.34 and Fig.35 , an example of a planar structure of an ECO basic cell 1010 (ECO_T) including a through cell including a decoupling capacitor formed of a PMOS transistor is described. Fig.34 FIG. 1 is a top view of an ECO basic cell 1010 (ECO_T) including a through cell including a decoupling capacitor formed by a PMOS transistor. Fig.35 is an equivalent circuit diagram of a through cell including a decoupling capacitor formed by a PMOS transistor. Fig.34 In the example, the interlayer insulating film is omitted. Fig.34 In the example, the case where two M1 wirings 130a (130a_1 and 130a_2) are provided passing through the through cell in the Y direction is described. The M1 wiring 130a is not electrically connected to each transistor of the through cell. Alternatively, there may be only one M1 wiring 130a.

[0307] like Fig.34 As shown, one end of the PMOS transistor TP10 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_110.

[0308] One end common to the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11 ) is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wiring) via the M1 wiring 130_111 .

[0309] One end of the PMOS transistor TP11 is connected to the M2 wirings 150_1 and 150_2 (power supply voltage wirings) via the M1 wiring 130_112.

[0310] One end of the NMOS transistor TN10 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_113.

[0311] One end shared by the NMOS transistors TN10 and TN11 (the other end of the NMOS transistors TN10 and TN11), the gate electrode 111 of the PMOS transistor TP10, the gate electrode 111 of the PMOS transistor TP11, the gate electrode 111 of the NMOS transistor TN10, and the gate electrode 111 of the NMOS transistor TN11 are connected to the M2 wirings 150_3 and 150_4 (ground voltage wiring) via the M1 wiring 130_114.

[0312] One end of the NMOS transistor TN11 is connected to the M2 wirings 150_3 and 150_4 (ground voltage wirings) via the M1 wiring 130_115 .

[0313] Between the M1 wiring 130_110 and the M1 wiring 130_111 and between the M1 wiring 130_113 and the M1 wiring 130_114, an M1 wiring 130a_1 passing through the through cell in the Y direction is arranged. The M1 wiring 130a_1 is not electrically connected to each transistor of the through cell.

[0314] Between the M1 wiring 130_111 and the M1 wiring 130_112 and between the M1 wiring 130_114 and the M1 wiring 130_115, an M1 wiring 130a_2 passing through the through cell in the Y direction is arranged. The M1 wiring 130a_2 is not electrically connected to each transistor of the through cell.

[0315] like Fig.35 As shown, the gates of the PMOS transistors TP10 and TP11 are grounded. The power supply voltage VDD is applied to the source and drain of the PMOS transistors TP10 and TP11. The gates, sources and drains of the NMOS transistors TN10 and TN11 are grounded. Thus, the potentials of the terminals of the transistors are fixed. The PMOS transistors TP10 and TP11 function as decoupling capacitors between the power supply voltage VDD and the ground voltage VSS.

[0316] 1.6.4 Fourth variant

[0317] Next, a fourth modification of the first embodiment will be described. In the fourth modification, a method for manufacturing a semiconductor device different from that of the first embodiment will be described. Fig.36 and Fig.371 is a flow chart of a method for manufacturing a semiconductor device. Fig. 20 and Fig.21 The explanation will focus on the differences.

[0318] like Fig.36 As shown, the steps S1 to S7 are the same as those of the first embodiment. Fig. 20 same.

[0319] like Fig.37 As shown, when the circuit design is changed (S8_Yes), metal ECO is executed. In this example, the unified execution uses Fig.21 The ECO logic unit of S9 and the through unit of S13 described above are changed (S21). More specifically, through S21, the planar layout of the semiconductor device 1 is changed from that of the first embodiment to that of the second embodiment. Fig.24 The floor plan shown changes to Fig.26 Floor plan shown.

[0320] Next, the ECO logic cells are connected using the M1 wiring 130 , the M2 wiring 150 , the M3 wiring 170 , and the M4 wiring 190 using the through cell ( S22 ).

[0321] The layout check of the wiring is performed (S23). In this example, if the layout check is not passed (S23_No), the process proceeds to S21 and metal ECO is performed again.

[0322] If there is no change in the circuit design (S8_Yes), or if the layout check is passed (S23_Yes), the wiring layout is determined (S14). Thus, the layout design is completed.

[0323] When the wiring layout is finalized, the manufacturing process of the semiconductor device shown in S15 to S16 is performed in the same manner as in the first embodiment.

[0324] 1.6.5 Effects of Modification Example of First Embodiment

[0325] According to the structure of the modification of the first embodiment, the same effects as those of the first embodiment can be obtained.

[0326] Furthermore, the first modification example, the second modification example, the third modification example, and the fourth modification example may be combined.

[0327] 2. Second Implementation

[0328] Next, a second embodiment will be described. In the second embodiment, a case where the semiconductor device 1 is a NOR flash memory will be described. The following description will focus on the differences from the first embodiment.

[0329] 2.1 Overall structure of semiconductor devices

[0330] Reference Fig.38 , an example of the overall structure of the semiconductor device 1 is described. Fig.38 1 is a block diagram showing the overall structure of the semiconductor device 1. Fig.38 In the figure, a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0331] like Fig.38 As shown, the semiconductor device 1 is a NOR type flash memory.

[0332] The semiconductor device 1 includes a memory cell array 31 , a row control circuit 32 , a column control circuit 33 , an address register 34 , a data buffer 35 , an input / output shift register 36 , a voltage generating circuit 37 , and a sequencer 38 .

[0333] The memory cell array 31 includes a plurality of memory cells (memory cell transistors) MTx. In the semiconductor device 1, the gate of each memory cell MTx is connected to a corresponding one of a plurality of word lines WL. One end of the current path of each memory cell MTx is connected to a corresponding one of a plurality of bit lines BL. The other end of the current path of each memory cell MTx is connected to a source line and, for example, is grounded. The plurality of memory cells MTx are arranged in a two-dimensional array or a three-dimensional array.

[0334] The memory cell MTx is a field effect transistor having a stacked gate structure and a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film.

[0335] The row control circuit 32 selects a word line WL corresponding to address information among a plurality of word lines WL. The row control circuit 32 applies a predetermined voltage to the selected word line WL (and non-selected word lines WL) in a write operation, a read operation, an erase operation, and the like.

[0336] The row control circuit 32 includes a digital signal control circuit 32 a that processes a received digital signal.

[0337] The column control circuit 33 selects a bit line BL corresponding to address information among a plurality of bit lines BL. The row control circuit 32 applies a predetermined voltage to the selected bit line BL (and unselected bit lines BL) in a write operation, a read operation, an erase operation, and the like.

[0338] The column control circuit 33 includes a digital signal control circuit 33 a that processes a received digital signal.

[0339] The address register 34 temporarily stores the address information from the input / output shift register 36. The address register 34 sends the address information to the row control circuit 32 and the column control circuit 33.

[0340] The address register 34 functions as a digital signal control circuit that processes a received digital signal (address information).

[0341] The data buffer 35 temporarily stores the read data from the memory cell array 31 and the write data from the input / output shift register 36 .

[0342] The input / output shift register 36 temporarily stores data (signal DQ) transmitted between the memory cell array 31 and the outside of the semiconductor device 1. The data (signal DQ) may include read data, write data, and (or) address information. The input / output shift register 36 sends the address information to the address register 34. The input / output shift register 36 sends the write data to the data buffer 35. The input / output shift register 36 sends the read data supplied from the memory cell array 31 to the outside of the semiconductor device 1. The input / output shift register 36 can perform parallel-serial conversion of the data (signal DQ).

[0343] The input / output shift register 36 includes a digital signal control circuit 36 ​​a that processes a received digital signal.

[0344] The voltage generation circuit 37 generates a plurality of voltages used in each of the write operation, the read operation, and the erase operation. The voltage generation circuit 37 supplies the generated voltages to the row control circuit 32 and the column control circuit 33 and the like.

[0345] The voltage generating circuit 37 includes a digital signal control circuit 37 a that processes the received digital signal.

[0346] The sequencer 38 controls the overall operation of the semiconductor device 1 based on various control signals such as the reset signal RESETn, the hold signal HOLDn, and the write protection signal Wn.

[0347] The sequencer 38 functions as a digital signal control circuit that processes received digital signals (various control signals).

[0348] In addition, the semiconductor device 1 may include other components such as a status register. The status register temporarily stores a status signal indicating the internal operation status of the semiconductor device 1 and the execution result of the operation.

[0349] Similar to the first embodiment, the automatic placement and routing technology is used in the layout design of various digital signal control circuits included in the semiconductor device 1 .

[0350] 2.2 Effects of this embodiment

[0351] According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

[0352] 3. Third Implementation

[0353] Next, the third embodiment is described. In the third embodiment, the case where the semiconductor device 1 is a DRAM (Dynamic Random Access Memory) is described. In addition, the semiconductor device 1 may also be a volatile semiconductor memory device other than a DRAM. For example, the semiconductor device 1 may also be an SRAM (Static RAM). The following description focuses on the differences from the first and second embodiments.

[0354] 3.1 Overall Structure of Semiconductor Devices

[0355] Reference Fig.39 , an example of the overall structure of the semiconductor device 1 is described. Fig.39 1 is a block diagram showing the overall structure of the semiconductor device 1. Fig.39 In the figure, a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0356] like Fig.39 As shown, the semiconductor device 1 is a DRAM.

[0357] The semiconductor device 1 includes a memory cell array 51, a row decoder 52, a column decoder 53, an instruction decoder 54, an address decoder 55, an instruction / address input circuit 56, a read amplifier circuit 57, a transmission gate 58, a read / write amplifier circuit (RWAMP) 59, an input / output circuit 60, a clock input circuit 61, an internal clock generation circuit 62, and a voltage generation circuit 63.

[0358] The memory cell array 51 includes a plurality of memory cells MC. The memory cells MC of the DRAM 51 each include a cell capacitor CC and a cell transistor CT. The gate of the cell transistor CT is connected to a corresponding one of a plurality of word lines WL. One end of the current path of the cell transistor CT is connected to the bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is grounded. The cell capacitor CC is capable of storing an amount of charge corresponding to the stored data. The cell transistor CT switches the conduction / non-conduction between the cell capacitor CC and the bit line BL (selection / non-selection of the memory cell MC). The plurality of memory cells MC are arranged in a two-dimensional array or a three-dimensional array in the memory cell array 51.

[0359] For example, the memory cell array 51 includes a plurality of banks. Each bank is a control unit including a plurality of memory cells. The plurality of banks can operate independently of each other.

[0360] The row decoder 52 controls selection / non-selection of a row (for example, a word line WL) of the memory cell array 51 based on a result of decoding the address information and a result of decoding the command.

[0361] The column decoder 53 controls selection / non-selection of a column (eg, bit line BL) of the memory cell array 51 based on a result of decoding the address information and a result of decoding the command.

[0362] The instruction decoder 54 decodes the instruction from the instruction / address input circuit 56 . The instruction decoder 54 sends the decoding result of the instruction to the row decoder 52 and the column decoder 53 .

[0363] The address decoder 55 decodes the address information from the command / address input circuit 56. The address decoder 55 sends the decoded result of the address information to the row decoder 52 and the column decoder 53.

[0364] The command / address input circuit 56 receives a command / address signal CA supplied from the outside. The command / address signal CA includes a command and address information. The command / address input circuit 56 sends the command to the command decoder 54. The command / address input circuit 56 sends the address information to the address decoder 55.

[0365] The sense amplifier circuit 57 senses and amplifies the signal from the memory cell MC during the read operation. The sense amplifier circuit 57 sends the signal from the memory cell MC as read data to the input-output circuit 60 via the transmission gate 58 and the read / write amplifier circuit 59. The sense amplifier circuit 57 receives the write data from the input-output circuit 60 via the transmission gate 58 and the read / write amplifier circuit 59. The sense amplifier circuit 57 outputs a signal corresponding to the write data to the bit line BL.

[0366] The transfer gate 58 controls data transfer between the sense amplifier circuit 57 and the read / write amplifier circuit 59 .

[0367] The read / write amplifier circuit 59 amplifies the level (signal value) of a signal corresponding to the read data and the level of a signal corresponding to the write data.

[0368] The input-output circuit 60 functions as an interface circuit for data (signal DQ) transmitted between the memory cell array 51 and the outside of the DRAM 50. The input-output circuit 60 sends write data to the memory cell array 51 at a timing synchronized with the internal clock CLK2. The input-output circuit 60 sends read data to a device outside the DRAM 50 at a timing synchronized with the internal clock CLK2. For example, the input-output circuit 60 receives a data mask signal DM. Thus, the input-output circuit 60 performs mask processing on the data (signal DQ).

[0369] The input / output circuit 60 includes a digital signal control circuit 60 a that processes a received digital signal.

[0370] The clock input circuit 61 receives a clock (hereinafter referred to as an external clock) CLK1 from the outside and sends the external clock CLK1 to the internal clock generation circuit 62 .

[0371] The internal clock generation circuit 62 generates the internal clock CLK2 based on the external clock CLK1. The internal clock generation circuit 62 sends the generated internal clock CLK2 to the input / output circuit 60 and the like.

[0372] The voltage generating circuit 63 uses the power supply voltage VDD and the ground voltage VSS from the outside to generate a plurality of voltages used in various operations of the DRAM 50. The voltage generating circuit 63 sends the generated voltages to other circuits (for example, the read / write amplifier circuit 59).

[0373] Similar to the first embodiment, the automatic placement and routing technology is used in the layout design of the digital signal control circuit included in the semiconductor device 1 .

[0374] 3.2 Effects of this Implementation

[0375] According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

[0376] 4. Fourth Implementation

[0377] Next, a fourth embodiment will be described. In the fourth embodiment, a case where the semiconductor device 1 is an image sensor will be described. Hereinafter, the description will be mainly focused on the differences from the first to third embodiments.

[0378] 4.1 Overall Structure of Semiconductor Devices

[0379] Reference Fig.40 , an example of the overall structure of the semiconductor device 1 is described. Fig.40 1 is a block diagram showing the overall structure of the semiconductor device 1. Fig.40In the figure, a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0380] like Fig.40 As shown, the semiconductor device 1 is an image sensor.

[0381] The semiconductor device 1 includes a pixel array 71 , a row scanning circuit 72 , a column processing circuit 73 , a column scanning circuit 74 , a system control circuit 75 , and a signal processing circuit 76 .

[0382] The pixel array 71 has a plurality of pixels PX. The plurality of pixels PX are arranged in a two-dimensional grid along the row direction and the column direction. Each pixel PX has a photoelectric conversion element. The photoelectric conversion element generates a charge corresponding to the amount of light received and accumulates the generated charge. A filter may be provided in the pixel array 71 for the light incident surface of each pixel PX. For example, the arrangement pattern of the plurality of filters is, for example, a Bayer pattern.

[0383] In the pixel array 71 , a plurality of pixels PX arranged in a row direction are commonly connected to a pixel drive line PDL. In the pixel array 71 , a plurality of pixels PX arranged in a column direction are commonly connected to a corresponding one of a plurality of vertical signal lines VSL.

[0384] The row scanning circuit 72 is connected to one end of a plurality of pixel drive lines PDL. The row scanning circuit 72 generates a drive signal for driving a signal readout from the pixel PX. The row scanning circuit 72 drives all pixels PX of the pixel array 71 simultaneously or in units of rows via the plurality of pixel drive lines PDL.

[0385] The row scanning circuit 72 includes a digital signal control circuit 72 a that processes a received digital signal.

[0386] The signals output from the plurality of pixels PX driven by the row scanning circuit 72 are supplied to the column processing circuit 73 through each vertical signal line VSL according to each pixel PX arranged in the row direction. The column processing circuit 73 performs a predetermined signal processing on the signal supplied via the vertical signal line VSL. Thus, the column processing circuit 73 generates a pixel signal. The column processing circuit 73 can temporarily store the generated pixel signal. For example, the column processing circuit 73 performs a noise removal process, an analog-to-digital conversion (AD conversion) process, etc. The digital signal obtained by the AD conversion is output to the signal processing circuit 76.

[0387] The column processing circuit 73 includes a digital signal control circuit 73 a that processes a received digital signal.

[0388] The column scanning circuit 74 sequentially selects readout circuits corresponding to the arrangement of pixel signals from the column processing circuit 73. Through the selective scanning by the column scanning circuit 74, pixel signals processed for each pixel in the column processing circuit 73 are output in a predetermined order.

[0389] The column scanning circuit 74 includes a digital signal control circuit 74 a that processes the received digital signal.

[0390] The system control circuit 75 receives a system clock signal and the like via a controller (not shown) outside the image sensor 70. The system control circuit 75 includes a timing generator and the like. The timing generator generates various timing signals based on the system clock signal. Thus, the system control circuit 75 drives the row scanning circuit 72, the column processing circuit 73, the column scanning circuit 74, and the like based on the various timing signals generated.

[0391] The system control circuit 75 functions as a digital signal control circuit that processes a received digital signal.

[0392] The signal processing circuit 76 has at least a calculation processing function and performs various signal processing such as calculation processing on the pixel signal output from the column processing circuit 73 .

[0393] The signal processing circuit 76 functions as a digital signal control circuit that processes a received digital signal.

[0394] The digital signal output from the signal processing circuit 76 is output to an image processing circuit 79 outside the image sensor 70. The image processing circuit 79 performs predetermined processing on the digital signal, thereby generating an image signal for displaying an image on a predetermined display device.

[0395] Similar to the first embodiment, the automatic placement and routing technology is used in the layout design of the digital signal control circuit included in the semiconductor device 1 .

[0396] 4.2 Effects of this Implementation

[0397] According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

[0398] 5. Fifth Implementation

[0399] Next, the fifth embodiment is described. In the fifth embodiment, the case where the semiconductor device 1 is an MRAM (Magnetoresistive Random Access Memory) that uses a resistance change element as a storage element is described. In the case of MRAM, as a resistance change element, an element (also called an MTJ element) having a magnetoresistive effect through a magnetic tunnel junction (MTJ). The following description focuses on the differences from the first to fourth embodiments. In addition, a semiconductor device that uses a resistance change element as a storage element may be, for example, a ReRAM (Resistive Random Access Memory), a PCRAM (Phase-Change Random Access Memory), or the like.

[0400] 5.1 Overall Structure of Semiconductor Devices

[0401] Reference Fig.41 , an example of the overall structure of the semiconductor device 1 is described. Fig.41 1 is a block diagram showing the overall structure of the semiconductor device 1. Fig.41 In the figure, a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0402] like Fig.41 As shown, the semiconductor device 1 includes a memory cell array 91 , a row decoder 92 , a sense amplifier and a write driver (SA / WD) 93 , a page buffer 94 , an input / output circuit 95 , and a control circuit 96 .

[0403] The memory cell array 91 includes a plurality of memory cells MC corresponding to rows and columns. In addition, the memory cells MC in the same row are connected to the same word line WL, and the two ends of the memory cells MC in the same column are connected to the same bit line BL. The bit line BL includes, for example, a local bit line and a global bit line. The memory cell MC includes a variable resistance element. The variable resistance element can write data by changing its resistance state, and functions as a storage element that can non-volatilely retain the written data and can read it.

[0404] The row decoder 92 is connected to the memory cell array 91 via the word line WL. The row decoder 92 decodes a row address that specifies the row direction of the memory cell array 91. The word line WL is selected based on the decoding result, and a voltage required for operations such as data writing and reading is supplied to the selected word line WL.

[0405] The row decoder 92 includes a digital signal control circuit 92a for processing the received digital signal.

[0406] SA / WD93 is connected to the memory cell array 91 via the bit line BL. SA / WD93 supplies voltage to the memory cell MC of the operation object via the bit line BL, and writes and reads data to the memory cell MC. More specifically, the write driver WD of SA / WD93 writes data to the memory cell MC. In addition, the read amplifier SA of SA / WD93 reads data from the memory cell MC.

[0407] SA / WD93 includes a digital signal control circuit 93a for processing the received digital signal.

[0408] The page buffer 94 temporarily holds data written into the memory cell array 91 and data read out from the memory cell array 91 in data units called pages.

[0409] The page buffer 94 includes a digital signal control circuit 94 a that processes the received digital signal.

[0410] The input / output circuit 95 transmits various signals received from the outside of the semiconductor device 1 to the control circuit 96 and the page buffer 94 , and transmits various information from the control circuit 96 and the page buffer 94 to the outside of the semiconductor device 1 .

[0411] The input / output circuit 95 includes a digital signal control circuit 95 a that processes a received digital signal.

[0412] The control circuit 96 is connected to the row decoder 92, SA / WD 93, page buffer 94, and input / output circuit 95. The control circuit 96 controls the row decoder 92, SA / WD 93, and page buffer 94 according to various signals received by the input / output circuit 95 from outside the semiconductor device 1.

[0413] The control circuit 96 functions as a digital signal control circuit that processes a received digital signal.

[0414] Similar to the first embodiment, the automatic placement and routing technology is used in the layout design of the digital signal control circuit included in the semiconductor device 1 .

[0415] 5.2 Circuit Structure of Memory Cell Array

[0416] Next, refer to Fig.42 An example of the structure of the memory cell array 91 will be described. Fig.42 is a circuit diagram of the memory cell array 91. Fig.42In the example of , the memory cell MC, the word line WL, and the bit line BL are represented by being classified by a suffix including an index ("<>").

[0417] like Fig.42 As shown in FIG. 1 , a plurality of memory cells MC are arranged in a matrix in the memory cell array 91. Each memory cell MC corresponds to a plurality of bit lines BL (BL <0> BL <1> ,…,BL <n>) and a plurality of word lines WL(WL <0> , WL <1> ,…,WL <m>) in a word line group (M and N are arbitrary integers). That is, the memory cell MC<i,j> (0≤i≤M, 0≤j≤N) connected to word line WL and bit line BL <j>between.

[0418] Memory Cell MC<i,j> Contains selector SEL<i,j> MTJ<i,j> . Selector SEL<i,j> MTJ<i,j> For example, selector SEL<i,j> One end of a word line WL The other end is connected to the magnetoresistive element MTJ<i,j> One end of the magnetoresistive element MTJ<i,j> The other end of the bit line BL <j>connect.

[0419] The selector SEL (hereinafter also referred to as "switch element") functions as a switch that controls the current supply to the magnetoresistive element MTJ during the write operation and the read operation to the corresponding magnetoresistive element MTJ. More specifically, for example, when the voltage applied to the memory cell MC is less than a preset threshold voltage, the selector SEL in the memory cell MC acts as an insulator with a large resistance value to cut off the current (becomes in an off state). On the other hand, when the voltage applied to the memory cell MC is greater than the threshold voltage, the selector SEL acts as a conductor with a small resistance value to allow the current to flow (becomes in an on state). That is, the selector SEL has the following function: regardless of the direction of the flowing current, it switches whether the current is allowed to flow or cut off according to the magnitude of the voltage applied to the memory cell MC.

[0420] The selector SEL may be, for example, a two-terminal switch element. When the voltage applied between the two terminals is less than the threshold voltage, the selector SEL is in a high resistance state or a non-conducting state where almost no electricity flows. When the voltage applied between the two terminals is greater than the threshold voltage, the selector SEL is in a low resistance state, i.e., an electrically conductive state. The switch element can have this function regardless of the polarity of the voltage.

[0421] The magnetoresistive element MTJ functions as a storage element that stores data in a nonvolatile manner. The magnetoresistive element MTJ can switch between a low resistance state and a high resistance state according to the current supplied by the selector SEL. The magnetoresistive element MTJ can write data by changing its resistance state.

[0422] 5.3 Effects of this Implementation

[0423] According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

[0424] 6. Deformation, etc.

[0425] The semiconductor device of the above embodiment includes a first unit (1010), wherein the first unit includes: a first PMOS transistor (TP10); a second PMOS transistor (TP11), which is arranged in a first direction (X direction) with the first PMOS transistor, and one end of which is shared with one end of the first PMOS transistor; a first NMOS transistor (TN10), which is arranged in a second direction (Y direction) intersecting with the first direction with the first PMOS transistor; a second NMOS transistor (TN11), which is arranged in the first direction with the first NMOS transistor, and one end of which is shared with one end of the first NMOS transistor; a first wiring (130_90), which is electrically connected to the other end of the first PMOS transistor; a second wiring (130_91), which is electrically connected to one end of the first PMOS transistor and one end of the second PMOS transistor; a third wiring (130_92), which is electrically connected to the second PMOS transistor. the other end of the S transistor; a power supply voltage wiring (150_1), extending in the second direction, arranged above the first wiring, the second wiring and the third wiring, and electrically connected to the first wiring, the second wiring and the third wiring; a fourth wiring (130_93), electrically connected to the other end of the first NMOS transistor; a fifth wiring (130_94), electrically connected to one end of the first NMOS transistor and one end of the second NMOS transistor; a sixth wiring (130_95), electrically connected to the other end of the second NMOS transistor; a ground voltage wiring (150_3), extending in the second direction, arranged above the fourth wiring, the fifth wiring and the sixth wiring, and electrically connected to the fourth wiring, the fifth wiring and the sixth wiring; and a seventh wiring (130a), arranged in the same layer as the first to sixth wirings, and not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor.

[0426] By applying the above-described embodiment, a semiconductor device capable of suppressing an increase in development cost and an extension of development period can be provided.

[0427] In addition, the embodiment is not limited to the above-described form, and various modifications can be made.

[0428] For example, the semiconductor device 1 may be any semiconductor device to which the automatic placement and routing technology can be applied. The automatic placement and routing technology can also be used in scenarios other than the layout of digital control circuits.

[0429] For example, in the first embodiment, as a specific example of using a through-cell, a case is described in which the M1 wiring 130 of the ECO basic cell 1010 (ECO_NOR) configuring a NOR circuit is connected to the M1 wiring 130 of the ECO basic cell 1010 (ECO_I) configuring an inverter circuit via the ECO basic cell 1010 (ECO_T) configuring the through-cell, but the present invention is not limited to this. For example, the M1 wiring 130 of the ECO basic cell 1010 (ECO_NOR) configuring a NOR circuit can also be connected to the M1 wiring 130 of any one of the ECO basic cell 1010 (ECO_NAND) configuring a NAND circuit, the ECO basic cell 1010 (ECO_NOR) configuring other NOR circuits, the ECO basic cell 1010 (ECO_B) configuring a buffer circuit, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit via the ECO basic cell 1010 (ECO_T) configuring a through cell. For example, the M1 wiring 130 of the ECO basic cell 1010 (ECO_NAND) forming a NAND circuit can also be connected to the M1 wiring 130 of any one of the ECO basic cell 1010 (ECO_NAND) forming other NAND circuits, the ECO basic cell 1010 (ECO_I) forming an inverter circuit, the ECO basic cell 1010 (ECO_B) forming a buffer circuit, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit via the ECO basic cell 1010 (ECO_T) forming a through cell. For example, the M1 wiring 130 of the ECO basic cell 1010 (ECO_I) having an inverter circuit can be connected to the M1 wiring 130 of any one of the ECO basic cell 1010 (ECO_I) having other inverter circuits, the ECO basic cell 1010 (ECO_B) having a buffer circuit, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit via the ECO basic cell 1010 (ECO_T) having a through cell.For example, the M1 wiring 130 of the ECO basic cell 1010 (ECO_B) having a buffer circuit can be connected to the M1 wiring 130 of any one of the ECO basic cell 1010 (ECO_B) having other buffer circuits, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit via the ECO basic cell 1010 (ECO_T) having a through cell.

[0430] For example, the plan layout of the first embodiment Fig.26 The through-units in the region of coordinates (4, 2) and (5, 2) can also be equivalent to Figure 27 to Figure 29 ECO basic units 1010a and 1010b in FIG. Layout Fig.26 The through cells in the region with coordinates (5, 2) can also have Fig.16 , Fig.32 , Fig.34 The M1 wiring 130a_2 in the through cell is shown. Fig.26 The ECO logic cell in the region of coordinates (5, 1) can also communicate with the M1 wiring 130a_2 in the through cell in the region of coordinates (5, 2). Fig.26 The standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, and the standard cell 1003 of the inverter circuit in the region spanning the coordinates (5, 3) and (6, 3) are connected. Fig.26 The through cells in the region with coordinates (4, 3) and (4, 4) can have Fig.16 , Fig.32 , Fig.34 The M1 wiring 130a_2 in the through cell is shown.

[0431] For example, in the first embodiment, the standard cell and the ECO basic cell are described as planar cells, but the present invention is not limited thereto. The standard cell and the ECO basic cell may also be structures such as FinFETs and Nanosheets.

[0432] In FinFETs, the gate electrode faces two or more sides of the channel region. The channel region is formed in a convex shape formed on the surface of the semiconductor substrate. It is also possible to have multiple channels in one transistor.

[0433] In Nanosheets, gate electrodes are opposed to each other so as to surround a channel region. The channel region is formed in a flat-plate-shaped semiconductor layer. A plurality of flat-plate-shaped semiconductor layers may be stacked separately.

[0434] Furthermore, the “connection” in the above-mentioned embodiment also includes a state of indirect connection by interposing any other object such as a transistor or a resistor in between.

[0435] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and the scope of their equivalents.< / j> < / j> < / m> < / n>

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a first unit, wherein the first unit includes: a first PMOS transistor; A second PMOS transistor is arranged in a first direction with the first PMOS transistor, and one end of the second PMOS transistor is shared with one end of the first PMOS transistor; A first NMOS transistor is arranged in a second direction intersecting the first direction with the first PMOS transistor; A second NMOS transistor is arranged in the first direction with the first NMOS transistor, and one end of the second NMOS transistor is shared with one end of the first NMOS transistor; a first wiring electrically connected to the other end of the first PMOS transistor; a second wiring electrically connected to the one end of the first PMOS transistor and the one end of the second PMOS transistor; a third wiring electrically connected to the other end of the second PMOS transistor; a power supply voltage wiring extending in the second direction, disposed above the first wiring, the second wiring, and the third wiring, and electrically connected to the first wiring, the second wiring, and the third wiring; a fourth wiring electrically connected to the other end of the first NMOS transistor; a fifth wiring electrically connected to the one end of the first NMOS transistor and the one end of the second NMOS transistor; a sixth wiring electrically connected to the other end of the second NMOS transistor; a ground voltage wiring extending in the second direction, disposed above the fourth wiring, the fifth wiring, and the sixth wiring, and electrically connected to the fourth wiring, the fifth wiring, and the sixth wiring; as well as The seventh wiring is provided in the same layer as the first to sixth wirings and is not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

2. The semiconductor device according to claim 1, wherein: The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected to the power supply voltage wiring via the second wiring. A gate of the first NMOS transistor and a gate of the second NMOS transistor are electrically connected to the ground voltage wiring via the fifth wiring.

3. The semiconductor device according to claim 1, wherein: The gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are also electrically connected to the power supply voltage wiring via the second wiring.

4. The semiconductor device according to claim 1, wherein: A gate of the first PMOS transistor, a gate of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor are electrically connected to the ground voltage wiring via the fifth wiring.

5. The semiconductor device according to claim 1, wherein: The seventh wiring passes over the gate of the first PMOS transistor and the gate of the first NMOS transistor, over the first element isolation region surrounding the active regions of the first PMOS transistor and the second PMOS transistor, and over the second element isolation region surrounding the active regions of the first NMOS transistor and the second NMOS transistor.

6. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: a second unit, adjacent to one end of the first unit in the second direction; as well as a third unit, adjacent to the other end of the first unit in the second direction; The second cell and the third cell are electrically connected via the seventh wiring.

7. The semiconductor device according to claim 6, wherein: The second unit and the third unit are respectively any one of a NAND circuit, a NOR circuit, an inverter circuit and a buffer circuit.

8. The semiconductor device according to claim 1, wherein: The first unit further includes an eighth wiring, which passes through the first unit in the second direction, is arranged on the same layer as the first to seventh wirings, and is not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor and the seventh wiring.

9. The semiconductor device according to claim 8, wherein: The eighth wiring passes above the gate of the second PMOS transistor and the gate of the second NMOS transistor, above the first element isolation region surrounding the active regions of the first PMOS transistor and the second PMOS transistor, and above the second element isolation region surrounding the active regions of the first NMOS transistor and the second NMOS transistor.

10. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a fourth unit adjacent to the first unit in the first direction. The fourth unit comprises: a third PMOS transistor, adjacent to the second PMOS transistor in the first direction; a fourth PMOS transistor, arranged in the first direction with the third PMOS transistor, and having one end shared with one end of the third PMOS transistor; a third NMOS transistor, adjacent to the second NMOS transistor in the first direction, and arranged in parallel with the third PMOS transistor in the second direction; a fourth NMOS transistor, arranged in the first direction with the third NMOS transistor, and having one end shared with one end of the third NMOS transistor; a ninth wiring electrically connecting the other end of the third PMOS transistor to the power supply voltage wiring; a tenth wiring electrically connecting the one end of the third PMOS transistor and the one end of the fourth PMOS transistor to the power supply voltage wiring; an eleventh wiring electrically connecting the other end of the fourth PMOS transistor to the power supply voltage wiring; a twelfth wiring electrically connecting the other end of the third NMOS transistor to the ground voltage wiring; a thirteenth wiring electrically connecting the one end of the third NMOS transistor and the one end of the fourth NMOS transistor to the ground voltage wiring; and A fourteenth wiring electrically connects the other end of the fourth NMOS transistor to the ground voltage wiring.

11. The semiconductor device according to claim 10, wherein: The seventh wiring passes through the first cell and the fourth cell in the second direction, and is not electrically connected to the first to fourth PMOS transistors and the first to fourth NMOS transistors.

12. The semiconductor device according to claim 11, wherein: The seventh wiring passes above the gate of the third PMOS transistor and the gate of the second NMOS transistor, above the third element isolation region surrounding the active regions of the third PMOS transistor and the fourth PMOS transistor, and above the second element isolation region surrounding the active regions of the first NMOS transistor and the second NMOS transistor.

13. The semiconductor device according to claim 1, wherein: The one end, the other end and the gate of the first PMOS transistor are electrically connected to the power supply voltage wiring. The one end, the other end and the gate of the second PMOS transistor are electrically connected to the power supply voltage wiring. The one end, the other end and the gate of the first NMOS transistor are electrically connected to the ground voltage wiring. The one end, the other end, and a gate of the second NMOS transistor are electrically connected to the ground voltage wiring.

14. The semiconductor device according to claim 1, wherein: The one end, the other end and the gate of the first PMOS transistor are electrically connected to the power supply voltage wiring. The one end, the other end and the gate of the second PMOS transistor are electrically connected to the power supply voltage wiring. The one end and the other end of the first NMOS transistor are electrically connected to the ground voltage wiring, and the gate of the first NMOS transistor is electrically connected to the power supply voltage wiring. The one end and the other end of the second NMOS transistor are electrically connected to the ground voltage wiring, and a gate of the second NMOS transistor is electrically connected to the power supply voltage wiring.

15. The semiconductor device according to claim 1, wherein: The one end and the other end of the first PMOS transistor are electrically connected to the power supply voltage wiring, and the gate of the first PMOS transistor is electrically connected to the ground voltage wiring. The one end and the other end of the second PMOS transistor are electrically connected to the power supply voltage wiring, and the gate of the second PMOS transistor is electrically connected to the ground voltage wiring. The one end, the other end and the gate of the first NMOS transistor are electrically connected to the ground voltage wiring. The one end, the other end, and a gate of the second NMOS transistor are electrically connected to the ground voltage wiring.

16. A method for designing a semiconductor device, characterized in that: have: configuring a plurality of first unit processes; A step of connecting the plurality of first units by wiring; a step of arranging a plurality of second units in an area where the plurality of first units are not arranged; The step of changing at least one of the plurality of second units into a logic unit and changing at least another one of the plurality of second units into a third unit; as well as A step of connecting the logic cell to a first wiring that passes through the third cell and is not electrically connected to the third cell.

17. The method for designing a semiconductor device according to claim 16, wherein: The plurality of first units are any one of a NAND circuit, a NOR circuit, an inverter circuit and a buffer circuit, respectively. The plurality of second units are decoupling capacitors, The logic unit is any one of a NAND circuit, a NOR circuit, an inverter circuit, and a buffer circuit.

18. The method for designing a semiconductor device according to claim 16, wherein: In the step of changing, when the logic cell cannot be connected by wiring, the at least another one of the plurality of second cells is changed to the third cell.

19. A method for manufacturing a semiconductor device, characterized in that: have: configuring a plurality of first unit processes; A step of connecting the plurality of first units by wiring; a step of arranging a plurality of second units in an area where the plurality of first units are not arranged; A process for making a mask used in forming a transistor; A process of manufacturing a transistor based on the mask; The step of changing at least one of the plurality of second units into a logic unit and changing at least another one of the plurality of second units into a third unit; as well as a step of connecting the logic unit to a first wiring that passes through the third unit and is not electrically connected to the third unit; The step of manufacturing the mask and the step of connecting the logic cell to the first wiring are performed in parallel.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The step of manufacturing the transistor and the step of connecting the logic unit to the first wiring are performed in parallel.

Images