High-resistance time detection circuit, load current generation circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of converters, in particular to a high-resistance time detection circuit, a load current generation circuit, a chip and electronic equipment. The high-resistance time detection circuit comprises a current generation circuit, a capacitor charging circuit, an output control circuit and a shaping circuit, the current generating circuit is used for generating a first current signal; the capacitor charging circuit is used for controlling a first current signal to charge an energy storage capacitor when the converter circuit enters a high-resistance state, and the output control circuit is used for outputting a first marking signal under the triggering of a first triggering signal; and the shaping circuit is used for shaping the first mark signal to output a corresponding level trigger signal, and the level trigger signal is used for representing the high-resistance time of the high-resistance state of the converter circuit. By adopting the high-resistance time detection circuit provided by the invention, the high-resistance time of the converter circuit can be accurately sampled, so that the switching frequency is adjusted, and the working stability of the converter circuit is guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of converters, and in particular to a high-resistance time detection circuit, a load current generating circuit, a chip and an electronic device. Background Art

[0002] In a converter system, when the load current is low, the converter usually works in a discontinuous conduction mode (DCM) to reduce the power consumption of the system. After the converter enters the DCM mode, as the load current decreases, the switching frequency of the converter will be reduced. At the same time, when the converter works in the DCM mode, there will be a certain high-resistance time. Specifically, when the high-side power tube and the low-side power tube in the converter are turned off at the same time, the state in which the inductor current remains at 0A is called a high-resistance state, and the duration of the high-resistance state is called the high-resistance time. When the high-resistance time during the operation of the converter is large, the corresponding switching frequency of the converter will decrease. Therefore, in order to monitor the switching frequency of the converter and prevent its switching frequency from falling in certain sensitive frequency domains, it is usually necessary to accurately sample the high-resistance time when the converter is working. However, the accuracy of high-resistance time sampling in the related art is low and cannot meet the working requirements of the converter circuit. Summary of the invention

[0003] The present application provides a high-impedance time detection circuit, a load current generating circuit, a chip and an electronic device, the purpose of which is to accurately sample the duration of a high-impedance state of a converter circuit when it is working.

[0004] In a first aspect, the present application provides a high-impedance time detection circuit for detecting the high-impedance time when a converter circuit is working, the high-impedance time detection circuit comprising: a current generating circuit, a capacitor charging circuit, an output control circuit and a shaping circuit;

[0005] The current generating circuit is used to generate a first current signal and output the first current signal to the capacitor charging circuit;

[0006] The capacitor charging circuit is used to receive a first enable signal when the converter circuit enters a high-impedance state, control the first current signal to charge the energy storage capacitor according to the first enable signal, and output a first trigger signal when charging is completed;

[0007] The output control circuit is used to receive a second enable signal when the converter circuit enters a high-impedance state, and output a first flag signal under the triggering of the second enable signal and the first trigger signal;

[0008] The shaping circuit is used to perform shaping processing on the first flag signal to output a corresponding level trigger signal, and the level trigger signal is used to represent a first high-impedance time during which the high-impedance state of the converter circuit continues.

[0009] In one possible design, the current generating circuit includes a first transistor, a second transistor, and a first resistor;

[0010] The first electrode of the first transistor is connected to the control electrode of the second transistor, and the first electrode of the first transistor and the control electrode of the second transistor are both used to receive a first bias current; the control electrode of the first transistor is connected to the second electrode of the second transistor and the first end of the first resistor; the second electrode of the first transistor and the second end of the first resistor are both grounded; the first electrode of the second transistor is connected to the capacitor charging circuit.

[0011] In a possible design, the capacitor charging circuit includes a third transistor, a fourth transistor, a fifth transistor, an energy storage capacitor, and a NAND gate;

[0012] The control electrode of the third transistor, the first electrode of the third transistor and the control electrode of the fourth transistor are all connected to the first electrode of the second transistor, the second electrode of the third transistor is connected to the second electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both used to receive a power supply voltage;

[0013] The first electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the first electrode of the fifth transistor is connected to the first end of the energy storage capacitor, and the second end of the energy storage capacitor is grounded; the larger the capacitance value of the energy storage capacitor, the longer the corresponding first high impedance time;

[0014] The input end of the NAND gate is used to receive the high-impedance state detection signal and the first enable signal respectively, and the output end of the NAND gate is connected to the control electrode of the fifth transistor.

[0015] In one possible design, the output control circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0016] The second electrode of the sixth transistor is used to receive a second bias current, the control electrode of the sixth transistor is connected to the output end of the NAND gate, the first electrode of the sixth transistor is connected to the second electrode of the seventh transistor; the first electrode of the seventh transistor is connected to the first electrodes of the eighth transistor and the tenth transistor, and the second electrodes of the eighth transistor and the tenth transistor are both grounded;

[0017] The control electrode of the seventh transistor, the control electrode of the eighth transistor and the first electrode of the ninth transistor are all connected to the first electrode of the fifth transistor, the second electrode of the ninth transistor is grounded, and the control electrode of the ninth transistor and the control electrode of the tenth transistor are both used to receive the second enable signal;

[0018] The first enable signal and the second enable signal have opposite logic states.

[0019] In one possible design, the shaping circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a Schmitt inverter, and a first inverter;

[0020] The second electrode of the eleventh transistor is used to receive a third bias current, the control electrode of the eleventh transistor is connected to the output end of the NAND gate, the first electrode of the eleventh transistor is respectively connected to the first electrode of the twelfth transistor, the first electrode of the thirteenth transistor and the input end of the Schmidt inverter, and the second electrode of the twelfth transistor and the second electrode of the thirteenth transistor are both grounded;

[0021] The control electrode of the twelfth transistor is connected to the first electrode of the eighth transistor; the control electrode of the thirteenth transistor is used to receive the second enable signal;

[0022] The output end of the Schmitt inverter is connected to the input end of the first inverter, and the output end of the first inverter is used to output the level trigger signal.

[0023] In a second aspect, the present application further provides a load current generating circuit for use in a converter circuit, wherein the load current generating circuit comprises a first high-resistance time detection circuit, a second high-resistance time detection circuit, a random code generating circuit, and a dummy load circuit; the first high-resistance time detection circuit and the second high-resistance time detection circuit are the high-resistance time detection circuits described in any one of the above items, and the capacitance value of the energy storage capacitor in the second high-resistance time detection circuit is greater than the capacitance value of the energy storage capacitor in the first high-resistance time detection circuit;

[0024] The first high-resistance time detection circuit is used to output a first level trigger signal when detecting that the high-resistance time of the converter circuit reaches a first high-resistance time threshold; the second high-resistance time detection circuit is used to output a second level trigger signal when detecting that the high-resistance time of the converter circuit reaches a second high-resistance time threshold; the second high-resistance time threshold is greater than the first high-resistance time threshold;

[0025] The random code generating circuit is used to receive a clock signal and randomly generate a random code according to the clock signal;

[0026] The dummy load circuit is used to amplify the reference current according to the random code to obtain a random load current under the triggering of the first level trigger signal and / or the second level trigger signal.

[0027] In one possible design, the dummy load circuit includes a reference current generating circuit, a first current amplifying circuit, a second current amplifying circuit, and a third current amplifying circuit;

[0028] The reference current generating circuit is used to generate the reference current;

[0029] The first current amplifying circuit is used to amplify the reference current according to the first level trigger signal and the random code, and output a first amplified current;

[0030] The second current amplifying circuit is used to amplify the reference current according to the second level trigger signal and a preset amplification factor, and output a second amplified current;

[0031] The third current amplifier circuit is used to amplify the current after the first amplified current and the second amplified current merge, and output the random load current.

[0032] In one possible design, the reference current generating circuit includes a twenty-eight transistor, the first electrode and the control electrode of the twenty-eighth transistor are short-circuited, the first electrode and the control electrode of the twenty-eighth transistor are used to receive a fourth bias current, and the second electrode of the twenty-eighth transistor is used to receive a power supply voltage.

[0033] In one possible design, the first current amplifying circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0034] The control electrode of the fourteenth transistor is connected to the output end of the first high-resistance time detection circuit for receiving the first level trigger signal, and the first electrode of the fourteenth transistor is used to output the first amplified current; the second electrode of the fourteenth transistor is respectively connected to the first electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor, and the second electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor are respectively connected to the first electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor, and the second electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor are all used to receive the power supply voltage;

[0035] The control electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor are all connected to the output end of the random code generating circuit; the control electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-third transistor are all connected to the control electrode of the twenty-eighth transistor.

[0036] In a possible design, the size ratio of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor is 1:2:4:8.

[0037] In one possible design, the second current amplifying circuit includes a twenty-fourth transistor and a twenty-fifth transistor;

[0038] The control electrode of the 24th transistor is connected to the output end of the second high-resistance time detection circuit for receiving the second level trigger signal, the first electrode of the 24th transistor is connected to the first electrode of the 14th transistor, and the first electrode of the 24th transistor is used to output the second amplified current;

[0039] The second electrode of the 24th transistor is connected to the first electrode of the 25th transistor, the second electrode of the 25th transistor is used to receive the power supply voltage, and the control electrode of the 25th transistor is connected to the control electrode of the 28th transistor.

[0040] In a possible design, the third current amplifying circuit includes a twenty-sixth transistor, a twenty-seventh transistor, a second resistor and a third resistor;

[0041] The first electrode and the control electrode of the twenty-sixth transistor are both connected to the first electrode of the fourteenth transistor, the control electrode of the twenty-sixth transistor is connected to the control electrode of the twenty-seventh transistor, and the first electrode of the twenty-seventh transistor is grounded;

[0042] The second electrode of the twenty-sixth transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the second electrode of the twenty-seventh transistor, and the first electrode of the twenty-seventh transistor is the output end of the third current amplifying circuit, used to output the random load current.

[0043] In a third aspect, the present application further provides a converter circuit, wherein the converter circuit includes the high-impedance time detection circuit as described in any one of the above items; or the converter circuit includes the load current generating circuit as described in any one of the above items.

[0044] In a fourth aspect, the present application further provides a chip, wherein the chip includes the high-impedance time detection circuit as described in any one of the above items; or the chip includes the load current generating circuit as described in any one of the above items.

[0045] In a fifth aspect, the present application also provides an electronic device, the electronic device comprising the high-impedance time detection circuit as described in any one of the above items; or the electronic device comprising the load current generating circuit as described in any one of the above items.

[0046] The high-impedance time detection circuit provided by the first aspect above includes: a current generating circuit, a capacitor charging circuit, an output control circuit and a shaping circuit; a current generating circuit, used to generate a first current signal, and output the first current signal to the capacitor charging circuit; a capacitor charging circuit, used to receive a first enable signal when the converter circuit enters a high-impedance state, control the first current signal according to the first enable signal to charge the energy storage capacitor, and output a first trigger signal when the charging is completed; an output control circuit, used to receive a second enable signal when the converter circuit enters a high-impedance state, and output a first flag signal under the triggering of the second enable signal and the first trigger signal; a shaping circuit, used to shape the first flag signal to output a corresponding level trigger signal, and the level trigger signal is used to characterize the high-impedance time of the high-impedance state of the converter circuit. It can be seen that the high-impedance time detection circuit provided by the present application can accurately sample the high-impedance time when the converter circuit is working, so that the switching frequency of the converter can be adjusted according to the sampled high-impedance time, and the switching frequency of the converter is prevented from falling in some sensitive frequency domains, thereby ensuring the stability of the converter circuit.

[0047] The beneficial effects provided in the above-mentioned other aspects and the possible designs of the above-mentioned other aspects can be referred to the beneficial effects brought about by the above-mentioned first aspect and the possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of a converter circuit structure provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of the high-impedance time detection circuit structure provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of the overall structure of a load current generating circuit provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of the structure of a dummy load circuit provided in an embodiment of the present application;

[0052] Figure 5A schematic diagram of the converter circuit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0054] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0055] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0056] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0057] When the converter works in DCM mode, when it is detected that the inductor current on the energy storage inductor in the converter is reduced to 0A, the high-side power tube and the low-side power tube in the converter are controlled to be turned off at the same time, so that the inductor current remains at 0A, thereby saving power consumption. When the inductor current is reduced to 0A, it is usually also called a high-impedance state, and the time when the inductor current remains in the 0A state is generally called the high-impedance time.

[0058] When the high-impedance time during the operation of the converter is long, since the high-impedance time is generally much longer than the conduction time of the high-side power tube and the low-side power tube in the converter, it can be approximately considered that the high-impedance time during the operation of the converter is equal to its switching period. If the high-impedance time during the operation of the converter is long, the corresponding switching frequency of the converter will decrease. Therefore, in order to monitor the switching frequency of the converter and prevent its switching frequency from falling in certain sensitive frequency domains, it is usually necessary to accurately sample the high-impedance time when the converter is working. However, the accuracy of high-impedance time sampling in related technologies is low and cannot meet the working requirements of the converter circuit.

[0059] In order to overcome the defects in the above-mentioned related technologies and to achieve accurate sampling of the high-impedance time during the operation of the converter, the present application provides a high-impedance time detection circuit, which includes: a current generating circuit, a capacitor charging circuit, an output control circuit and a shaping circuit; the current generating circuit is used to generate a first current signal and output the first current signal to the capacitor charging circuit; the capacitor charging circuit is used to receive a first enable signal when the converter circuit enters a high-impedance state, control the first current signal according to the first enable signal to charge the energy storage capacitor, and output a first trigger signal when the charging is completed; the output control circuit is used to receive a second enable signal when the converter circuit enters a high-impedance state, and output a first flag signal under the triggering of the second enable signal and the first trigger signal; the shaping circuit is used to shape the first flag signal to output a corresponding level trigger signal, and the level trigger signal is used to characterize the high-impedance time of the high-impedance state of the converter circuit. It can be seen that by adopting the high-impedance time detection circuit provided in the present application, the high-impedance time of the converter circuit when it is working can be accurately sampled, so that the switching frequency of the converter can be adjusted according to the sampled high-impedance time, avoiding the switching frequency of the converter from falling into some sensitive frequency domains, thereby ensuring the stability of the converter circuit operation.

[0060] In order to more clearly describe the high-impedance time detection circuit and the load current generating circuit of the present application, the following embodiments illustrate the technical solution of the present application in combination with a specific converter circuit. It should be noted that the converter circuit provided below is only used to assist in explaining the high-impedance time detection circuit and the load current generating circuit provided by the present application, and does not mean that the high-impedance time detection circuit and the load current generating circuit provided by the present application can only be used in the converter circuit provided below.

[0061] Figure 1 For a schematic diagram of a converter circuit structure provided in an embodiment of the present application, see Figure 1 As shown, the converter circuit includes a high-side transistor NM1, a low-side transistor NM2, a first inductor L0, a first capacitor C1, a high-side transistor driving circuit HDRV, a low-side transistor driving circuit HDRV and a control circuit 21.

[0062] Wherein, two control output pins of the control circuit 21 are respectively connected to the input ends of the high-side transistor driving circuit HDRV and the low-side transistor driving circuit HDRV, and the output ends of the high-side transistor driving circuit HDRV and the low-side transistor driving circuit HDRV are respectively connected to the control electrodes of the high-side transistor NM1 and the low-side transistor NM2. The first electrode of the high-side transistor NM1 receives the power supply voltage VIN0, the second electrode of the high-side transistor NM1 is connected to the first end of the first inductor L0, the second end of the first inductor L0 is connected to the first end of the first capacitor C1, and at the same time, the first end of the first capacitor C1 is grounded, and the second end of the first capacitor C1 is the output end of the converter circuit. The second electrode of the high-side transistor NM1 is connected to the first electrode of the low-side transistor NM2, and the second electrode of the low-side transistor NM2 is connected to the second end of the first capacitor C1. Wherein, SW0 is the midpoint of the high-side transistor NM1 and the low-side transistor NM2.

[0063] Among them, the control circuit 21 is used to control the conduction and shutdown of the high-side transistor NM1 and the low-side transistor NM2 respectively to achieve the purpose of transforming the power supply voltage VIN0. The first inductor L0 and the first capacitor C1 are used to form an energy storage circuit to discharge to the outside after the high-side transistor NM1 is turned off.

[0064] It should be noted that this embodiment Figure 1 The high-side transistor NM1 and the low-side transistor NM2 in the converter circuit shown are both NMOS (N-Metal-Oxide-Semiconductor) tubes. In other embodiments, the high-side transistor NM1 and the low-side transistor NM2 can also be PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the high-side transistor NM1 and the low-side transistor NM2 are NMOS tubes, their first pole is the drain, their second pole is the source, and the control pole is the gate.

[0065] Figure 2 For a schematic diagram of the high-impedance time detection circuit structure provided in the embodiment of the present application, please refer to Figure 2As shown, the high-impedance time detection circuit 100 provided in this embodiment includes: a current generating circuit 11, a capacitor charging circuit 12, an output control circuit 13 and a shaping circuit 14; the current generating circuit 11 is used to generate a first current signal and output the first current signal to the capacitor charging circuit 12; the capacitor charging circuit 12 is used to receive the first enable signal EN when the converter circuit enters the high-impedance state, control the first current signal according to the first enable signal EN to charge the energy storage capacitor, and output a first trigger signal when the charging is completed; the output control circuit 13 is used to receive the second enable signal ENZ when the converter circuit enters the high-impedance state, and output a first flag signal under the triggering of the second enable signal ENZ and the first trigger signal; the shaping circuit 14 is used to shape the first flag signal to output a corresponding level trigger signal EN_DUMMY, and the level trigger signal EN_DUMMY is used to characterize the high-impedance time of the high-impedance state of the converter circuit.

[0066] See also Figure 1 As shown, in this embodiment, the input end of the high-impedance time detection circuit 100 can be specifically connected to the control circuit 21 of the converter to receive the high-impedance state detection signal HZ and the enable signal output by the control circuit 21. The high-impedance state detection signal and the enable signal are used to control the high-impedance time detection circuit 100 to start sampling when the converter enters the dead zone to detect the time when the converter circuit is in the high-impedance state, that is, to sample the high-impedance time output in this embodiment.

[0067] For details, please combine Figure 1 and Figure 2 As shown, the first enable signal EN and the second enable signal ENZ are two signals with opposite logic states, that is, when the logic state of the first enable signal EN is 1, the logic state of the second enable signal ENZ is 0. Specifically, a PWM signal can be used to represent the first enable signal EN and the second enable signal ENZ. When the PWM signal is at a high level, it indicates that the corresponding enable signal is working, and when the PWM signal is at a low level, it indicates that the corresponding enable signal is not working.

[0068] The high-impedance time detection circuit 100 provided in this embodiment is used to enable the circuit when the converter circuit enters the high-impedance time, and the high-impedance time is characterized by the charging time of the energy storage capacitor by the capacitor charging circuit 12. In this way, the high-impedance time of the converter circuit when it is working can be accurately sampled, so that the switching frequency of the converter can be adjusted according to the sampled high-impedance time, avoiding the switching frequency of the converter from falling into some sensitive frequency domains, thereby ensuring the stability of the converter circuit operation.

[0069] See also Figure 2As shown, in one embodiment, the current generating circuit 11 provided in this embodiment includes a first transistor Q1, a second transistor Q2 and a first resistor R1. The first electrode of the first transistor Q1 is connected to the control electrode of the second transistor Q2, and the first electrode of the first transistor Q1 and the control electrode of the second transistor Q2 are both used to receive the first bias current IBIAS1; the control electrode of the first transistor Q1 is connected to the second electrode of the second transistor Q2 and the first end of the first resistor R1; the second electrode of the first transistor Q1 and the second end of the first resistor R1 are both grounded GND; the first electrode of the second transistor Q2 is connected to the capacitor charging circuit 12.

[0070] It should be noted that the first transistor Q1 and the second transistor Q2 in the current generating circuit 11 provided in this embodiment are both NMOS (N-Metal-Oxide-Semiconductor) tubes. In other embodiments, the first transistor Q1 and the second transistor Q2 can also be PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the first transistor Q1 and the second transistor Q2 are NMOS tubes, their first pole is the drain, their second pole is the source, and the control pole is the gate.

[0071] It can be understood that when the circuit system is powered on, a first bias current IBIAS1 is generated, and then a loop formed by the first transistor Q1, the second transistor Q2 and the first resistor R generates a current of VGS_Q1 / R1 on the branch where the second electrode of the second transistor Q2 is located, that is, the first current signal in this embodiment is generated, wherein VGS_Q1 is the gate-source voltage of the first transistor Q1.

[0072] Furthermore, the magnitude of the first current signal may be adjusted by adjusting the resistance value of the first resistor R1. Specifically, the resistance value of the first resistor R1 is inversely proportional to the magnitude of the first current signal.

[0073] Please continue to see Figure 2As shown, the capacitor charging circuit 12 provided in this embodiment includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, an energy storage capacitor C1 and a NAND gate 10. Among them, the control electrode of the third transistor Q3, the first electrode of the third transistor Q3 and the control electrode of the fourth transistor Q4 are all connected to the first electrode of the second transistor Q2, the second electrode of the third transistor Q3 is connected to the second electrode of the fourth transistor Q4, and the second electrode of the third transistor Q3 and the second electrode of the fourth transistor Q4 are both used to receive the power supply voltage VDD. The first electrode of the fourth transistor Q4 is connected to the second electrode of the fifth transistor Q5, the first electrode of the fifth transistor Q5 is connected to the first end of the energy storage capacitor C1, and the second end of the energy storage capacitor C1 is grounded GND. Among them, the input end of the NAND gate 10 is respectively connected to the control circuit 21 in the converter circuit, and is respectively used to receive the high-impedance state detection signal HZ and the first enable signal EN output by the control circuit 21, and the output end of the NAND gate 10 is connected to the control electrode of the fifth transistor Q5.

[0074] In this embodiment, a PMOS current mirror structure is used to charge the energy storage capacitor C1. In other embodiments, an NMOS current mirror structure may also be used to charge the energy storage capacitor C1.

[0075] It should be noted that the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 in the current generating circuit 11 provided in this embodiment all use PMOS (P-Metal-Oxide-Semiconductor) tubes. In other embodiments, the fifth transistor Q5 may also use NMOS (N-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 all use PMOS tubes, their first pole is the drain, their second pole is the source, and the control pole is the gate.

[0076] During normal operation, the first enable signal EN is at a high level. When the control circuit 21 detects that the converter enters a high-impedance state, a high-impedance state detection signal HZ is output, and at this time, the high-impedance state detection signal HZ is also at a high level. When the first enable signal EN and the high-impedance state detection signal HZ are both at a high level, that is, when the first enable signal EN and the high-impedance state detection signal HZ are both valid, the fifth transistor Q5 is turned on, and the fourth transistor Q4 charges the energy storage capacitor C1 with the mirrored first current signal. The charging time of the energy storage capacitor C1 can represent the duration of the high-impedance state.

[0077] It is understandable that the larger the capacitance value of the energy storage capacitor C1, the longer the corresponding first high impedance time. Specifically, the capacitance value of the energy storage capacitor C1 is set according to the first high impedance time threshold HZ1 as needed. When the energy storage capacitor C1 is fully charged, it can be determined that the detected high impedance time reaches the first high impedance time threshold HZ1.

[0078] When the energy storage capacitor C1 is fully charged, a first trigger signal is output. Specifically, the first trigger signal is a voltage signal, that is, when the energy storage capacitor C1 is fully charged, the voltage on the first end of the energy storage capacitor C1 can trigger the output control circuit 13 to output a first flag signal. The first flag signal can indicate that the duration of the high-impedance state of the converter circuit reaches the set first high-impedance time threshold HZ1.

[0079] Please continue to see Figure 1 As shown, when the converter circuit enters the DCM mode, when it is detected that the inductor current on the first inductor L0 in the circuit is reduced to 0A, it is determined that the converter circuit enters the high-impedance state, and the logic state of the high-impedance state detection signal HZ is 1.

[0080] Please continue to see Figure 2 As shown, the output control circuit 13 includes a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9 and a tenth transistor Q10. The second electrode of the sixth transistor Q6 is used to receive the second bias current IBIAS2, the control electrode of the sixth transistor Q6 is connected to the output end of the NAND gate 10, the first electrode of the sixth transistor Q6 is connected to the second electrode of the seventh transistor Q7; the first electrode of the seventh transistor Q7 is connected to the first electrodes of the eighth transistor Q8 and the tenth transistor Q10, and the second electrode of the eighth transistor Q8 and the second electrode of the tenth transistor Q10 are both grounded GND. The control electrode of the seventh transistor Q7, the control electrode of the eighth transistor Q8 and the first electrode of the ninth transistor Q9 are all connected to the first electrode of the fifth transistor Q5, the second electrode of the ninth transistor Q9 is grounded GND, and the control electrode of the ninth transistor Q9 and the control electrode of the tenth transistor Q10 are both used to receive the second enable signal ENZ; the logic states of the first enable signal EN and the second enable signal ENZ are opposite.

[0081] The sixth transistor Q6 and the seventh transistor Q7 in the output control circuit 13 provided in this embodiment are both PMOS (P-Metal-Oxide-Semiconductor) tubes. In other embodiments, the sixth transistor Q6 and the seventh transistor Q7 can also be NMOS (N-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the sixth transistor Q6 and the seventh transistor Q7 are both PMOS tubes, their first pole is the drain, their second pole is the source, and the control pole is the gate.

[0082] It should be noted that the eighth transistor Q8, the ninth transistor Q9 and the tenth transistor Q10 in the output control circuit 13 provided in this embodiment are all NMOS (N-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the eighth transistor Q8, the ninth transistor Q9 and the tenth transistor Q10 are NMOS tubes, their first pole is the drain, their second pole is the source, and the control pole is the gate.

[0083] From the above description, it can be seen that the high-impedance time T that can just flip the output level of the detection circuit HZ It can be expressed as the following formula:

[0084]

[0085] In the above formula (1), C1 is the capacitance value of the energy storage capacitor C1, R1 is the resistance value of the first resistor R1, V GS_Q8 is the gate voltage of the eighth transistor Q8, that is, V GS_Q8 is the voltage value on the first terminal of the energy storage capacitor C1, I Q3 is the current value flowing through the third transistor Q3, that is, the first current signal generated by the current generating circuit 11 in this embodiment, V GS_Q3 is the voltage on the gate of the third transistor Q3. Since the third transistor Q3 and the eighth transistor Q8 have the same specifications and size, V GS_Q3 and V GS_Q8 Approximately equal, the two can cancel each other. Therefore, it can be seen that the high resistance time T HZ The size depends on the capacitance value of the energy storage capacitor C1 and the resistance value of the first resistor R1. Therefore, the capacitance value of the energy storage capacitor C1 and the resistance value of the first resistor R1 can be set reasonably according to the high-resistance time threshold that needs to be set.

[0086] At the same time, the above formula (1) can also be used as a calculation formula for the first high-resistance time threshold HZ1.

[0087] In this embodiment, the current values ​​of the first bias current IBIAS1 and the second bias current IBIAS2 are equal, and the sizes of the first transistor Q1 and the eighth transistor Q8 are the same, so V GS_Q3 and V GS_Q8 The gate-source voltage of NMOSFET in the high-resistance time detection circuit is approximately equal and can cancel each other out. This eliminates the deviation of the gate-source voltage of NMOSFET in different process angles and temperatures, making the sampling accuracy of the high-resistance time higher.

[0088] Please continue to see Figure 2As shown, the shaping circuit 14 provided in this embodiment includes an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a Schmitt inverter Sch0 and a first inverter INV0. Among them, the second electrode of the eleventh transistor Q11 is used to receive the third bias current IBIAS3, the control electrode of the eleventh transistor Q11 is connected to the output end of the NAND gate 10, the first electrode of the eleventh transistor Q11 is respectively connected to the first electrode of the twelfth transistor Q12, the first electrode of the thirteenth transistor Q13 and the input end of the Schmitt inverter Sch0, and the second electrode of the twelfth transistor Q12 and the second electrode of the thirteenth transistor Q13 are both grounded GND. Among them, the control electrode of the twelfth transistor Q12 is connected to the first electrode of the eighth transistor Q8; the control electrode of the thirteenth transistor Q13 is used to receive the second enable signal ENZ; the output end of the Schmitt inverter Sch0 is connected to the input end of the first inverter INV0, and the output end of the first inverter INV0 is used to output the level signal EN_DUMMY.

[0089] It can be understood that when the converter circuit does not enter the high-impedance state, the logic state of the high-impedance state detection signal HZ is 0, the logic state of the first enable signal EN is low, and the logic state of the second enable signal ENZ is high. The second enable signal ENZ controls the ninth transistor Q9 and the thirteenth transistor Q13 to be turned on. At this time, the level trigger signal EN_DUMMY output by the high-impedance time detection circuit 100 is reset to 0. When the converter circuit enters the high-impedance state, the logic state of the high-impedance state detection signal HZ is 1, the first enable signal EN is flipped to a high level, and the second enable signal ENZ is flipped to a low level, then the second enable signal ENZ controls the ninth transistor Q9 and the thirteenth transistor Q13 to turn off, and the gate voltage of the eighth transistor Q8 remains at 0V due to the existence of the energy storage capacitor C0, then the eighth transistor Q8 is turned off, and the gate of the twelfth transistor Q12 is pulled up to a high level by the second bias current IBIAS2, then the level trigger signal EN_DUMMY output by the high-impedance time detection circuit 100 remains at a low level. Then, the fourth transistor Q4 will mirror the first current signal of the third transistor Q3 and charge the energy storage capacitor C1. If the high-impedance time is long enough for the upper plate voltage of the energy storage capacitor C1 to be charged to a current sufficient for the seventh transistor Q7 to provide the second bias current IBIAS2, the gate voltage of the twelfth transistor Q12 will be pulled down to a low level by the tenth transistor Q10, and the level trigger signal EN_DUMMY output by the high-impedance time detection circuit 100 will flip to a high level, indicating that the high-impedance state duration of the converter circuit reaches the set first high-impedance time threshold HZ1.

[0090] It can be seen from the above analysis that the high-resistance time detection circuit 100 provided in this embodiment has a high-resistance time THZ It is only related to the capacitance value of the energy storage capacitor C1 and the resistance value of the first resistor R1, eliminating the influence of the difference of MOS tube devices in the circuit on the sampling result, so that the sampling accuracy of the high-resistance time is higher.

[0091] When the converter circuit enters the DCM operating mode, the switching frequency of the converter is only related to the load current at the output end of the converter. When the load current at the output end of the converter is large, the corresponding working cycle will be shortened, and the switching frequency of the converter will also increase. That is, when the load current is large, the switching frequency of the converter will also increase. On the contrary, when the load current becomes smaller, the switching frequency of the converter will also become smaller.

[0092] In some application scenarios, when the load at the output end of the converter circuit is fixed, the load current of the converter circuit generally does not change. In this way, when the converter circuit enters the DCM working mode, the switching frequency of the converter is always a constant value, which may cause the switching frequency of the converter to fall into some sensitive frequency domains. For example, the switching frequency and the frequency domains of some devices overlap with each other, which will also affect the stability of the normal operation of the converter.

[0093] In order to overcome the above technical defects, the present application also provides a load current generating circuit, which is used in a converter circuit. The load current generating circuit includes two high-resistance time detection circuits, a random code generating circuit and a dummy load circuit; the capacitance values ​​of the energy storage capacitors in the two high-resistance time detection circuits are different, and the corresponding high-resistance time thresholds are also different. When it is detected that the high-resistance time reaches the corresponding high-resistance time threshold, the corresponding level trigger signal is output; the random code generating circuit can randomly generate a random code; the dummy load circuit amplifies the reference current according to the corresponding level trigger signal and the random code, and specifically can amplify the reference current to a multiple corresponding to the random code to obtain a random load current, and input the generated random load current to the output end of the converter. In this way, since the amplification factor in the generated current amplification signal is randomly generated, the current value of the amplified random load current is also randomly changed. Since the switching frequency of the system is related to the load current when the converter works in the DCM mode, the randomly changed load current can make the switching frequency of the circuit change randomly, avoiding the fixed switching frequency falling in a sensitive frequency domain, thereby ensuring the stability of the converter circuit operation.

[0094] Figure 3 For the overall structural diagram of the load current generating circuit provided in the embodiment of the present application, please refer to Figure 3As shown, the load current generating circuit 300 provided in this embodiment includes a first high-impedance time detection circuit 301, a second high-impedance time detection circuit 302, a random code generating circuit 303 and a dummy load circuit 304. Among them, the input ends of the first high-impedance time detection circuit 301 and the second high-impedance time detection circuit 302 are used to receive the high-impedance state detection signal HZ, the output ends of the first high-impedance time detection circuit 301 and the second high-impedance time detection circuit 302 are connected to the dummy load circuit 304, and the input end of the random code generating circuit 303 is used to receive a clock signal, and the specific clock signal can be a PWM wave signal, which is valid when the PWM wave signal is at a high level. The output end of the random code generating circuit 303 is also connected to the dummy load circuit 304.

[0095] The circuit structures of the first high-impedance time detection circuit 301 and the second high-impedance time detection circuit 302 can refer to the above embodiments, and the circuit structures of the first high-impedance time detection circuit 301 and the second high-impedance time detection circuit 302 are the same, and the capacitance value of the energy storage capacitor in the second high-impedance time detection circuit 302 is greater than the capacitance value of the energy storage capacitor in the first high-impedance time detection circuit 301. Correspondingly, the high-impedance time threshold detected by the second high-impedance time detection circuit 302 is greater than the high-impedance time threshold corresponding to the first high-impedance time detection circuit 301.

[0096] The first high-impedance time detection circuit 301 is used to output a first level trigger signal EN_DUMMY1 when it is detected that the high-impedance time of the converter circuit reaches a first high-impedance time threshold HZ1; the second high-impedance time detection circuit 302 is used to output a second level trigger signal EN_DUMMY2 when it is detected that the high-impedance time of the converter circuit reaches a second high-impedance time threshold HZ2. In this embodiment, the second high-impedance time threshold HZ2 is greater than the first high-impedance time threshold HZ1.

[0097] Among them, the random code generating circuit 303 is used to receive a clock signal and randomly generate a random code according to the clock signal; the random code corresponds to the amplification factor of the random current; the dummy load circuit 304 is used to amplify the reference current according to the random code under the triggering of the first level trigger signal and / or the second level trigger signal to obtain a random load current.

[0098] During operation, if the first high-impedance time detection circuit 301 detects that the high-impedance time reaches the first high-impedance time threshold HZ1, it will control the first level trigger signal EN_DUMMY1 to be valid, and the binary random code will control the dummy load circuit 304 to generate a randomly changing load current at the output end. If the second high-impedance time detection circuit 302 detects that the high-impedance time reaches the second high-impedance time threshold HZ2, it will make the second level trigger signal EN_DUMMY2 valid, and control the load current generated by the dummy load circuit 304 to further increase, thereby making the switching frequency more random.

[0099] According to the load current generating circuit 300 provided in this embodiment, since the amplification factor in the generated current amplification signal is randomly generated, the current value of the amplified random load current also changes randomly. Since when the converter operates in DCM mode, the switching frequency of the system is related to the load current, the randomly changing load current can make the switching frequency of the circuit change randomly, avoiding the switching frequency from being fixed in a sensitive frequency domain, thereby ensuring the stability of the converter circuit operation.

[0100] Figure 4 This is a schematic diagram of the structure of the dummy load circuit provided in the embodiment of the present application. The dummy load circuit 304 is mainly used to amplify the reference current according to the random code and output the random load current according to the trigger of the level trigger signal. Figure 4 As shown, the dummy load circuit 304 provided in this embodiment includes a reference current generating circuit 41 , a first current amplifying circuit 42 , a second current amplifying circuit 43 and a third current amplifying circuit 44 .

[0101] The reference current generating circuit 41 is used to generate a reference current. The first current amplifying circuit 42 is used to amplify the reference current according to the first level trigger signal EN_DUMMY1 and the random code, and output the first amplified current. The second current amplifying circuit 43 is used to amplify the reference current according to the second level trigger signal EN_DUMMY2 and the preset amplification factor, and output the second amplified current; the third current amplifying circuit 44 is used to amplify the current after the first amplified current and the second amplified current merge, and output the random load current.

[0102] It can be understood that in one application scenario, the dummy load circuit 304 of this embodiment is equivalent to a current three-stage amplifier circuit. After receiving the first level trigger signal EN_DUMMY1 output by the first high-resistance time detection circuit 301, the first current amplifier circuit 42 is used to amplify the reference current according to the first level trigger signal EN_DUMMY1 and the random code, and output the first amplified current. At this time, the second current amplifier circuit 43 is not working, so the output second amplified current is zero, and the third current amplifier circuit 44 is equivalent to only amplifying the first amplified current output by the first current amplifier circuit 42 again to obtain a random load current.

[0103] In another application scenario, since the high-resistance time threshold detected by the second high-resistance time detection circuit 302 is greater than the high-resistance time threshold corresponding to the first high-resistance time detection circuit 301, when it is detected that the second high-resistance time detection circuit 302 outputs the second level trigger signal EN_DUMMY2, it indicates that the first high-resistance time detection circuit 301 has output the first level trigger signal EN_DUMMY1. At this time, the first current amplifier circuit 42 and the second current amplifier circuit 43 work simultaneously. After receiving the first level trigger signal EN_DUMMY1 output by the first high-resistance time detection circuit 301, the first current amplifier circuit 42 is used to amplify the reference current according to the first level trigger signal EN_DUMMY1 and the random code, and output the first amplified current. At the same time, the second current amplifier circuit 43 amplifies the reference current according to the second level trigger signal EN_DUMMY2 and the preset amplification factor, and outputs the second amplified current; the third current amplifier circuit 44 is used to amplify the current after the first amplified current and the second amplified current merge again, and output the random load current. It can be seen that when the second current amplifier circuit 43 is triggered to work, the output random load current will increase.

[0104] Specifically, in this embodiment, the second high-resistance time threshold HZ2 corresponding to the second high-resistance time detection circuit 302 can be set to twice the first high-resistance time threshold HZ1. That is, the time length for the capacitance value of the energy storage capacitor in the second high-resistance time detection circuit 302 to be fully charged is twice that of the first high-resistance time detection circuit 301.

[0105] Please continue to see Figure 4 As shown, the reference current generating circuit 41 of the present embodiment includes a 28th transistor Q28, the first electrode and the control electrode of the 28th transistor Q28 are short-circuited, the first electrode and the control electrode of the 28th transistor Q28 are used to receive the fourth bias current IBIA4, and the second electrode of the 28th transistor Q28 is used to receive the power supply voltage VDD. When the 28th transistor Q28 is turned on under the action of the fourth bias current IBIA4, the reference current flows through it.

[0106] In this embodiment, the 28th transistor Q28 adopts a PMOS (P-Metal-Oxide-Semiconductor) tube. In other embodiments, the 28th transistor Q28 can also adopt an NMOS (N-Metal-Oxide-Semiconductor) tube. For example, in this embodiment, when the 28th transistor Q28 adopts a PMOS tube, its first electrode is a drain electrode, its second electrode is a source electrode, and the control electrode is a gate electrode.

[0107] Please continue to see Figure 4 As shown, the first current amplifier circuit 42 of this embodiment includes a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twentieth transistor Q20, a twenty-first transistor Q21, a twenty-second transistor Q22 and a twenty-third transistor Q23. Among them, the control electrode of the fourteenth transistor Q14 is connected to the output end of the first high-impedance time detection circuit 301, and is used to receive the first level trigger signal EN_DUMMY1. The first electrode of the fourteenth transistor Q14 is used to output the first amplified current; the second electrode of the fourteenth transistor Q14 is respectively connected to the first electrodes of the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17 and the eighteenth transistor Q18, and the second electrodes of the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17 and the eighteenth transistor Q18 are respectively connected to the first electrodes of the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21 and the twenty-second transistor Q22, and the second electrodes of the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21 and the twenty-second transistor Q22 are all used to receive the power supply voltage VDD. The control electrodes of the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17 and the eighteenth transistor Q18 are all connected to the output end of the random code generating circuit 303; the control electrodes of the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, the twenty-second transistor Q22 and the twenty-third transistor Q23 are all connected to the control electrode of the twenty-eighth transistor Q28.

[0108] In this embodiment, the fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, the eighteenth transistor Q18, the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, the twenty-second transistor Q22 and the twenty-third transistor Q23 are all PMOS (P-Metal-Oxide-Semiconductor) tubes. In other embodiments, the fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, the eighteenth transistor Q18, the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, the twenty-second transistor Q22 and the twenty-third transistor Q23 may also be NMOS (N-Metal-Oxide-Semiconductor) tubes. For example, in this embodiment, when the fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, the eighteenth transistor Q18, the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, the twenty-second transistor Q22 and the twenty-third transistor Q23 are PMOS tubes, their first pole is the drain, their second pole is the source, and their control pole is the gate.

[0109] In this embodiment, the size ratio of the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, and the twenty-second transistor Q22 is 1:2:4:8. It can be understood that the branches where the nineteenth transistor Q19, the twentieth transistor Q20, the twenty-first transistor Q21, and the twenty-second transistor Q22 are located can respectively amplify the reference current by one time, two times, four times, and eight times. Among them, the size of the twenty-third transistor Q23 can also be set to 2 to 4 times that of the twenty-eighth transistor Q28, that is, the twenty-third transistor Q23 can also amplify the reference current by 2 to 4 times, and the amplified currents merge into the first amplified current and then flow through the fourteenth transistor Q14.

[0110] In this embodiment, the random code generating circuit 303 randomly generates a set of four-bit binary random codes at a high level, and the random code determines the amplification factor of the first current amplifier circuit 42. For example, the random code generated by the random code generating circuit 303 is 1000, and the random code can be expressed as S4S3S2S1. When the random code is 1000, it means that S4 is 1, S1, S2 and S3 are all 0, and the eighteenth transistor Q18 is turned on, so that the twenty-second transistor Q22 amplifies the reference current by 8 times.

[0111] In some embodiments, the first current amplifying circuit 42 also includes a second inverter INV1, the input end of the second inverter INV1 is used to receive a first level trigger signal EN_DUMMY1, and the output end of the second inverter INV1 is connected to the gate of the fourteenth transistor Q14. When the first level trigger signal EN_DUMMY1 is a high level, it is converted to a low level through the second inverter INV1 to trigger the fourteenth transistor Q14 to turn on, thereby outputting the amplified first amplified current.

[0112] Please continue to see Figure 4 As shown, the second current amplifying circuit 43 of this embodiment includes a twenty-fourth transistor Q24 and a twenty-fifth transistor Q25; the control electrode of the twenty-fourth transistor Q24 is connected to the output end of the second high-impedance time detection circuit 302, for receiving the second level trigger signal EN_DUMMY2, the first electrode of the twenty-fourth transistor Q24 is connected to the first electrode of the fourteenth transistor Q14, and the first electrode of the twenty-fourth transistor Q24 is used to output the second amplified current; the second electrode of the twenty-fourth transistor Q24 is connected to the first electrode of the twenty-fifth transistor Q25, the second electrode of the twenty-fifth transistor Q25 is used to receive the power supply voltage VDD, and the control electrode of the twenty-fifth transistor Q25 is connected to the control electrode of the twenty-eighth transistor Q28.

[0113] The size of the twenty-fifth transistor Q25 may also be set to be 2 to 4 times that of the twenty-eighth transistor Q28, that is, the twenty-fifth transistor Q25 may also amplify the reference current by 2 to 4 times to obtain the second amplified current.

[0114] The twenty-fourth transistor Q24 and the twenty-fifth transistor Q25 in the second current amplifier circuit 43 of this embodiment are both PMOS (P-Metal-Oxide-Semiconductor) tubes, whose first electrode is a drain, whose second electrode is a source, and whose control electrode is a gate.

[0115] In some embodiments, the second current amplifying circuit 43 also includes a third inverter INV2, the input end of the third inverter INV2 is used to receive the second level trigger signal EN_DUMMY2, and the output end of the third inverter INV2 is connected to the gate of the twenty-fourth transistor Q24. When the second level trigger signal EN_DUMMY2 is a high level, it is converted to a low level through the third inverter INV2 to trigger the twenty-fourth transistor Q24 to turn on, thereby outputting the amplified second amplified current.

[0116] Please continue to see Figure 4As shown, the third current amplifier circuit 44 includes a twenty-sixth transistor Q26, a twenty-seventh transistor Q27, a second resistor R2, and a third resistor R3; the first electrode and the control electrode of the twenty-sixth transistor Q26 are both connected to the first electrode of the fourteenth transistor Q14, the control electrode of the twenty-sixth transistor Q26 is connected to the control electrode of the twenty-seventh transistor Q27, and the first electrode of the twenty-seventh transistor Q27 is grounded GND. The second electrode of the twenty-sixth transistor Q26 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second electrode of the twenty-seventh transistor Q27, and the first electrode of the twenty-seventh transistor Q27 is the output end of the third current amplifier circuit 44, which is used to output a random load current.

[0117] The first amplified current flowing from the fourteenth transistor Q14 and the second amplified current flowing from the twenty-fourth transistor Q24 both pass through the twenty-sixth transistor Q26 .

[0118] In this embodiment, the twenty-sixth transistor Q26 and the twenty-seventh transistor Q27 are both NMOS transistors, whose first pole is the drain, whose second pole is the source, and whose control pole is the gate; in other embodiments, the twenty-sixth transistor Q26 and the twenty-seventh transistor Q27 can also be PMOS transistors.

[0119] The size of the twenty-seventh transistor Q27 is much larger than that of the twenty-sixth transistor Q26, and the resistance of the third resistor R3 is much smaller than the resistance of the second resistor R2, so that the twenty-seventh transistor Q27 can mirror-amplify the current flowing through the twenty-sixth transistor Q26. Generally, the current flowing through the twenty-sixth transistor Q26 is at the uA level, and after being mirror-amplified by the twenty-seventh transistor Q27, the current flowing through the twenty-seventh transistor Q27 is at the mA level.

[0120] Generally, the high-resistance time in the converter circuit is approximately equal to the switching period. When the load current is low, the high-resistance time is much longer than the conduction time of the high-side transistor NM1 and the low-side transistor NM2. Therefore, it can be approximately considered that the high-resistance time is approximately equal to the switching period.

[0121] According to the load current generating circuit provided by the present embodiment, when the high impedance time of the converter is less than the first high impedance time threshold HZ1, the first level trigger signal EN_DUMMY1 and the second level trigger signal EN_DUMMY2 are both low level, the fourteenth transistor Q14 and the twenty-fourth transistor Q24 are both turned off, and at this time, there is no current output on the twenty-sixth transistor Q26 and the twenty-seventh transistor Q27, that is, no random load flows through the output. When it is detected that the high impedance time is greater than the first high impedance time threshold HZ1 and less than the second high impedance time threshold HZ2, the first level trigger signal EN_DUMMY1 flips to a high level to enable the fourteenth transistor Q14 to turn on, and a current with a random proportion to the fourth bias current IBIA4 will flow through the twenty-sixth transistor Q26, and the twenty-seventh transistor Q27 will amplify the current of the twenty-sixth transistor Q26 and flow into the output terminal VOUT of the converter. Since the converter of the present embodiment is a buck-boost converter as an example, its output voltage is a negative level, so the current direction is to flow from the ground potential into VOUT.

[0122] When it is detected that the high-impedance time is greater than the second high-impedance time threshold HZ2, the second level trigger signal EN_DUMMY2 flips to a high level, the twenty-fourth transistor Q24 will be turned on, and a fixed bias current will be added to the twenty-sixth transistor Q26, that is, the dummy load will add a second amplified current to the previously randomly changing current. Since the switching cycle and the load current are negatively correlated in the DCM mode, after the second amplified current is added, the switching cycle will be reduced, and the probability that the high-impedance time in the next switching cycle falls back to the interval between the first high-impedance time threshold HZ1 and the second high-impedance time threshold HZ2 will be greater. After falling back to this interval, the second level trigger signal EN_DUMMY2 will control the twenty-fourth transistor Q24 to turn off, thereby reducing one amplified current. This can further increase the randomness of the switching frequency in the DCM mode, avoid the switching frequency being fixed in a sensitive frequency domain, and thus ensure the stability of the converter circuit.

[0123] Figure 5 For a schematic diagram of the converter circuit structure provided in the embodiment of the present application, please refer to Figure 5 As shown, the converter circuit includes a high-side transistor NM1, a low-side transistor NM2, a first inductor L0, a first capacitor C1, a high-side transistor driving circuit HDRV, a low-side transistor driving circuit HDRV and a control circuit 21. At the same time, the converter circuit also includes a load current generating circuit 300 as provided in the above embodiment. The output terminal GND of the load current generating circuit 300 is connected to the ground terminal PGND in the converter circuit to output the load current to the converter circuit.

[0124] From the above analysis, it can be seen that the converter circuit of this embodiment adds the load current generating circuit 300, so that the load current can change randomly, avoiding the switching frequency of the converter from being fixed in a certain sensitive frequency domain, thereby ensuring the stability of the converter circuit operation.

[0125] The embodiment of the present application further provides a chip, which includes the high-impedance time detection circuit 100 provided in the above embodiments; or the chip includes the load current generation circuit 300 provided in the above embodiments. It can be understood that the chip in this embodiment has the same technical effects as the above high-impedance time detection circuit 100 or the load current generation circuit 300, which will not be described in detail here.

[0126] The embodiment of the present application also provides an electronic device, which includes a converter circuit; or the electronic device includes a load current generating circuit 300 as provided in the above embodiments. It can be understood that the electronic device in this embodiment has the same technical effects as the above high-impedance time detection circuit 100 or the load current generating circuit 300, which will not be described in detail here.

[0127] The electronic device in this embodiment may be a power adapter, a smart phone, a tablet computer, a laptop computer, or other electronic device.

[0128] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A high-resistance time detection circuit, used to detect the high-resistance time of a converter circuit when it is working, characterized in that: The high-resistance time detection circuit comprises: a current generating circuit, a capacitor charging circuit, an output control circuit and a shaping circuit; The current generating circuit is used to generate a first current signal and output the first current signal to the capacitor charging circuit; The capacitor charging circuit is used to receive a first enable signal when the converter circuit enters a high-impedance state, control the first current signal to charge the energy storage capacitor according to the first enable signal, and output a first trigger signal when charging is completed; The output control circuit is used to receive a second enable signal when the converter circuit enters a high-impedance state, and output a first flag signal under the triggering of the second enable signal and the first trigger signal; The shaping circuit is used to perform shaping processing on the first flag signal to output a corresponding level trigger signal, and the level trigger signal is used to indicate that the duration of the high-impedance state of the converter circuit reaches a corresponding high-impedance time threshold.

2. The high-impedance time detection circuit according to claim 1, characterized in that: The current generating circuit includes a first transistor, a second transistor and a first resistor; The first electrode of the first transistor is connected to the control electrode of the second transistor, and the first electrode of the first transistor and the control electrode of the second transistor are both used to receive a first bias current; the control electrode of the first transistor is connected to the second electrode of the second transistor and the first end of the first resistor; the second electrode of the first transistor and the second end of the first resistor are both grounded; the first electrode of the second transistor is connected to the capacitor charging circuit.

3. The high-impedance time detection circuit according to claim 2, characterized in that: The capacitor charging circuit includes a third transistor, a fourth transistor, a fifth transistor, an energy storage capacitor and a NAND gate; The control electrode of the third transistor, the first electrode of the third transistor and the control electrode of the fourth transistor are all connected to the first electrode of the second transistor, the second electrode of the third transistor is connected to the second electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both used to receive a power supply voltage; The first electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the first electrode of the fifth transistor is connected to the first end of the energy storage capacitor, and the second end of the energy storage capacitor is grounded; the larger the capacitance value of the energy storage capacitor, the longer the corresponding high impedance time; The input end of the NAND gate is used to receive the high-impedance state detection signal and the first enable signal respectively, and the output end of the NAND gate is connected to the control electrode of the fifth transistor.

4. The high-resistance time detection circuit according to claim 3, characterized in that: The output control circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The second electrode of the sixth transistor is used to receive a second bias current, the control electrode of the sixth transistor is connected to the output end of the NAND gate, the first electrode of the sixth transistor is connected to the second electrode of the seventh transistor; the first electrode of the seventh transistor is connected to the first electrodes of the eighth transistor and the tenth transistor, and the second electrodes of the eighth transistor and the tenth transistor are both grounded; The control electrode of the seventh transistor, the control electrode of the eighth transistor and the first electrode of the ninth transistor are all connected to the first electrode of the fifth transistor, the second electrode of the ninth transistor is grounded, and the control electrode of the ninth transistor and the control electrode of the tenth transistor are both used to receive the second enable signal; The first enable signal and the second enable signal have opposite logic states.

5. The high-resistance time detection circuit according to claim 4, characterized in that: The shaping circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a Schmitt inverter and a first inverter; The second electrode of the eleventh transistor is used to receive a third bias current, the control electrode of the eleventh transistor is connected to the output end of the NAND gate, the first electrode of the eleventh transistor is respectively connected to the first electrode of the twelfth transistor, the first electrode of the thirteenth transistor and the input end of the Schmidt inverter, and the second electrode of the twelfth transistor and the second electrode of the thirteenth transistor are both grounded; The control electrode of the twelfth transistor is connected to the first electrode of the eighth transistor; the control electrode of the thirteenth transistor is used to receive the second enable signal; The output end of the Schmitt inverter is connected to the input end of the first inverter, and the output end of the first inverter is used to output the level trigger signal.

6. A load current generating circuit, used in a converter circuit, characterized in that: The load current generating circuit comprises a first high-resistance time detection circuit, a second high-resistance time detection circuit, a random code generating circuit and a dummy load circuit; the first high-resistance time detection circuit and the second high-resistance time detection circuit are the high-resistance time detection circuits according to any one of claims 1 to 5, and the capacitance value of the energy storage capacitor in the second high-resistance time detection circuit is greater than the capacitance value of the energy storage capacitor in the first high-resistance time detection circuit; The first high-resistance time detection circuit is used to output a first level trigger signal when detecting that the high-resistance time of the converter circuit reaches a first high-resistance time threshold; The second high-resistance time detection circuit is used to output a second level trigger signal when detecting that the high-resistance time of the converter circuit reaches a second high-resistance time threshold; The second high-resistance time threshold is greater than the first high-resistance time threshold; The random code generating circuit is used to receive a clock signal and randomly generate a random code according to the clock signal; The dummy load circuit is used to amplify the reference current according to the random code to obtain a random load current under the triggering of the first level trigger signal and / or the second level trigger signal.

7. The load current generating circuit according to claim 6, characterized in that: The dummy load circuit includes a reference current generating circuit, a first current amplifying circuit, a second current amplifying circuit and a third current amplifying circuit; The reference current generating circuit is used to generate the reference current; The first current amplifying circuit is used to amplify the reference current according to the first level trigger signal and the random code, and output a first amplified current; The second current amplifying circuit is used to amplify the reference current according to the second level trigger signal and a preset amplification factor, and output a second amplified current; The third current amplifier circuit is used to amplify the current after the first amplified current and the second amplified current merge, and output the random load current.

8. The load current generating circuit according to claim 7, characterized in that: The reference current generating circuit includes a twenty-eighth transistor, a first electrode and a control electrode of the twenty-eighth transistor are short-circuited, the first electrode and the control electrode of the twenty-eighth transistor are used to receive a fourth bias current, and a second electrode of the twenty-eighth transistor is used to receive a power supply voltage.

9. The load current generating circuit according to claim 8, characterized in that: The first current amplifying circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; The control electrode of the fourteenth transistor is connected to the output end of the first high-resistance time detection circuit for receiving the first level trigger signal, and the first electrode of the fourteenth transistor is used to output the first amplified current; the second electrode of the fourteenth transistor is respectively connected to the first electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor, and the second electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor are respectively connected to the first electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor, and the second electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor are all used to receive the power supply voltage; The control electrodes of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor are all connected to the output end of the random code generating circuit; the control electrodes of the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-third transistor are all connected to the control electrode of the twenty-eighth transistor.

10. The load current generating circuit according to claim 9, characterized in that: The size ratio of the nineteenth transistor, the twentieth transistor, the twenty-first transistor and the twenty-second transistor is 1:2:4:

8.

11. The load current generating circuit according to claim 8 or 9, characterized in that: The second current amplifying circuit includes a twenty-fourth transistor and a twenty-fifth transistor; The control electrode of the twenty-fourth transistor is connected to the output end of the second high-impedance time detection circuit for receiving the second level trigger signal, the first electrode of the twenty-fourth transistor is connected to the first electrode of the fourteenth transistor, and the first electrode of the twenty-fourth transistor is used to output the second amplified current; The second electrode of the 24th transistor is connected to the first electrode of the 25th transistor, the second electrode of the 25th transistor is used to receive the power supply voltage, and the control electrode of the 25th transistor is connected to the control electrode of the 28th transistor.

12. The load current generating circuit according to claim 9, characterized in that: The third current amplifying circuit includes a twenty-sixth transistor, a twenty-seventh transistor, a second resistor and a third resistor; The first electrode and the control electrode of the twenty-sixth transistor are both connected to the first electrode of the fourteenth transistor, the control electrode of the twenty-sixth transistor is connected to the control electrode of the twenty-seventh transistor, and the first electrode of the twenty-seventh transistor is grounded; The second electrode of the twenty-sixth transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the second electrode of the twenty-seventh transistor, and the first electrode of the twenty-seventh transistor is the output end of the third current amplifying circuit, used to output the random load current.

13. A converter circuit, characterized in that: The converter circuit includes the high-impedance time detection circuit as described in any one of claims 1-5; or the converter circuit includes the load current generation circuit as described in any one of claims 6-12.

14. A chip, characterized in that: The chip includes the high-impedance time detection circuit as described in any one of claims 1-5; or the chip includes the load current generation circuit as described in any one of claims 6-12.

15. An electronic device, characterized in that: The electronic device comprises the high-impedance time detection circuit as described in any one of claims 1-5; or the electronic device comprises the load current generating circuit as described in any one of claims 6-12.

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