Defect detection method and device for electronic control part of new energy automobile

Abstract

The invention discloses a flaw detection method and device for an electric control component of a new energy automobile, and the method comprises the steps: applying an AC signal in a range of 100kHz-10MHz to the electric control component, and obtaining the impedance response characteristics of each parasitic coupling region of a power device through a differential detection mode; performing multi-port network analysis on the impedance response characteristics, and extracting a distributed capacitance value of each parasitic coupling region; performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics in the switching process; calculating a capacitance deviation value according to the parasitic characteristics, and determining a defect area and the type thereof; and verifying the stability of the flaw area and the type thereof under the conditions of temperature cycle and vibration stress to obtain a reliability evaluation result. According to the technical scheme of the invention, accurate identification and reliability evaluation can be carried out on tiny flaws caused by abnormal stray capacitance in the electric control part of the new energy automobile.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection of electric control components of new energy vehicles, and in particular to a defect detection method and device for electric control components of new energy vehicles. Background Art

[0002] The electronic control components of new energy vehicles are key components of the vehicle power system, mainly including power semiconductor devices and their drive circuits. The power devices are responsible for the energy conversion of the high-voltage DC bus, and control the switch state through the gate drive signal to achieve variable speed and voltage regulation of the motor. In order to improve the system power density and reduce switching losses, the operating frequency of modern electronic control components is constantly increasing, especially after the use of new semiconductor materials such as silicon carbide, the switching frequency has reached the range of 100kHz-10MHz.

[0003] As the operating frequency increases, the problems caused by parasitic parameters in electronic control components are becoming increasingly prominent. In particular, parasitic capacitance inside power devices, including gate-source, drain-source, and Miller capacitance, can cause abnormal phenomena such as parasitic oscillation and increased switching loss under high-frequency working conditions. These anomalies often originate from tiny defects inside the device, such as gate oxide defects, PN junction breakdown, etc. Traditional static parameter testing methods are difficult to detect such defects, and conventional dynamic testing cannot accurately locate the fault location. Therefore, there is an urgent need for a method that can accurately detect and evaluate the abnormal parasitic capacitance inside electronic control components under high-frequency working conditions to ensure the reliable operation of new energy vehicles. Summary of the invention

[0004] The main purpose of the present invention is to solve the technical problem of how to accurately identify tiny defects caused by abnormal parasitic capacitance inside the device and evaluate its reliability when the electronic control components of new energy vehicles work in a high-frequency state.

[0005] A first aspect of the present invention provides a method for detecting defects in an electric control component of a new energy vehicle, the method comprising: Apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and use a differential detection method to obtain the impedance response characteristics of each parasitic coupling area of ​​the power device; Performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area; Performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; Calculating capacitance deviation according to the parasitic characteristics, and determining defect areas and types thereof; The stability of the defect area and its type is verified under temperature cycling and vibration stress conditions to obtain reliability evaluation results.

[0006] Optionally, applying an AC signal in the range of 100kHz-10MHz to the electric control component and obtaining the impedance response characteristics of each parasitic coupling region of the power device by a differential detection method includes: A high-frequency response probe is arranged at a first parasitic coupling surface between the gate and source of the power device and a second parasitic coupling surface between the drain and source as a reference detection end; A differential probe is arranged on the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power loop as a differential detection terminal; Applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end, and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device; The high frequency response data of the reference detection end and the differential detection end are collected, and the impedance response characteristics of each parasitic coupling region are calculated.

[0007] Optionally, applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end, and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device, includes: The gate drive voltage when the power device is turned on is used as the reference, and the initial amplitude of the AC scanning signal is set to 30% of it; Applying a scanning signal with an initial frequency of 100 kHz to the reference detection end, and recording a gate opening threshold point of a power device; Dynamically calculate the signal application time of the next frequency point according to the response time of the gate opening threshold point; The signal application time is compensated according to a 50kHz step amount to eliminate the phase delay caused by the parasitic loop; After compensation, the signal frequency is gradually increased to 10MHz to maintain the trigger synchronization of each frequency point.

[0008] Optionally, collecting high frequency response data of the reference detection end and the differential detection end and calculating impedance response characteristics of each parasitic coupling region includes: Performing amplitude normalization processing on the high frequency response data of the reference detection end to obtain a reference response sequence; Calibrate the high frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence; Calculating the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase characteristic; Compensating the high frequency response data according to the coupling phase characteristics to obtain an actual impedance value; The actual impedance value is mapped according to the physical position of the parasitic coupling region to obtain an impedance response characteristic.

[0009] Optionally, performing a multi-port network analysis on the impedance response characteristics to extract a distributed capacitance value of each parasitic coupling region includes: Performing fast Fourier transform on the impedance response characteristics in the gate drive circuit and the power main circuit respectively to obtain dual-circuit amplitude-frequency characteristics; The dual-loop amplitude-frequency characteristics are used to establish interconnection network equations according to three sets of coupling relationships between gate-source, drain-source and gate-drain, and the transmission function of each coupling region is obtained; Performing odd-even mode separation on the transmission function to obtain common-mode and differential-mode impedance components; Reconstructing the common-mode and differential-mode impedance components within a fixed time window of the Miller platform to obtain equivalent parameters of each coupling region; The equivalent parameters are corrected and compensated according to the actual switching frequency point to obtain the distributed capacitance value of each parasitic coupling area.

[0010] Optionally, performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process includes: The distributed capacitance value is segmented in time sequence according to the turn-on phase, Miller platform phase and turn-off phase of the power device to obtain three characteristic sequences; Calculating the voltage change rate of the characteristic sequences in the on-phase and the off-phase to obtain the switch stress characteristics; Performing parasitic oscillation analysis on the characteristic sequence of the Miller platform phase to obtain the oscillation characteristics of the platform phase; Based on the voltage reversal point of the switching cycle, the switch stress characteristics and the plateau oscillation characteristics are synchronously marked to obtain the timing characteristics of the parasitic parameters; The timing characteristics are reconstructed under different switching rate conditions to obtain parasitic characteristics during the switching process.

[0011] Optionally, performing parasitic oscillation analysis on the characteristic sequence of the Miller platform phase to obtain the platform phase oscillation characteristics includes: Identify the boundary of the gate voltage plateau period of the characteristic sequence to obtain the start and end time of the Miller platform; Extracting peak and valley values ​​of the oscillation waveform of the drain voltage within the start and end times to obtain an oscillation amplitude sequence; Calculating the attenuation coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation; Correlating the damping characteristic with the rate of change of the drain current to obtain a triggering characteristic of the parasitic oscillation; An oscillation energy distribution diagram is established according to the trigger characteristics and attenuation law to obtain the plateau oscillation characteristics.

[0012] Optionally, calculating the capacitance deviation according to the parasitic characteristics and determining the defective area and its type includes: Comparing the parasitic parameters of the gate-source region in the parasitic characteristics with a reference value to obtain a first deviation; Comparing the parasitic parameters of the drain-source region in the parasitic characteristics with the reference value to obtain a second deviation; Locate the points where the first deviation and the second deviation exceed the threshold value according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area; Matching the physical coordinates of the abnormal area with the PN junction distribution map of the power device to obtain the defect type; The difference between the parasitic parameters of the area corresponding to the defect type and the standard threshold is calculated to obtain the capacitance deviation.

[0013] Optionally, verifying the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result includes: During the temperature cycle, the impedance characteristics of the defect area are scanned at four temperature points: -40°C, 25°C, 85°C and 125°C, and the temperature stress response curve is obtained; During the vibration process, parameters are measured at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz as required by automotive electronic standards to obtain the vibration stress response curve; Extract parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain the temperature stress influencing factor; The vibration stress response curve is re-measured at the defect position in three states: on, Miller platform and off, to obtain the vibration stress influencing factor; According to the acceleration effect of the temperature stress influencing factor and the vibration stress influencing factor on the defect parameters, a reliability evaluation result is obtained.

[0014] A second aspect of the present invention provides a defect detection device for electric control components of new energy vehicles, comprising: The signal injection module is used to apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and obtain the impedance response characteristics of each parasitic coupling area of ​​the power device by differential detection; A network analysis module, used to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance value of each parasitic coupling area; A time-frequency processing module, used to perform time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; A defect recognition module, used to calculate the capacitance deviation according to the parasitic characteristics, and determine the defect area and its type; The reliability evaluation module is used to verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

[0015] The defect detection method of the electric control component of a new energy vehicle provided by the present invention realizes the high-precision acquisition of the impedance characteristics of each parasitic coupling area of ​​the power device by adopting the differential detection method. In particular, the detection end is set at the key coupling surfaces such as the gate source and the drain source, and the frequency domain characteristics of the parasitic parameters can be fully captured in combination with the broadband scanning signal of 100kHz-10MHz. Furthermore, through the multi-port network analysis technology, the complex impedance characteristics are successfully decomposed into distributed capacitance values, laying a data foundation for subsequent defect identification. In the time-frequency feature analysis link, the switching process of the power device is divided into three stages: conduction, Miller platform and shutdown, and the parasitic characteristics are extracted respectively, making the defect detection more targeted. At the same time, the present invention establishes a defect positioning method based on the capacitance deviation, combined with temperature cycle and vibration stress verification, which can not only accurately identify the defect location and type, but also evaluate its stability under the actual working environment. This multi-dimensional detection and evaluation scheme effectively solves the problem of accurate detection of parasitic capacitance anomalies under high-frequency working conditions, and provides technical support for the reliability guarantee of electric control components of new energy vehicles. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of an embodiment of a method for detecting defects in an electric control component of a new energy vehicle according to an embodiment of the present invention; Figure 2 It is a schematic diagram of an embodiment of a defect detection device for electric control components of a new energy vehicle in an embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, "and / or" in the full text includes three solutions. Taking A and / or B as an example, it includes technical solution A, technical solution B, and technical solution that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, which must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] An embodiment of the present application provides a method for detecting defects in electronic control components of a new energy vehicle. Figure 1 A flow chart of a defect detection method for electric control components of new energy vehicles provided in one embodiment of the present application. In this embodiment, the method includes: See also Figure 1 , applying an AC signal in the range of 100kHz-10MHz to the electronic control component, and using a differential detection method to obtain the impedance response characteristics of each parasitic coupling area of ​​the power device; In one embodiment of the present invention, an AC signal in the range of 100kHz-10MHz is applied to the electric control component, and the impedance response characteristics of each parasitic coupling area of ​​the power device are obtained by differential detection, including: setting a high-frequency response probe at a first parasitic coupling surface between the gate and source and a second parasitic coupling surface between the drain and source of the power device as a reference detection end; setting a differential probe at the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power circuit as a differential detection end; applying an AC scanning signal with an initial frequency of 100kHz to the reference detection end, and according to the switching frequency characteristics of the power device, gradually increasing the excitation frequency to 10MHz in steps of 50kHz; collecting high-frequency response data of the reference detection end and the differential detection end, and calculating the impedance response characteristics of each parasitic coupling area.

[0023] Specifically, in the process of defect detection of electronic control components of new energy vehicles, it is first necessary to understand the structural characteristics of the detection object. The core component of the electronic control component is the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), which is a power switching device used for power conversion, responsible for converting the DC bus voltage (usually 400 volts to 800 volts) into the AC voltage required to drive the motor. MOSFET is mainly composed of three electrodes: gate, source and drain. The switching function is achieved by applying voltage to the gate to control the conduction or shutdown between the source and drain. In the application of new energy vehicles, in order to improve the energy conversion efficiency, more and more silicon carbide MOSFETs are used. The switching frequency of this device can reach hundreds of kilohertz, but it also brings the problem of aggravated parasitic parameter effects.

[0024] When performing defect detection, it is first necessary to set up detection probes at key locations of MOSFET. Specifically, high-frequency response probes are set as reference detection terminals at the first parasitic coupling plane between the gate and source (i.e., the overlapping area between the gate metal layer and the source metal layer of the power device chip, which will form a tiny capacitor with a typical value of a few nanofarads, which directly affects the switching speed of the device) and the second parasitic coupling plane between the drain and source (i.e., the overlapping area between the drain metal layer and the source metal layer of the chip, the parasitic capacitance of this area is usually between a few hundred picofarads and a few nanofarads, which will affect the turn-off characteristics of the device). Taking a silicon carbide MOSFET with a rated voltage of 1200V as an example, the high-frequency response probe set between its gate and source adopts a metal microstrip line structure (width 0.2 mm, thickness 35 microns), and the probe is 0.5 mm away from the chip surface. The microstrip line structure is selected because it has good high-frequency transmission characteristics and can accurately control its characteristic impedance (usually designed to be 50 ohms, matching the test system). The bandwidth of the probe needs to reach above 50MHz (-3dB bandwidth point) to ensure that the high-frequency response characteristics can be accurately captured.

[0025] At the same time, a differential probe is set as a differential detection terminal on the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power loop. The Miller platform area here refers to a special time period in the MOSFET switching process: when the device switches from the off state to the on state, due to the rapid drop of the drain voltage (typical value is 50 volts per microsecond), the gate voltage will remain constant at a certain voltage value (usually 2-3 times the device threshold voltage) through the coupling effect of the Miller capacitance (parasitic capacitance between the gate and the drain), and this platform period usually lasts 1-2 microseconds. The power loop refers to the current path formed from the positive pole of the power supply through the MOSFET to the negative pole of the power supply. The wiring parasitic inductance in this loop (typical value is 10-20 nanohenries) will resonate with the parasitic capacitance of the device to produce high-frequency oscillations.

[0026] The differential probe is arranged symmetrically, that is, a probe is placed on each side of the Miller area, and the distance between the two probes is kept within 10 mm to reduce the loss in the differential signal transmission process. For example, in the power loop, one differential probe is placed 5 mm from the power supply end, and the other is placed 5 mm from the ground end. The probe adopts a coaxial structure (inner conductor diameter 0.5 mm, outer shielding layer diameter 2 mm), and the outer shielding layer is grounded. The shielding effect reduces the external electromagnetic field interference by more than 40 decibels.

[0027] After the probe arrangement is completed, an AC scanning signal is applied to the reference detection end. The reason for selecting the initial frequency of 100kHz is that the impedance generated by the parasitic capacitance of the MOSFET (measured in 10 nanofarads) is about 160 ohms. This resistance value can ensure that the signal has sufficient strength for transmission, and will not cause the signal to short-circuit due to too low impedance. The scanning signal uses a sine wave with an amplitude set to 1 volt (this value is much lower than the gate threshold voltage of the device of 3-5 volts, so it will not trigger the device switching action), and is transmitted through a coaxial cable with a characteristic impedance of 50 ohms. The frequency is gradually increased in steps of 50kHz. The basis for selecting this step value is that the impedance change of adjacent frequency points does not exceed 5%, which not only ensures the measurement accuracy, but also keeps the entire scanning process within 1 minute.

[0028] The data acquisition uses a high-speed data acquisition system, whose core indicators include: sampling rate 100MHz, resolution 12 bits (can distinguish 0.025% signal changes), and dynamic range 70dB. The sampling rate is set to more than 10 times the signal frequency in order to accurately reconstruct the waveform and avoid spectrum aliasing. For example, the sampling rate is 100MHz at an excitation frequency of 10MHz, that is, 10 points are collected per signal cycle, and the complete response waveform can be reconstructed using an interpolation algorithm through these discrete points. The collected data is processed by a bandpass filter (the passband range is ±10% of the excitation frequency), and after filtering out power frequency interference and high-frequency noise, it is used to calculate the impedance response characteristics of each parasitic coupling area. Finally, the common mode noise is eliminated through differential processing (that is, the data at the differential detection end is subtracted from the data at the reference detection end) to obtain accurate impedance characteristics. This method can increase the signal-to-noise ratio by more than 20dB, which is equivalent to increasing the measurement accuracy by 10 times.

[0029] In one embodiment of the present invention, an AC scanning signal with an initial frequency of 100kHz is applied to the reference detection end, and the excitation frequency is gradually increased to 10MHz in steps of 50kHz according to the switching frequency characteristics of the power device, including: taking the gate drive voltage when the power device is turned on as a reference, and setting the initial amplitude of the AC scanning signal to 30% of it; applying a scanning signal with an initial frequency of 100kHz to the reference detection end, and recording the gate opening threshold point of the power device; dynamically calculating the signal application time of the next frequency point according to the response time of the gate opening threshold point; compensating the signal application time in steps of 50kHz to eliminate the phase delay caused by the parasitic loop; and gradually increasing the signal frequency to 10MHz at the moment after compensation to maintain the trigger synchronization of each frequency point.

[0030] Specifically, in order to achieve accurate detection of MOSFET devices, it is first necessary to determine the appropriate excitation signal amplitude. In the normal operation of MOSFET, the gate drive voltage (usually 12 volts or 15 volts) is a key parameter to ensure reliable conduction of the device. This drive voltage needs to be sufficiently greater than the gate threshold voltage (for silicon carbide MOSFET, the typical value is 2.5-3.5 volts) to reduce conduction losses. When performing defect detection, 30% of the gate drive voltage at turn-on is selected as the initial amplitude of the AC scan signal. For example, if the drive voltage is 15 volts, the scan signal amplitude is set to 4.5 volts. The reason for selecting this ratio is that the amplitude is large enough to ensure the signal-to-noise ratio of signal detection (usually greater than 40 decibels), and will not cause the device to turn on accidentally (because after the scan signal is superimposed on the gate-source bias voltage, the total voltage is still lower than the turn-on threshold).

[0031] After applying a scanning signal with an initial frequency of 100kHz to the reference detection end, it is necessary to record the gate turn-on threshold point of the power device. This threshold point refers to the moment when the gate voltage reaches the minimum voltage value required to turn on the device. For silicon carbide MOSFET, this value is usually around 3 volts. The recording method is to use a high-speed voltage probe (bandwidth not less than 500MHz) at the gate end, and the input capacitance of the probe must be less than 2 pico-farads to avoid affecting the measurement accuracy. At the same time, a reference voltage probe is set at the source end to obtain an accurate gate-source voltage through differential measurement. In actual operation, it can be observed that during the period when the gate-source voltage rises from 0 to the threshold voltage, the inflection point where the drain current begins to rise rapidly can be observed. The moment corresponding to this inflection point is the turn-on threshold point.

[0032] After obtaining the threshold point, the signal application time of the next frequency point is dynamically calculated based on its response time. The response time is defined as the time interval from applying the scanning signal to reaching the threshold point. This time reflects the impact of the device's parasitic parameters on signal transmission. For example, if the response time is measured to be 200 nanoseconds at 100kHz, then this delay needs to be considered when calculating the signal application time of 150kHz (the frequency point after increasing the 50kHz step). The specific calculation method is: divide the response time by the current frequency period to obtain the phase delay angle, which will be used for subsequent compensation.

[0033] In the process of adjusting the frequency in 50kHz steps, the signal application time needs to be compensated. This is because there is a resonant loop formed by parasitic inductance (mainly from leads and packages, with a typical value of several nanohenries) and parasitic capacitance in the power device, which will cause phase delay during signal transmission. The compensation method is: advance the signal application time according to the phase delay measured at the previous frequency point. Taking the 150kHz frequency point as an example, if the phase delay at 100kHz is measured to be 30 degrees, then when applying a 150kHz signal, the trigger time needs to be advanced by a time equivalent to 30 degrees of phase (i.e. 555.6 nanoseconds).

[0034] Finally, in the process of gradually increasing the frequency to 10MHz, the trigger synchronization of each frequency point needs to be maintained. This means that at each frequency point, the application time of the signal must maintain a fixed phase relationship with the switching cycle of the device. The implementation method is to use a phase-locked loop circuit to lock the phase of the scanning signal to the phase of the device gate drive signal. The bandwidth of the phase-locked loop is set to 1 / 10 of the scanning frequency, which can ensure phase tracking while avoiding interference with the measurement signal. Through this synchronization mechanism, it is ensured that the data obtained during the entire scanning process has time correlation, providing a reliable basis for subsequent parameter extraction.

[0035] In one embodiment of the present invention, the collecting of high-frequency response data of the reference detection end and the differential detection end and the calculating of the impedance response characteristics of each parasitic coupling region include: performing amplitude normalization processing on the high-frequency response data of the reference detection end to obtain a reference response sequence; calibrating the high-frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence; calculating the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase feature; compensating the high-frequency response data according to the coupling phase feature to obtain an actual impedance value; and mapping the actual impedance value according to the physical position of the parasitic coupling region to obtain an impedance response characteristic.

[0036] Specifically, in the process of obtaining the parasitic characteristics of power devices, the collected raw data needs to be processed. The first is to perform amplitude normalization on the high-frequency response data of the reference detection end. The data collected by the reference detection end contains the voltage and current information obtained from the two coupling surfaces between the gate-source and the drain-source. The amplitude range of these data may vary from a few millivolts to a few volts. The specific method of normalization is: divide the response amplitude of each frequency point by the amplitude of the excitation signal at that frequency. For example, when the excitation signal amplitude is 4.5 volts, if the response amplitude measured at a certain frequency point is 2.25 volts, the normalized value is 0.5. This processing eliminates the influence of the amplitude fluctuation of the excitation signal at different frequency points, making the data comparable.

[0037] When calibrating the data of the differential detection end, it is necessary to use the reference response sequence as a reference. The differential detection end is located at the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power circuit. The parasitic effects of these locations are more complicated. The calibration process must first consider the frequency response characteristics of the probe itself: in the frequency range of 100kHz to 10MHz, the gain and phase responses of the probe are not completely flat, and the calibration coefficient of the probe needs to be used for correction. For example, if the gain attenuation of the probe is -0.5 dB and the phase shift is -2 degrees at the 5MHz frequency point, the measured data needs to be compensated accordingly. The calibrated differential response sequence reflects the true parasitic characteristics of each coupling area.

[0038] The calculation of the phase difference between the reference response sequence and the differential response sequence is the key to identifying parasitic coupling effects. During the switching process of the MOSFET, due to the charging and discharging effects of the parasitic capacitance, the responses of different coupling regions will have phase differences. The calculation method is: first obtain the analytical signals of the two sequences through Hilbert transform, and then calculate their instantaneous phase difference. For example, during the Miller platform, if the phase of the reference sequence is 30 degrees and the phase of the differential sequence is 45 degrees, the phase difference is 15 degrees. This phase difference reflects the signal delay effect caused by the Miller capacitance. By analyzing the trend of the phase difference at different frequency points, the coupling phase feature can be obtained, which quantifies the dynamic impact of the parasitic parameters.

[0039] After obtaining the coupling phase characteristics, the high-frequency response data needs to be compensated to obtain the actual impedance value. The compensation process takes three aspects into consideration: first, the inductive reactance component caused by parasitic inductance (for example, for a parasitic inductance of 5 nanohenry, the inductive reactance at a frequency of 5MHz is 157 ohms), second, the capacitive reactance component caused by parasitic capacitance (for a parasitic capacitance of 10 nanofarads, the capacitive reactance at a frequency of 5MHz is 3.18 ohms), and finally, the on-resistance component (usually tens to hundreds of milliohms). These components are combined through complex operations to obtain the actual impedance value of each test point.

[0040] The last step is to map the actual impedance value to the physical structure of the device. The chip structure of MOSFET usually contains multiple units, each of which has a source region, a drain region, and a gate region. The mapping process requires establishing a correspondence between the test points and the physical location of the chip. For example, for a 10 square millimeter chip, a 10×10 grid coordinate system can be established to correspond the measured impedance value to a specific physical location. Through this mapping, the spatial distribution characteristics of parasitic parameters can be intuitively displayed. For example, in areas where the gate metal layer and the source metal layer overlap more, the parasitic capacitance value will be significantly larger. This distribution feature provides an important basis for subsequent defect detection, because abnormal impedance distribution often indicates potential quality problems.

[0041] Please continue reading Figure 1 , performing a multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area; In one embodiment of the present invention, the impedance response characteristics are subjected to multi-port network analysis to extract the distributed capacitance value of each parasitic coupling region, including: performing fast Fourier transform on the impedance response characteristics in the gate drive circuit and the power main circuit respectively to obtain the dual-circuit amplitude-frequency characteristics; establishing an interconnection network equation for the dual-circuit amplitude-frequency characteristics according to three sets of coupling relationships of gate-source, drain-source and gate-drain to obtain the transmission function of each coupling region; performing odd-even mode separation on the transmission function to obtain common-mode and differential-mode impedance components; reconstructing the common-mode and differential-mode impedance components within a fixed time window of a Miller platform to obtain equivalent parameters of each coupling region; and correcting and compensating the equivalent parameters according to the actual switching frequency points to obtain the distributed capacitance value of each parasitic coupling region.

[0042] Specifically, in the electric control components of new energy vehicles, the parasitic parameters of MOSFET are distributed in the gate drive circuit and the main power circuit. First, the acquired impedance response characteristics need to be processed by fast Fourier transform, which converts the time domain signal into the frequency domain. Among them, the gate drive circuit mainly includes the connection path from the gate drive chip to the MOSFET gate, and the measured voltage range is usually 0-20 volts; the main power circuit includes a large current path from the positive pole of the power supply through the MOSFET to the negative pole, and the measured voltage can reach hundreds of volts. A 2048-point FFT (fast Fourier transform) is used for the transformation, so that a frequency resolution of 0.5kHz can be obtained. For example, when the switching transient voltage of the gate drive circuit is 12 volts and the rise time is 100 nanoseconds, the main frequency component distribution can be obtained by FFT at around 3.5MHz.

[0043] When the obtained dual-loop amplitude-frequency characteristics are used to establish the interconnection network equation, three main coupling relationships need to be considered. The gate-source coupling is mainly determined by the gate oxide capacitance (typical value is 2-3 nanofarads); the drain-source coupling is affected by the junction capacitance (depletion layer capacitance, which varies with the drain-source voltage, with typical values ​​ranging from hundreds of picofarads to several nanofarads); and the gate-drain coupling (i.e. Miller capacitance) directly affects the switching characteristics. For example, in a certain model of 1200-volt silicon carbide MOSFET, when the drain-source voltage is 600 volts, the junction capacitance is about 200 picofarads and the Miller capacitance is about 50 picofarads. The interconnection network equation established based on these parameters adopts the Y parameter form, which can intuitively represent the admittance relationship between each port.

[0044] The purpose of performing odd-even mode separation on the transmission function is to distinguish between common-mode interference and differential-mode signals. During the MOSFET switching process, the common-mode signal mainly comes from the power supply ripple and ground noise, which is manifested as interference superimposed on each measurement point in the same phase; while the differential-mode signal reflects the actual switching characteristics. The separation method is: perform eigenvalue decomposition on the measured transfer function matrix, the larger eigenvalue corresponds to the differential-mode component (usually 10-20 decibels larger than the common-mode component), and the smaller eigenvalue corresponds to the common-mode component. Taking actual measurement as an example, if the transmission impedance measured at 5MHz is 100 ohms, after separation, 80 ohms of differential-mode impedance and 20 ohms of common-mode impedance may be obtained.

[0045] When reconstructing data during the Miller plateau, the time window selected is usually 1-2 microseconds. This is because during the Miller plateau, the drain voltage of the MOSFET changes rapidly (typically at a rate of 50 volts / microsecond), while the gate voltage remains relatively stable, and the parasitic parameter characteristics are most obvious at this time. The data reconstruction uses a sliding average method, and the window length is selected to be 1 / 10 of the switching period, which can effectively suppress high-frequency noise without losing effective information. For example, for a switching frequency of 100kHz, a time window of 1 microsecond is selected, and parameter calculations are performed every 0.1 microseconds.

[0046] Finally, when correcting and compensating the equivalent parameters, the characteristics of the actual switching frequency point need to be considered. The junction capacitance and Miller capacitance of MOSFET will change at different switching frequencies, and this change is related to voltage stress and temperature. The compensation method is to establish a lookup table containing correction coefficients under different working conditions. For example, when the junction temperature of the device rises from 25 degrees Celsius to 100 degrees Celsius, the parasitic capacitance may increase by 15-20%, and the parameter value needs to be adjusted accordingly. Through this compensation, the final distributed capacitance value can accurately reflect the parasitic characteristics of the device under actual working conditions, providing a reliable basis for defect detection.

[0047] Please continue reading Figure 1 , performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; In one embodiment of the present invention, the time-frequency characteristic analysis of the distributed capacitance value to obtain the parasitic characteristics in the switching process includes: segmenting the distributed capacitance value according to the turn-on phase, Miller platform phase and turn-off phase of the power device to obtain three characteristic sequences; calculating the voltage change rate of the characteristic sequences of the turn-on phase and the turn-off phase to obtain the switching stress characteristics; performing parasitic oscillation analysis on the characteristic sequence of the Miller platform phase to obtain the plateau oscillation characteristics; synchronously marking the switch stress characteristics and the plateau oscillation characteristics based on the voltage reversal point of the switching cycle to obtain the timing characteristics of the parasitic parameters; and reconstructing the characteristics of the timing characteristics under different switching rate conditions to obtain the parasitic characteristics in the switching process.

[0048] Specifically, in order to accurately analyze the dynamic characteristics of power devices, it is necessary to perform timing analysis on the obtained distributed capacitance values. The switching process of MOSFET can be divided into three key stages: the conduction stage (the device is turned off to fully turned on, lasting about 200-300 nanoseconds), the Miller platform stage (this stage is also called the stable platform period, which refers to the feedback effect caused by the rapid change of the drain voltage during the switching process, causing the gate voltage to stay at a fixed level value. This fixed level is usually 2-3 times the gate threshold voltage and lasts for about 1-2 microseconds), and the turn-off stage (the device is turned on to fully turned off, lasting about 300-400 nanoseconds). When the distributed capacitance values ​​are segmented according to these three stages, the change characteristics of the gate voltage are used as the segmentation basis. For example, when the gate voltage rises from 0 to the threshold voltage (about 3 volts), it is the starting point of the conduction stage, when the voltage reaches the stable platform level (about 6-7 volts), it enters the Miller platform stage, and when the voltage begins to drop, it enters the turn-off stage.

[0049] The device is subjected to the greatest voltage stress during the turn-on and turn-off phases. The voltage change rate during the turn-on phase is calculated by measuring the time required for the drain voltage to drop from a high level (e.g., 400 volts) to a low level (about 1-2 volts), with a typical value of 50 volts per microsecond. The opposite is true during the turn-off phase, where the rate of change of the voltage from a low level to a high level is measured. The voltage change rate during these two phases directly reflects the switching stress characteristics. For example, if the measured voltage change rate during the turn-on process exceeds 100 volts per microsecond, it means that the device may have excessive switching stress, which is often related to excessive parasitic inductance (from device leads and PCB wiring, with a typical value of 10-20 nanohenries).

[0050] Parasitic oscillation analysis in the Miller platform phase is particularly important because the device is in the most sensitive working state at this time. Oscillation analysis must first identify the characteristics of the oscillation waveform: oscillation frequency (usually in the range of 5-20MHz, determined by the resonance of parasitic inductance and junction capacitance), amplitude (normally should be less than 5% of the DC bus voltage), and decay time constant (reflects the damping characteristics of the circuit, typical value is 200-300 nanoseconds). For example, at a 400-volt DC bus voltage, if an oscillation amplitude of more than 40 volts is observed and the decay time constant exceeds 500 nanoseconds, it indicates the presence of abnormal parasitic resonance.

[0051] The voltage reversal point of the switching cycle is an important reference for feature synchronization. The voltage reversal point refers to the moment when the drain voltage begins to change rapidly, which is usually synchronized with the gate voltage reaching the threshold voltage. During the synchronization marking process, the stress characteristics and oscillation characteristics within each switching cycle are aligned according to the time offset relative to the reversal point. For example, if the oscillation in a switching process occurs 200 nanoseconds after the reversal point, this time relationship needs to be consistent in all sampling cycles so that the dynamic characteristics of the parasitic parameters can be correctly evaluated.

[0052] Finally, the timing characteristics need to be reconstructed under different switching speed conditions. The switching speed is determined by the gate drive circuit and can usually be adjusted by changing the gate resistor (typically ranging from 2 ohms to 20 ohms). The above analysis process needs to be repeated for each switching speed. For example, when using a 5 ohm gate resistor, the measured rise time may be 100 nanoseconds and the oscillation frequency is 15MHz; when using a 15 ohm resistor, the rise time may be extended to 300 nanoseconds and the oscillation frequency is reduced to 10MHz. By comparing the characteristic changes under different conditions, the parasitic characteristics of the device can be fully evaluated, especially the influence of parasitic parameters on switching performance. This comprehensive characteristic analysis provides reliable data support for subsequent defect diagnosis.

[0053] In one embodiment of the present invention, the parasitic oscillation analysis is performed on the characteristic sequence of the Miller platform phase to obtain the platform period oscillation characteristics, including: identifying the boundaries of the gate voltage platform period of the characteristic sequence to obtain the start and end times of the Miller platform; extracting the peak and valley values ​​of the oscillation waveform of the drain voltage within the start and end times to obtain an oscillation amplitude sequence; calculating the attenuation coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation; correlating the damping characteristics with the drain current change rate to obtain the triggering characteristics of the parasitic oscillation; and establishing an oscillation energy distribution diagram based on the triggering characteristics and the attenuation law to obtain the platform period oscillation characteristics.

[0054] Specifically, in the switching process of MOSFET, the parasitic oscillation analysis of the Miller plateau period is crucial for defect detection. First, the boundary of the gate voltage plateau period needs to be identified for the characteristic sequence. Specifically, the gate voltage will show three obvious voltage stages during the switching process: first, it rises rapidly from 0 volts to the threshold voltage (about 3 volts), then maintains a constant voltage (about 6-7 volts) during the stable plateau period, and finally rises rapidly to the drive voltage (about 12-15 volts). The starting point of the plateau period refers to the moment when the gate voltage reaches the stable platform level, and the end point is the moment when the voltage begins to rise rapidly for the second time. For example, in a certain model of 1200 volt silicon carbide MOSFET, when a 15 volt drive voltage is used, it can be observed that the gate voltage maintains a plateau period of about 1.5 microseconds at 6.5 volts.

[0055] Within the determined start and end time of the plateau period, the oscillation waveform of the drain voltage needs to be analyzed. These oscillations originate from the resonance formed by parasitic inductance (mainly from device leads and PCB wiring, with a typical value of 10-20 nanohenries) and junction capacitance (which varies with drain-source voltage, with a typical value of 100-500 picofarads). Peak-to-valley value extraction uses a local extreme value detection algorithm and sets a minimum amplitude threshold (usually 1% of the DC bus voltage) to filter out noise. For example, under a 400-volt DC bus voltage, if the first peak of the observed oscillation waveform is 430 volts and the first valley is 370 volts, the amplitude of the first oscillation is 30 volts. All peak-to-valley values ​​are recorded in chronological order to form an oscillation amplitude sequence.

[0056] The decay of the oscillation amplitude sequence reflects the energy loss characteristics of the circuit. The attenuation coefficient is calculated using the logarithmic decay rate method: the amplitude ratio of adjacent oscillation cycles is taken as the natural logarithm. Under normal circumstances, due to the damping effect in the circuit (mainly from the device on-resistance and PCB line loss), the oscillation will gradually decay. For example, if the amplitudes of three consecutive oscillation cycles are 30 volts, 20 volts, and 13 volts, respectively, the attenuation coefficient of each cycle can be calculated to be approximately 0.4, which reflects the damping characteristics of the circuit. Too small an attenuation coefficient (such as less than 0.2) indicates that the circuit is underdamped and may cause continuous high-frequency oscillation.

[0057] The triggering of parasitic oscillations is closely related to the rate of change of the drain current. During the Miller plateau, the rate of change of the drain current (di / dt) is typically between a few hundred amperes and a few thousand amperes per microsecond. The current rate of change data can be obtained by measuring the current transformer (bandwidth must reach 50MHz or more). For example, when the drain current changes at a rate of 1000 amperes per microsecond, if a sudden increase in the oscillation amplitude is observed, this correlation reflects the triggering characteristics of the parasitic oscillation. Excessive di / dt tends to excite stronger oscillations, which is directly related to the inductive effect of the parasitic inductance (the induced voltage is equal to the inductance value multiplied by the di / dt).

[0058] Finally, an oscillation energy distribution diagram needs to be established to fully characterize the oscillation characteristics of the plateau period. The horizontal axis of the energy distribution diagram is time (covering the entire plateau period, usually 1-2 microseconds), and the vertical axis is frequency (usually in the range of 5-20MHz). The energy intensity in the diagram is represented by the depth of color. For example, it can be observed that within 200 nanoseconds at the beginning of the plateau period, the oscillation energy near 10MHz is the strongest, and then gradually decays to the low frequency band. This time-frequency energy distribution feature can intuitively reflect the dynamic influence of parasitic parameters, especially the drift of oscillation frequency and the attenuation process of energy. By comparing the energy distribution diagrams of different devices, abnormal parasitic oscillation phenomena can be effectively identified, providing an important basis for defect detection.

[0059] Please continue reading Figure 1 , calculating the capacitance deviation according to the parasitic characteristics, and determining the defect area and its type; In one embodiment of the present invention, the capacitance deviation is calculated according to the parasitic characteristics to determine the defective area and its type, including: comparing the parasitic parameters of the gate-source region in the parasitic characteristics with the baseline value to obtain a first deviation; comparing the parasitic parameters of the drain-source region in the parasitic characteristics with the baseline value to obtain a second deviation; locating the points where the first deviation and the second deviation exceed the threshold value according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area; matching the physical coordinates of the abnormal area with the PN junction distribution diagram of the power device to obtain the defect type; and performing difference calculation between the parasitic parameters of the area corresponding to the defect type and the standard threshold value to obtain the capacitance deviation.

[0060] Specifically, in the defect detection of MOSFET devices, it is necessary to compare and analyze the measured parasitic characteristics with the standard values. The first is the comparison of parasitic parameters in the gate-source region, which mainly includes the gate oxide capacitance (for 1200V silicon carbide MOSFET, the normal value is about 2-3 nanofarads) and the superposition capacitance of the gate metallization layer and the source region. The selection of the reference value is based on the statistical average of qualified products in the same batch, and the ±10% range is usually used as the normal fluctuation range. For example, if the gate-source capacitance of a device is measured to be 3.5 nanofarads and the reference value is 3 nanofarads, the first deviation is +16.7%, which exceeds the normal fluctuation range, which may indicate that there is a defect in the gate oxide layer.

[0061] The comparison of parameters in the drain-source region is more complicated because the parasitic capacitance in this region (mainly the PN junction capacitance) changes with the drain-source voltage. In a device with a rated voltage of 1200 volts, when the drain-source voltage is 0, the junction capacitance can reach 500 pF, and it will drop to about 200 pF at a bias voltage of 600 volts. The comparison needs to be made under the same bias conditions. For example, at a bias of 600 volts, if the drain-source capacitance of a device is measured to be 300 pF, and the baseline value is 200 pF, the second deviation is +50%. This significant deviation is usually related to abnormal PN junction doping concentration or local breakdown.

[0062] The spatial positioning of the deviation is achieved through the chip layout coordinate system. Modern power MOSFETs usually adopt a strip or hexagonal unit structure, and each chip contains thousands of basic units. Taking a 10 mm × 10 mm chip as an example, a 100 × 100 grid coordinate system can be established with a resolution of 0.1 mm. If the gate-source capacitance deviation is detected to exceed 20% at the coordinate point (35, 42), the point is marked as an abnormal area. Usually, all points with deviations exceeding ±15% are recorded, and the collection of these points forms the boundary of the abnormal area.

[0063] The PN junction distribution of power MOSFET has a specific geometric structure. In the vertical double diffusion structure, the P-type body region is located below the source metal, and the N-type drift region is located below it to the drain. By matching the physical coordinates of the abnormal area with the PN junction distribution map, the specific type of defect can be determined. For example, if the abnormal points are mainly distributed at the edge of the gate area and appear as an abnormal increase in the gate-source capacitance, this usually indicates a breakdown of the gate oxide layer; if the abnormality is concentrated in the P-type region at the center of the cell and the drain-source capacitance is too large, it may be a defect in the intrinsic layer (drift region); if the abnormality appears at the edge of the source metallization layer, it appears as an instability of the parasitic capacitance, which may be a source floating phenomenon.

[0064] Finally, it is necessary to conduct a quantitative evaluation of the identified defective areas. The evaluation method is to calculate the difference between the parasitic parameters in the defective area and the standard threshold. The standard threshold is determined based on the design specifications of the device. For example, for a gate oxide breakdown type defect, if the gate-source capacitance of a certain area exceeds 1.5 times the standard value, the recorded capacitance deviation is +50%. Through this quantitative analysis, the severity of the defect can be evaluated, providing a basis for device screening and reliability prediction. For example, when the capacitance deviation of a certain area exceeds +30%, it should be judged as a potential reliability risk even if the device is still working normally.

[0065] Please continue reading Figure 1 , verify the stability of the defect area and its type under temperature cycling and vibration stress conditions, and obtain reliability evaluation results.

[0066] In one embodiment of the present invention, verifying the stability of the defect area and its type under temperature cycling and vibration stress conditions to obtain a reliability evaluation result includes: during the temperature cycling process, scanning the impedance characteristics of the defect area at four temperature points of -40°C, 25°C, 85°C and 125°C to obtain a temperature stress response curve; during the vibration process, measuring parameters at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz required by automotive electronic standards to obtain a vibration stress response curve; extracting parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain a temperature stress influence factor; retesting the defect position of the vibration stress response curve in three states of on, Miller platform and off to obtain a vibration stress influence factor; and obtaining a reliability evaluation result based on the acceleration effect of the temperature stress influence factor and the vibration stress influence factor on the defect parameters.

[0067] Specifically, MOSFET needs to withstand complex environmental stresses in practical applications, especially temperature cycling and mechanical vibration. In the reliability evaluation process, temperature cycling tests are first performed in accordance with automotive-grade standards. The reasons for selecting the four temperature points of -40°C, 25°C, 85°C and 125°C are: -40°C is the extreme operating temperature in winter in cold areas, when the carrier mobility of the device is significantly reduced; 25°C is the room temperature reference point; 85°C is the typical operating temperature in the engine compartment; 125°C is the maximum junction temperature limit of the power device. Stay at each temperature point for no less than 30 minutes to ensure that the temperature is fully stable. For example, when the device temperature rises from 25°C to 85°C, the gate-source capacitance may increase by 10-15%, and this change needs to be accurately captured by impedance characteristic scanning.

[0068] The vibration test follows the requirements of automotive electronic standards (such as AEC-Q101) and selects five typical frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz. The selection of these frequency points is based on the actual working conditions of the vehicle: 10Hz corresponds to low-frequency vibration of the vehicle body, 100Hz reflects engine idling vibration, 500Hz represents medium-frequency mechanical resonance, and 1000Hz and 2000Hz correspond to high-frequency resonance and electromagnetic vibration. The vibration amplitude is set to 1.5G (about 14.7 meters per second squared) according to the standard. During the test, a professional vibration table is used to strictly fix the device and monitor the vibration parameters in real time through an acceleration sensor. For example, under 1000Hz vibration, it is necessary to observe the stress distribution of the device package pins and the fluctuation of parasitic parameters.

[0069] The parameter extraction of the temperature stress response curve is concentrated on the characteristic frequency points of the power device. For a device with a switching frequency of 100kHz, it is necessary to analyze the response characteristics at 100kHz (fundamental wave), 200kHz (second harmonic) and 300kHz (third harmonic). At each frequency point, three parameters are mainly concerned: impedance amplitude (reflecting the temperature coefficient of parasitic capacitance, with a typical value of 0.2% / ℃), phase angle (reflecting the dynamic characteristics of parasitic parameters) and quality factor (characterizing loss characteristics). Taking the gate-source capacitance as an example, if the impedance amplitude measured at 85℃ is 15% lower than that at 25℃, and the second harmonic component is abnormally increased, this temperature stress influencing factor indicates a potential reliability risk.

[0070] The vibration stress response curve needs to be analyzed under three key working conditions of the device. In the on state, pay attention to the integrity of the gate drive waveform (vibration may cause distortion of the drive signal); during the Miller platform, focus on monitoring the changes in parasitic oscillations (mechanical vibration may aggravate electrical oscillations); in the off state, it is necessary to observe the stability of the drain-source voltage. For example, when under 1000Hz vibration, if the parasitic oscillation amplitude during the Miller platform increases by 30% compared to static conditions, this vibration stress impact factor indicates that there is a hidden danger in the mechanical stability of the device.

[0071] Finally, by comprehensively analyzing the effects of temperature and vibration stress, the development trend of defects can be evaluated. The acceleration effect is mainly reflected in three aspects: first, the thermomechanical stress caused by temperature cycling may accelerate the degradation of the gate oxide layer (the failure rate increases by about one time for every 10°C increase); second, the mechanical fatigue caused by vibration will affect the reliability of wire bonding; and finally, the coupling of the two stresses often produces a synergistic effect. For example, if the parasitic parameter deviation of a defective area increases by more than 50% when the stress is applied alone at 85°C and 1000Hz vibration, the expected life of the device needs to be reduced to half of the nominal value. This quantitative reliability evaluation result provides an important basis for device screening and application design.

[0072] The above describes the defect detection method of the electric control component of a new energy vehicle in the embodiment of the present invention. The following describes the defect detection device of the electric control component of a new energy vehicle in the embodiment of the present invention. Figure 2 In one embodiment of the present invention, a defect detection device for electric control components of new energy vehicles includes: The signal injection module 201 is used to apply an AC signal in the range of 100kHz-10MHz to the electric control component, and obtain the impedance response characteristics of each parasitic coupling area of ​​the power device by differential detection; A network analysis module 202, used to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance value of each parasitic coupling area; A time-frequency processing module 203, used to perform time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; A defect identification module 204, used to calculate the capacitance deviation according to the parasitic characteristics, and determine the defect area and its type; The reliability evaluation module 205 is used to verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

[0073] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A defect detection method for electric control components of new energy vehicles, characterized in that: include: Apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and use a differential detection method to obtain the impedance response characteristics of each parasitic coupling area of ​​the power device; Performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area; Performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; Calculating capacitance deviation according to the parasitic characteristics, and determining defect areas and types thereof; The stability of the defect area and its type is verified under temperature cycling and vibration stress conditions to obtain reliability evaluation results.

2. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The method of applying an AC signal in the range of 100kHz-10MHz to the electric control component and obtaining the impedance response characteristics of each parasitic coupling region of the power device by a differential detection method includes: A high-frequency response probe is arranged at a first parasitic coupling surface between the gate and source of the power device and a second parasitic coupling surface between the drain and source as a reference detection end; A differential probe is arranged on the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power loop as a differential detection terminal; Applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end, and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device; The high frequency response data of the reference detection end and the differential detection end are collected, and the impedance response characteristics of each parasitic coupling region are calculated.

3. The defect detection method for electric control components of new energy vehicles according to claim 2 is characterized in that: The method of applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device includes: The gate drive voltage when the power device is turned on is used as the reference, and the initial amplitude of the AC scanning signal is set to 30% of it; Applying a scanning signal with an initial frequency of 100 kHz to the reference detection end, and recording a gate opening threshold point of a power device; Dynamically calculate the signal application time of the next frequency point according to the response time of the gate opening threshold point; The signal application time is compensated according to a 50kHz step amount to eliminate the phase delay caused by the parasitic loop; After compensation, the signal frequency is gradually increased to 10MHz to maintain the trigger synchronization of each frequency point.

4. The defect detection method for electric control components of new energy vehicles according to claim 2 is characterized in that: The collecting high frequency response data of the reference detection end and the differential detection end and calculating the impedance response characteristics of each parasitic coupling region includes: Performing amplitude normalization processing on the high frequency response data of the reference detection end to obtain a reference response sequence; Calibrate the high frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence; Calculating the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase characteristic; Compensating the high frequency response data according to the coupling phase characteristics to obtain an actual impedance value; The actual impedance value is mapped according to the physical position of the parasitic coupling region to obtain an impedance response characteristic.

5. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area includes: Performing fast Fourier transform on the impedance response characteristics in the gate drive circuit and the power main circuit respectively to obtain dual-circuit amplitude-frequency characteristics; The dual-loop amplitude-frequency characteristics are used to establish interconnection network equations according to three sets of coupling relationships between gate-source, drain-source and gate-drain, and the transmission function of each coupling region is obtained; Performing odd-even mode separation on the transmission function to obtain common-mode and differential-mode impedance components; Reconstructing the common-mode and differential-mode impedance components within a fixed time window of the Miller platform to obtain equivalent parameters of each coupling region; The equivalent parameters are corrected and compensated according to the actual switching frequency point to obtain the distributed capacitance value of each parasitic coupling area.

6. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process includes: The distributed capacitance value is segmented in time sequence according to the turn-on phase, Miller platform phase and turn-off phase of the power device to obtain three characteristic sequences; Calculating the voltage change rate of the characteristic sequences in the on-phase and the off-phase to obtain the switch stress characteristics; Performing parasitic oscillation analysis on the characteristic sequence of the Miller platform phase to obtain the oscillation characteristics of the platform phase; Based on the voltage reversal point of the switching cycle, the switch stress characteristics and the plateau oscillation characteristics are synchronously marked to obtain the timing characteristics of the parasitic parameters; The timing characteristics are reconstructed under different switching rate conditions to obtain parasitic characteristics during the switching process.

7. The defect detection method for electric control components of new energy vehicles according to claim 6 is characterized in that: The parasitic oscillation analysis is performed on the characteristic sequence of the Miller platform phase to obtain the oscillation characteristics of the platform phase, including: Identify the boundary of the gate voltage plateau period of the characteristic sequence to obtain the start and end time of the Miller platform; Extracting peak and valley values ​​of the oscillation waveform of the drain voltage within the start and end times to obtain an oscillation amplitude sequence; Calculating the attenuation coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation; Correlating the damping characteristic with the rate of change of the drain current to obtain a triggering characteristic of the parasitic oscillation; An oscillation energy distribution diagram is established according to the trigger characteristics and attenuation law to obtain the plateau oscillation characteristics.

8. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The step of calculating the capacitance deviation according to the parasitic characteristics and determining the defect area and its type includes: Comparing the parasitic parameters of the gate-source region in the parasitic characteristics with a reference value to obtain a first deviation; Comparing the parasitic parameters of the drain-source region in the parasitic characteristics with the reference value to obtain a second deviation; Locate the points where the first deviation and the second deviation exceed the threshold value according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area; Matching the physical coordinates of the abnormal area with the PN junction distribution map of the power device to obtain the defect type; The difference between the parasitic parameters of the area corresponding to the defect type and the standard threshold is calculated to obtain the capacitance deviation.

9. The defect detection method for electric control components of new energy vehicles according to claim 1, characterized in that: The stability of the defect area and its type is verified under temperature cycle and vibration stress conditions to obtain reliability evaluation results, including: During the temperature cycle, the impedance characteristics of the defect area are scanned at four temperature points: -40°C, 25°C, 85°C and 125°C, and the temperature stress response curve is obtained; During the vibration process, the parameters are measured at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz as required by automotive electronic standards to obtain the vibration stress response curve; Extract parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain the temperature stress influencing factor; The vibration stress response curve is re-measured at the defect position in three states: on, Miller platform and off, to obtain the vibration stress influencing factor; According to the acceleration effect of the temperature stress influencing factor and the vibration stress influencing factor on the defect parameters, a reliability evaluation result is obtained.

10. A defect detection device for electric control components of new energy vehicles, characterized in that: The defect detection device of the electric control component of the new energy vehicle comprises: The signal injection module is used to apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and obtain the impedance response characteristics of each parasitic coupling area of ​​the power device by differential detection; A network analysis module, used to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance value of each parasitic coupling area; A time-frequency processing module, used to perform time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; A defect recognition module, used to calculate the capacitance deviation according to the parasitic characteristics, and determine the defect area and its type; The reliability evaluation module is used to verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

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