Test circuit and control method thereof, storage medium and chip
By designing a test circuit including a first signal selection unit, a register unit and a second signal selection unit, the test module to be arbitrarily cut and divided, the problems of insufficient test coverage and tight interface resources in the prior art are solved, and efficient test coverage is achieved.
Patent Information
- Application Number
- CN202311302590.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-09
- Publication Date
- 2025-04-11
AI Technical Summary
In the prior art, the test coverage rate needs to be improved, and the number of ports added when encapsulating the core is large, resulting in tight interface resources.
A test circuit is designed, including a first signal selection unit, a register unit and a second signal selection unit. Through these units, the output signals of the insertion point in the test module are tested and cut, and any cutting and division of the test module is realized, and the test circuit is inserted for testing.
Through the design of this test circuit, the measurability of the output signal at the insertion point in the module to be tested and the measurability of the subsequent load circuit is realized, the test coverage of the circuit is improved, the number of interfaces is reduced, and the interface resources are saved.
Smart Images
Figure CN119805154A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a test circuit and a control method thereof, a storage medium, and a chip. Background Art
[0002] In the process of integrated circuit manufacturing, in order to provide high test coverage, Design For Test (DFT) technology based on scan chain and automatic test pattern generation (ATPG) is widely used.
[0003] When a core with testability design inserted is to be integrated into the top-level design, the core's scan structure will be combined with the top-level scan structure, making it impossible to test the core alone. This is where the wrapper core comes in. Each wrapper core has a wrapper chain to isolate the core from the surrounding logic. The wrapper chain is a string of wrapper cells, which include scan cells and multiplexers, inserted between the I / O port and the core logic. Figure 1 As shown in the figure, a package area is inserted into the I / O port of the core, and the package area can pass the I / O signal or serve as an input capture value or an output launch value.
[0004] Adding a packaging area to the core I / O port allows the test vector to be fed in through the port, which can improve the coverage of the logic at the port. However, a good design generally does not design a large amount of combinational logic at the interface of the module. Instead, after the signal is input, it will first pass through a register before entering other logic of the module. The register can be inserted into the scan chain, so that the logic connected to the register output port can be arbitrarily configured to complete the test.
[0005] However, the test coverage in the existing technology needs to be improved. Summary of the invention
[0006] The present application can arbitrarily cut and divide the module to be tested and insert the test circuit for testing, thereby improving the test coverage.
[0007] In order to solve the above technical problems, an embodiment of the present invention provides a test circuit, the test circuit comprising:
[0008] A first signal selection unit, wherein the first input end of the first signal selection unit is coupled to the output end of the insertion point in the module to be tested, and the second input end of the first signal selection unit is coupled to the output end of the previous test module or the test vector input end; a register unit, wherein the input end of the register unit is coupled to the output end of the first signal selection unit, the output end of the register unit is the output end of the test module, and the register unit is used to register the signal from the first signal selection unit; a second signal selection unit, wherein the first input end of the second signal selection unit is coupled to the output end of the insertion point in the module to be tested, and the second input end of the second signal selection unit is coupled to the output end of the register unit, and the second signal selection unit is used to selectively output the output signal of the insertion point in the module to be tested or the signal in the register unit to a subsequent load circuit.
[0009] Optionally, the control end of the first signal selection unit is connected to a first selection signal, and the first selection signal is used to control the first signal selection unit of the first-level test module to output the output signal of the insertion point in the module to be tested or the test vector, and the first selection signal is used to control the first signal selection unit of other-level test modules to output the output signal of the insertion point in the module to be tested or the output signal of the previous-level test module.
[0010] Optionally, the control end of the second signal selection unit is connected to a second selection signal, and the second selection signal is used to control the second signal selection unit to output the output signal of the insertion point in the module to be tested or the signal in the register unit.
[0011] Optionally, when the second selection signal is at a first level, the test circuit operates in a non-test mode, and the second signal selection unit outputs the output signal of the insertion point in the module to be tested to a subsequent load circuit; when the second selection signal is at a second level, the test circuit operates in a test mode, and the second signal selection unit outputs the signal in the register unit to a subsequent load circuit.
[0012] Optionally, the first signal selection unit includes a first multiplexer or a first logic combination circuit.
[0013] Optionally, the second signal selection unit includes a second multiplexer or a second logic combination circuit.
[0014] Optionally, the register unit includes a register, or two cascaded latches.
[0015] In a second aspect, the present application also discloses a control method for a test circuit, the control method comprising: in a test mode, controlling a first signal selection unit in at least one cascaded test module to output an output signal of an insertion point in the module to be tested, and a register unit in at least one cascaded test module to register the output signal of the insertion point in the module to be tested; controlling the first signal selection unit in at least one cascaded test module to output an output signal in a register unit coupled thereto; controlling the second signal selection unit in at least one cascaded test module to output a signal in a register unit coupled thereto to a subsequent load circuit coupled thereto.
[0016] Optionally, before the first signal selection unit in controlling at least one cascaded test module outputs the output signal of the insertion point in the module to be tested, the method also includes: controlling the first signal selection unit in the first-level test module to output a test vector; and controlling the first signal selection unit in other-level test modules to output the output signal in the coupled register unit.
[0017] Optionally, the control method further includes: in a non-test mode, controlling the second signal selection unit to output the output signal of the insertion point in the module to be tested to the subsequent load circuit.
[0018] In a third aspect, the present application further discloses a computer-readable storage medium having a computer program stored thereon, wherein the computer program executes the steps of the control method when executed by a processor.
[0019] In a fourth aspect, the present application further discloses a chip, the chip comprising: an operation unit or a logic unit, including an insertion point in a module to be tested; the test circuit; and at least one subsequent load circuit.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0021] In the technical solution of the present application, the test circuit includes at least one cascaded test module, and the test module includes: a first signal selection unit, a first input end of the first signal selection unit is coupled to the output end of the insertion point in the module to be tested, and a second input end of the first signal selection unit is coupled to the output end of the previous test module or the test vector input end; a register unit, an input end of the register unit is coupled to the output end of the first signal selection unit, the output end of the register unit is the output end of the test module, and the register unit is used to store the signal from the first signal selection unit; a second signal selection unit, a first input end of the second signal selection unit is coupled to the output end of the insertion point in the module to be tested, a second input end of the second signal selection unit is coupled to the output end of the register unit, and the second signal selection unit is used to selectively output the output signal of the insertion point in the module to be tested or the signal in the register unit to the next-stage load circuit. In the present application, by setting a first signal selection unit, a register unit, and a second signal selection unit, the output signal of the insertion point in the module to be tested and the subsequent load circuit are tested, and the module to be tested can be arbitrarily cut and divided, and the key node (that is, the above-mentioned insertion point) is found and the test circuit is inserted for testing, so as to achieve the testability of the output signal of the insertion point in the module to be tested and the testability of the subsequent load circuit, and improve the test coverage of the circuit. In addition, by setting a second signal selection unit, it can output the output signal of the insertion point in the module to be tested to the subsequent load circuit in the non-test mode, so as to bypass the test circuit and ensure the performance of the chip.
[0022] Furthermore, in a chip with a scan chain, the interface of the test module can reuse the interface of the scan chain, further reducing the number of interfaces to improve the test coverage of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a structural schematic diagram of a packaging core in the prior art;
[0024] Figure 2 It is a structural schematic diagram of a packaging area in the prior art;
[0025] Figure 3 is a structural schematic diagram of a test circuit provided by an embodiment of the present invention;
[0026] Figure 4 is a specific structural diagram of a test module provided by an embodiment of the present invention;
[0027] Figure 5 is a specific structural diagram of another test circuit provided by an embodiment of the present invention;
[0028] Figure 6 It is a schematic diagram of a control method for a test circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0029] As described in the background technology, the test coverage in the prior art needs to be improved.
[0030] In addition, the insertion of the package area structure will add more ports, while the interface resources in the existing chips are relatively tight.
[0031] Specifically, Figure 2 As shown, with the insertion of the package area structure, the added ports are capture_en, cfi, shift_en, cti, and shift_clk.
[0032] Among them, capture_en represents the capture enable signal port. The capture enable signal is used to control when the encapsulation area captures. When the signal is low, the encapsulation area captures the value of the core function input. When the signal is high, the encapsulation area maintains the current state.
[0033] Cfi represents the core functional input port. For the input encapsulation area, the input comes from the peripheral logic around the core; for the output encapsulation area, the input comes from the core.
[0034] shift_en represents the scan enable signal port of the package area. When the scan enable signal is high, the package area shifts the test input and test output of the package area; when the signal is low, the package area captures the value of the core function input or maintains the current state, depending on the value of capture_en at this time.
[0035] cti represents the core test input port, that is, the test input end of the package area. The input signal of this port can come from the primary input (PI) or the output end of the previous package area.
[0036] shift_clk represents the clock signal port of the package area, which is driven by the clock inside the core.
[0037] In addition, cfo represents the core functional output port. For the input package area, the output drives the core; for the output package area, the output drives the core peripheral logic.
[0038] In addition, cto represents the core test output port, that is, the test output end of the package area. The output signal of this port can drive the primary output (PO) or serve as the test input of the next package area.
[0039] In the present application, by setting a first signal selection unit, a register unit, and a second signal selection unit, the output signal of the insertion point in the module to be tested and the subsequent load circuit are tested, and the module to be tested can be arbitrarily cut and divided and inserted into the test circuit for testing, so as to achieve the testability of the output signal of the insertion point in the module to be tested and the testability of the subsequent load circuit, and improve the test coverage of the circuit. In addition, by setting a second signal selection unit, it can output the output signal of the insertion point in the module to be tested to the subsequent load circuit in the non-test mode, so as to bypass the test circuit and ensure the performance of the chip.
[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0041] Figure 3 It is a structural schematic diagram of a test circuit according to an embodiment of the present invention.
[0042] like Figure 3 As shown, the test circuit includes at least one level of test module 30. Each test module 30 may include a first signal selection unit 301, a register unit 302 and a second signal selection unit 303.
[0043] Each of the first signal selection units 301 and each of the second signal selection units 303 has two input terminals. The output terminal of the first signal selection unit 301 is coupled to the input terminal of the register unit 302, and the output terminal of the register unit 302 is coupled to the second input terminal of the second signal selection unit 303. The output terminal of the second signal selection unit 303 is coupled to the subsequent load circuit.
[0044] In this embodiment, the first signal selection unit 301 is used to selectively input the output signal of the insertion point in the receiving test module or the test vector to the register unit 302. The register unit 302 is used to register the signal from the first signal selection unit 301. The second signal selection unit 303 is used to selectively output the output signal of the insertion point in the module to be tested or the signal in the register unit 302 to the subsequent load circuit.
[0045] In this embodiment, the insertion point in the module to be tested is usually a key node in the module to be tested.
[0046] Specifically, in the first-level test module 30, the first input terminal I00 of the first signal selection unit 301 is coupled to the output terminal of the insertion point in the receiving test module, that is, the output signal of the insertion point in the receiving test module is received; the second input terminal I01 of the first signal selection unit 301 is coupled to the test vector input terminal, that is, the test vector is received.
[0047] In the second-level test module 30, the first input terminal I10 of the first signal selection unit 301 is coupled to the output terminal of the insertion point in the receiving test module, that is, receives the output signal of the insertion point in the receiving test module; the second input terminal I11 of the first signal selection unit 301 is coupled to the output terminal of the previous-level test module, that is, the output terminal of the register unit 302 in the first-level test module 30, to receive the signal in the register unit 302 in the previous-level test module 30.
[0048] Similarly, in the third-stage test module 30 to the last-stage test module 30 , the second input terminal of the first signal selection unit 301 is coupled to the output terminal of the previous-stage test module, and the rest is the same as the previous-stage test module 30 , which will not be described again.
[0049] Furthermore, the control end of each first signal selection unit 301 is connected to the first selection signal Seclect0. The first selection signal Seclect0 is used to control the first signal selection unit 301 of the first-level test module 30 to output the output signal or test vector of the insertion point in the module to be tested, and the first selection signal is used to control the first signal selection unit 301 of other-level test modules 30 to output the output signal of the insertion point in the module to be tested or the output signal of the previous-level test module 30.
[0050] For example, taking the insertion point in the module to be tested as a high fan-out combinational logic gate as an example, when the first selection signal Select0 is 0, the first signal selection unit 301 selects the signal at the first input end, that is, the data from the output pin of the high fan-out combinational logic gate; when the first selection signal Select0 is 1, the first signal selection unit 301 selects the signal at the second input end, that is, the data from the register.
[0051] Furthermore, the control end of each second signal selection unit 303 receives the second selection signal Seclect1. The second selection signal Seclect1 is used to control the second signal selection unit 303 to output the output signal of the insertion point in the module to be tested or the signal in the register unit 302.
[0052] For example, taking the insertion point in the module to be tested as a high fan-out combinational logic gate, when the second selection signal Select1 is 0, the second signal selection unit 303 selects data from the output pin of the high fan-out combinational logic gate; when the second selection signal Select1 is 11, the second signal selection unit 303 selects the signal from the register unit 302.
[0053] Furthermore, the control ends of the first signal selection units 301 are connected, and the control ends of the second signal selection units 303 are connected. That is, multiple first signal selection units 301 can reuse the same first selection signal Seclect0, and multiple second signal selection units 303 can reuse the same second selection signal Seclect1.
[0054] When testing the test circuit of the embodiment of the present invention, the added ports are two input ends of the first signal selection unit, the input end of the first selection signal Seclect0 and the input end of the second selection signal Seclect1. The number of added ports is very small, which can greatly save interface resources.
[0055] In a non-limiting embodiment, if the circuit where the insertion point in the module to be tested is located does not include a scan chain, then the control end of the first signal selection unit, the control end of the second signal selection unit, the output end of the test module and the input end of the test vector need to serve as external ports.
[0056] In another non-limiting embodiment, if the circuit where the insertion point in the module to be tested is located includes a scan chain, the first selection signal Select0 is connected to the enable signal port scanen of the scan chain, and the second selection signal Select1 is connected to the enable mode scanmode port of the scan chain. The enable signal port scanen is used to access the enable signal, which can control the operation of the scan chain; the enable mode scanmode port is used to access the enable mode control signal, which can control the operation mode of the scan chain. The test module is directly connected to the scan chain.
[0057] Specifically, the polarity of the first selection signal Select0 and the enable signal of the scan chain are kept consistent, and the polarity of the second selection signal Select1 and the enable mode control signal are kept consistent. Otherwise, an inverter needs to be connected between the control end of the first signal selection unit and the enable signal port scanen, and an inverter needs to be connected between the control end of the second signal selection unit and the enable mode scanmode port as needed to ensure that the polarity meets the configuration under different configurations.
[0058] The following is an explanation based on different working modes of the test circuit.
[0059] 1. Normal function mode (non-test mode).
[0060] In this mode, the second selection signal Select1 is at the first level, for example, the first level is a high level, and the second signal selection unit 303 outputs the output signal of the insertion point in the module to be tested to the subsequent load circuit. In other words, the input end of the second signal selection unit 303 is connected to the output signal of the insertion point in the module to be tested, and the signal is output as its output signal to the subsequent load circuit.
[0061] This means that in normal operating mode, the test circuit will be bypassed to ensure that the output signal of the insertion point in the module to be tested in the chip can be output to the subsequent load circuit in real time to ensure the normal operating performance of the chip.
[0062] 2. Test Mode
[0063] In this mode, the first selection signal Select0 is first configured to be the third level, for example, the third level is a high level, so that each test module 30 is connected end to end, the first signal selection unit 301 of the first-level test module 30 selects to access the test vector, and the first signal selection unit 301 of the other-level test modules 30 selects to access the output signal of the register unit 302 in the previous-level test module. The output signal of the test circuit is the output signal of the register unit 302 in the last-level test module 30, and based on the output signal, it can be tested whether the functions of each register unit 302 in the test circuit are normal.
[0064] Then, the first selection signal Select0 is configured to be the fourth level, for example, the fourth level is a low level, and the first signal selection unit 301 of each level of the test module 30 selects the output signal of the insertion point connected to the receiving test module. After the clock edge arrives, the output signal of the insertion point in the receiving test module can be stored in each storage unit 302; then, the first selection signal Select0 is configured to be the third level, so that the signal in each storage unit 302 can be transmitted to the subsequent test module and output through the output port of the test circuit. In other words, the output signal of the insertion point in each module to be tested connected to the test circuit can be transmitted through the port shiftOut.
[0065] The above embodiments can achieve the testability of the insertion points in the module to be tested and improve the test coverage. In addition, in order to achieve the testability of the subsequent load circuit, the test circuit can be controlled to perform the following process.
[0066] Specifically, the first signal selection unit 301 in the first-stage test module 30 is controlled to input a test vector. The first signal selection unit 301 in the subsequent test module 30 is controlled to input a signal in the register unit 302 in the previous-stage test module. After the test vector is stored in each register unit 302, the second signal selection unit 303 is controlled to select the signal in the register unit 302 and output it to the subsequent load circuit, that is, the test vector is respectively input to each subsequent load circuit.
[0067] At this point, by observing the output signal of the subsequent load circuit, the testability of the subsequent load circuit can be achieved and the test coverage can be improved.
[0068] like Figure 4 As shown, Figure 4 A specific structure of the test module is shown.
[0069] In this embodiment, the first signal selection unit is a first multiplexer MUX1, and the second signal selection unit is a second multiplexer MUX2. The register unit includes a register.
[0070] I0 and I1 represent two input terminals of the first multiplexer MUX1 , namely, a first input terminal and a second input terminal, respectively.
[0071] Shiftout represents the output end of the register. In the test circuit composed of multiple test modules, the output end of the register in the last test module is the output end of the test circuit.
[0072] In another non-limiting embodiment, the first signal selection unit may also be a first logic combination circuit, which may select two input signals. Correspondingly, the second signal selection unit may also be a second logic combination circuit.
[0073] In another non-limiting embodiment, the register unit may also be two cascaded latches or D flip-flops.
[0074] It should be noted that the first signal selection unit, the second selection unit and the register unit may also be any other feasible circuit structure, and the present application does not impose any limitation on this.
[0075] Please refer to Figure 5 , Figure 5 The specific connection relationship between the test circuit and the insertion point in the module to be tested in the chip and the load circuit is shown.
[0076] Specifically, Figure 53 shows a three-level test module, and the insertion points comb11, comb12 and comb13 in the three modules to be tested, wherein the insertion points in each module to be tested correspond to three load circuits. Specifically, the insertion point comb11 in the module to be tested corresponds to the load circuits comb21, comb22 and comb23, the insertion point comb12 in the module to be tested corresponds to the load circuits comb24, comb25 and comb26, and the insertion point comb13 in the module to be tested corresponds to the load circuits comb27, comb28 and comb29.
[0077] Specifically, the first input end of the first signal selection unit of the first-stage test module is coupled to the output end of the insertion point comb11 in the test module, and the second input end is coupled to the test vector input end shiftIn, and the test vector input end shiftIn is used to access the test vector. The output end of the second signal selection unit of the first-stage test module is coupled to the input ends of the load circuits comb21, comb22 and comb23.
[0078] Accordingly, the first input end of the first signal selection unit of the second-stage test module is coupled to the output end of the insertion point comb12 in the test module, and the second input end is coupled to the output end of the register unit in the first-stage test module. The output end of the second signal selection unit of the second-stage test module is coupled to the input ends of the load circuits comb24, comb25 and comb26.
[0079] The first input end of the first signal selection unit of the third-level test module is coupled to the output end of the insertion point comb13 in the test module, and the second input end is coupled to the output end of the register unit in the second-level test module. The output end of the second signal selection unit of the third-level test module is coupled to the input ends of the load circuits comb27, comb28 and comb29. The output end of the register unit of the third-level test module is the output end shiftOut of the test circuit.
[0080] Please refer to Figure 6 , Figure 6 A schematic diagram showing a testing method for a testing circuit is shown.
[0081] In step 601, in the test mode, the first signal selection unit in at least one cascaded test module is controlled to output the output signal of the insertion point in the module to be tested, and the storage unit in at least one cascaded test module stores the output signal of the insertion point in the module to be tested.
[0082] Specifically, the first signal selection unit in at least one cascaded test module may be controlled by the level of the first selection signal Select0 to output the output signal of the insertion point in the module to be tested.
[0083] In step 602, a first signal selection unit in at least one cascaded test module is controlled to output an output signal in a register unit coupled thereto.
[0084] Specifically, the first signal selection unit in at least one cascaded test module may be controlled to output the output signal in the coupled register unit by the level of the first selection signal Select0. For example, the first selection signal Select0 is 1.
[0085] In step 603, the second signal selection unit in at least one cascaded test module is controlled to output the signal in the coupled register unit to the coupled subsequent load circuit.
[0086] Specifically, the second signal selection unit can be controlled by the level of the second selection signal Select1 to output the signal in the coupled register unit to the coupled subsequent load circuit.
[0087] In a specific embodiment, the following steps may be performed before step 601: controlling the first signal selection unit in the first-level test module to output a test vector; and controlling the first signal selection unit in other-level test modules to output the output signal in the coupled register unit.
[0088] The embodiment of the present invention can test whether the functions of each register unit 302 in the test circuit are normal through the above steps.
[0089] Furthermore, the above method may also include the following steps: in a non-test mode, controlling the second signal selection unit to output the output signal of the insertion point in the module to be tested to a subsequent load circuit.
[0090] In the embodiment of the present invention, the test circuit will be bypassed to ensure that the output signal of the insertion point in the module to be tested in the chip can be output to the subsequent load circuit in real time to ensure the normal working performance of the chip.
[0091] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.
[0092] It is understandable that, in a specific implementation, the control method can be implemented in the form of a software program, and the software program runs in a processor integrated inside a chip or a chip module. The method can also be implemented in the form of software combined with hardware, which is not limited in this application.
[0093] In a specific application scenario, an embodiment of the present invention inserts a test module into a high fan-out combinational logic node (i.e., an insertion point in the module to be tested) that causes more combinational logic coverage to be low, so that the node is configurable and testable, thereby improving the logic coverage.
[0094] In another specific application scenario, the embodiment of the present invention applies the test module to a circuit of combinational logic operations, which can improve the test coverage of the circuit.
[0095] The embodiment of the present invention further discloses a chip, which may include the aforementioned test circuit, and may also include an insertion point in the module to be tested and a subsequent load circuit. Specifically, the insertion point in the module to be tested may be a high fan-out combinational logic node, or a combinational logic operation circuit, which is not limited in the present application.
[0096] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in hardware such as circuits.
[0097] The embodiment of the present application also discloses a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and the steps of the aforementioned method can be executed when the computer program is run. The storage medium may include a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.
[0098] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.
[0099] The "plurality" appearing in the embodiments of the present application refers to two or more.
[0100] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.
[0101] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.
[0102] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.
[0103] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0104] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0105] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0106] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0107] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application.
[0108] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.
Claims
1. A test circuit, characterized in that: The method comprises at least one cascaded test module, wherein the test module comprises: a first signal selection unit, wherein a first input end of the first signal selection unit is coupled to an output end of an insertion point in a to-be-tested module, and a second input end of the first signal selection unit is coupled to an output end of a previous-stage test module or a test vector input end; a register unit, wherein an input end of the register unit is coupled to an output end of the first signal selection unit, an output end of the register unit is an output end of the test module, and the register unit is used to register a signal from the first signal selection unit; A second signal selection unit, wherein a first input end of the second signal selection unit is coupled to an output end of an insertion point in the module to be tested, a second input end of the second signal selection unit is coupled to an output end of the register unit, and the second signal selection unit is used to selectively output an output signal of the insertion point in the module to be tested or a signal in the register unit to a subsequent load circuit.
2. The test circuit according to claim 1, characterized in that: The control end of the first signal selection unit is connected to a first selection signal, and the first selection signal is used to control the first signal selection unit of the first-level test module to output the output signal of the insertion point in the module to be tested or the test vector, and the first selection signal is used to control the first signal selection unit of other-level test modules to output the output signal of the insertion point in the module to be tested or the output signal of the previous-level test module.
3. The test circuit according to claim 1, characterized in that: The control end of the second signal selection unit is connected to a second selection signal, and the second selection signal is used to control the second signal selection unit to output the output signal of the insertion point in the module to be tested or the signal in the register unit.
4. The test circuit according to claim 3, characterized in that: When the second selection signal is at a first level, the test circuit operates in a non-test mode, and the second signal selection unit outputs the output signal of the insertion point in the module to be tested to a subsequent load circuit; when the second selection signal is at a second level, the test circuit operates in a test mode, and the second signal selection unit outputs the signal in the register unit to a subsequent load circuit.
5. The test circuit according to claim 1, characterized in that: The first signal selection unit includes a first multiplexer or a first logic combination circuit.
6. The test circuit according to claim 1, characterized in that: The second signal selection unit includes a second multiplexer or a second logic combination circuit.
7. The test circuit according to claim 1, characterized in that: The register unit includes a register, or two cascaded latches.
8. A control method based on the test circuit according to any one of claims 1 to 7, characterized in that: include: In the test mode, the first signal selection unit in at least one cascaded test module is controlled to output the output signal of the insertion point in the module to be tested, and the register unit in at least one cascaded test module registers the output signal of the insertion point in the module to be tested; Controlling the first signal selection unit in the at least one cascaded test module to output the output signal in the coupled register unit; The second signal selection unit in the at least one cascaded test module is controlled to output the signal in the coupled register unit to the coupled subsequent load circuit.
9. The control method of the test circuit according to claim 8, characterized in that: Before the first signal selection unit in the at least one cascaded test module is controlled to output the output signal of the insertion point in the module to be tested, the method further includes: Controlling the first signal selection unit in the first-level test module to output a test vector; The first signal selection unit in the other level test module is controlled to output the output signal in the coupled register unit.
10. The control method of the test circuit according to claim 8, characterized in that: Also includes: In the non-test mode, the second signal selection unit is controlled to output the output signal of the insertion point in the module to be tested to the subsequent load circuit.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the control method according to any one of claims 9 to 10 are executed.
12. A chip, characterized in that: include: Arithmetic units or logic units, including insertion points in the module to be tested; The test circuit according to any one of claims 1 to 7; At least one subsequent load circuit.