Insertion method of sub-resolution auxiliary graph

Abstract

The invention provides a method for inserting a sub-resolution auxiliary pattern, which comprises the following steps of: correcting an isolated or semi-isolated sub-pattern by adopting a reverse photoetching technology to obtain a free-form layout pattern inserted at the periphery of the sub-pattern, and then replacing the free-form layout pattern by utilizing a rectangular sub-resolution auxiliary pattern combination to obtain a sub-resolution auxiliary pattern. The rectangular sub-resolution auxiliary graph combination comprises a plurality of rectangular sub-resolution auxiliary graphs, a gap is formed between every two adjacent rectangular sub-resolution auxiliary graphs, and finally carrying out ring-like fitting on the rectangular sub-resolution auxiliary graph combination to obtain a closed ring-like sub-resolution auxiliary graph. And the ring-like sub-resolution auxiliary graph is used for replacing a rectangular sub-resolution auxiliary graph combination to be nested and inserted on the peripheries of all sub-graphs in sequence, so that the problems that a traditional sub-resolution auxiliary graph insertion method is long in time period and small in process window, an actual graph is easy to generate a relatively large fillet, and the processing cost is low are solved. Therefore, the problem of process difference caused by different pattern densities of the integrated circuit layout is solved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device manufacturing technology, in particular to a method for inserting sub-resolution auxiliary graphics. Background Art

[0002] The process window (PW) is very important in the photolithography process. The size of the process window directly affects the yield of semiconductor device manufacturing. The larger the process window, the higher the semiconductor manufacturing yield. Sub-resolution assist features (SRAF) are added between semi-isolated or isolated layout patterns to increase the process window and avoid the process differences caused by different pattern densities in the integrated circuit layout due to rounded corners at the right angles of the layout caused by optical diffraction during the photolithography process, thereby reducing or even avoiding the resulting poor functionality of contact holes and process defects between patterns.

[0003] like Figure 1 and Figure 2 As shown, for isolated sub-graphs in the layout graph (such as Figure 1 ) and semi-isolated sub-graphs (such as Figure 2 When performing traditional sub-resolution auxiliary graphic insertion (as shown in the figure), in order to avoid the inserted sub-resolution auxiliary graphics being exposed and developed to produce unnecessary graphics, causing defects and affecting the semiconductor manufacturing yield, a rule-based sub-resolution auxiliary graphic insertion method is mainly adopted. Specifically, when the spacing between sub-graphics 1 is greater than or equal to a preset value, a rectangular sub-resolution auxiliary graphic combination 2 is added, and there is a gap between adjacent rectangular sub-resolution auxiliary graphics 3. The characteristic parameters included in the insertion rule mainly include the width of the rectangular sub-resolution auxiliary graphic, the spacing between adjacent rectangular sub-resolution auxiliary graphic combinations, the spacing between the sub-graphics of the rectangular sub-resolution auxiliary graphic combination to the layout graphic, and the number of rectangular sub-resolution auxiliary graphics added.

[0004] The shapes and types of sub-resolution auxiliary graphics in the rule-based sub-resolution auxiliary graphics insertion method are simple, and the establishment of rules is relatively dependent on the experience of engineers and the data of semiconductor manufacturing production lines. It often takes multiple iterations based on the experience of engineers to obtain more appropriate parameters. The time cycle is long and the process window is small, which reduces the semiconductor manufacturing yield and prolongs the semiconductor manufacturing cycle. In addition, since there are gaps between adjacent rectangular sub-resolution auxiliary graphics, the graphics actually formed on the wafer are prone to produce larger fillets at the corresponding positions of the gaps, resulting in process differences in the integrated circuit layout due to different graphic densities. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for inserting a sub-resolution auxiliary graphic, which is used to solve the problems that the traditional sub-resolution auxiliary graphic insertion method in the prior art has a long time period and a small process window, reduces the semiconductor manufacturing yield, and prolongs the semiconductor manufacturing cycle. In addition, since there are gaps between adjacent rectangular sub-resolution auxiliary graphics, the actual graphics are prone to produce larger rounded corners at the corresponding positions of the gaps, which leads to process differences in the integrated circuit layout due to different graphic densities.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for inserting a sub-resolution auxiliary graphic, the method comprising:

[0007] S1, selecting a layout graphic, wherein the layout graphic includes at least one sub-graphic;

[0008] S2, modifying the layout pattern by using reverse photolithography technology to obtain at least one free-form layout pattern sequentially nested and inserted in the periphery of all the sub-patterns;

[0009] S3, replacing the free-form layout pattern with a rectangular sub-resolution auxiliary pattern combination, wherein the rectangular sub-resolution auxiliary pattern combination includes a plurality of rectangular sub-resolution auxiliary patterns, and there are gaps between adjacent rectangular sub-resolution auxiliary patterns;

[0010] S4, performing quasi-annular fitting on the rectangular sub-resolution auxiliary graphic combination to obtain a closed quasi-annular sub-resolution auxiliary graphic, and inserting the quasi-annular sub-resolution auxiliary graphic into the periphery of all the sub-graphics in sequence instead of the rectangular sub-resolution auxiliary graphic combination.

[0011] Optionally, the method for obtaining the rectangular sub-resolution auxiliary graphic combination in step S3 includes:

[0012] S31, performing closed loop fitting on all the free-form layout graphics, and extracting characteristic parameters from the obtained circular loop fitting graphics; the characteristic parameters include the spacing B between the rectangular sub-resolution auxiliary graphics combination closest to the sub-graphic and the sub-graphic, the width D of the rectangular sub-resolution auxiliary graphics, and the spacing C between two adjacent rectangular sub-resolution auxiliary graphics combinations;

[0013] S32, obtaining the rectangular sub-resolution auxiliary graphic combination according to the characteristic parameters.

[0014] Furthermore, in step S31, the least square method is used to perform closed loop fitting on the free-form layout graph.

[0015] Furthermore, the layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When (2*B+D)≤A<(2*B+C+2*D), in step S4, one of the quasi-annular sub-resolution auxiliary patterns is inserted at the periphery of each sub-pattern, and adjacent edges of two adjacent quasi-annular sub-resolution auxiliary patterns overlap.

[0016] Furthermore, the layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When (2*B+C+2*D)≤A<(2*B+2*C+3*D), in step S4, one of the quasi-annular sub-resolution auxiliary patterns is inserted on the periphery of each sub-pattern, and there is a spacing between two adjacent quasi-annular sub-resolution auxiliary patterns.

[0017] Furthermore, the layout graphic includes more than two sub-graphics, and the spacing between two adjacent sub-graphics is A. When (2*B+2*C+3*D)≤A<(2*B+3*C+4*D), in step S4, two of the quasi-annular sub-resolution auxiliary graphics are nested in sequence on the periphery of each sub-graphic, and the adjacent edges of the two outer sides of the quasi-annular sub-resolution auxiliary graphics of two adjacent sub-graphics overlap.

[0018] Furthermore, the layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When A≥(2*B+3*C+4*D), in step S4, two quasi-annular sub-resolution auxiliary patterns are sequentially nested and inserted on the periphery of each sub-pattern, and there is a spacing between the two outer quasi-annular sub-resolution auxiliary patterns of two adjacent sub-patterns.

[0019] Optionally, after step S4, the following steps are further included:

[0020] S5, simulating the layout pattern after inserting the quasi-annular sub-resolution auxiliary pattern;

[0021] S6, comparing the simulation pattern with the target pattern. If the comparison result exceeds the allowable error, adjust the correction process parameters of the reverse lithography technology in step S2, and then repeat steps S2 to S6 until the comparison result does not exceed the allowable error.

[0022] Optionally, the quasi-annular sub-resolution auxiliary pattern is formed by a plurality of edges being arranged in sequence at an inclined angle of 45°.

[0023] Optionally, the sub-pattern of the layout pattern is a through hole.

[0024] As described above, the method for inserting sub-resolution auxiliary graphics of the present invention first uses reverse lithography technology to correct isolated or semi-isolated sub-graphics to obtain a free-form layout graphic inserted on the periphery of the sub-graphic, and then uses a rectangular sub-resolution auxiliary graphic combination to replace the free-form layout graphic. The rectangular sub-resolution auxiliary graphic combination includes multiple rectangular sub-resolution auxiliary graphics, and there is a gap between adjacent rectangular sub-resolution auxiliary graphics. Finally, the rectangular sub-resolution auxiliary graphic combination is subjected to quasi-annular fitting to obtain a closed quasi-annular sub-resolution auxiliary graphic, and the quasi-annular sub-resolution auxiliary graphic replaces the rectangular sub-resolution auxiliary graphic combination and is sequentially nested and inserted on the periphery of all sub-graphics, thereby solving the problems of the traditional sub-resolution auxiliary graphic insertion method in the prior art having a long time cycle and a small process window, affecting the semiconductor manufacturing yield and lengthening the semiconductor manufacturing cycle, and because there is a gap between adjacent rectangular sub-resolution auxiliary graphics, the actual graphic is prone to produce larger rounded corners at the position corresponding to the gap, thereby leading to the problem of process differences caused by different graphic densities in the integrated circuit layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram showing the prior art of inserting sub-resolution auxiliary graphics into an isolated sub-graphic.

[0026] Figure 2 It is a schematic diagram showing the prior art of inserting sub-resolution auxiliary graphics into a semi-isolated sub-graphic.

[0027] Figure 3 FIG. 1 is a flow chart of a method for inserting a sub-resolution auxiliary pattern according to the present invention.

[0028] Figures 4 to 6 It is a schematic diagram showing the steps of the method for inserting a sub-resolution auxiliary pattern into an isolated sub-pattern according to the present invention.

[0029] Figure 7 It is a schematic diagram showing the actual pattern obtained after inserting a ring-like sub-resolution auxiliary pattern into an isolated sub-pattern according to the present invention.

[0030] Figure 8 It is a schematic diagram showing an actual pattern obtained after inserting a quasi-annular sub-resolution auxiliary pattern when the spacing A between two adjacent semi-isolated sub-patterns satisfies A≥(2*B+3*C+4*D) according to the present invention.

[0031] Figures 9 to 11 It is a schematic diagram showing the steps of inserting a quasi-annular sub-resolution auxiliary pattern when the spacing A between two adjacent semi-isolated sub-patterns satisfies (2*B+2*C+3*D)≤A<(2*B+3*C+4*D) according to the present invention.

[0032] Fig.12 It is a schematic diagram of the actual graphics obtained after inserting a quasi-annular sub-resolution auxiliary graphics when the spacing A between two adjacent semi-isolated layout graphics satisfies (2*B+2*C+3*D)≤A<(2*B+3*C+4*D) according to the present invention.

[0033] Fig.13 It shows a schematic diagram of the present invention performing a quasi-annular sub-resolution auxiliary graphic insertion and the actual graphic obtained when the spacing A between two adjacent semi-isolated layout graphics satisfies (2*B+C+2*D)≤A<(2*B+2*C+3*D).

[0034] Fig.14 It shows a schematic diagram of inserting a quasi-annular sub-resolution auxiliary pattern and the actual pattern obtained when the spacing A between two adjacent semi-isolated layout patterns satisfies (2*B+D)≤A<(2*B+C+2*D) according to the present invention.

[0035] Component number description

[0036] 1. 10 sub-graphics

[0037] 2. 12 rectangular sub-resolution auxiliary graphics combination

[0038] 3. 120 rectangular sub-resolution auxiliary graphics

[0039] 11 Free-form layout graphics

[0040] 13 types of circular sub-resolution auxiliary graphics

[0041] 14 Actual graphics

[0042] Steps S1 to S4 DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] See also Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] like Figure 3 As shown, this embodiment provides a method for inserting a sub-resolution auxiliary graphic, and the insertion method includes:

[0046] S1, selecting a layout graphic, wherein the layout graphic includes at least one sub-graphic;

[0047] S2, modifying the layout pattern by using reverse photolithography technology to obtain at least one free-form layout pattern sequentially nested and inserted in the periphery of all the sub-patterns;

[0048] S3, replacing the free-form layout pattern with a rectangular sub-resolution auxiliary pattern combination, wherein the rectangular sub-resolution auxiliary pattern combination includes a plurality of rectangular sub-resolution auxiliary patterns, and there are gaps between adjacent rectangular sub-resolution auxiliary patterns;

[0049] S4, performing quasi-annular fitting on the rectangular sub-resolution auxiliary graphic combination to obtain a closed quasi-annular sub-resolution auxiliary graphic, and inserting the quasi-annular sub-resolution auxiliary graphic into the periphery of all the sub-graphics in sequence instead of the rectangular sub-resolution auxiliary graphic combination.

[0050] The method for inserting sub-resolution auxiliary graphics of the present embodiment first uses the reverse lithography technology to correct the isolated or semi-isolated sub-graphics to obtain a free-form layout graphic inserted at the periphery of the sub-graphics, and then uses a rectangular sub-resolution auxiliary graphic combination to replace the free-form layout graphic. The rectangular sub-resolution auxiliary graphic combination includes a plurality of rectangular sub-resolution auxiliary graphics, and there is a gap between adjacent rectangular sub-resolution auxiliary graphics. Finally, the rectangular sub-resolution auxiliary graphic combination is subjected to quasi-annular fitting to obtain a closed quasi-annular sub-resolution auxiliary graphic, and the quasi-annular sub-resolution auxiliary graphic is sequentially nested and inserted at the periphery of all sub-graphics instead of the rectangular sub-resolution auxiliary graphic combination, so as to solve the problems that the traditional sub-resolution auxiliary graphic insertion method in the prior art has a long time cycle and a small process window, which affects the semiconductor manufacturing yield and prolongs the semiconductor manufacturing cycle. In addition, since there is a gap between adjacent rectangular sub-resolution auxiliary graphics, the actual graphic is prone to produce a larger rounded corner at the position corresponding to the gap, thereby causing the process difference caused by different graphic densities in the integrated circuit layout.

[0051] The method for inserting sub-resolution auxiliary graphics of this embodiment is described in detail below with reference to specific drawings.

[0052] like Figure 4 As shown, step S1 is first performed to select a layout pattern, wherein the layout pattern includes at least one sub-pattern 10 .

[0053] The sub-graphic 10 may be, for example, a through hole, and the sub-graphic 10 is an isolated graphic or a semi-isolated graphic relative to a dense graphic selected based on a predetermined rule, wherein the predetermined rule may be, for example, that the spacing between adjacent sub-graphics 10 is greater than or equal to a predetermined value, and the predetermined value is set according to actual process requirements and is not overly limited here.

[0054] like Figure 4 As shown, step S2 is then performed to modify the layout pattern using reverse photolithography technology to obtain at least one free-form layout pattern 11 sequentially nested and inserted in the periphery of all the sub-patterns 10.

[0055] Inverse Lithography Technology (ILT) is a technology that obtains corresponding layout graphics by inverting and calculating target graphics on a wafer; the free-form layout graphics 11 serve as sub-resolution auxiliary graphics, and their number and form are related to the shape and size of the target graphics on the wafer and the modified process parameters of the inverse lithography technology.

[0056] like Figure 5 As shown, step S3 is then performed to replace the free-form layout pattern 11 with a rectangular sub-resolution auxiliary pattern combination 12; the rectangular sub-resolution auxiliary pattern combination 12 includes a plurality of rectangular sub-resolution auxiliary patterns 120, and there are gaps between adjacent rectangular sub-resolution auxiliary patterns 120.

[0057] As a preferred example, the method for obtaining the rectangular sub-resolution auxiliary graphic combination 12 in step S3 includes:

[0058] S31, using a least squares method such as the one described above to perform closed circle fitting on all the free-form layout graphics 11, and extracting characteristic parameters from the obtained circle fitting graphics; the characteristic parameters include the spacing B between the rectangular sub-resolution auxiliary graphic combination 12 closest to the sub-graphic 10 and the sub-graphic 10, the width D of the rectangular sub-resolution auxiliary graphic 120, and the spacing C between two adjacent rectangular sub-resolution auxiliary graphic combinations 12.

[0059] It should be noted here that the spacing B between the rectangular sub-resolution auxiliary graphic combination 12 closest to the sub-graphic 10 and the sub-graphic 10 and the spacing C between two adjacent rectangular sub-resolution auxiliary graphic combinations 12 refer to the minimum distance between target objects.

[0060] As a specific example of extracting the spacing C between adjacent rectangular sub-resolution auxiliary pattern combinations 12 in the characteristic parameters, the reverse photolithography technology is used to correct the layout pattern in step S2, and based on the shape and size of the target pattern and the corrected process parameters of the reverse photolithography technology, for example, two or more free-form layout patterns 11 can be obtained that are sequentially nested and inserted in the periphery of the sub-pattern 10. In step S31, closed ring fitting is performed on the two or more free-form layout patterns 11 to obtain two or more concentric ring fitting patterns, and the characteristic parameters of the spacing C between adjacent rectangular sub-resolution auxiliary pattern combinations 12 are extracted from the two or more concentric ring fitting patterns.

[0061] It should be noted that the obtained characteristic parameters can be used as rules for the sub-resolution auxiliary pattern insertion method, in which the spacing C between adjacent rectangular sub-resolution auxiliary pattern combinations 12 can be applied to the spacing between adjacent rectangular sub-resolution auxiliary pattern combinations 12 at the periphery of different sub-patterns 10. Based on the rules, when modifying a layout pattern including more than two semi-isolated sub-patterns 10, the inserted sub-resolution auxiliary pattern can be appropriately adjusted according to the spacing between two adjacent sub-patterns 10.

[0062] S32, obtaining the rectangular sub-resolution auxiliary graphic combination 12 according to the characteristic parameters.

[0063] like Figure 6 As shown, step S4 is then performed to perform quasi-annular fitting on the rectangular sub-resolution auxiliary graphic combination 12 to obtain a closed quasi-annular sub-resolution auxiliary graphic 13, and the quasi-annular sub-resolution auxiliary graphic 13 is inserted into the periphery of all the sub-graphics in sequence instead of the rectangular sub-resolution auxiliary graphic combination 12.

[0064] This embodiment is described by taking the two free-form layout graphics 11 obtained in step S2 as an example. Figure 4 As shown, the two free-form layout patterns 11 include an inner free-form layout pattern and an outer free-form layout pattern which are sequentially nested and inserted into the outer periphery of the sub-pattern 10; Figure 5 As shown, the rectangular sub-resolution auxiliary graphic combination 12 obtained at the corresponding position includes an inner rectangular sub-resolution auxiliary graphic combination and an outer rectangular sub-resolution auxiliary graphic combination sequentially nested and inserted in the periphery of the sub-graphic 10; Figure 6 As shown, the quasi-annular sub-resolution auxiliary pattern 13 includes an inner quasi-annular sub-resolution auxiliary pattern and an outer quasi-annular sub-resolution auxiliary pattern which are sequentially nested and inserted in the outer periphery of the sub-pattern 10 .

[0065] As a preferred example, the quasi-annular sub-resolution auxiliary graphic 13 used in this embodiment is composed of multiple edges arranged in sequence at an inclined angle of 45° to form a closed quasi-annular sub-resolution auxiliary graphic 13 inserted on the periphery of the layout graphic, which can not only meet the requirements of the layout manufacturing process, but also improve the process window of the layout graphic.

[0066] As an example, generally speaking, step S4 also includes:

[0067] S5, simulating the layout pattern after inserting the quasi-annular sub-resolution auxiliary pattern 13;

[0068] S6, comparing the simulation pattern with the target pattern. If the comparison result exceeds the allowable error, adjust the correction process parameters of the reverse lithography technology in step S2, and then repeat steps S2 to S6 until the comparison result does not exceed the allowable error.

[0069] like Figure 7 FIG. 1 is a schematic diagram of an actual pattern 14 obtained on a wafer after the sub-pattern 10 is modified by the above insertion method. Since the closed annular sub-resolution auxiliary pattern 13 is used to replace the prior art sub-pattern 14, the sub-pattern 14 is formed on the wafer. Figure 1 In the rectangular sub-resolution auxiliary pattern combination 2 shown in the figure, the gaps between adjacent rectangular sub-resolution auxiliary patterns 3 are filled, so that the actual pattern 14 has a smaller rounded corner, reducing or even avoiding the process differences caused by different pattern densities in the integrated circuit layout.

[0070] When the layout pattern includes more than two semi-isolated sub-patterns 10, it is necessary to first determine the relationship between the spacing between two adjacent sub-patterns 10 and the rule for inserting sub-resolution auxiliary patterns, and appropriately adjust the inserted sub-resolution auxiliary patterns according to the determination result. Here, it is defined that the spacing between two adjacent semi-isolated sub-patterns 10 is A, and A refers to the minimum spacing between two adjacent semi-isolated sub-patterns 10. Figures 8 to 14 As shown, this embodiment is described by taking three semi-isolated sub-graphs 10 as an example.

[0071] As an example, Figure 8As shown, when A≥(2*B+3*C+4*D), when inserting the sub-resolution auxiliary pattern into the sub-pattern 10, the specific method is the same as the method for inserting the isolated sub-pattern 10 in the layout pattern in the above embodiment, which will not be repeated here. However, due to the spacing limit between two adjacent semi-isolated sub-patterns 10, two quasi-annular sub-resolution auxiliary patterns 13 are used in step S4 to be nested and inserted in sequence on the periphery of each sub-pattern 10, and there is a gap between the two outer quasi-annular sub-resolution auxiliary patterns 13 of the two adjacent sub-patterns 10. After the semi-isolated sub-pattern 10 is corrected by the insertion method, the actual pattern 14 obtained on the wafer is as shown in FIG. Figure 8 As shown, since the closed annular sub-resolution auxiliary pattern 13 is used to replace the rectangular sub-resolution auxiliary pattern combination 12, the gaps between adjacent rectangular sub-resolution auxiliary patterns 120 are filled, so that the actual pattern 14 has a smaller rounded corner, which reduces or even avoids the process differences caused by different pattern densities in the integrated circuit layout, thereby reducing or even avoiding the resulting poor functionality of the contact holes and process defects between the patterns.

[0072] As an example, Figures 9 to 11 As shown, when the distance between two adjacent semi-isolated sub-patterns 10 continues to decrease to (2*B+2*C+3*D)≤A<(2*B+3*C+4*D), the method for inserting sub-resolution auxiliary patterns into the sub-patterns 10 includes: Fig. 9 As shown, a layout pattern is selected, the layout pattern includes more than two sub-patterns 10; the spacing between two adjacent semi-isolated sub-patterns 10 is (2*B+2*C+3*D)≤A<(2*B+3*C+4*D); then the semi-isolated sub-patterns 10 are corrected by using reverse lithography technology to obtain two free-form layout patterns 11 sequentially nested and inserted in the periphery of all the sub-patterns 10; as shown Fig.10 As shown, the free-form layout pattern 11 is replaced by a rectangular sub-resolution auxiliary pattern combination 12; the rectangular sub-resolution auxiliary pattern combination 12 includes a plurality of rectangular sub-resolution auxiliary patterns 120, and there is a gap between adjacent rectangular sub-resolution auxiliary patterns 120; as shown Fig.11As shown, the rectangular sub-resolution auxiliary pattern combination 12 is subjected to quasi-annular fitting to obtain a closed quasi-annular sub-resolution auxiliary pattern 13, and the quasi-annular sub-resolution auxiliary pattern 13 is sequentially nested and inserted in the periphery of all the sub-patterns 10 instead of the rectangular sub-resolution auxiliary pattern combination 12. Due to the spacing limit between two adjacent semi-isolated sub-patterns 10, two quasi-annular sub-resolution auxiliary patterns 13 are sequentially nested and inserted in the periphery of each sub-pattern 10, and the adjacent sides of the two outer sides of the quasi-annular sub-resolution auxiliary patterns 13 of two adjacent sub-patterns 10 overlap.

[0073] As an example, Fig.12 As shown, it is a schematic diagram of the actual pattern 14 obtained on the wafer after the semi-isolated sub-pattern 10 is corrected by the above-mentioned insertion method when (2*B+2*C+3*D)≤A<(2*B+3*C+4*D). Since the annular sub-resolution auxiliary pattern 13 is used to replace the rectangular sub-resolution auxiliary pattern combination 12, the gaps between adjacent rectangular sub-resolution auxiliary patterns 120 are filled, so that the actual pattern 14 has a smaller rounded corner, which reduces or even avoids the process differences caused by different pattern densities in the integrated circuit layout, thereby reducing or even avoiding the resulting poor functionality of the contact holes and process defects between patterns.

[0074] As an example, Fig.13 As shown, when the spacing between two adjacent semi-isolated sub-patterns 10 is (2*B+C+2*D)≤A<(2*B+2*C+3*D), when the semi-isolated sub-patterns 10 are corrected by using sub-resolution auxiliary patterns, due to the spacing limit between the two adjacent semi-isolated sub-patterns 10, a quasi-annular sub-resolution auxiliary pattern 13 is inserted at the periphery of each sub-pattern 10 in step S4, and there is a gap between the two adjacent quasi-annular sub-resolution auxiliary patterns 13. The obtained actual pattern 14 has a smaller rounded corner, which reduces or even avoids the process difference caused by different pattern densities in the integrated circuit layout, thereby reducing or even avoiding the poor functionality of the contact hole and the process defects between patterns caused by this.

[0075] As an example, Fig.14As shown, when the spacing between two adjacent sub-patterns 10 continues to decrease to (2*B+D)≤A<(2*B+C+2*D), when the semi-isolated sub-patterns 10 are corrected by using sub-resolution auxiliary patterns, due to the spacing limit between the two adjacent semi-isolated sub-patterns 10, a quasi-annular sub-resolution auxiliary pattern 13 is inserted at the periphery of each sub-pattern 10 in step S4, and the adjacent sides of the two adjacent quasi-annular sub-resolution auxiliary patterns 13 overlap. The obtained actual pattern 14 has a smaller rounded corner, which reduces or even avoids the process difference caused by different pattern densities in the integrated circuit layout, thereby reducing or even avoiding the poor functionality of the contact holes and process defects between patterns caused by this.

[0076] In summary, the method for inserting sub-resolution auxiliary graphics of the present invention first uses reverse lithography technology to correct isolated or semi-isolated sub-graphics to obtain a free-form layout graphic inserted in the periphery of the sub-graphics, and then uses a rectangular sub-resolution auxiliary graphic combination to replace the free-form layout graphic, the rectangular sub-resolution auxiliary graphic combination includes multiple rectangular sub-resolution auxiliary graphics, and there is a gap between adjacent rectangular sub-resolution auxiliary graphics, and finally performs quasi-annular fitting on the rectangular sub-resolution auxiliary graphic combination to obtain a closed quasi-annular sub-resolution auxiliary graphic, and the quasi-annular sub-resolution auxiliary graphic replaces the rectangular sub-resolution auxiliary graphic combination and is sequentially nested and inserted in the periphery of all sub-graphics, so as to solve the problem that the traditional sub-resolution auxiliary graphic insertion method in the prior art has a long time cycle and a small process window, which affects the semiconductor manufacturing yield and prolongs the semiconductor manufacturing cycle, and because there is a gap between adjacent rectangular sub-resolution auxiliary graphics, the actual graphic is prone to produce a large rounded corner at the corresponding position of the gap, thereby causing the problem of process differences caused by different graphic densities in the integrated circuit layout. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for inserting a sub-resolution auxiliary graphic, characterized in that: The insertion method comprises: S1, selecting a layout graphic, wherein the layout graphic includes at least one sub-graphic; S2, modifying the layout pattern by using reverse photolithography technology to obtain at least one free-form layout pattern sequentially nested and inserted in the periphery of all the sub-patterns; S3, replacing the free-form layout pattern with a rectangular sub-resolution auxiliary pattern combination, wherein the rectangular sub-resolution auxiliary pattern combination includes a plurality of rectangular sub-resolution auxiliary patterns, and there are gaps between adjacent rectangular sub-resolution auxiliary patterns; S4, performing quasi-annular fitting on the rectangular sub-resolution auxiliary graphic combination to obtain a closed quasi-annular sub-resolution auxiliary graphic, and inserting the quasi-annular sub-resolution auxiliary graphic into the periphery of all the sub-graphics in sequence instead of the rectangular sub-resolution auxiliary graphic combination.

2. The method for inserting a sub-resolution auxiliary graphic according to claim 1, characterized in that: The method for obtaining the rectangular sub-resolution auxiliary graphic combination in step S3 includes: S31, performing closed loop fitting on all the free-form layout graphics, and extracting characteristic parameters from the obtained circular loop fitting graphics; the characteristic parameters include the spacing B between the rectangular sub-resolution auxiliary graphics combination closest to the sub-graphic and the sub-graphic, the width D of the rectangular sub-resolution auxiliary graphics, and the spacing C between two adjacent rectangular sub-resolution auxiliary graphics combinations; S32, obtaining the rectangular sub-resolution auxiliary graphic combination according to the characteristic parameters.

3. The method for inserting a sub-resolution auxiliary graphic according to claim 2, characterized in that: In step S31, the least square method is used to perform closed loop fitting on the free-form layout graph.

4. The method for inserting a sub-resolution auxiliary pattern according to claim 2, characterized in that: The layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When (2*B+D)≤A<(2*B+C+2*D), in step S4, one of the quasi-annular sub-resolution auxiliary patterns is inserted at the periphery of each sub-pattern, and the adjacent edges of two adjacent quasi-annular sub-resolution auxiliary patterns overlap.

5. The method for inserting a sub-resolution auxiliary graphic according to claim 2, characterized in that: The layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When (2*B+C+2*D)≤A<(2*B+2*C+3*D), in step S4, one of the quasi-annular sub-resolution auxiliary patterns is inserted on the periphery of each sub-pattern, and there is a spacing between two adjacent quasi-annular sub-resolution auxiliary patterns.

6. The method for inserting a sub-resolution auxiliary pattern according to claim 2, characterized in that: The layout graphic includes more than two sub-graphics, and the spacing between two adjacent sub-graphics is A. When (2*B+2*C+3*D)≤A<(2*B+3*C+4*D), in step S4, two quasi-annular sub-resolution auxiliary graphics are used to be nested and inserted in sequence on the periphery of each sub-graphic, and the adjacent edges of the two outer sides of the quasi-annular sub-resolution auxiliary graphics of two adjacent sub-graphics overlap.

7. The method for inserting a sub-resolution auxiliary graphic according to claim 2, characterized in that: The layout pattern includes more than two sub-patterns, and the spacing between two adjacent sub-patterns is A. When A≥(2*B+3*C+4*D), in step S4, two quasi-annular sub-resolution auxiliary patterns are used to be nested and inserted in sequence on the periphery of each sub-pattern, and there is a spacing between the two outer quasi-annular sub-resolution auxiliary patterns of two adjacent sub-patterns.

8. The method for inserting sub-resolution auxiliary graphics according to claim 1, characterized in that: After step S4, the following steps are also included: S5, simulating the layout pattern after inserting the quasi-annular sub-resolution auxiliary pattern; S6, comparing the simulation pattern with the target pattern. If the comparison result exceeds the allowable error, adjust the correction process parameters of the reverse lithography technology in step S2, and then repeat steps S2 to S6 until the comparison result does not exceed the allowable error.

9. The method for inserting a sub-resolution auxiliary pattern according to claim 1, characterized in that: The quasi-annular sub-resolution auxiliary pattern is formed by a plurality of edges being arranged in sequence at an inclined angle of 45°.

10. The method for inserting sub-resolution auxiliary graphics according to claim 1, characterized in that: The sub-pattern of the layout pattern is a through hole.

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