Deviation rectification alignment method and device applied to direct writing photoetching machine, medium and photoetching machine

Abstract

The invention discloses a deviation rectification and alignment method and device applied to a direct-writing photoetching machine, a medium and a photoetching machine.The deviation rectification and alignment method applied to the direct-writing photoetching machine comprises the steps that when a medium layer has deviation rectification requirements, partition rigid transformation parameters of chip theoretical patterns in the medium layer corresponding to chips in a chip layer are obtained; the partition rigid transformation parameter comprises displacement; obtaining the iteration displacement step length based on the displacement of the chip theoretical pattern in the dielectric layer corresponding to each chip; the position of the chip theoretical pattern in the dielectric layer corresponding to each chip is corrected based on the iteration displacement step length until the dielectric layer and the chip layer meet a first condition, the chip theoretical pattern in the dielectric layer moves in the vector direction of the displacement during correction, and the dielectric layer and the chip layer meet a second condition; the vector direction is the direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the chip corresponding to the chip layer. According to the method provided by the invention, the alignment precision in a multi-chip packaging process is improved, and the condition of inaccurate pattern alignment caused by patch errors is corrected.

Description

Technical Field

[0001] The present invention relates to the technical field of photolithography machines, and in particular to a method for correcting and aligning a direct-write photolithography machine, as well as a correcting and aligning control device, a computer-readable storage medium and a direct-write photolithography machine. Background Art

[0002] With the development of chip packaging technology, especially in advanced packaging, the interconnection of multiple chips plays a vital role in improving chip performance. In the packaging process of multi-chip interconnection, due to patch errors, it is difficult to ensure that the dielectric layer and the line layer (RDL, Redistribution Layer) are accurately aligned with the pads on each chip in the subsequent process, resulting in inaccurate pattern alignment, holes or poor connections, etc., affecting the production yield of the chip.

[0003] In the prior art, although the equipment based on direct-write lithography technology has flexible exposure capabilities, the algorithm for graphic correction has poor adaptability when facing high-density interconnection of multiple chips, and it is difficult to cope with the complex changes caused by chip patch errors. This leads to low pattern exposure accuracy and cannot meet the requirements of the packaging process for high-precision alignment. When performing multi-chip packaging, traditional step-and-step lithography equipment can only perform global rigid transformations by adjusting the position of the mask template. This method can only perform global adjustments and cannot perform fine local corrections on each chip. As a result, the tolerance for the patch errors of each chip is low, and it cannot effectively cope with the complex situation of high-density interconnection of multiple chips, resulting in a low process yield. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to propose a correction and alignment method applied to a direct writing lithography machine, which improves the alignment accuracy in the multi-chip packaging process, corrects the inaccurate pattern alignment caused by patch errors, and enhances the tolerance to chip patch errors, thereby improving the reliability and stability of the packaging process and improving the production yield.

[0005] The second objective of the present invention is to provide a deviation correction and alignment control device for a direct writing lithography machine.

[0006] A third object of the present invention is to provide a computer-readable storage medium.

[0007] The fourth objective of the present invention is to provide a direct writing lithography machine.

[0008] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a correction and alignment method for a direct-write lithography machine, comprising: in a first exposure process, the chip layer and the dielectric layer are aligned to meet a first condition, the first condition comprising that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold; when the dielectric layer has a correction requirement, the partitioned rigid transformation parameters of each chip in the chip layer corresponding to the theoretical chip pattern in the dielectric layer are obtained, the partitioned rigid transformation parameters comprising displacement; an iterative displacement step is obtained based on the displacement of each chip corresponding to the theoretical chip pattern in the dielectric layer; based on the iterative displacement step, the position of each chip corresponding to the theoretical chip pattern in the dielectric layer is corrected until the dielectric layer and the chip layer meet the first condition, wherein during correction, the theoretical chip pattern in the dielectric layer moves along the vector direction of the displacement, and the vector direction is the direction from the center coordinate of the theoretical chip pattern on the dielectric layer to the center coordinate of the chip corresponding to the chip layer.

[0009] According to the correction and alignment method applied to the direct writing lithography machine of the embodiment of the present invention, when there is a correction demand for the dielectric layer, that is, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, first obtain the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer, wherein the parameter contains displacement information, so as to realize local adjustment for different chip patch errors, rather than relying solely on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical pattern of the chip on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, and finally ensure that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the method of the present invention can effectively compensate for the patch errors between different chips by combining partition rigid transformation with iterative displacement step correction, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip patch errors, and thus improve the production yield.

[0010] In some embodiments, obtaining the iterative displacement step according to the displacement of each chip corresponding to the theoretical pattern of the chip in the dielectric layer includes: determining the direction angle and the modulus of the displacement of each chip corresponding to the theoretical pattern of the chip in the dielectric layer; determining the iterative displacement step according to the direction angle and the modulus and a preset number of iterations.

[0011] In some embodiments, the correction and alignment method also includes: performing a global rigid transformation on the dielectric layer based on the alignment mark points of each chip in the chip layer, wherein the alignment mark points include the alignment points on each chip and the center coordinate points of each chip, and the center coordinate points are obtained based on the alignment points on the corresponding chip; obtaining a first distance between each chip and the center coordinates of the theoretical pattern of the corresponding chip in the dielectric layer after the global rigid transformation; when the first distance is greater than or equal to the first center distance threshold, determining that the dielectric layer has a correction requirement.

[0012] In some embodiments, the partitioned rigid transformation parameters include the rotation angle of each chip corresponding to the theoretical pattern of the chip in the dielectric layer, and the correction and alignment method also includes: obtaining the iterative rotation angle of each chip; during correction, correcting the rotation angle corresponding to the theoretical pattern of the chip in the dielectric layer based on the iterative rotation angle of each chip.

[0013] In some embodiments, obtaining the iterative rotation angle of each chip includes: obtaining the actual offset angle of each chip; and obtaining the iterative rotation angle of each chip according to the actual offset angle, the rotation angle of the global rigid transformation of the medium layer, and a preset number of iterations.

[0014] In some embodiments, the deflection correction and alignment method also includes: in the second exposure process, the circuit layer and the dielectric layer are aligned to meet a second condition, and the second condition includes that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than a second center distance threshold; obtaining the global rigid transformation parameters of the circuit layer; when the global rigid transformation parameters make the second exposure process meet the second condition, the deflection correction of the dielectric layer is completed; or, when the global rigid transformation parameters make the second exposure process fail to meet the second condition, the deflection correction of the dielectric layer fails.

[0015] In order to achieve the above-mentioned objectives, the second aspect of the present invention provides an embodiment of a deflection correction and alignment control device applied to a direct-write lithography machine, comprising: at least one processor; a memory communicatively connected to the at least one processor; the memory stores a computer program executable by the at least one processor, and when the at least one processor executes the computer program, the deflection correction and alignment method applied to the direct-write lithography machine described in the above embodiment is implemented.

[0016] According to the deflection correction and alignment control device applied to the direct writing lithography machine of the embodiment of the present invention, at least one processor implements the deflection correction and alignment method applied to the direct writing lithography machine described in the above embodiment by executing a computer program. When there is a deflection correction demand in the dielectric layer, that is, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, first obtain the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer, wherein the parameter contains displacement information, so as to realize local adjustment for different chip patch errors, rather than relying only on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinate of the theoretical pattern of the chip on the dielectric layer gradually approaches the center coordinate of the corresponding chip in the chip layer, and finally ensures that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, and satisfies the first condition. Therefore, the method of the present invention can effectively compensate for the patch errors between different chips by combining partition rigid transformation with iterative displacement step correction, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip patch errors, and thus improve the production yield.

[0017] In order to achieve the above-mentioned purpose, a computer-readable storage medium of an embodiment of the third aspect of the present invention stores a computer program thereon, and when the computer program is executed, the deviation correction and alignment method applied to a direct-write lithography machine described in the above embodiment is implemented.

[0018] According to the computer-readable storage medium of an embodiment of the present invention, by adopting the correction and alignment method applied to the direct-write lithography machine described in the above embodiment, the alignment accuracy in the multi-chip packaging process is improved, the inaccurate pattern alignment caused by chip mounting errors is corrected, and the tolerance to chip mounting errors is enhanced, thereby improving the reliability and stability of the packaging process and improving the production yield.

[0019] In order to achieve the above-mentioned purpose, the direct-writing lithography machine of the fourth aspect of the embodiment of the present invention includes the deflection correction and alignment control device applied to the direct-writing lithography machine as described in the above embodiment; or, the direct-writing lithography machine includes a deflection correction and alignment system and a control system, and the control system is connected to the deflection correction and alignment system, and the control system is used to control the deflection correction and alignment system according to the deflection correction and alignment method applied to the direct-writing lithography machine as described in the above embodiment.

[0020] According to the direct writing lithography machine of the embodiment of the present invention, the control system is connected with the correction and alignment system, and the correction and alignment system is controlled by adopting the correction and alignment method applied to the direct writing lithography machine described in the above embodiment. Specifically, when there is a correction demand for the dielectric layer, that is, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer are first obtained, wherein the parameter contains displacement information to achieve local adjustment for different chip patch errors, rather than relying solely on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical pattern of the chip on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, and finally ensure that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the direct-write lithography machine of the present invention can effectively compensate for the patch errors between different chips by combining partitioned rigid transformation and iterative displacement step correction, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip patch errors, and thus improve the production yield.

[0021] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a flow chart of a method for correcting and aligning a direct-write lithography machine according to an embodiment of the present invention; Figure 2 (a) is a schematic diagram of four chip placement theoretical patterns according to an embodiment of the present invention; Figure 2 (b) is a schematic diagram of four chips having mounting errors according to an embodiment of the present invention; Figure 3 is a schematic diagram of the relative positions of an offset chip with a patch error in a chip layer and a theoretical pattern of a chip in a dielectric layer according to an embodiment of the present invention; Figure 4 is a schematic diagram of performing a global rigid transformation on a dielectric layer according to an embodiment of the present invention; Figure 5is an overall flow chart of a method for correcting and aligning a direct-write lithography machine according to an embodiment of the present invention; Figure 6 1. It is a schematic diagram comparing the yield of the correction and alignment results of a direct-write lithography machine and a stepper lithography device when interconnecting multiple-region chips according to an embodiment of the present invention; Figure 7 is a block diagram of a deflection correction and alignment control device applied to a direct writing lithography machine according to an embodiment of the present invention; Figure 8 is a block diagram of a direct write lithography machine according to an embodiment of the present invention; Fig. 9 is a block diagram of a direct-write lithography machine according to yet another embodiment of the present invention.

[0023] Reference numerals: Direct writing lithography machine 100; A deflection correction and alignment control device 1 applied to a direct writing lithography machine; a deflection correction and alignment system 2; a control system 3; an exposure system 4; Processor 11; Memory 12. DETAILED DESCRIPTION

[0024] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0025] Reference below Figure 1-Figure 6 A method for correcting and aligning a direct-write lithography machine according to an embodiment of the present invention is described.

[0026] Figure 1 FIG. 1 is a flow chart of a method for correcting and aligning a direct-write lithography machine according to an embodiment of the present invention. Figure 1 As shown, the method for correcting and aligning the direct writing lithography machine includes at least steps S1-S4, which are as follows: S1, in a first exposure process, the chip layer and the dielectric layer are aligned to meet a first condition, wherein the first condition includes that a maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold.

[0027] In some embodiments, the chip layer may refer to a substrate (e.g., a silicon substrate) on which a chip structure has been formed, on which a chip pattern already exists. The dielectric layer may refer to a photoresist, an insulating dielectric, or other material layer superimposed on the chip layer, which needs to be patterned to ensure alignment with the chip layer.

[0028] In some embodiments, the chip layer may refer to a layer of substrate in the packaging process of a silicon wafer or bare chip that has completed circuit manufacturing, that is, a layer formed by chips after wafer dicing, chip testing, preliminary packaging or bonding. In the packaging process, the chip layer may include each independent chip and key patterns pre-formed on the chip, such as alignment marks, pads, etc.

[0029] In some embodiments, the chip layer is the basis of the entire packaging process, and its alignment accuracy directly determines the alignment effect of the subsequent dielectric layer and circuit layer. The pre-defined patterns and alignment marks on the chip layer provide reference information for subsequent alignment correction, ensuring that the pattern of the dielectric layer can be accurately aligned with the key areas (such as pads) on the chip, thereby ensuring that the packaged chip can achieve correct electrical interconnection and function.

[0030] In some embodiments, the dielectric layer may refer to a substrate material covering the chip layer for protection, isolation, or as a subsequent process (such as rewiring, interconnection), and common ones include a PI (Polyimide) layer, a photoresist layer, or other insulating layers.

[0031] In some embodiments, the dielectric layer not only serves as electrical isolation and mechanical support, but also needs to be patterned to form a specific structure so as to interconnect with the chip layer pattern (such as pads). Correct alignment is very important to ensure the precise connection between the dielectric layer pattern and the chip layer pattern, so the alignment accuracy directly affects the yield of the packaging process and the performance of the final chip.

[0032] In some embodiments, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern may refer to the maximum distance between the center position of each theoretical chip pattern on the dielectric layer and the center position of the actual pattern (or alignment mark) on the chip layer in the entire alignment area. This parameter reflects the overall alignment accuracy between the two layers. If the distance is large, it means that there is a large deviation in the alignment between the dielectric layer pattern and the chip layer pattern, which may cause defects such as broken holes or poor connections in subsequent processes. This value can be used as a basis for judging whether further correction is needed.

[0033] In some embodiments, the first circle center distance threshold is a preset maximum allowable overlay circle center distance, which can be determined based on specific packaging process requirements, device structure size, alignment resolution of process equipment or yield requirements, etc. Only when the maximum overlay circle center distance between the dielectric layer pattern and the chip layer pattern is less than the first circle center distance threshold can the dielectric layer pattern be accurately aligned with the key area (such as the pad) on the chip, avoiding hole breakage or connection errors caused by excessive errors, which affects the chip yield.

[0034] Therefore, the first condition serves as the basic judgment criterion in the first exposure process to determine whether further deflection correction is required to ensure that the alignment accuracy between layers has met the requirements before entering the subsequent process, thereby ensuring the stability of the entire packaging process and the performance of the final product.

[0035] S2, when there is a need for correction of the dielectric layer, obtaining partition rigid transformation parameters of each chip in the chip layer corresponding to the theoretical pattern of the chip in the dielectric layer, wherein the partition rigid transformation parameters include displacement.

[0036] In some embodiments, the need for correction of the dielectric layer can mean that after the first exposure process is completed, it is found through detection that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a preset first center distance threshold, that is, the alignment error between the dielectric layer pattern and the chip layer pattern is large, the alignment accuracy does not meet the requirements, and a subsequent correction step is required.

[0037] Specifically, Figure 2 As shown, taking the package of four chips as an example, Figure 2 (a) in the figure shows that there is no placement error when the four chips are interconnected. Figure 2 (b) in the figure indicates that due to the patch error, the four chips each have a certain rotation and translation, which requires further correction and adjustment.

[0038] In some embodiments, the theoretical pattern of the chip in the dielectric layer may refer to an ideal pattern predefined on the dielectric layer through a graphic design file such as GDS (Graphic Data System) during the design stage, and its position and shape are generated according to the design requirements of the chip layer. In other words, the position of the chip layer to which the dielectric layer should be aligned when there is no patch error. The theoretical pattern is used as a reference for correction and is compared with the actual alignment pattern (such as chip mark, pad or electrode position) on the chip layer. By comparing the positional relationship between the theoretical pattern and the actual chip pattern, the offset can be calculated and data support can be provided for correction.

[0039] In some embodiments, the partitioned rigid transformation parameters may refer to the transformation parameters obtained by independently calculating the theoretical pattern of the chip in the dielectric layer corresponding to each chip in the chip layer. This method allows local and fine adjustment of the offset error of each chip, thereby more accurately compensating for the local alignment deviation caused by the patch error.

[0040] In some embodiments, the coordinate information of the actual alignment mark point of each chip on the chip layer is obtained by a high-precision alignment detection system (such as an optical alignment system or an electron beam alignment system). At the same time, the predetermined coordinate information of the theoretical pattern of the chip in the dielectric layer is extracted from the design data. Based on these two sets of coordinate information, the offset error of each chip can be calculated, thereby determining the displacement of the theoretical pattern of the chip in the corresponding dielectric layer.

[0041] S3, obtaining an iterative displacement step length based on the displacement of the chip theoretical pattern in the dielectric layer corresponding to each chip.

[0042] In some embodiments, the iterative displacement step may refer to the distance that the theoretical pattern of the chip in the dielectric layer moves along the correction direction at each adjustment during the correction process. It is a small step applied in each iteration after decomposing the initial displacement (i.e., the offset between the theoretical pattern of the chip and the actual position of the chip), rather than correcting all of it in place at one time. By using the iterative displacement step for multiple iterative adjustments, the error between the theoretical pattern and the actual position can be gradually reduced, making the alignment process smoother and avoiding overcompensation or oscillation that may be caused by a large one-time correction. Multiple fine-tuning helps to detect and correct the residual error in each iteration, thereby ultimately achieving high-precision alignment.

[0043] S4, based on the iterative displacement step, correct the position of the chip theoretical pattern in the dielectric layer corresponding to each chip until the dielectric layer and the chip layer meet the first condition, wherein during the correction, the chip theoretical pattern in the dielectric layer moves along the displacement vector direction, and the vector direction is the direction from the center coordinate of the chip theoretical pattern on the dielectric layer to the center coordinate of the chip corresponding to the chip layer.

[0044] In some embodiments, during the correction process, the theoretical chip pattern in the dielectric layer will move in the direction from the center coordinate of the theoretical chip pattern on the dielectric layer to the center coordinate of the corresponding chip on the chip layer, because this direction is exactly the error direction between the theoretical chip pattern and the actual position of the corresponding chip. By moving in this direction, the displacement error can be compensated, so that the center of the theoretical chip pattern gradually approaches the center of the corresponding chip on the chip layer, thereby achieving accurate alignment.

[0045] According to the correction and alignment method applied to the direct writing lithography machine of the embodiment of the present invention, when there is a correction demand for the dielectric layer, that is, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, first obtain the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer, wherein the parameter contains displacement information, so as to realize local adjustment for different chip patch errors, rather than relying solely on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical pattern of the chip on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, and finally ensure that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the present invention adopts a method of iterative correction based on the center connection line of each chip in the chip layer and its corresponding dielectric layer theoretical pattern, which can effectively deal with the local patch error differences that may exist in each chip in the multi-chip interconnect packaging, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip patch errors, and thus improve the production yield.

[0046] In some embodiments, the iterative displacement step is obtained according to the displacement of the chip theoretical pattern in the dielectric layer corresponding to each chip, including: determining the direction angle and modulus of the displacement of the chip theoretical pattern in the dielectric layer corresponding to each chip, and determining the iterative displacement step according to the direction angle and modulus and a preset number of iterations.

[0047] Specifically, Figure 3 As shown in the figure, xOy is the global coordinate system used to describe the actual chip placement position and the theoretical chip pattern in the dielectric layer. Point A is the center point of the offset chip with placement error in the chip layer, and point B is the center point of the theoretical chip pattern in the dielectric layer. α represents the angular deviation of the actual chip placement position relative to the theoretical chip pattern. By establishing the xOy coordinate system, the vector and vector , where the vector Represents the position vector from the origin O to point A, vector Represents the position vector from the origin O to point B.

[0048] Furthermore, according to the vector and vector You can get vector , where the vector It is the vector pointing from point B to point A, that is, during correction, the theoretical pattern of the chip in the dielectric layer moves along the direction of this vector. It can be calculated by vector subtraction. The specific formula is as follows: ; Its modulus and direction angle can be calculated by the following formula: ; ; ; ; ; ; in, is the horizontal coordinate of point A, is the horizontal coordinate of point B, is the offset of point A relative to point B in the x direction, is the ordinate of point A, is the ordinate of point B, is the offset of point A relative to point B in the y direction, For vector The cosine value of the direction angle, L is the vector The mold length.

[0049] Furthermore, if the preset number of iterations is set to N, each displacement is decomposed into the x and y axes as follows: ; ; in, is the iterative displacement step size in the x direction for each iteration, is the iterative displacement step size in the y direction for each iteration.

[0050] Therefore, by moving along the direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the corresponding chip on the chip layer (i.e., vector direction), with iterative displacement step size and The correction is performed gradually and iterated multiple times until the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold. The theoretical chip pattern on the dielectric layer will gradually approach the actual position of the corresponding chip on the chip layer, thereby achieving precise alignment.

[0051] In some embodiments, the correction and alignment method further includes: performing a global rigid transformation on the dielectric layer based on the alignment mark points of each chip in the chip layer, wherein the alignment mark points include the alignment points on each chip and the center coordinate points of each chip, and the center coordinate points are obtained based on the alignment points on the corresponding chip. Obtain a first distance between each chip and the center coordinates of the theoretical pattern of the corresponding chip in the dielectric layer after the global rigid transformation. When the first distance is greater than or equal to the first center distance threshold, it is determined that the dielectric layer has a correction requirement.

[0052] Among them, the alignment points on each chip can be specific marks pre-set on the chip, which are used to detect and calibrate the position of the chip in the packaging process. Multiple alignment points can be set on each chip. The center coordinate point of each chip can be obtained by averaging the coordinates of multiple alignment points on the same chip or by a specific calculation method. Based on these alignment mark points, the dielectric layer is adjusted as a whole using the global rigid transformation method, that is, according to certain translation (and rotation when necessary) parameters, the pattern on the dielectric layer roughly corresponds to the alignment mark point on the chip layer, thereby preliminarily realizing the alignment between the two layers.

[0053] In some embodiments, after the global rigid transformation is completed, for each chip, there will be a corresponding chip theoretical pattern on the dielectric layer after the global rigid transformation, and its center coordinates can be calculated. Then, the system calculates the first distance, that is, the distance between the actual center coordinates of each chip on the chip layer and the center coordinates of the corresponding chip theoretical pattern in the dielectric layer after the global rigid transformation. This distance reflects the alignment error between the two layers of patterns after the global rigid transformation. If the first distance is greater than or equal to the first circle center distance threshold, it means that after the global rigid transformation, the alignment error between the two layers of patterns is still large, that is, the global rigid transformation has not yet achieved the required alignment accuracy. At this time, it is necessary to further use the partitioned rigid transformation and iterative displacement step correction method to compensate for the local error.

[0054] Specifically, the coordinates of m alignment points on each chip are measured, and the center coordinate point of each chip and the angle error caused by the patch are calculated. (i=1, 2, 3...m). The calculation formula for the center coordinate point of each chip is as follows: ; ; in, is the horizontal coordinate of the center point, The vertical coordinate of the center point. is the horizontal coordinate of the ith alignment point on the chip, is the ordinate of the ith alignment point on the chip, and m is the number of alignment points on the chip.

[0055] Furthermore, according to the coordinates of the alignment points on each chip and the center coordinates of each chip, the dielectric layer is globally rigidly transformed to adjust the position of the dielectric layer as a whole and preliminarily achieve alignment with the chip layer. Figure 4 As shown, the calculation formula of the global rigid transformation is as follows: ; in, , is the transformed chuck (controlling the moving stage) coordinate, x and y are the theoretical pattern coordinates of the chip, is the rotation angle of the global rigid transformation of the dielectric layer, tx is the translation in the x direction, and ty is the translation in the y direction.

[0056] Therefore, after the global rigid transformation, each chip theoretical pattern on the dielectric layer will obtain an updated central coordinate, that is, the central coordinate of the chip theoretical pattern after the global rigid transformation.

[0057] Furthermore, the first distance between each chip and the center coordinates of the corresponding chip theoretical pattern in the dielectric layer after global rigid transformation is calculated. If the first distance is less than the first circle center distance threshold, it means that the error after global rigid transformation has met the exposure accuracy requirements, and the dielectric layer and circuit layer can be directly exposed without further intelligent correction. If the first distance is greater than or equal to the first circle center distance threshold, it means that there is still a large error after global rigid transformation and the exposure accuracy requirements cannot be met. At this time, partition rigid transformation and iterative correction are required.

[0058] Furthermore, when it is determined that the dielectric layer needs to be corrected, the partitioned rigid transformation parameters of the chip theoretical pattern in the dielectric layer corresponding to each chip in the chip layer are obtained, and the iterative displacement step is obtained based on the partitioned rigid transformation parameters of the chip theoretical pattern in the dielectric layer corresponding to each chip. The position of the chip theoretical pattern in the dielectric layer corresponding to each chip is continuously corrected based on the iterative displacement step until the dielectric layer and the chip layer meet the first condition that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold.

[0059] In some embodiments, the partition rigid transformation parameter includes not only the displacement of the chip theoretical pattern in the medium layer corresponding to each chip in the chip layer, but also the rotation angle of the chip theoretical pattern in the medium layer corresponding to each chip. Therefore, the correction alignment method further includes: obtaining the iterative rotation angle of each chip, and during correction, correcting the rotation angle of the chip theoretical pattern in the corresponding medium layer based on the iterative rotation angle of each chip to improve the rotation alignment accuracy.

[0060] Among them, the iterative rotation angle is introduced in the partition rigid transformation parameter, so that the system can gradually correct the rotation angle of the theoretical pattern of the chip in the dielectric layer based on the iterative rotation angle of each chip, thereby realizing a dynamic rotation correction process from overall to local, from coarse adjustment to fine adjustment. This step-by-step iterative correction strategy can not only effectively compensate for the rotation offset of each chip caused by patch errors, but also avoid the instability that may be caused by a one-time large adjustment, ensure the alignment accuracy in the multi-chip packaging process, and further improve the overall production yield. In some embodiments, obtaining the iterative rotation angle of each chip includes: obtaining the actual offset angle of each chip, and obtaining the iterative rotation angle of each chip according to the actual offset angle, the rotation angle of the global rigid transformation of the dielectric layer, and the preset number of iterations.

[0061] In some embodiments, during the actual packaging process, the pre-set alignment mark points on each chip may deviate in position and angle due to patch errors. The system determines the actual offset angle of each chip by detecting the coordinate information of these alignment mark points and using geometric calculation methods (such as least squares method to fit a straight line or calculate the average angle).

[0062] Furthermore, the iterative rotation angle of each chip is calculated by combining the actual offset angle of each chip, the rotation angle of the global rigid transformation of the dielectric layer, and the preset number of iterations. The specific calculation formula is as follows: ; in, (i=1, 2, 3...m) is the iterative rotation angle, (i=1, 2, 3...m) is the actual offset angle of each chip, is the rotation angle of the global rigid transformation of the medium layer, and N is the preset number of iterations.

[0063] In some embodiments, the deflection correction and alignment method further includes: in the second exposure process, the circuit layer and the dielectric layer are aligned to meet the second condition, and the second condition includes that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than the second center distance threshold. The global rigid transformation parameters of the circuit layer are obtained, and when the global rigid transformation parameters make the second exposure process meet the second condition, the deflection correction of the dielectric layer is completed. Alternatively, when the global rigid transformation parameters make the second exposure process not meet the second condition, the deflection correction of the dielectric layer fails.

[0064] Specifically, after completing the alignment and deviation correction of the dielectric layer and the chip layer in the first exposure process, the entire packaging process still needs to perform a second exposure process, that is, further exposing the dielectric layer to form a circuit layer. In this process, the circuit layer pattern and the dielectric layer pattern must also achieve a predetermined alignment accuracy. For this reason, the "second condition" is introduced, which is defined as: the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than the second center distance threshold. Among them, the second center distance threshold is a pre-set maximum allowable overlay center distance, which can be determined based on factors such as specific packaging process requirements, device structure size, alignment resolution or yield requirements of process equipment. The requirement of the second condition ensures that the circuit layer pattern can be accurately aligned with the dielectric layer pattern after exposure, ensuring that subsequent interconnections (such as pad connections, conductive lines) can be reliably connected.

[0065] Furthermore, in the second exposure process, in order to achieve accurate alignment between the circuit layer and the dielectric layer, the system can adjust the circuit layer pattern as a whole through global rigid transformation parameters. Among them, the global rigid transformation parameters may include displacement and rotation angle. It is calculated based on the alignment mark points of the entire circuit layer pattern and the dielectric layer pattern. Specifically, the system can collect the position data of each alignment mark point on the circuit layer and compare it with the position of the pattern after correction on the dielectric layer. By calculating the differences between these positions, the system can obtain an overall rigid transformation matrix, which contains the parameters required to translate and rotate the circuit layer pattern to the optimal alignment state. Then, the circuit layer pattern is rotated and translated as a whole using the global rigid transformation parameters to align it with the dielectric layer pattern.

[0066] Furthermore, after the adjustment is completed, the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern after the global rigid transformation is measured to determine whether the alignment result meets the second condition. If the maximum overlay center distance is less than the second center distance threshold, it means that the global rigid transformation parameters are accurate enough to make the alignment error between the circuit layer and the dielectric layer within an acceptable range, then it is considered that the second exposure process has met the requirements, thereby determining that the correction of the dielectric layer has been completed and the entire alignment process is successful. If the maximum overlay center distance is greater than or equal to the second center distance threshold, it means that the global rigid transformation has failed to make the circuit layer and the dielectric layer achieve the required alignment accuracy, and then it is determined that the correction of the dielectric layer has failed.

[0067] Figure 5 FIG. 1 is an overall flow chart of a method for correcting and aligning a direct-write lithography machine according to an embodiment of the present invention. Figure 5 As shown, the overall process of the correction and alignment method applied to the direct writing lithography machine includes at least steps S10-S26, which are as follows: S10, start.

[0068] S11, measuring the coordinates of the alignment mark points on each chip in the chip layer and the actual offset angle caused by the patch.

[0069] S12, performing a global rigid transformation on the dielectric layer based on the alignment mark points of each chip in the chip layer.

[0070] S13, calculating a first distance between each chip and the center coordinates of the corresponding chip theoretical pattern in the dielectric layer after the global rigid transformation.

[0071] S14, determining whether the first distance is greater than or equal to a first circle center distance threshold, if so, proceeding to step S15, if not, proceeding to step S16.

[0072] S15, determining that the medium layer needs to be corrected.

[0073] S16, directly exposing the dielectric layer and the circuit layer.

[0074] S17, obtaining partition rigid transformation parameters of the theoretical chip pattern in the dielectric layer corresponding to each chip in the chip layer.

[0075] S18, obtaining an iterative displacement step and an iterative rotation angle based on the partitioned rigid transformation parameters of the theoretical chip pattern in the dielectric layer corresponding to each chip.

[0076] S19, correcting the position of the theoretical chip pattern in the dielectric layer corresponding to each chip based on the iterative displacement step, and correcting the rotation angle of the theoretical chip pattern in the dielectric layer corresponding to each chip based on the iterative rotation angle of each chip.

[0077] S20, determining whether the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold, if so, proceeding to step S21, if not, returning to step S19.

[0078] S21, performing a global rigid transformation on the circuit layer to obtain a global rigid transformation parameter of the circuit layer.

[0079] S22, correcting the position of the circuit layer pattern based on the global rigid transformation parameter of the circuit layer.

[0080] S23, judging whether the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than the second center distance threshold, if so, proceeding to step S24, if not, proceeding to step S25.

[0081] S24, the medium layer deviation correction is completed.

[0082] S25, the dielectric layer correction fails.

[0083] S26, end.

[0084] In general, this method effectively improves the alignment accuracy between layers in the multi-chip packaging process, and can correct the pattern misalignment problem caused by patch errors. It enhances the tolerance to chip patch errors, thereby improving the reliability and stability of the packaging process and increasing production yield.

[0085] In some embodiments, the stepper lithography equipment mainly relies on the mask to project the pattern onto the chip. This type of equipment can generally only perform a global rigid transformation on the entire pattern, that is, it cannot adjust the alignment of the pattern according to the needs of different areas. Among them, the global rigid transformation is only a simple translation, rotation or scaling of the entire exposure pattern, without considering the local deviations or errors that may exist between different areas, so the tolerance for patch errors (that is, the angle or position errors of the chip during the mounting process) is low. In other words, this type of equipment can only make a unified adjustment to the entire exposure pattern, and cannot flexibly adapt to the actual position changes of each chip, thereby limiting its application in high-precision packaging.

[0086] The direct-write lithography machine uses laser direct-write technology, which directly exposes the pattern on the chip surface through digitalization. This device uses the correction and alignment method applied to the direct-write lithography machine in the embodiment of the present invention, allowing the individual patch errors (including rotation angle and displacement deviation) of multiple chips to be independently calculated and adjusted to greatly improve the tolerance for chip patch errors. This means that even if there are certain errors in the chip mounting process, the direct-write lithography machine can correct the position of the pattern through the correction and alignment method applied to the direct-write lithography machine in the embodiment of the present invention, making the alignment accuracy in the multi-chip packaging process more accurate, and ultimately improving the product yield.

[0087] Therefore, in high-density interconnection scenarios, traditional stepper lithography equipment may not be able to effectively deal with errors due to its low tolerance for patch errors, resulting in a high defect rate. In contrast, the direct-write lithography equipment based on the deflection correction and alignment method applied to a direct-write lithography machine according to an embodiment of the present invention can perform pattern alignment more flexibly and accurately in a high-density interconnection environment, and therefore has greater advantages.

[0088] In some embodiments, Figure 6 Describes the comparison of the correction yield of direct write lithography machine and stepper lithography equipment at different angles and displacements, such as Figure 6 As shown, the black bar graph represents a translation error of ±3μm, the dark gray bar graph represents a translation error of ±2μm, and the light gray bar graph represents a translation error of ±1μm. ±0.005°, ±0.01°, ±0.015°, and ±0.02° represent different angular errors.

[0089] therefore, Figure 6The correction yields of the direct-write lithography machine and the stepper lithography equipment based on the correction and alignment method for the direct-write lithography machine according to the embodiment of the present invention under different rotation errors (±0.005° to ±0.02°) and different translation errors (±1μm, ±2μm, ±3μm) are compared. It can be seen from the figure that when the direct-write lithography machine performs alignment correction on multiple chips, its correction yield is always higher than that of the stepper lithography equipment.

[0090] Reference below Figure 7 A deflection correction and alignment control device applied to a direct writing lithography machine according to an embodiment of the present invention is described.

[0091] Figure 7 is a block diagram of a deflection correction and alignment control device applied to a direct writing lithography machine according to an embodiment of the present invention. Figure 7 As shown, the deflection correction and alignment control device 1 applied to a direct writing lithography machine includes: a memory 12 and at least one processor 11.

[0092] In some embodiments, at least one processor 11 may be one processor 11, or may be two processors 11, three processors 11, five processors 11, or multiple processors 11. The processor 11 may be a single-core or multi-core processor 11, which is used to execute the correction and alignment algorithm and control logic. The processor 11 may be a central processing unit (CPU), a graphics processor (GPU), a digital signal processor (DSP), or an application-specific integrated circuit (ASIC) in the correction and alignment control device 1 of the direct-write lithography machine.

[0093] In some embodiments, the memory 12 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), flash memory, etc., for storing program code, data, and temporary information required for runtime.

[0094] In some embodiments, the memory 12 is communicatively connected to at least one processor 11, and the memory 12 stores a computer program that can be executed by at least one processor 11. When at least one processor 11 executes the computer program, the deviation correction and alignment method applied to the direct writing lithography machine described in the above embodiment is implemented.

[0095] According to the deflection correction and alignment control device 1 applied to a direct-write lithography machine according to an embodiment of the present invention, at least one processor 11 implements the deflection correction and alignment method applied to a direct-write lithography machine described in the above embodiment by executing a computer program. When there is a deflection correction demand in the dielectric layer, that is, when the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, first obtain the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer, wherein the parameter contains displacement information, so as to realize local adjustment for different chip patch errors, rather than relying solely on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the chip corresponding to the chip layer. Through multiple iterative corrections, the center coordinate of the theoretical pattern of the chip on the dielectric layer gradually approaches the center coordinate of the chip corresponding to the chip layer, and finally ensures that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the method of the present invention can effectively compensate for the patch errors between different chips by combining partition rigid transformation with iterative displacement step correction, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip patch errors, and thus improve the production yield.

[0096] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed, the method for correcting and aligning the direct-write lithography machine described in the above embodiment is implemented.

[0097] The computer-readable storage medium of the embodiments of the present invention may include, but is not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0098] According to the computer-readable storage medium of an embodiment of the present invention, by adopting the correction and alignment method applied to the direct-write lithography machine described in the above embodiment, the alignment accuracy in the multi-chip packaging process is improved, the inaccurate pattern alignment caused by chip mounting errors is corrected, and the tolerance to chip mounting errors is enhanced, thereby improving the reliability and stability of the packaging process and improving the production yield.

[0099] Reference below Figure 8-Figure 9 A direct write lithography machine according to an embodiment of the present invention is described.

[0100] Figure 8is a block diagram of a direct write lithography machine according to an embodiment of the present invention, such as Figure 8 As shown, the direct writing lithography machine 100 includes the deviation correction and alignment control device 1 applied to the direct writing lithography machine as described in the above embodiment.

[0101] Fig. 9 is a block diagram of a direct write lithography machine according to yet another embodiment of the present invention, Fig. 9 As shown, the direct-write lithography machine 100 includes a correction and alignment system 2 and a control system 3 .

[0102] In some embodiments, the correction and alignment system 2 is mainly responsible for realizing the precise alignment of each layer of pattern (e.g., chip layer, dielectric layer, circuit layer) during the direct write lithography process. The correction and alignment system 2 may include, but is not limited to: a high-precision imaging module, an alignment mark detection module, a data transmission interface, an actuator interface, etc. Among them, a high-precision imaging module (e.g., a high-precision CCD camera or a laser detector) can be used to capture the alignment mark points of each chip in the chip layer and provide accurate position information. The alignment mark detection module can automatically detect the alignment mark points (e.g., alignment points, center coordinate points) using an image processing algorithm, and output the precise coordinates of each mark point. The data transmission interface can transmit the collected data and calculation results to the control system to ensure real-time control and feedback closed loop. The actuator interface can be used to pass the correction instructions to the motion control components of the direct write lithography machine 100, such as a stepper drive, an optical focusing device, etc., to achieve physical position and angle adjustment.

[0103] In some embodiments, the control system 3 may include but is not limited to: a processor, a memory, a communication interface, etc., wherein the processor is responsible for executing the correction and alignment algorithm, performing data operations and decision control. The memory is used to store the running program, process parameters, alignment data and intermediate calculation results. The communication interface is used to exchange data with the correction and alignment system 2, the exposure system 3, etc. to achieve collaborative control.

[0104] In some embodiments, the control system 3 is connected to the deflection correction and alignment system 2, and the control system 3 is used to control the deflection correction and alignment system 2 according to the deflection correction and alignment method applied to the direct writing lithography machine described in the above embodiments.

[0105] According to the direct writing lithography machine 100 of the embodiment of the present invention, the control system 3 is connected to the correction and alignment system 2, and the correction and alignment system 2 is controlled by adopting the correction and alignment method applied to the direct writing lithography machine described in the above embodiment. Specifically, when there is a correction demand for the dielectric layer, that is, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to the first center distance threshold, the partition rigid transformation parameters of each chip in the chip layer relative to the theoretical pattern of the chip in the dielectric layer are first obtained, wherein the parameter contains displacement information to achieve local adjustment for different chip patch errors, rather than relying solely on global rigid transformation, thereby improving the adaptability to patch errors. Then, based on the displacement of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step length is obtained, and the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is adjusted by using the step length, so that it moves along the vector direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the chip corresponding to the chip layer. Through multiple iterations of correction, the center coordinates of the theoretical pattern of the chip on the dielectric layer gradually approach the center coordinates of the corresponding chip on the chip layer, and finally ensure that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the direct-write lithography machine 100 of the present invention can effectively compensate for the patch errors between different chips by combining partition rigid transformation and iterative displacement step correction, improve the alignment accuracy in the multi-chip packaging process, and enhance the tolerance to chip patch errors, thereby improving the production yield.

[0106] In some embodiments, Fig. 9 As shown, the direct-write lithography machine 100 further includes an exposure system 4, which is connected to the control system 3. The exposure system 4 is used to perform exposure when a first condition is met in the first exposure process and to perform exposure when a second condition is met in the second exposure process.

[0107] In some embodiments, the exposure system 4 may include, but is not limited to: a light source, an optical system, a motion platform or an exposure table, an exposure control module, etc. Among them, the light source (such as a laser, an electron beam) is used to generate an exposure beam to ensure that the pattern exposure is clear and uniform. The optical system may include lenses, reflectors, apertures, etc., which are used to control the shape, focal length and uniformity of the light beam to project the design pattern onto the target substrate. The motion platform or exposure table can achieve precise positioning and movement of the substrate or photoresist through precise mechanical control to ensure that the pattern after alignment covers the entire chip or dielectric layer area. The exposure control module can communicate with the control system 3, and dynamically adjust the exposure parameters (such as exposure time, light intensity, etc.) according to the alignment results and preset parameters to ensure that the exposure operation is performed only when the first condition or the second condition is met.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0109] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for correcting and aligning a direct-write lithography machine, characterized in that: include: In the first exposure process, the chip layer and the dielectric layer are aligned to meet a first condition, wherein the first condition includes that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold; When the dielectric layer needs to be corrected, a partition rigid transformation parameter of each chip in the chip layer corresponding to a theoretical pattern of the chip in the dielectric layer is obtained, wherein the partition rigid transformation parameter includes a displacement; Obtaining an iterative displacement step length based on the displacement of each chip corresponding to a theoretical pattern of the chip in the dielectric layer; Based on the iterative displacement step, the position of each chip corresponding to the theoretical pattern of the chip in the dielectric layer is corrected until the dielectric layer and the chip layer meet the first condition, wherein during the correction, the theoretical pattern of the chip in the dielectric layer moves along the vector direction of the displacement, and the vector direction is the direction from the center coordinate of the theoretical pattern of the chip on the dielectric layer to the center coordinate of the chip corresponding to the chip layer.

2. The deviation correction and alignment method according to claim 1, characterized in that: The step of obtaining the iterative displacement step according to the displacement of each chip corresponding to the theoretical pattern of the chip in the dielectric layer comprises: Determining the direction angle and modulus length of the displacement of each chip corresponding to the theoretical pattern of the chip in the dielectric layer; The iterative displacement step size is determined according to the direction angle, the modulus length and a preset number of iterations.

3. The deviation correction and alignment method according to claim 1 or 2, characterized in that: The deviation correction and alignment method also includes: Performing a global rigid transformation on the dielectric layer based on the alignment mark points of each chip in the chip layer, wherein the alignment mark points include the alignment points on each chip and the center coordinate points of each chip, and the center coordinate points are obtained according to the alignment points on the corresponding chip; Obtaining a first distance between each chip and the center coordinates of a corresponding chip theoretical pattern in the dielectric layer after the global rigid transformation; When the first distance is greater than or equal to the first circle center distance threshold, it is determined that the medium layer needs to be corrected.

4. The deviation correction and alignment method according to claim 3, characterized in that: The partition rigid transformation parameter includes the rotation angle of each chip corresponding to the theoretical pattern of the chip in the dielectric layer, and the deviation correction and alignment method further includes: Obtaining an iterative rotation angle of each chip; During correction, the rotation angle of the theoretical pattern of the chips in the dielectric layer is corrected based on the iterative rotation angle of each chip.

5. The deviation correction and alignment method according to claim 4, characterized in that: The obtaining of the iterative rotation angle of each chip comprises: Obtaining the actual offset angle of each chip; The iterative rotation angle of each chip is obtained according to the actual offset angle, the rotation angle of the global rigid transformation of the dielectric layer and a preset number of iterations.

6. The deviation correction and alignment method according to claim 1, characterized in that: The deviation correction and alignment method also includes: In the second exposure process, the circuit layer and the dielectric layer are aligned to meet a second condition, wherein the second condition includes that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than a second center distance threshold; Obtaining global rigid transformation parameters of the circuit layer; When the global rigid transformation parameter makes the second exposure process meet the second condition, the dielectric layer deflection correction is completed; Alternatively, when the global rigid transformation parameter causes the second exposure process to fail to satisfy the second condition, the dielectric layer deflection correction fails.

7. A deviation correction and alignment control device applied to a direct writing lithography machine, characterized in that: include: at least one processor; a memory communicatively coupled to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, and when the at least one processor executes the computer program, the method for correcting and aligning the direct-write lithography machine described in any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the deviation correction and alignment method applied to a direct writing lithography machine as described in any one of claims 1 to 6 is implemented.

9. A direct writing lithography machine, characterized in that: The direct writing lithography machine comprises the deviation correction and alignment control device applied to the direct writing lithography machine according to claim 7; Alternatively, the direct-write lithography machine includes a deflection correction and alignment system and a control system, the control system is connected to the deflection correction and alignment system, and the control system is used to control the deflection correction and alignment system according to the deflection correction and alignment method applied to the direct-write lithography machine according to any one of claims 1-6.

10. The direct writing lithography machine according to claim 9, characterized in that: The direct-write lithography machine also includes an exposure system, which is connected to the control system. The exposure system is used to perform exposure when a first condition is met in a first exposure process and to perform exposure when a second condition is met in a second exposure process.

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