Methods and apparatus for alignment and correction in direct-write lithography machines, dielectric materials and lithography machines

Abstract

This invention discloses a method and apparatus for alignment correction in direct-write lithography, as well as a dielectric material and a lithography machine. The alignment correction method for direct-write lithography includes: when alignment correction is required in the dielectric layer, obtaining partitioned rigid transformation parameters of the theoretical chip patterns in the dielectric layer corresponding to each chip in the chip layer, the partitioned rigid transformation parameters including displacement; obtaining an iterative displacement step size based on the displacement of the theoretical chip patterns in the dielectric layer corresponding to each chip; correcting the position of the theoretical chip patterns in the dielectric layer corresponding to each chip based on the iterative displacement step size until the dielectric layer and the chip layer satisfy a first condition, wherein, during correction, the theoretical chip patterns in the dielectric layer move along the vector direction of the displacement, the vector direction being from the center coordinates of the theoretical chip patterns on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. This invention improves the alignment accuracy in multi-chip packaging processes and corrects inaccurate pattern alignment caused by die-mounting errors.

Description

Technical Field

[0001] This invention relates to the field of lithography technology, and in particular to a spin-correction and alignment method for a direct-write lithography machine, as well as a spin-correction and alignment control device, a computer-readable storage medium, and a direct-write lithography machine. Background Technology

[0002] With the development of chip packaging technology, especially in advanced packaging, the interconnection of multiple chips plays a crucial role in improving chip performance. In multi-chip interconnection packaging processes, due to placement errors, it is difficult to ensure that the dielectric layer and redistribution layer (RDL) are accurately aligned with the pads on each chip in subsequent processes. This leads to inaccurate pattern alignment, resulting in problems such as holes or poor connections, which affects the chip production yield.

[0003] In existing technologies, while direct-write lithography equipment offers flexible exposure capabilities, its pattern correction algorithms are poorly adapted to high-density interconnections of multiple chips, making it difficult to handle complex variations caused by chip placement errors. This results in low pattern exposure accuracy, failing to meet the high-precision alignment requirements of packaging processes. Traditional stepper lithography equipment, when performing multi-chip packaging, can only achieve a global rigid transformation by adjusting the position of the mask template. This method only allows for global adjustments and cannot perform fine-grained local correction for each chip, thus having low tolerance for individual chip placement errors. It cannot effectively handle the complexities of high-density interconnections of multiple chips, leading to low process yields. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one objective of this invention is to propose a correction and alignment method for direct-write lithography machines. This method improves the alignment accuracy in multi-chip packaging processes, corrects inaccurate pattern alignment caused by chip placement errors, enhances tolerance to chip placement errors, thereby improving the reliability and stability of the packaging process and increasing production yield.

[0005] The second objective of this invention is to provide a spin correction and alignment control device for use in direct-write lithography machines.

[0006] A third objective of this invention is to provide a computer-readable storage medium.

[0007] The fourth objective of this invention is to provide a direct-write lithography machine.

[0008] To achieve the above objectives, a first aspect of the present invention provides a polarization correction and alignment method for a direct-write lithography machine, comprising: in a first exposure process, aligning a chip layer and a dielectric layer to satisfy a first condition, the first condition including that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold; when the dielectric layer has a polarization correction requirement, obtaining partition rigidity transformation parameters of each chip in the chip layer corresponding to the theoretical pattern of the chip in the dielectric layer, the partition rigidity transformation parameters including displacement; obtaining an iterative displacement step size based on the displacement of each chip corresponding to the theoretical pattern of the chip in the dielectric layer; correcting the position of each chip corresponding to the theoretical pattern of the chip in the dielectric layer based on the iterative displacement step size until the dielectric layer and the chip layer satisfy the first condition, wherein, during correction, the theoretical pattern of the chip in the dielectric layer moves along the vector direction of the displacement, the vector direction being the direction from the center coordinates of the theoretical pattern of the chip on the dielectric layer to the center coordinates of the corresponding chip in the chip layer.

[0009] According to the alignment correction method for a direct-write lithography machine according to embodiments of the present invention, when there is an alignment correction requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the method first obtains the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and this step size is used to adjust the position of the theoretical chip pattern in the dielectric layer corresponding to each chip, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, ultimately ensuring that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the method of the present invention, by combining partition rigid transformation and iterative displacement step size correction, can effectively compensate for the chip mounting error between different chips, improve the alignment accuracy in multi-chip packaging process, enhance the tolerance to chip mounting error, and thus improve production yield.

[0010] In some embodiments, obtaining the iterative displacement step size based on the displacement of each chip corresponding to the theoretical chip pattern in the dielectric layer includes: determining the orientation angle and magnitude of the displacement of each chip corresponding to the theoretical chip pattern in the dielectric layer; and determining the iterative displacement step size based on the orientation angle, the magnitude, and a preset number of iterations.

[0011] In some embodiments, the alignment correction method further includes: performing a global rigid transformation on the dielectric layer based on the alignment markers of each chip in the chip layer, wherein the alignment markers include alignment points on each chip and center coordinate points of each chip, and the center coordinate points are obtained based on the alignment points on the corresponding chips; obtaining a first distance between each chip and the center coordinates of the corresponding theoretical chip pattern in the dielectric layer after the global rigid transformation; and determining that the dielectric layer has an alignment correction requirement when the first distance is greater than or equal to the first center distance threshold.

[0012] In some embodiments, the partition rigid transformation parameters include the rotation angle of each chip corresponding to the theoretical chip pattern in the dielectric layer, and the alignment correction method further includes: obtaining the iterative rotation angle of each chip; and correcting the rotation angle of the theoretical chip pattern in the dielectric layer based on the iterative rotation angle of each chip during correction.

[0013] In some embodiments, obtaining the iterative rotation angle of each chip includes: obtaining the actual offset angle of each chip; and obtaining the iterative rotation angle of each chip based on the actual offset angle, the rotation angle of the global rigid transformation of the dielectric layer, and a preset number of iterations.

[0014] In some embodiments, the alignment correction method further includes: in a second exposure process, aligning the circuit layer and the dielectric layer to meet a second condition, the second condition including that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than a second center distance threshold; obtaining global rigidity transformation parameters of the circuit layer; when the global rigidity transformation parameters cause the second exposure process to meet the second condition, the dielectric layer alignment correction is completed; or, when the global rigidity transformation parameters cause the second exposure process to fail to meet the second condition, the dielectric layer alignment correction fails.

[0015] To achieve the above objectives, a second aspect of the present invention provides a spin correction and alignment control device for a direct-write lithography machine, comprising: at least one processor; a memory communicatively connected to the at least one processor; the memory storing a computer program executable by the at least one processor, wherein the at least one processor executes the computer program to implement the spin correction and alignment method for a direct-write lithography machine described in the above embodiment.

[0016] According to an embodiment of the present invention, a bias correction and alignment control device for a direct-write lithography machine implements the bias correction and alignment method for a direct-write lithography machine described above by at least one processor executing a computer program. When there is a bias correction requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer are first obtained. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and the position of the theoretical chip pattern in the dielectric layer corresponding to each chip is adjusted using this step size, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, ultimately ensuring that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the method of the present invention, by combining partition rigid transformation and iterative displacement step size correction, can effectively compensate for the chip mounting error between different chips, improve the alignment accuracy in multi-chip packaging process, enhance the tolerance to chip mounting error, and thus improve production yield.

[0017] To achieve the above objectives, a computer-readable storage medium according to a third aspect of the present invention stores a computer program thereon, which, when executed, implements the alignment correction method for a direct-write lithography machine described in the above embodiments.

[0018] According to embodiments of the present invention, the computer-readable storage medium, by employing the alignment correction method for direct-write lithography machines described in the above embodiments, improves the alignment accuracy in multi-chip packaging processes, corrects inaccurate pattern alignment caused by chip placement errors, enhances the tolerance to chip placement errors, thereby improving the reliability and stability of the packaging process and increasing production yield.

[0019] To achieve the above objectives, a direct-write lithography machine according to a fourth aspect of the present invention includes a bias correction and alignment control device for a direct-write lithography machine as described in the above embodiments; or, the direct-write lithography machine includes a bias correction and alignment system and a control system, wherein the control system is connected to the bias correction and alignment system, and the control system is used to control the bias correction and alignment system according to the bias correction and alignment method for a direct-write lithography machine as described in the above embodiments.

[0020] According to an embodiment of the present invention, the direct-write lithography machine has a control system connected to a bias correction and alignment system. The bias correction and alignment system is controlled using the bias correction and alignment method described in the above embodiment. Specifically, when there is a bias correction requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer are first obtained. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and this step size is used to adjust the position of the theoretical chip pattern in the dielectric layer corresponding to each chip, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, ultimately ensuring that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the direct-write lithography machine of the present invention can effectively compensate for the chip placement error between different chips by combining partition rigid transformation and iterative displacement step size correction, improve the alignment accuracy in multi-chip packaging process, enhance the tolerance to chip placement error, and thus improve the production yield.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0023] Figure 1 This is a flowchart of a polarization correction and alignment method applied to a direct-write lithography machine according to an embodiment of the present invention;

[0024] Figure 2 (a) is a schematic diagram of four chip patch theoretical patterns according to an embodiment of the present invention;

[0025] Figure 2 (b) is a schematic diagram of four chips exhibiting surface mount errors according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram showing the relative positions of an offset chip with a surface mount error in a chip layer and a theoretical chip pattern in a dielectric layer, according to an embodiment of the present invention.

[0027] Figure 4This is a schematic diagram of a global rigidity transformation of a dielectric layer according to an embodiment of the present invention;

[0028] Figure 5 This is an overall flowchart of a polarization correction and alignment method applied to a direct-write lithography machine according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram comparing the yield of alignment results of a direct-write lithography machine and a stepper lithography device during multi-region chip interconnection according to an embodiment of the present invention.

[0030] Figure 7 This is a block diagram of a spin correction and alignment control device applied to a direct-write lithography machine according to an embodiment of the present invention;

[0031] Figure 8 This is a block diagram of a direct-write lithography machine according to an embodiment of the present invention;

[0032] Figure 9 This is a block diagram of a direct-write lithography machine according to yet another embodiment of the present invention.

[0033] Figure label:

[0034] Direct-write lithography machine 100;

[0035] 1. A polarization alignment control device for direct-write lithography machines; 2. A polarization alignment system; 3. A control system; 4. An exposure system;

[0036] Processor 11; Memory 12. Detailed Implementation

[0037] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0038] The following is for reference. Figures 1-6 This invention describes a method for correcting alignment applied to a direct-write lithography machine according to an embodiment of the present invention.

[0039] Figure 1 This is a flowchart of a polarization correction and alignment method applied to a direct-write lithography machine according to an embodiment of the present invention, as shown below. Figure 1 As shown, the alignment method applied to a direct-write lithography machine includes at least steps S1-S4, as detailed below:

[0040] S1, in the first exposure process, the chip layer and the dielectric layer are aligned to meet the first condition, the first condition including that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold.

[0041] In some embodiments, the chip layer may refer to a substrate (e.g., a silicon substrate) on which a chip structure has already been formed, and on which a chip pattern already exists. The dielectric layer may refer to photoresist, insulating dielectric, or other material layers superimposed on the chip layer, and needs to be patterned to ensure alignment with the chip layer.

[0042] In some embodiments, a chip layer can refer to a substrate layer on a silicon wafer or bare chip that has undergone circuit fabrication during the packaging process, i.e., the layer formed by the chips after wafer dicing, chip testing, preliminary packaging, or die mounting. In the packaging process, the chip layer can include individual chips and pre-formed key patterns on the chips, such as alignment marks and pads.

[0043] In some embodiments, the chip layer is the foundation of the entire packaging process, and its alignment accuracy directly determines the alignment effect of subsequent dielectric and circuit layers. Predefined patterns and alignment marks on the chip layer provide reference information for subsequent alignment correction, ensuring that the pattern of the dielectric layer can be precisely aligned with critical areas (such as pads) on the chip, thereby ensuring that the packaged chip can achieve correct electrical interconnection and function.

[0044] In some embodiments, the dielectric layer can refer to the substrate material covering the chip layer for protection, isolation, or as a base material for subsequent processes (such as rewiring or interconnection), commonly including PI (Polyimide) layers, photoresist layers, or other insulating layers.

[0045] In some embodiments, the dielectric layer not only serves as electrical isolation and mechanical support, but also needs to be patterned to form a specific structure for interconnection with the chip layer pattern (such as pads). Proper alignment is crucial for ensuring accurate connection between the dielectric layer pattern and the chip layer pattern; therefore, alignment accuracy directly affects the packaging process yield and the final chip performance.

[0046] In some embodiments, the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern can refer to the maximum distance between the center position of the theoretical chip pattern on the dielectric layer and the center position of the actual pattern (or alignment mark) on the chip layer within the entire alignment region. This parameter reflects the overall alignment accuracy between the two layers. If this distance is large, it indicates a significant misalignment between the dielectric layer pattern and the chip layer pattern, which may lead to defects such as vias or poor connections in subsequent processes. This value can serve as a basis for determining whether further correction is needed.

[0047] In some embodiments, the first center-to-center distance threshold is a preset maximum allowable center-to-center distance. This threshold can be determined based on factors such as specific packaging process requirements, device structure dimensions, alignment resolution of the process equipment, or yield requirements. Only when the maximum center-to-center distance between the dielectric layer pattern and the chip layer pattern is less than the first center-to-center distance threshold can it be ensured that the dielectric layer pattern can be accurately aligned with critical areas (such as pads) on the chip, avoiding vias or connection errors caused by excessive errors, which would affect chip yield.

[0048] Therefore, the first condition serves as the basic judgment criterion in the first exposure process to determine whether further correction processing is needed to ensure that the alignment accuracy between each layer has met the requirements before entering subsequent processes, thereby ensuring the stability of the entire packaging process and the performance of the final product.

[0049] S2, when there is a need for correction in the dielectric layer, obtain the partitioned rigid transformation parameters of the theoretical pattern of each chip in the dielectric layer. The partitioned rigid transformation parameters include displacement.

[0050] In some embodiments, the need for correction of the dielectric layer can be indicated by the following: after the first exposure process is completed, it is found by detection that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a preset first center distance threshold. In other words, the alignment error between the dielectric layer pattern and the chip layer pattern is large, and the alignment accuracy does not meet the requirements, so subsequent correction steps are required.

[0051] Specifically, such as Figure 2 As shown, taking a four-chip package as an example, Figure 2 (a) indicates that there was no chip placement error when the four chips were interconnected. Figure 2 (b) indicates that due to the mounting error, each of the four chips has a certain degree of rotation and translation, which requires further correction and adjustment.

[0052] In some embodiments, the theoretical chip pattern in the dielectric layer can refer to an ideal pattern predefined on the dielectric layer during the design phase using graphic design files such as GDS (Graphic Data System). Its position and shape are generated according to the design requirements of the chip layer. In other words, it represents the chip layer position that the dielectric layer should align with when there are no placement errors. This theoretical pattern serves as a correction reference, used to compare with actual alignment patterns (such as chip markings, pads, or electrode positions) existing on the chip layer. By comparing the positional relationship between the theoretical pattern and the actual chip pattern, the offset can be calculated, providing data support for correction.

[0053] In some embodiments, the partition rigid transformation parameter can refer to the transformation parameter obtained by independently calculating the theoretical pattern of the chip in the corresponding dielectric layer of each chip in the chip layer. This method allows for local and fine adjustment of the offset error of each chip, thereby more accurately compensating for local alignment deviations caused by the mounting error.

[0054] In some embodiments, the coordinate information of the actual alignment mark points of each chip on the chip layer is obtained through a high-precision alignment detection system (e.g., an optical alignment system or an electron beam alignment system). Simultaneously, the predetermined coordinate information of the theoretical chip pattern in the dielectric layer is extracted from the design data. Based on these two sets of coordinate information, the offset error of each chip can be calculated, thereby determining the displacement of its corresponding theoretical chip pattern in the dielectric layer.

[0055] S3, the iterative displacement step size is obtained based on the displacement of the theoretical pattern of the chip in the corresponding dielectric layer of each chip.

[0056] In some embodiments, the iterative displacement step size can refer to the distance the theoretical chip pattern in the dielectric layer moves along the correction direction during each adjustment in the alignment process. It is a small step size applied in each iteration after decomposing the initial displacement (i.e., the offset between the theoretical chip pattern and the actual chip position), rather than correcting the entire position at once. By using an iterative displacement step size for multiple iterations, the error between the theoretical pattern and the actual position can be gradually reduced, making the alignment process smoother and avoiding overcompensation or oscillations that may be caused by a large correction at once. Multiple fine-tunings help detect and correct remaining errors in each iteration, ultimately achieving high-precision alignment.

[0057] S4, based on the iterative displacement step size, correct the position of the chip theoretical pattern in the dielectric layer corresponding to each chip until the dielectric layer and the chip layer satisfy the first condition. During the correction, the chip theoretical pattern in the dielectric layer moves along the vector direction of the displacement. The vector direction is from the center coordinates of the chip theoretical pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer.

[0058] In some embodiments, during the correction process, the theoretical chip pattern in the dielectric layer will move along a direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. This is because this direction is precisely the error direction between the actual positions of the theoretical chip pattern and the corresponding chip. By moving along this direction, the displacement error can be compensated, and the center of the theoretical chip pattern can gradually approach the center of the corresponding chip in the chip layer, thereby achieving precise alignment.

[0059] According to the alignment correction method for a direct-write lithography machine according to embodiments of the present invention, when there is an alignment correction requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the method first obtains the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and this step size is used to adjust the position of the theoretical chip pattern in the dielectric layer corresponding to each chip, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, ultimately ensuring that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the present invention adopts an iterative correction method based on the center connection line of the theoretical pattern of each chip in the chip layer and its corresponding dielectric layer. This method can effectively handle the local chip placement error differences that may exist in each chip in the multi-chip interconnect package, improve the alignment accuracy in the multi-chip packaging process, enhance the tolerance to chip placement errors, and thus improve the production yield.

[0060] In some embodiments, obtaining the iterative displacement step size based on the displacement of the theoretical chip pattern in the corresponding dielectric layer of each chip includes: determining the direction angle and magnitude of the displacement of the theoretical chip pattern in the corresponding dielectric layer of each chip, and determining the iterative displacement step size based on the direction angle, magnitude, and a preset number of iterations.

[0061] Specifically, such as Figure 3 As shown, xOy is a global coordinate system used to describe the actual chip placement position and the theoretical chip pattern in the dielectric layer. Point A is the center point of the offset chip in the dielectric layer where placement errors occur, and point B is the center point of the theoretical chip pattern in the dielectric layer. α represents the angular deviation of the actual chip placement position relative to the theoretical chip pattern. By establishing the xOy coordinate system, vectors can be obtained. sum vector , where vector This represents the position vector from the origin O to point A. This represents the position vector from the origin O to point B.

[0062] Furthermore, based on vectors sum vector Vectors can be obtained , where vector It is the vector pointing from point B to point A, meaning that during correction, the theoretical chip pattern in the dielectric layer moves along the direction of this vector. It can be calculated by subtracting vectors. The specific formula is as follows:

[0063] ;

[0064] Its modulus and orientation angle can be calculated using the following formulas:

[0065] ;

[0066] ;

[0067] ;

[0068] ;

[0069] ;

[0070] ;

[0071] in, Let A be the x-coordinate of point A. Let B be the x-coordinate. Let A be the offset of point A relative to point B in the x-direction. Let A be the ordinate of point A. Let B be the ordinate of point B. Let be the offset of point A relative to point B in the y-direction. For vectors The cosine of the direction angle, where L is a vector. The length of the module.

[0072] Furthermore, if the preset number of iterations is set to N, then each displacement is decomposed into x and y axes as follows:

[0073] ;

[0074] ;

[0075] in, Let x be the iteration displacement step size in the x-direction for each iteration. Let be the step size of the iteration displacement in the y-direction for each iteration.

[0076] Therefore, by following the direction (i.e., vector) from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip on the chip layer... (direction), with iterative displacement step size and The process involves gradual corrections and multiple iterations until the maximum overlay distance between the dielectric layer pattern and the chip layer pattern is less than the first center-to-center distance threshold. The theoretical chip pattern on the dielectric layer will gradually approach the actual position of the corresponding chip on the chip layer, thereby achieving precise alignment.

[0077] In some embodiments, the alignment correction method further includes: performing a global rigid transformation on the dielectric layer based on alignment markers of each chip in the chip layer, wherein the alignment markers include alignment points on each chip and center coordinate points of each chip, and the center coordinate points are obtained based on the alignment points on the corresponding chips. A first distance is obtained between each chip and the center coordinates of the corresponding theoretical chip pattern in the globally rigidly transformed dielectric layer. When the first distance is greater than or equal to a first center-to-center distance threshold, it is determined that the dielectric layer requires alignment correction.

[0078] The alignment points on each chip can be specific markers pre-set on the chip, used to detect and calibrate the chip's position during the packaging process. Multiple alignment points can be set on each chip. The center coordinates of each chip can be obtained by averaging the coordinates of multiple alignment points on the same chip or through a specific calculation method. Based on these alignment markers, a global rigid transformation method is used to adjust the dielectric layer as a whole. That is, according to certain translation (and rotation if necessary) parameters, the pattern on the dielectric layer roughly corresponds to the alignment markers on the chip layer, thus initially achieving alignment between the two layers.

[0079] In some embodiments, after the global rigid transformation is completed, for each chip, there will be a theoretical chip pattern on the dielectric layer after the global rigid transformation, and its center coordinates can be calculated. Then, the system calculates a first distance, which is the distance between the actual center coordinates of each chip on the chip layer and the center coordinates of the corresponding theoretical chip pattern in the dielectric layer after the global rigid transformation. This distance reflects the alignment error between the two patterns after the global rigid transformation. If the first distance is greater than or equal to a first center-to-center distance threshold, it indicates that the alignment error between the two patterns is still large after the global rigid transformation, that is, the global rigid transformation has not yet achieved the required alignment accuracy. In this case, it is necessary to further use the method of partitioned rigid transformation and iterative displacement step size correction to compensate for the local error.

[0080] Specifically, the coordinates of m alignment points on each chip are measured, and the center coordinates of each chip and the angular error caused by the chip mounting are calculated. (i=1, 2, 3...m). The formula for calculating the center coordinates of each chip is as follows:

[0081] ;

[0082] ;

[0083] in, The x-coordinate of the center point The ordinate of the center point is y. Let x be the x-coordinate of the i-th alignment point on the chip. Let be the ordinate of the i-th alignment site on the chip, and m be the number of alignment sites on the chip.

[0084] Furthermore, based on the coordinates of the alignment points on each chip and the center coordinates of each chip, a global rigid transformation is performed on the dielectric layer to adjust its position as a whole, thus initially achieving alignment with the chip layers. The position of the dielectric layer after the global rigid transformation is as follows: Figure 4 As shown, the formula for calculating the global rigid transformation is as follows:

[0085] ;

[0086] in, , Here are the transformed chuck (control platform) coordinates, and x and y are the theoretical pattern coordinates of the chip. Let tx be the rotation angle of the global rigid transformation of the medium layer, tx be the translation in the x-direction, and ty be the translation in the y-direction.

[0087] Therefore, after the global rigid transformation, each chip theoretical pattern on the dielectric layer will obtain an updated center coordinate, which is the center coordinate of the chip theoretical pattern after the global rigid transformation.

[0088] Furthermore, the first distance between each chip and the center coordinates of the corresponding theoretical chip pattern in the dielectric layer after global rigid transformation is calculated. If the first distance is less than the first center-to-center distance threshold, it indicates that the error after global rigid transformation meets the exposure accuracy requirements, and the dielectric layer and circuit layer can be directly exposed without further intelligent correction. If the first distance is greater than or equal to the first center-to-center distance threshold, it indicates that there is still a large error after global rigid transformation, which cannot meet the exposure accuracy requirements. In this case, partitioned rigid transformation and iterative correction are required.

[0089] Furthermore, when it is determined that the dielectric layer has a correction requirement, the partition rigid transformation parameters of the theoretical pattern of the chip in the dielectric layer corresponding to each chip in the chip layer are obtained. Based on the partition rigid transformation parameters of the theoretical pattern of the chip in the dielectric layer corresponding to each chip, the iterative displacement step size is obtained. Based on the iterative displacement step size, the position of the theoretical pattern of the chip in the dielectric layer corresponding to each chip is continuously corrected until the dielectric layer and the chip layer satisfy the first condition that the maximum overlay circle center distance between the dielectric layer pattern and the chip layer pattern is less than the first circle center distance threshold.

[0090] In some embodiments, the partition rigid transformation parameters include not only the displacement of the theoretical chip pattern in the corresponding dielectric layer for each chip in the chip layer, but also the rotation angle of the theoretical chip pattern in the corresponding dielectric layer for each chip. Therefore, the alignment correction method further includes: obtaining the iterative rotation angle of each chip, and during correction, correcting the rotation angle of the theoretical chip pattern in the corresponding dielectric layer based on the iterative rotation angle of each chip to improve the rotation alignment accuracy.

[0091] In this system, an iterative rotation angle is introduced into the rigid transformation parameters of the partition. This allows the system to progressively correct the rotation angle of the theoretical chip pattern in the dielectric layer based on the iterative rotation angle of each chip, thereby achieving a dynamic rotation correction process from overall to local, and from coarse to fine adjustment. This progressive iterative correction strategy not only effectively compensates for the rotational offset of each chip caused by placement errors, but also avoids the instability that may be caused by a large-scale adjustment at once, ensuring the alignment accuracy in multi-chip packaging processes and further improving the overall production yield. In some embodiments, obtaining the iterative rotation angle of each chip includes: obtaining the actual offset angle of each chip, and obtaining the iterative rotation angle of each chip based on the actual offset angle, the rotation angle of the global rigid transformation of the dielectric layer, and a preset number of iterations.

[0092] In some embodiments, during the actual packaging process, the pre-set alignment marks on each chip may deviate in position and angle due to placement errors. The system determines the actual offset angle of each chip by detecting the coordinate information of these alignment marks and using geometric calculation methods (such as least squares fitting of a straight line or calculation of the average angle).

[0093] Furthermore, by combining the actual offset angle of each chip, the rotation angle of the global rigid transformation of the dielectric layer, and the preset number of iterations, the iterative rotation angle of each chip is calculated. The specific calculation formula is as follows:

[0094] ;

[0095] in, (i=1, 2, 3...m) represents the iterative rotation angle. (i=1, 2, 3...m) represents the actual offset angle of each chip. The rotation angle is the global rigid transformation angle of the medium layer, and N is the preset number of iterations.

[0096] In some embodiments, the alignment correction method further includes: in the second exposure step, aligning the circuit layer and the dielectric layer to meet a second condition, the second condition including that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than a second center distance threshold. A global rigidity transformation parameter of the circuit layer is obtained; when the global rigidity transformation parameter causes the second exposure step to meet the second condition, the dielectric layer alignment correction is completed. Alternatively, when the global rigidity transformation parameter causes the second exposure step to fail to meet the second condition, the dielectric layer alignment correction fails.

[0097] Specifically, after the alignment and correction of the dielectric layer and chip layer in the first exposure step, the entire packaging process requires a second exposure step, which involves further exposure on the dielectric layer to form the circuit layer. In this step, the circuit layer pattern and the dielectric layer pattern must also achieve a predetermined alignment accuracy. To this end, a "second condition" is introduced, defined as: the maximum center-to-center distance between the circuit layer pattern and the dielectric layer pattern is less than a second center-to-center distance threshold. The second center-to-center distance threshold is a pre-set maximum allowable center-to-center distance, which can be determined based on specific packaging process requirements, device structure dimensions, alignment resolution of the process equipment, or yield requirements. This second condition ensures that the circuit layer pattern can be precisely aligned with the dielectric layer pattern after exposure, ensuring reliable connection of subsequent interconnects (such as pad connections and conductive lines).

[0098] Furthermore, in the second exposure process, to achieve precise alignment between the circuit layer and the dielectric layer, the system can adjust the circuit layer pattern as a whole using global rigid transformation parameters. These global rigid transformation parameters can include displacement and rotation angles. They are calculated based on the alignment markers of the entire circuit layer pattern and the dielectric layer pattern. Specifically, the system can collect the position data of each alignment marker on the circuit layer and compare it with the corrected pattern position on the dielectric layer. By calculating the differences between these positions, the system can obtain a global rigid transformation matrix, which contains the parameters required to translate and rotate the circuit layer pattern to the optimal alignment state. Then, the global rigid transformation parameters are used to rotate and translate the circuit layer pattern as a whole, aligning it with the dielectric layer pattern.

[0099] Furthermore, after adjustment, the alignment result is determined to meet the second condition by measuring the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern after global rigid transformation. If the maximum overlay center distance is less than the second center distance threshold, it indicates that the global rigid transformation parameters are accurate enough to keep the alignment error between the circuit layer and the dielectric layer within an acceptable range. In this case, the second exposure process is considered to have met the requirements, thus confirming that the dielectric layer correction is complete and the entire alignment process is successful. If the maximum overlay center distance is greater than or equal to the second center distance threshold, it indicates that the global rigid transformation failed to achieve the required alignment accuracy between the circuit layer and the dielectric layer. In this case, the dielectric layer correction is considered to have failed.

[0100] Figure 5 This is an overall flowchart of a polarization correction and alignment method applied to a direct-write lithography machine according to an embodiment of the present invention, as shown below. Figure 5 As shown, the overall process of the alignment method applied to a direct-write lithography machine includes at least steps S10-S26, as detailed below:

[0101] S10, Begin.

[0102] S11 measures the coordinates of alignment marks on each chip in the chip layer, as well as the actual offset angle caused by the chip mounting.

[0103] S12, global rigid transformation of the dielectric layer is performed based on the alignment marks of each chip in the chip layer.

[0104] S13, calculate the first distance between each chip and the center coordinates of the corresponding chip theoretical pattern in the dielectric layer after global rigid transformation.

[0105] S14. Determine whether the first distance is greater than or equal to the first center distance threshold. If yes, proceed to step S15; otherwise, proceed to step S16.

[0106] S15, It is determined that the dielectric layer has a correction requirement.

[0107] S16 directly exposes the dielectric layer and circuit layer.

[0108] S17, obtain the partitioning rigid transformation parameters of the theoretical pattern of the chip in the corresponding dielectric layer for each chip in the chip layer.

[0109] S18, based on the partitioned rigid transformation parameters of the theoretical pattern of the chip in the corresponding dielectric layer of each chip, the iterative displacement step size and iterative rotation angle are obtained.

[0110] S19, the position of the theoretical pattern of the chip in the corresponding dielectric layer of each chip is corrected based on the iterative displacement step size, and the rotation angle of the theoretical pattern of the chip in the corresponding dielectric layer is corrected based on the iterative rotation angle of each chip.

[0111] S20, determine whether the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold. If yes, proceed to step S21; otherwise, return to step S19.

[0112] S21, perform a global rigid transformation on the line layer to obtain the global rigid transformation parameters of the line layer.

[0113] S22, based on the global rigid transformation parameters of the line layer, corrects the position of the line layer pattern.

[0114] S23. Determine whether the maximum overlap distance between the circuit layer pattern and the dielectric layer pattern is less than the second center distance threshold. If yes, proceed to step S24; otherwise, proceed to step S25.

[0115] S24, the correction of the dielectric layer is complete.

[0116] S25, dielectric layer correction failed.

[0117] S26, End.

[0118] In summary, this method effectively improves the alignment accuracy between layers in multi-chip packaging and can correct pattern misalignment problems caused by chip placement errors. It enhances the tolerance to chip placement errors, thereby improving the reliability and stability of the packaging process and increasing production yield.

[0119] In some embodiments, stepper lithography equipment primarily relies on a photomask to project a pattern onto the chip. Such equipment typically only allows for a global rigid transformation of the entire pattern, meaning it cannot adjust the alignment of the pattern according to the needs of different areas. This global rigid transformation is merely a simple translation, rotation, or scaling of the entire exposed pattern, without considering potential local deviations or errors between different areas. Therefore, it has a low tolerance for placement errors (i.e., angular or positional errors that occur during chip placement). In other words, this type of equipment can only make a uniform adjustment to the entire exposed pattern and cannot flexibly adapt to the actual positional changes of each chip, thus limiting its application in high-precision packaging.

[0120] Direct-write lithography machines utilize laser direct-write technology, digitally exposing patterns directly onto the chip surface. This equipment employs the alignment correction method described in this invention, allowing independent calculation and adjustment of individual chip placement errors (including rotation angle and displacement deviations), significantly improving tolerance for chip placement errors. This means that even if chip placement errors exist, the direct-write lithography machine can correct the pattern position using the alignment correction method described in this invention, resulting in more precise alignment in multi-chip packaging processes and ultimately improving product yield.

[0121] Therefore, traditional stepper lithography equipment, in high-density interconnect scenarios, may not be able to effectively handle errors due to its low tolerance for placement errors, resulting in a high defect rate. In contrast, the direct-write lithography equipment based on the alignment correction method applied to direct-write lithography machines according to embodiments of the present invention can perform pattern alignment more flexibly and accurately in high-density interconnect environments, thus having a greater advantage.

[0122] In some embodiments, Figure 6The comparison of polarization correction yield between direct-write lithography machines and stepper lithography equipment under different angles and displacements is described, such as... Figure 6 As shown, black bars represent translation errors of ±3μm, dark gray bars represent translation errors of ±2μm, and light gray bars represent translation errors of ±1μm. ±0.005°, ±0.01°, ±0.015°, and ±0.02° represent different angular errors.

[0123] therefore, Figure 6 The alignment and correction yields of a direct-write lithography machine and a stepper lithography machine, based on the alignment and correction method of this invention, were compared under different rotational errors (±0.005° to ±0.02°) and different translational errors (±1μm, ±2μm, ±3μm). As can be seen from the figures, the alignment and correction yield of the direct-write lithography machine is consistently higher than that of the stepper lithography machine when performing alignment and correction on multiple chips.

[0124] The following is for reference. Figure 7 This invention describes a spin correction and alignment control device applied to a direct-write lithography machine according to an embodiment of the present invention.

[0125] Figure 7 This is a block diagram of a bias correction and alignment control device applied to a direct-write lithography machine according to an embodiment of the present invention, such as... Figure 7 As shown, the alignment control device 1 applied to a direct-write lithography machine includes: a memory 12 and at least one processor 11.

[0126] In some embodiments, at least one processor 11 can be one processor 11, or multiple processors 11, such as two processors 11, three processors 11, five processors 11, etc. The processor 11 can be a single-core or multi-core processor 11 used to execute the alignment algorithm and control logic. The processor 11 can be a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC) in the alignment control device 1 of the direct-write lithography machine.

[0127] In some embodiments, memory 12 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), flash memory, etc., for storing program code, data, and temporary information required during runtime.

[0128] In some embodiments, the memory 12 is communicatively connected to at least one processor 11, and the memory 12 stores a computer program that can be executed by at least one processor 11. When the at least one processor 11 executes the computer program, it implements the alignment correction method for a direct-write lithography machine as described in the above embodiments.

[0129] According to an embodiment of the present invention, the alignment control device 1 for a direct-write lithography machine implements the alignment method for a direct-write lithography machine described above by at least one processor 11 when executing a computer program. When there is an alignment requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer are first obtained. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and the position of the theoretical chip pattern in the dielectric layer corresponding to each chip is adjusted using this step size, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip in the chip layer, ultimately ensuring that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, satisfying the first condition. Therefore, the method of the present invention, by combining partition rigid transformation and iterative displacement step size correction, can effectively compensate for the chip mounting error between different chips, improve the alignment accuracy in multi-chip packaging process, enhance the tolerance to chip mounting error, and thus improve production yield.

[0130] This invention also proposes a computer-readable storage medium storing a computer program thereon, which, when executed, implements the alignment method for the direct-write lithography machine described in the above embodiments.

[0131] The computer-readable storage medium in the embodiments of the present invention may include, but is not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be described in detail here.

[0132] According to embodiments of the present invention, the computer-readable storage medium, by employing the alignment correction method for direct-write lithography machines described in the above embodiments, improves the alignment accuracy in multi-chip packaging processes, corrects inaccurate pattern alignment caused by chip placement errors, enhances the tolerance to chip placement errors, thereby improving the reliability and stability of the packaging process and increasing production yield.

[0133] The following is for reference. Figures 8-9 A direct-write lithography machine according to an embodiment of the present invention is described.

[0134] Figure 8 This is a block diagram of a direct-write lithography machine according to an embodiment of the present invention, such as... Figure 8 As shown, the direct-write lithography machine 100 includes the alignment control device 1 for the direct-write lithography machine described in the above embodiment.

[0135] Figure 9 This is a block diagram of a direct-write lithography machine according to yet another embodiment of the present invention, such as... Figure 9 As shown, the direct-write lithography machine 100 includes a spin correction and alignment system 2 and a control system 3.

[0136] In some embodiments, the alignment system 2 is primarily responsible for achieving precise alignment of each layer of patterns (e.g., chip layer, dielectric layer, circuit layer) during the direct-write lithography process. The alignment system 2 may include, but is not limited to, a high-precision imaging module, an alignment mark detection module, a data transmission interface, and an actuator interface. The high-precision imaging module (e.g., a high-precision CCD camera or laser detector) can be used to capture alignment mark points of each chip in the chip layer, providing accurate positional information. The alignment mark detection module can automatically detect alignment mark points (e.g., alignment points, center coordinate points) using image processing algorithms and output the precise coordinates of each mark point. The data transmission interface can transmit the acquired data and calculation results to the control system, ensuring real-time control and feedback closed-loop. The actuator interface can be used to transmit alignment commands to the motion control components of the direct-write lithography machine 100, such as stepper drivers and optical focusing devices, to achieve adjustments in physical position and angle.

[0137] In some embodiments, the control system 3 may include, but is not limited to, a processor, a memory, and a communication interface. The processor is responsible for executing the alignment algorithm, performing data calculations, and making decision-making controls. The memory stores the running program, process parameters, alignment data, and intermediate calculation results. The communication interface is used to interact with the alignment system 2, the exposure system 3, etc., to achieve coordinated control.

[0138] In some embodiments, the control system 3 is connected to the alignment system 2, and the control system 3 is used to control the alignment system 2 according to the alignment method applied to the direct-write lithography machine described in the above embodiments.

[0139] According to an embodiment of the present invention, the direct-write lithography machine 100 has a control system 3 connected to a bias correction and alignment system 2. The bias correction and alignment system 2 is controlled by the bias correction and alignment method described in the above embodiment for direct-write lithography. Specifically, when there is a bias correction requirement in the dielectric layer, i.e., the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is greater than or equal to a first center distance threshold, the partitioned rigid transformation parameters of each chip in the chip layer relative to the theoretical chip pattern in the dielectric layer are first obtained. These parameters include displacement information to achieve local adjustments for different chip mounting errors, rather than relying solely on global rigid transformation, thereby improving adaptability to mounting errors. Then, based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip, an iterative displacement step size is obtained, and this step size is used to adjust the position of the theoretical chip pattern in the dielectric layer corresponding to each chip, moving it along a vector direction from the center coordinates of the theoretical chip pattern on the dielectric layer to the center coordinates of the corresponding chip in the chip layer. Through multiple iterative corrections, the center coordinates of the theoretical chip pattern on the dielectric layer gradually approach the center coordinates of the corresponding chip on the chip layer, ultimately ensuring that the maximum overlay distance between the dielectric layer pattern and the chip layer pattern is less than the first center distance threshold, thus satisfying the first condition. Therefore, the direct-write lithography machine 100 of this invention, by combining partitioned rigid transformation and iterative displacement step size correction, can effectively compensate for the placement errors between different chips, improve the alignment accuracy in multi-chip packaging processes, enhance the tolerance to chip placement errors, and thereby improve production yield.

[0140] In some embodiments, such as Figure 9 As shown, the direct-write lithography machine 100 also includes an exposure system 4, which is connected to the control system 3. The exposure system 4 is used to perform exposure when a first condition is met in the first exposure process and to perform exposure when a second condition is met in the second exposure process.

[0141] In some embodiments, the exposure system 4 may include, but is not limited to, a light source, an optical system, a motion platform or exposure stage, and an exposure control module. The light source (such as a laser or electron beam) generates the exposure beam, ensuring clear and uniform pattern exposure. The optical system may include lenses, mirrors, apertures, etc., to control the shape, focal length, and uniformity of the beam, projecting the designed pattern onto the target substrate. The motion platform or exposure stage can achieve precise positioning and movement of the substrate or photoresist through precise mechanical control, ensuring that the aligned pattern covers the entire chip or dielectric layer area. The exposure control module can communicate with the control system 3, dynamically adjusting exposure parameters (such as exposure time, light intensity, etc.) based on the alignment result and preset parameters, ensuring that exposure operation is performed only when a first condition or a second condition is met.

[0142] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0143] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for correcting and aligning offsets in a direct-write lithography machine, characterized in that, include: In the first exposure process, the chip layer and the dielectric layer are aligned to meet a first condition, which includes that the maximum overlay center distance between the dielectric layer pattern and the chip layer pattern is less than a first center distance threshold. When the dielectric layer has a correction requirement, the partition rigid transformation parameters of each chip in the chip layer corresponding to the theoretical pattern of the chip in the dielectric layer are obtained. The partition rigid transformation parameters include displacement, wherein the displacement is calculated based on the coordinate information of the actual alignment mark points of each chip in the chip layer and the predetermined coordinate information of the theoretical pattern of the chip in the dielectric layer. The iterative displacement step size corresponding to each chip is obtained based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip. The position of the theoretical chip pattern in the dielectric layer corresponding to each chip is corrected based on the iterative displacement step size until the dielectric layer and the chip layer satisfy the first condition. During the correction, the theoretical chip pattern in the dielectric layer corresponding to each chip moves along the vector direction corresponding to the displacement. The vector direction is from the center coordinate of the theoretical chip pattern on the dielectric layer to the center coordinate of the corresponding chip in the chip layer.

2. The alignment correction method according to claim 1, characterized in that, The step of obtaining the iterative displacement step size based on the displacement of the theoretical chip pattern in the dielectric layer corresponding to each chip includes: Determine the direction angle and magnitude of the displacement of each chip corresponding to the theoretical chip pattern in the dielectric layer; The iterative displacement step size is determined based on the orientation angle, the modulus, and the preset number of iterations.

3. The alignment correction method according to claim 1 or 2, characterized in that, The alignment correction method further includes: A global rigid transformation is performed on the dielectric layer based on the alignment markers of each chip in the chip layer. The alignment markers include alignment points on each chip and center coordinate points of each chip. The center coordinate points are obtained based on the alignment points on the corresponding chips. Obtain the first distance between each chip and the center coordinates of the corresponding theoretical chip pattern in the dielectric layer after the global rigid transformation; When the first distance is greater than or equal to the first center distance threshold, it is determined that the dielectric layer has a correction requirement.

4. The alignment correction method according to claim 3, characterized in that, The partition rigid transformation parameters include the rotation angle of each chip corresponding to the theoretical pattern of the chip in the dielectric layer, and the alignment correction method further includes: Obtain the iterative rotation angle of each chip; During the correction, the rotation angle of the theoretical pattern of the chip in the dielectric layer is corrected based on the iterative rotation angle of each chip.

5. The alignment correction method according to claim 4, characterized in that, Obtaining the iterative rotation angle of each chip includes: Obtain the actual offset angle of each chip; The iterative rotation angle of each chip is obtained based on the actual offset angle, the rotation angle of the global rigid transformation of the dielectric layer, and the preset number of iterations.

6. The alignment correction method according to claim 1, characterized in that, The alignment correction method further includes: In the second exposure process, the circuit layer and the dielectric layer are aligned to meet the second condition, which includes that the maximum overlay center distance between the circuit layer pattern and the dielectric layer pattern is less than the second center distance threshold. Obtain the global rigid transformation parameters of the line layer; When the global rigidity transformation parameters cause the second exposure process to meet the second condition, the dielectric layer correction is completed; Alternatively, if the global rigidity transformation parameters cause the second exposure process to fail to meet the second condition, the dielectric layer correction fails.

7. A bias correction and alignment control device for use in a direct-write lithography machine, characterized in that, include: At least one processor; A memory that is communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, and when the at least one processor executes the computer program, it implements the alignment method for a direct-write lithography machine as described in any one of claims 1-6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the alignment and correction method for a direct-write lithography machine as described in any one of claims 1-6.

9. A direct-write lithography machine, characterized in that, The direct-write lithography machine includes the alignment control device for the direct-write lithography machine as described in claim 7; Alternatively, the direct-write lithography machine includes a polarization alignment system and a control system, wherein the control system is connected to the polarization alignment system and the control system is used to control the polarization alignment system according to any one of claims 1-6.

10. The direct-write lithography machine according to claim 9, characterized in that, The direct-write lithography machine also includes an exposure system connected to the control system. The exposure system is used to perform exposure when a first condition is met in the first exposure process and to perform exposure when a second condition is met in the second exposure process.

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