Input direct current adaptive calibration circuit

Abstract

The invention relates to the technical field of input direct current amplifiers, and discloses an input direct current self-adaptive calibration circuit. A first input signal controls a first controlled current source, a second controlled current source and a third controlled current source; the negative end of the first controlled current source is connected with one end of the first switch; the other end of the first switch is connected with one end of the second switch and one end of the buffer capacitor; the other end of the second switch is connected with the positive end of the second controlled current source; the negative end of the third controlled current source is connected with one end of the variable resistance network, the negative input end of the first comparator and the negative input end of the second comparator; the positive input end of the first comparator is connected with the highest threshold value of the first input signal; the positive input end of the second comparator is connected with the lowest threshold value of the first input signal. The problem of output saturation caused by input direct current of the amplifier is solved. According to the invention, the technical effects of flexibility, adjustability, large DC input range and fast stable speed are achieved.

Description

Technical Field

[0001] The invention relates to the technical field of input direct current amplifiers, and in particular to an input direct current adaptive calibration circuit. Background Art

[0002] There are three main types of existing DC adaptive calibration circuits: the first type manually collects the DC component of the input signal before the amplifier works normally, and uses the collected data as a fixed offset to offset after the amplifier works normally. This method is time-consuming and labor-intensive, and is a one-time calibration, and cannot adjust the feedback voltage in real time.

[0003] The second method uses an ADC (analog to digital converter) to sample and quantize the amplified signal in real time, and then controls the DAC (digital to analog converter) to output the feedback voltage after digital signal processing. This solution uses a mixed digital-analog feedback method, and the feedback accuracy is limited by the accuracy of the DAC, which can easily lead to loop instability and high cost.

[0004] The third method is to filter the input signal and directly feed it back to the bias voltage input of the closed-loop amplifier through analog means. However, this method is difficult to apply to low-frequency targets. When the signal frequency is low, the cutoff frequency of the filter needs to be lower than the signal frequency, which results in a very large time constant, so the loop takes a long time to stabilize.

[0005] In summary, in order to solve the above problems, this application proposes an input DC adaptive amplifier circuit solution based on an analog feedback network, which uses the charging and discharging of current to adjust the feedback voltage in real time and continuously. The circuit has a large DC input range and a fast stabilization speed, and can effectively avoid the output saturation problem caused by the DC input of the amplifier. Summary of the invention

[0006] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention provides an input DC adaptive calibration circuit, which enables the amplifier to normally amplify useful signals under a large DC offset voltage, and effectively avoids the output saturation problem caused by the input DC of the amplifier.

[0007] The present invention provides an input DC adaptive calibration circuit, comprising: a buffer capacitor, a first controlled current source, a second controlled current source, a third controlled current source, a first comparator, a second comparator, a variable resistor network, a first switch and a second switch: a first input signal controls the output current of the first controlled current source, the second controlled current source and the third controlled current source; the positive end of the first controlled current source is connected to a power supply; the negative end of the first controlled current source is connected to one end of the first switch; the other end of the first switch is connected to one end of the second switch and one end of the buffer capacitor; the other end of the second switch is connected to the positive end of the second controlled current source; the second The negative end of the controlled current source is grounded; the other end of the buffer capacitor is grounded; the positive end of the third controlled current source is connected to a power supply; the negative end of the third controlled current source is connected to one end of the variable resistance network, the negative input end of the first comparator and the negative input end of the second comparator; the other end of the variable resistance network is grounded; the positive input end of the first comparator is connected to the highest threshold of the first input signal; the output end of the first comparator is used to control the on and off of the first switch and the resistance value of the variable resistance network; the positive input end of the second comparator is connected to the lowest threshold of the first input signal; the output end of the second comparator is used to control the on and off of the second switch and the resistance value of the variable resistance network; one end of the buffer capacitor outputs a feedback signal.

[0008] An input DC adaptive calibration circuit provided according to the present invention also includes: an input stage amplifier, which is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal and a signal output terminal: the signal input terminal is connected to the second input signal; the signal output terminal outputs the first input signal.

[0009] An input DC adaptive calibration circuit provided according to the present invention also includes a first buffer, wherein the positive input terminal of the first buffer is connected to one end of a buffer capacitor; and the output terminal of the first buffer is connected to the bias voltage input terminal and the negative input terminal of the first buffer.

[0010] An input DC adaptive calibration circuit provided according to the present invention also includes: a driving amplifier, an NMOS driving tube, a load resistor and a fourth controlled current source: the positive input terminal of the driving amplifier is connected to the signal output terminal; the output terminal of the driving amplifier is connected to the gate of the NMOS driving tube; one end of the load resistor is connected to the source of the NMOS driving tube and the negative input terminal of the driving amplifier; the other end of the load resistor is grounded; the negative end of the fourth controlled current source is connected to the drain of the NMOS driving tube.

[0011] According to an input DC adaptive calibration circuit provided by the present invention, the input stage amplifier also includes an adder: the output end of the adder is connected to the signal input end; the first input end of the adder inputs the DC bias component of the second input signal; the second input end of the adder inputs the detection signal component of the second input signal.

[0012] According to an input DC adaptive calibration circuit provided by the present invention, the first switch is a PMOS tube, and the second switch is an NMOS tube.

[0013] According to an input DC adaptive calibration circuit provided by the present invention, the first controlled current source, the second controlled current source and the third controlled current source are all sub-current mirrors of a common-source and common-gate current mirror.

[0014] According to an input DC adaptive calibration circuit provided by the present invention, the fourth controlled current source is a mother current mirror of a common-source common-gate current mirror.

[0015] According to an input DC adaptive calibration circuit provided by the present invention, when the voltage of the feedback signal is higher than the highest threshold, the resistance of the variable resistor network increases, and the voltage at the negative input terminal of the first comparator and the second comparator will jump upward; when the voltage of the feedback signal is lower than the lowest threshold, the resistance of the variable resistor network decreases, and the voltage at the negative input terminal of the first comparator and the second comparator will jump downward.

[0016] The above one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects: the feedback loop of the present invention is flexible and adjustable, and the output current of the current source and the size of the charging capacitor can be configured according to different application scenarios, and the feedback speed can be controlled; the resistance value can be configured according to different application scenarios, and the threshold of the actual output voltage can be adjusted. The present invention has a simple structure and low cost. Since ultra-low frequency filtering is not required, ultra-large resistors or capacitors are not required, which is conducive to on-chip integration; reducing the working current of the controlled current source can reduce system power consumption.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 The present invention is a schematic diagram of the structure of an input DC adaptive calibration circuit provided by the present invention.

[0020] Figure 2 It is a schematic diagram of an implementation example of an input DC adaptive calibration circuit provided by the present invention.

[0021] Figure 3 It is a simulation diagram A of the adjustment process of an input DC adaptive calibration circuit provided by the present invention.

[0022] Figure 4 It is a simulation diagram B of the adjustment process of an input DC adaptive calibration circuit provided by the present invention.

[0023] Reference numerals: 1. Input stage amplifier; 2. First buffer; 3. Buffer capacitor; 4. First controlled current source; 5. Second controlled current source; 6. Third controlled current source; 7. First comparator; 8. Second comparator; 9. First switch; 10. Second switch; 11. Variable resistor network; 12. Driver amplifier; 13. NMOS driver tube; 14. Fourth controlled current source; 15. Load resistor; 16. First resistor; 17. Second resistor; 18. Third resistor; 19. First switch transistor; 20. Second switch transistor; 21. First input signal input terminal; 22. Feedback signal output terminal; 23. First input signal highest threshold input terminal; 24. First input signal lowest threshold input terminal; 25. First input terminal of adder; 26. Second input terminal of adder; 27. Power supply; 28. Output signal output terminal. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0025] In the description of the embodiments of the present invention, it should be noted that the terms “first”, “second” and “third” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0026] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0028] Example: like Figure 1 The present invention provides an input DC adaptive calibration circuit, comprising: a buffer capacitor 3, a first controlled current source 4, a second controlled current source 5, a third controlled current source 6, a first comparator 7, a second comparator 8, a variable resistor network 11, a first switch 9 and a second switch 10: The first input signal controls the output current magnitudes of the first controlled current source 4, the second controlled current source 5 and the third controlled current source 6; The positive terminal of the first controlled current source 4 is connected to the power supply 27; The negative terminal of the first controlled current source 4 is connected to one end of the first switch 9; The other end of the first switch 9 is connected to one end of the second switch 10 and one end of the buffer capacitor 3; The other end of the second switch 10 is connected to the positive end of the second controlled current source 5; The negative terminal of the second controlled current source 5 is grounded; The other end of the buffer capacitor 3 is grounded; The positive terminal of the third controlled current source 6 is connected to the power supply 27; The negative terminal of the third controlled current source 6 is connected to one end of the variable resistance network 11, the negative input terminal of the first comparator 7 and the negative input terminal of the second comparator 8; The other end of the variable resistance network 11 is grounded; The positive input terminal of the first comparator 7 is connected to the highest threshold of the first input signal; The output end of the first comparator 7 is used to control the on-off of the first switch 9 and the resistance value of the variable resistor network 11; The positive input terminal of the second comparator 8 is connected to the lowest threshold of the first input signal; The output end of the second comparator 8 is used to control the on-off of the second switch 10 and the resistance value of the variable resistor network 11; One end of the buffer capacitor 3 outputs a feedback signal, and the feedback signal is output from a feedback signal output end 22 .

[0029] The first input signal is input from the first input signal input terminal 21, and is used to control the first controlled current source 4, the second controlled current source 5, and the third controlled current source 6. The first controlled current source 4, the second controlled current source 5, and the third controlled current source 6 are all common-source and common-gate current mirrors, and are used to copy the first input signal proportionally to the corresponding circuit. The first controlled current source 4 and the third controlled current source 6 can change according to the change of the output voltage of the closed-loop amplifier circuit. The greater the output voltage of the feedback signal deviates from the set threshold range, the faster the feedback adjustment speed of the circuit.

[0030] The highest threshold of the first input signal is input to the positive input terminal of the first comparator 7 via the highest threshold input terminal 23 of the first input signal. The first comparator 7 is used to control the on-off of the first switch 9 and the resistance value of the variable resistor network 11 .

[0031] The lowest threshold of the first input signal is input to the positive input terminal of the second comparator 8 via the lowest threshold input terminal 24 of the first input signal. The second comparator 8 is used to control the on-off of the second switch 10 and the resistance value of the variable resistance network 11 .

[0032] The first comparator 7, the second comparator 8 and the variable resistor network 11 can suppress interference to a certain extent and improve the noise tolerance of the circuit. When the output voltage of the feedback signal is slightly higher than the set highest threshold, the resistance of the variable resistor network 11 increases, and the negative input voltage of the first comparator 7 and the second comparator 8 will jump upward. When the output voltage of the feedback signal is slightly lower than the set lowest threshold, the resistance of the variable resistor network 11 decreases, and the negative input voltage of the first comparator 7 and the second comparator 8 will jump downward.

[0033] Specific embodiments of the present invention are as follows Figure 2 As shown: The embodiment of the present invention further includes an input stage amplifier 1: the input stage amplifier 1 is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal and a signal output terminal: The signal input terminal is connected to a second input signal; The output signal output terminal 28 outputs the first input signal.

[0034] The embodiment of the present invention further includes a first buffer 2: The positive input terminal of the first buffer 2 is connected to one end of the buffer capacitor 3; The output terminal of the first buffer 2 is connected to the bias voltage input terminal and the negative input terminal of the first buffer 2 .

[0035] The embodiment of the present invention further includes a driving amplifier 12, an NMOS driving tube 13, a load resistor 15 and a fourth controlled current source 14: The positive input terminal of the driving amplifier 12 is connected to the signal output terminal; The output end of the driving amplifier 12 is connected to the gate of the NMOS driving tube 13; One end of the load resistor 15 is connected to the source of the NMOS driver tube 13 and the negative input end of the driver amplifier 12; The other end of the load resistor 15 is grounded; The negative end of the fourth controlled current source 14 is connected to the drain of the NMOS driving tube 13 .

[0036] The input stage amplifier 1 of the embodiment of the present invention further includes an adder: The output end of the adder is connected to the signal input end; The first input terminal 25 of the adder inputs the DC bias component of the second input signal; The second input terminal 26 of the adder receives the detection signal component of the second input signal.

[0037] In the embodiment of the present invention, the DC bias component of the second input signal is inputted through the first input terminal 25 of the adder; the detection signal component of the second input signal is inputted through the second input terminal 26 of the adder. The input stage amplifier 1 is a closed-loop amplifier circuit. The DC bias component and the detection signal component of the second input signal are added and amplified by the input stage amplifier 1 to obtain the first input signal. The voltage is , is input into the positive input terminal of the driver amplifier 12. Since the driver amplifier 12 and the NMOS driver tube 13 form a negative feedback, the negative terminal voltage of the driver amplifier 12 is The resistance value of load resistor 15 is , the current flowing through the load resistor 15 is The first controlled current source 4, the second controlled current source 5, the third controlled current source 6, and the fourth controlled current source 14 are all current mirrors of a common source and common gate structure, which can accurately replicate the current in proportion. , and the current ratio between the four current mirrors is adjustable. In particular, the current of the fourth controlled current source 14 is , the voltage of the first input signal After voltage-current-voltage conversion, , The comparison voltage is the lowest threshold value of the first input signal. and the highest threshold of the first input signal , controlling the first switch 9 and the second switch 10 to charge and discharge the buffer capacitor 3. In the embodiment of the present invention, the first switch 9 uses a PMOS tube, and the second switch 10 uses an NMOS tube.

[0038] when When the first comparator 7 and the second comparator 8 both output a high level, the first switch 9 is turned off, the second switch 10, the first switch transistor 19 and the second switch transistor 20 are turned on, and the first resistor 16 and the second resistor 17 are connected in parallel. The impedance of the point decreases, The voltage will jump downward, the buffer capacitor 3 starts to discharge, and the feedback voltage At this time, the first resistor 16, the second resistor 17 and the third resistor 18 are connected in parallel. It can be expressed as: in, is the current of the second controlled current source and the current of the fourth controlled current source The current mirror ratio is , is the resistance value of the first resistor 16, is the resistance value of the second resistor 17, is the resistance value of the third resistor 18, Indicates resistors connected in parallel.

[0039] Since the resistance value of the first resistor 16 is and the resistance value of the second resistor 17 Generally much larger than the resistance value of the third resistor 18 .along with The decline, Gradually rising, It also increased accordingly.

[0040] when When the first comparator 7 outputs a high level, the second comparator 8 outputs a low level, the second switch transistor 20 is turned on, the first switch 9, the second switch 10 and the first switch transistor 19 are all turned off, and the disconnection of the first resistor 16 causes the point The impedance increases, There will be an upward jump, and the buffer capacitor 3 will not be charged or discharged. The voltage remains unchanged. At this time, the second resistor 17 and the third resistor 18 are connected in parallel. It can be expressed as: when When the first comparator 7 and the second comparator 8 both output a low level, the first switch 9, the second switch 10, the first switch transistor 19 and the second switch transistor 20 are all turned off, and the disconnection of the first resistor 16 and the second resistor 17 causes the point The impedance increases again, The voltage will jump upward, and the buffer capacitor 3 will start to charge. The voltage rises. At this time, It can be expressed as: The resistance change of the variable resistor network 11 in the present invention is similar to the positive feedback effect, which can suppress interference to a certain extent and improve the noise tolerance of the circuit. The greater the deviation from the set threshold range, the greater the charge and discharge current of the buffer capacitor 3, and the feedback voltage The faster the adjustment speed.

[0041] When the entire circuit is stable, the first input signal becomes the output signal, and the output signal output terminal 28 outputs the output signal.

[0042] The adjustment process of the embodiment of the present invention is as follows Figure 3 and Figure 4 As shown, the resistance of the load resistor 15 is Set as , the resistance of the first resistor 16 Set as , the resistance of the second resistor 17 Set as , the resistance of the third resistor 18 Set as , the capacitance value of buffer capacitor 3 is set to , the current of the fourth controlled current source and the current of the third controlled current source The current mirror ratio is set to 1:10, and the current of the fourth controlled current source , the current of the first controlled current source and a current mirror of a second controlled current source The ratio is 1:1:1, the detection signal component of the second input signal is 1mV, a 10KHz sinusoidal signal, the DC bias component of the second input signal is a step signal of 0.1V, the second input signal is a superimposed waveform of the detection signal component and the DC bias component, the amplification factor of the input stage amplifier 1 is 250 times, and the threshold of the first input signal is: , When the step signal is an upward step, the output signal will immediately saturate to 2.5V, and as the feedback signal rises, the signal gradually returns to normal; when the step signal is a downward step, the output signal will immediately saturate to 0V, and as the feedback signal decreases, the signal gradually returns to normal. When the charge and discharge current is set to twice the original, the feedback adjustment time is reduced to half of the original.

[0043] The embodiment of the present invention uses an analog method to achieve continuous adjustment of the feedback voltage, and the stabilization speed is relatively fast. The input signal is first amplified by the input stage amplifier 1, and then enters the input DC adaptive amplifier circuit. The controlled current source adjusts the current size in real time according to the output voltage of the input stage amplifier 1. The comparator compares the output of the input stage amplifier 1 with the threshold voltage, adjusts the resistance of the variable resistor network 11, and controls the switch to charge and discharge the buffer capacitor 3. Finally, the voltage on the buffer capacitor 3 is fed back to the bias voltage input terminal of the input stage amplifier 1 through the buffer.

[0044] The embodiment of the present invention can suppress interference to a certain extent and improve the noise tolerance of the circuit. When the output voltage of the input stage amplifier 1 is slightly higher than the set highest threshold, the resistance of the variable resistor network 11 increases, and the negative input voltage of the first comparator 7 and the second comparator 8 will jump upward. When the output voltage of the input stage amplifier 1 is slightly lower than the set lowest threshold, the resistance of the variable resistor network 11 decreases, and the negative input voltage of the first comparator 7 and the second comparator 8 will jump downward.

[0045] The embodiment of the present invention can change the output voltage of the input stage amplifier 1 according to the change of the output voltage of the input stage amplifier 1. The greater the output voltage of the input stage amplifier 1 deviates from the set threshold range, the faster the feedback adjustment speed of the circuit.

[0046] The feedback loop of the embodiment of the present invention is flexible and adjustable. The output current of the current source and the size of the buffer capacitor 3 can be configured according to different application scenarios, and the feedback speed can be controlled; the resistance value can be configured according to different application scenarios, and the threshold of the actual output voltage can be adjusted.

[0047] The embodiment of the present invention has a simple structure and low cost. Since ultra-low frequency filtering is not required, no ultra-large resistor or capacitor is required, which is conducive to on-chip integration. Reducing the operating current of the controlled current source can reduce system power consumption.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An input DC adaptive calibration circuit, characterized in that: include: Buffer capacitor, first controlled current source, second controlled current source, third controlled current source, first comparator, second comparator, variable resistor network, first switch and second switch: A first input signal controls the output current magnitudes of the first controlled current source, the second controlled current source and the third controlled current source; The positive terminal of the first controlled current source is connected to a power supply; A negative terminal of the first controlled current source is connected to one terminal of the first switch; The other end of the first switch is connected to one end of the second switch and one end of the buffer capacitor; The other end of the second switch is connected to the positive end of the second controlled current source; The negative terminal of the second controlled current source is grounded; The other end of the buffer capacitor is grounded; The positive terminal of the third controlled current source is connected to a power supply; The negative terminal of the third controlled current source is connected to one end of the variable resistance network, the negative input terminal of the first comparator and the negative input terminal of the second comparator; The other end of the variable resistor network is grounded; The positive input terminal of the first comparator is connected to the highest threshold of the first input signal; The output end of the first comparator is used to control the on-off of the first switch and the resistance value of the variable resistor network; The positive input terminal of the second comparator is connected to the lowest threshold of the first input signal; The output terminal of the second comparator is used to control the on-off of the second switch and the resistance value of the variable resistance network; One end of the buffer capacitor outputs a feedback signal.

2. The input DC adaptive calibration circuit according to claim 1, characterized in that: It also includes an input stage amplifier: the input stage amplifier is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal and a signal output terminal: The signal input terminal is connected to a second input signal; The signal output terminal outputs a first input signal.

3. The input DC adaptive calibration circuit according to claim 2, characterized in that: Also includes the first buffer: The positive input terminal of the first buffer is connected to one end of the buffer capacitor; The output terminal of the first buffer is connected to the bias voltage input terminal and the negative input terminal of the first buffer.

4. The input DC adaptive calibration circuit according to claim 2, characterized in that: It also includes a driver amplifier, an NMOS driver tube, a load resistor and a fourth controlled current source: The positive input terminal of the driving amplifier is connected to the signal output terminal; The output end of the driving amplifier is connected to the gate of the NMOS driving tube; One end of the load resistor is connected to the source of the NMOS driver tube and the negative input end of the driver amplifier; The other end of the load resistor is grounded; The negative end of the fourth controlled current source is connected to the drain of the NMOS driving tube.

5. The input DC adaptive calibration circuit according to claim 3, characterized in that: The input stage amplifier also includes an adder: The output end of the adder is connected to the signal input end; The first input terminal of the adder inputs the DC bias component of the second input signal; The second input terminal of the adder inputs the detection signal component of the second input signal.

6. The input DC adaptive calibration circuit according to claim 1, characterized in that: The first switch is a PMOS tube, and the second switch is an NMOS tube.

7. The input DC adaptive calibration circuit according to claim 1, characterized in that: The first controlled current source, the second controlled current source and the third controlled current source are all sub-current mirrors of a cascode current mirror.

8. The input DC adaptive calibration circuit according to claim 4, characterized in that: The fourth controlled current source is a parent current mirror of a cascode current mirror.

9. The input DC adaptive calibration circuit according to any one of claims 1 to 8, characterized in that: When the voltage of the feedback signal is higher than the highest threshold, the resistance of the variable resistor network increases, and the voltage at the negative input terminal of the first comparator and the second comparator will jump upward. When the voltage of the feedback signal is lower than the lowest threshold, the resistance of the variable resistor network decreases, and the voltage at the negative input terminal of the first comparator and the second comparator will jump downward.

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