Power-on timing control circuit and monitoring method, device and data acquisition board thereof

Abstract

The application provides a power-on timing control circuit and a monitoring method and device thereof and a data acquisition board card, the first controller is used for sending an enable signal to control the power-on timing of each power rail, and the second controller is used for monitoring the state of each power rail, so that the complexity of the hardware platform and the difficulty of PCB design are reduced, and the software workload is reduced. The technical problem that in the prior art, an additional chip is added to the existing hardware platform, a CPLD is used to control the power-on timing of each power rail, and an ADC is used to monitor the state of each power rail in the board, so that the complexity of the hardware platform is high, the difficulty of PCB design is great, and the software workload is large.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data acquisition processing circuit, in particular to a power-on timing control circuit and a monitoring method and device thereof, and a data acquisition board card. BACKGROUND

[0002] With the development of data acquisition board cards, the functional requirements for data acquisition board cards are gradually increasing. In addition to basic data acquisition capabilities, high-performance computing capabilities, storage capabilities, and board health state monitoring capabilities are also required. Therefore, while retaining the original functional circuits, the data acquisition board card introduces a DSP coprocessor for implementing specific algorithm calculation, introduces an SSD solid state disk grain for backing up raw data, and introduces an MCU powered by an independent power supply VCC for implementing board health state monitoring.

[0003] In addition to the FPGA originally mounted on the data acquisition board card, the newly introduced DSP coprocessor and SSD solid state disk grain have strict requirements for power-on timing. Accurate control of power-on timing is crucial to ensure stable operation of the processor. Any power supply that does not meet the requirements may cause the processor to malfunction, and in severe cases, the processor may not even boot up. Therefore, a power-on timing control monitoring circuit is needed to control the power-on timing and timely detect processor power supply link faults.

[0004] In related technologies, the existing power timing control circuit design scheme uses a CPLD to separately control the power-on timing of each power supply rail, and uses an ADC to monitor the state of each power supply rail in the board. This scheme requires additional chips on the existing hardware platform, which not only increases the complexity of the hardware platform, but also increases the difficulty of PCB design and software workload. SUMMARY

[0005] The present application provides a power-on timing control circuit and a monitoring method and device thereof, and a data acquisition board card to solve the problems of high complexity of the hardware platform, high difficulty of PCB design, and high software workload.

[0006] In the first aspect of the embodiments of the present application, a power-on timing control circuit is first provided, which comprises a first controller, a second controller, M load modules, and M power supply modules. Each power supply module contains a different number of power supply chip sets, and each power supply chip set contains at least one power supply chip. M is a positive integer.

[0007] The i-th end pin of the first controller is connected to the enable end of the power supply chip in the first power supply chip set of the i-th power supply module.

[0008] In the i-th power module, any two adjacent power chip groups are connected in series, and the power chips contained in each power chip group in the i-th power module are connected in parallel.

[0009] The i-th pin of the second controller is connected to the signal terminal of the power chip in the last power chipset of the i-th power module.

[0010] The signal terminals of the power chips in each power chip group of the i-th power module are connected one-to-one with the pins of the i-th load module, where i is 1, 2, 3, ..., M in sequence.

[0011] In one alternative implementation, each of the power modules includes a different number of resistors and power supplies;

[0012] The signal terminals of the power chips in each power chip group of the i-th power module are connected in series with the pins of the i-th load module through a resistor and a power supply, respectively.

[0013] In an optional implementation, the i-th pin of the first controller outputs an enable signal, which is used to control the startup of the corresponding power module;

[0014] The enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal.

[0015] In one optional implementation, the signal terminal of the power chip in the last power chipset of the i-th power module outputs a circuit signal.

[0016] The i-th pin of the second controller receives the circuit signal.

[0017] In a second aspect of this embodiment, a monitoring method for a power-on timing control circuit is also provided, applied to the power-on timing control circuit described in any one of the first aspects above, the method comprising:

[0018] First controller enable initialization;

[0019] The first controller enables M power modules according to a preset enabling sequence, where M is a positive integer;

[0020] The first controller sends an enable signal from its i-th pin, which is used to sequentially activate each power chip group in each power module.

[0021] After the enable signal is received by the enable terminal of the power chip in the first power chip group of the i-th power module, the output circuit signal is sequentially transmitted to the next power chip group.

[0022] The i-th pin of the second controller monitors the signal terminal of the power chip in the last power chipset of the i-th power module to determine whether the i-th power module is powered on normally. The i-th pins are 1, 2, 3, ..., M.

[0023] In an optional implementation, the i-th terminal of the second controller determines whether the i-th power module is powered on normally by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module, including:

[0024] If the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chipset, then it is determined that the i-th power module is powered on normally.

[0025] If the i-th pin of the second controller does not detect the output of the circuit signal from the signal terminal of the power chip in the last power chip group, then it is determined that the i-th power module is abnormal.

[0026] In an optional implementation, the step of determining that the i-th power module is abnormal if the signal terminal of the power chip in the last power chipset is not detected to output the circuit signal at the i-th pin of the second controller includes:

[0027] Based on a preset time threshold, re-monitor whether the signal terminal of the power chip in the last power chipset outputs the circuit signal;

[0028] If the i-th pin of the second controller does not detect the output of the circuit signal from the signal terminal of the power chip in the last power chipset, then the i-th power module is determined to be a faulty power module, and the faulty power module is reported.

[0029] If the i-th pin of the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, then the i-th power module is determined to be powered on normally.

[0030] In an optional implementation, after the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, and determines that the i-th power module is powered on normally, the method further includes:

[0031] Perform a reset operation on the i-th load module.

[0032] In a third aspect of this application, a monitoring device for a power-on timing control circuit is provided, applied to the power-on timing control circuit described in any one of the first aspects above, the device comprising:

[0033] An initialization module is used for enabling and initializing the first controller.

[0034] A power control module is used by the first controller to control the enabling of M power modules according to a preset enabling sequence, where M is a positive integer;

[0035] The signal transmitting module is used to send an enable signal through the i-th pin of the first controller, and the enable signal is used to sequentially start each power chip group in the power module;

[0036] A power enable module is used so that after the enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset.

[0037] The power monitoring module is used to monitor the signal terminal of the power chip in the last power chipset of the i-th power module by the i-th pin of the second controller to determine whether the i-th power module is powered on normally, where i is 1, 2, 3, ..., M in sequence.

[0038] In a fourth aspect of the embodiments of this application, a data acquisition board is also provided, characterized in that it includes a power-on timing control circuit as described in any one of the first aspects above.

[0039] In a fifth aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0040] Memory, used to store computer programs;

[0041] When a processor executes a program stored in a memory, it implements the steps of the monitoring method for the power-on timing control circuit described in any of the second aspects above.

[0042] In a sixth aspect of the embodiments of this application, a storage medium is also provided, wherein the storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of the monitoring method for the power-on timing control circuit described in any of the second aspects above.

[0043] In a seventh aspect of the embodiments of this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the monitoring method of the power-on timing control circuit described in any of the second aspects above.

[0044] The technical solution provided in this application reduces the complexity of the hardware platform and the difficulty of PCB design, and decreases the software workload by sending an enable signal to control the power-on sequence of each power rail through a first controller and monitoring the status of each power rail through a second controller. This solves the technical problems in the prior art, which involves adding extra chips to the existing hardware platform, using a CPLD to individually control the power-on sequence of each power rail, and using an ADC to monitor the status of each power rail on the board, resulting in high hardware platform complexity, high PCB design difficulty, and a large software workload. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0048] Figure 1 A schematic diagram of a power-on timing control circuit provided in an embodiment of this application;

[0049] Figure 2 A schematic diagram illustrating the implementation process of a monitoring method for a power-on timing control circuit provided in this application embodiment;

[0050] Figure 3 A schematic diagram illustrating the implementation process of another power-on timing control circuit monitoring method provided in this application embodiment;

[0051] Figure 4 A schematic diagram illustrating the implementation process of another power-on timing control circuit monitoring method provided in this application embodiment;

[0052] Figure 5 A schematic diagram of the structure of a monitoring device for a power-on timing control circuit provided in an embodiment of this application;

[0053] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0056] To address the technical challenges of existing technologies that involve adding extra chips to existing hardware platforms, using CPLDs to individually control the power-on timing of each power rail, and employing ADCs to monitor the status of each power rail on the board, resulting in high hardware platform complexity, complex PCB design, and a large amount of software workload, this application provides a power-on timing control circuit, its monitoring method, device, and data acquisition board. This circuit uses a first controller to send an enable signal to control the power-on timing of each power rail, and a second controller to monitor the status of each power rail, thereby reducing hardware platform complexity, PCB design difficulty, and software workload.

[0057] like Figure 1 The diagram shown is a structural schematic of a power-on timing control circuit provided in an embodiment of this application. The power-on timing control circuit 18 includes: a first controller 10, a second controller 11, M load modules 12, and M power modules 13. Each power module contains a different number of power chip sets 14, each power chip set contains at least one power chip 15, and each power module contains a different number of resistors 16 and power supplies 17. M is a positive integer.

[0058] The i-th pin of the first controller 10 is connected to the enable pin of the power chip 15 in the first power chipset 14 of the i-th power module 13.

[0059] In the i-th power module 13, any two adjacent power chip groups 14 are connected in series, and the power chips 15 contained in each power chip group 14 in the i-th power module 13 are connected in parallel.

[0060] The i-th pin of the second controller 11 is connected to the signal terminal of the power chip 15 in the last power chipset 14 of the i-th power module 13.

[0061] The signal terminals of the power chips 15 included in each power chip group 14 in the i-th power module 13 are connected one-to-one with the pins of the i-th load module 12, i being 1, 2, 3, ..., M in sequence.

[0062] In the i-th power module 13, the signal terminals of the power chips 15 included in each power chip group 14 are connected one-to-one with the pins of the i-th load module 12, including being connected in series through a resistor 16 and a power supply 17.

[0063] The i-th pin of the first controller 10 above emits an enable signal to control the startup of the corresponding power module.

[0064] The enable terminal of the power chip 15 in the first power chip group 14 of the i-th power module 13 mentioned above receives the enable signal.

[0065] In the embodiments of this application, such as Figure 1 As shown, the enable pin of the first controller is connected to the enable pin of the power chip 15-1-1 in the first power chip group 14-1 of the i-th power module 13. The signal terminal of the power chip 15-1-1 is connected to the load module through the first resistor 16 and the first power supply 17. When the power chip group 14-1 outputs a voltage that meets the requirements, it will enable the next power chip group 14-2 through the signal terminal of the power chip 15-1-1, and so on, until the last power chip group 14-n is enabled. The signal terminal of the power chip 15-n-1 is connected to the i-th pin of the second controller 11.

[0066] The technical solution provided in this application reduces the complexity of the hardware platform and the difficulty of PCB design, and decreases the software workload by sending an enable signal to control the power-on sequence of each power rail through a first controller and monitoring the status of each power rail through a second controller. This solves the technical problems in the prior art, which involves adding extra chips to the existing hardware platform, using a CPLD to individually control the power-on sequence of each power rail, and using an ADC to monitor the status of each power rail on the board, resulting in high hardware platform complexity, high PCB design difficulty, and a large software workload.

[0067] like Figure 2 The diagram shown is a schematic representation of the implementation flow of a monitoring method for a power-on timing control circuit provided in this application embodiment, which may specifically include the following steps:

[0068] S201, First controller enable initialization.

[0069] In this embodiment, the first controller may be a microcontroller (MCU), including a processor, memory, and input / output interfaces, which can be used to control the startup sequence of the power modules and monitor the power status. The first control unit's enable initialization may involve preparing to output an enable signal to the corresponding power module, thereby ensuring that subsequent power supply and control can be executed smoothly. This embodiment does not limit this aspect.

[0070] For example, the MCU can be enabled and initialized so that it can successfully output an enable signal to the corresponding power module.

[0071] S202, the first controller controls the M power modules to enable according to the preset enable sequence, where M is a positive integer.

[0072] In this embodiment, the preset enable sequence is set according to the startup sequence of the load modules, which can ensure that the power-on sequence of the power modules matches the startup requirements of the load modules, thereby more effectively ensuring the power-on stability of the entire system and the smooth operation of the load. The first controller controls the enable of M power modules according to the preset enable sequence.

[0073] For example, when M is 3, among the three load modules—FPGA, DSP, and SSD—the FPGA needs to be powered on first to ensure the correct loading of its internal logic and configuration. Therefore, the power supply module for the FPGA must be powered on first. Since the DSP and SSD do not have a direct startup dependency, the first controller can flexibly choose which module to enable first. Thus, the first controller can enable the power supply module corresponding to the FPGA first, and then enable the power supply module corresponding to either the DSP or the SSD.

[0074] S203, the i-th pin of the first controller sends an enable signal, which is used to sequentially start each power chipset in each power module.

[0075] In this embodiment, the first controller sends enable signals one by one through the i-th pin corresponding to the first controller according to the preset enable sequence, thereby activating each power chip group corresponding to the power module. The enable signal can be a level signal (such as high level or low level), a pulse signal or other signal type, and this embodiment does not limit it.

[0076] For example, when M is 3, among the three load modules—FPGA, DSP, and SSD—the FPGA needs to be powered on first to ensure the correct loading of its internal logic and configuration. Therefore, the power supply module for the FPGA must be powered on first. Since the DSP and SSD do not have a direct startup dependency, the first controller can flexibly choose which module to enable first. The first controller can enable the power supply module corresponding to the FPGA first, and then enable the power supply module corresponding to either the DSP or the SSD. Therefore, the first controller's enable pin 1 first sends an enable signal to the power supply module corresponding to the FPGA, the second enable pin sends an enable signal to the power supply module corresponding to the DSP, and finally the third enable pin sends an enable signal to the power supply module corresponding to the SSD.

[0077] S204, after the enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset.

[0078] In this embodiment, each power chipset contains at least one power chip. In each power module, the enable terminal of the power chip in the first power chipset receives an enable signal, and the power chip in the first power chipset starts working, thereby outputting circuit signals to the next power chipset in sequence. The circuit signals can be level signals (such as high or low level), pulse signals, or other signal types; this embodiment does not limit the specific type of signal.

[0079] For example, suppose the i-th power module contains three power chipsets: power chipset A, power chipset B, and power chipset C. When the enable signal from the first controller arrives and activates the power chip in power chipset A, power chipset A will start working and output a circuit signal. This signal is then transmitted to power chipset B, and the power chip in power chipset B, upon receiving the signal, will also start working and continue transmitting circuit signals to power chipset C. Therefore, the power chipsets within the entire power module will start sequentially according to a preset enabling order.

[0080] S205, the i-th pin of the second controller monitors the signal terminal of the power chip in the last power chipset of the i-th power module to determine whether the i-th power module is powered on normally, i is 1, 2, 3, ..., M in sequence.

[0081] In this embodiment, the i-th pin of the second controller monitors the signal terminal of the power chip in the last power chipset of the i-th power module to determine whether the i-th power module is powered on normally, where i is 1, 2, 3, ..., M. The second controller can be a microcontroller, and this embodiment does not limit its implementation.

[0082] For example, the i-th pin of the microcontroller can determine whether the i-th power module is not powered on normally or is powered on normally by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module.

[0083] Based on the above description of the technical solution provided in the embodiments of this application, the first controller enables and initializes. According to a preset enabling sequence, the first controller enables M power modules, where M is a positive integer. The i-th pin of the first controller sends an enable signal, which is used to sequentially activate each power chip group in each power module. After receiving the enable signal, the enable terminal of the power chip in the first power chip group of the i-th power module outputs a signal to the next power chip group. The i-th pin of the second controller monitors the signal terminal of the power chip in the last power chip group of the i-th power module to determine whether the i-th power module is powered on normally, where i is 1, 2, 3, ..., M. Thus, by monitoring the signal terminal of the power chip in the last power chip group of the i-th power module through the i-th pin of the second controller to determine whether the i-th power module is powered on normally, the power-on sequence can be controlled, and power link faults can be detected and addressed promptly.

[0084] like Figure 3 The diagram shown illustrates the implementation flow of another power-on timing control circuit monitoring method provided in this application embodiment, which may specifically include the following steps:

[0085] S301, First controller enable initialization.

[0086] In this embodiment of the application, this step is similar to step S201 above, and will not be described in detail here.

[0087] S302, the first controller controls the enabling of M power modules according to the preset enabling sequence, where M is a positive integer.

[0088] In this embodiment of the application, this step is similar to step S202 above, and will not be described in detail here.

[0089] S303, the i-th pin of the first controller sends an enable signal, which is used to sequentially start each power chipset in each power module.

[0090] In this embodiment of the application, this step is similar to step S203 above, and will not be described in detail here.

[0091] S304, after the enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset.

[0092] In this embodiment of the application, this step is similar to step S204 above, and will not be described in detail here.

[0093] S305, if the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chipset, then the i-th power module is determined to be powered on normally.

[0094] In this embodiment of the application, when the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chip group, it is determined that the i-th power module is powered on normally.

[0095] For example, for the power modules corresponding to the load modules FPGA, DSP, and SSD, if the signal terminal of the last power chip in the power module corresponding to the load module FPGA and DSP outputs a circuit signal, then the power modules corresponding to the load module FPGA and DSP are powered on normally.

[0096] In addition, after determining that the i-th power module is powered on normally, the i-th load module can also be reset.

[0097] In this embodiment, resetting the i-th load module can be performed by sending a reset signal to the i-th load module. The reset signal can be a level signal, a pulse signal, or other signal types. After receiving the reset signal, the i-th load module can clear its internal registers, reset its state machine, and shut down unnecessary power-consuming units, ensuring that the i-th load module can start running from a clean and initialized state. This embodiment does not limit this.

[0098] S306 If the i-th pin of the second controller does not detect the signal output circuit signal of the power chip in the last power chipset, then it is determined that the i-th power module is abnormal.

[0099] In this embodiment of the application, when the i-th pin of the second controller does not detect the signal output circuit signal of the power chip in the last power chip group, it is determined that the i-th power module exists.

[0100] For example, for the power modules corresponding to the load modules FPGA, DSP, and SSD, if the signal terminal of the last power chip group in the power module corresponding to the load module FPGA and DSP does not output a circuit signal, then the power module corresponding to the load module FPGA and DSP is abnormal.

[0101] If the i-th power module malfunctions, such as Figure 4 The diagram shown illustrates the implementation flow of another power-on timing control circuit monitoring method provided in this application embodiment, which may specifically include the following steps:

[0102] S401, based on a preset time threshold, re-monitors whether the signal terminal of the power chip in the last power chipset outputs a circuit signal.

[0103] In this embodiment, when the i-th pin of the second controller fails to detect the power chip in the last power chipset not outputting a circuit signal for the first time, it is determined that the power module is abnormal. Based on a preset time threshold, the system re-monitors whether the power chip in the last power chipset is outputting a circuit signal. The preset time threshold refers to the pre-set interval between the first monitoring of the power-on timing control circuit, when an abnormality is detected, and the second monitoring. This interval can be 100ms, 200ms, or 300ms; this embodiment does not limit the specific time threshold.

[0104] For example, when the first pin of the second controller fails to detect that the signal terminal of the power chip in the last power chipset is not outputting a circuit signal for the first time, it is determined that there is an abnormality in the power module. The preset time threshold is 100ms. After the first monitoring ends, there is a 100ms delay before re-monitoring whether the signal terminal of the power chip in the last power chipset is outputting a circuit signal.

[0105] S402, if the i-th pin of the second controller does not detect the signal output circuit signal of the power chip in the last power chipset, then the i-th power module is determined to be a faulty power module and the faulty power module is reported.

[0106] In this embodiment, after a preset time threshold is delayed, the signal terminal of the power chip in the last power chip group is detected by the i-th pin of the second controller to see if a circuit signal is output. If no circuit signal is detected at the signal terminal of the power chip in the last power chip group, the i-th power module is determined to be a faulty power module, and the faulty power module is reported to facilitate subsequent repair of the faulty power module.

[0107] For example, when the first pin of the second controller fails to detect the power chip in the last power chipset not outputting a circuit signal for the first time, it is determined that there is an abnormality in the power module. The preset time threshold is 100ms. After the first monitoring ends, there is a 100ms delay before re-monitoring whether the power chip in the last power chipset outputs a circuit signal. If no circuit signal is detected, then there is a circuit fault in the first power module. The first power module is a faulty power module, and the faulty power module is reported to facilitate subsequent maintenance of the first power module.

[0108] S403, if the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chipset, then the i-th power module is determined to be powered on normally.

[0109] In this embodiment of the application, when the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chip group, it is determined that the i-th power module is powered on normally.

[0110] For example, for the power modules corresponding to the load modules FPGA, DSP, and SSD, if the signal terminal of the last power chip in the power module corresponding to the load module FPGA and DSP outputs a circuit signal, then the power modules corresponding to the load module FPGA and DSP are powered on normally.

[0111] In addition, after determining that the i-th power module is powered on normally, the i-th load module can also be reset.

[0112] In this embodiment, resetting the i-th load module can be performed by sending a reset signal to the i-th load module. The reset signal can be a level signal, a pulse signal, or other signal types. After receiving the reset signal, the i-th load module can clear its internal registers, reset its state machine, and shut down unnecessary power-consuming units, ensuring that the i-th load module can start running from a clean and initialized state. This embodiment does not limit this.

[0113] Corresponding to the above method embodiments, this application also provides a monitoring device for power-on timing control circuits, such as... Figure 5 As shown, as an example Figure 5 The device shown can be applied to the monitoring method of any power-on timing control circuit in the above-mentioned embodiments. The device may include an initialization module 501, a power control module 502, a signal transmission module 503, a power enable module 504, and a power detection module 505.

[0114] Initialization module 501 is used for enabling and initializing the first controller;

[0115] The signal transmitting module 502 is used to send an enable signal through the i-th pin of the first controller. The enable signal is used to sequentially start each power chip group in the power module.

[0116] The power enable module 503 is used to transmit the output circuit signal to the next power chipset after the enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal.

[0117] The power monitoring module 504 is used to monitor the signal terminal of the power chip in the last power chipset of the i-th power module by the i-th pin of the second controller to determine whether the i-th power module is powered on normally. i is 1, 2, 3, ..., M in sequence.

[0118] This application also provides a data acquisition board, including any of the power-on timing control circuits described in the above embodiments.

[0119] This application also provides an electronic device, such as... Figure 6 As shown, it includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604.

[0120] Memory 603 is used to store computer programs;

[0121] In one embodiment of this application, when the processor 601 executes a program stored in the memory 603, it performs the following steps:

[0122] The first controller is enabled and initialized. According to the preset enable sequence, the first controller enables M power modules, where M is a positive integer. The i-th pin of the first controller sends an enable signal, which is used to sequentially start each power chip group in each power module. After the enable terminal of the power chip in the first power chip group of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chip group. The i-th pin of the second controller determines whether the i-th power module is powered on normally by monitoring the signal terminal of the power chip in the last power chip group of the i-th power module. i is 1, 2, 3, M in sequence.

[0123] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0124] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0125] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0126] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0127] In another embodiment provided in this application, a storage medium is also provided, which stores instructions that, when run on a computer, cause the computer to execute the monitoring method of the power-on timing control circuit described in any of the above embodiments.

[0128] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the monitoring method of the power-on timing control circuit described in any of the above embodiments.

[0129] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted from one storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0130] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0131] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0132] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A power-on timing control circuit, characterized in that, The power-on timing control circuit includes: a first controller, a second controller, M load modules, and M power modules. Each power module contains a different number of power chipsets, and each power chipset contains at least one power chip. M is a positive integer. The i-th pin of the first controller is connected to the enable pin of the power chip in the first power chipset of the i-th power module. In the i-th power module, any two adjacent power chip groups are connected in series, and the power chips contained in each power chip group in the i-th power module are connected in parallel. The i-th pin of the second controller is connected to the signal terminal of the power chip in the last power chipset of the i-th power module. The signal terminals of the power chips in each power chip group of the i-th power module are connected one-to-one with the pins of the i-th load module, where i is 1, 2, 3, ..., M in sequence.

2. The power-on timing control circuit according to claim 1, characterized in that, Each of the power modules contains a different number of resistors and power supplies; The signal terminals of the power chips in each power chip group of the i-th power module are connected in series with the pins of the i-th load module through a resistor and a power supply, respectively.

3. The power-on timing control circuit according to claim 1, characterized in that, The first controller sends an enable signal from its i-th pin, which is used to control the startup of the corresponding power module. The enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal.

4. The power-on timing control circuit according to claim 1, characterized in that, The signal output circuit signal of the power chip in the last power chipset of the i-th power module; The i-th pin of the second controller receives the circuit signal.

5. A method for monitoring a power-on timing control circuit, characterized in that, The method, applied to the power-on timing control circuit as described in any one of claims 1 to 4, comprises: First controller enable initialization; The first controller enables M power modules according to a preset enabling sequence, where M is a positive integer; The first controller sends an enable signal from its i-th pin, which is used to sequentially activate each power chip group in each power module. After the enable signal is received by the enable terminal of the power chip in the first power chip group of the i-th power module, the output circuit signal is sequentially transmitted to the next power chip group. The i-th pin of the second controller monitors the signal terminal of the power chip in the last power chipset of the i-th power module to determine whether the i-th power module is powered on normally. The i-th pins are 1, 2, 3, ..., M.

6. The method according to claim 5, characterized in that, The i-th terminal of the second controller determines whether the i-th power module is powered on normally by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module, including: If the i-th pin of the second controller detects the signal output circuit signal of the power chip in the last power chipset, then it is determined that the i-th power module is powered on normally. If the i-th pin of the second controller does not detect the output of the circuit signal from the signal terminal of the power chip in the last power chip group, then it is determined that the i-th power module is abnormal.

7. The method according to claim 6, characterized in that, If the second controller's i-th pin does not detect the output of the circuit signal from the power chip in the last power chipset, then the i-th power module is determined to be abnormal, including: Based on a preset time threshold, re-monitor whether the signal terminal of the power chip in the last power chipset outputs the circuit signal; If the i-th pin of the second controller does not detect the output of the circuit signal from the signal terminal of the power chip in the last power chipset, then the i-th power module is determined to be a faulty power module, and the faulty power module is reported. If the i-th pin of the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, then the i-th power module is determined to be powered on normally.

8. The method according to claim 6 or claim 7, characterized in that, If the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, and the i-th power module is determined to be powered on normally, the method further includes: Perform a reset operation on the i-th load module.

9. A monitoring device for a power-on timing control circuit, characterized in that, The device, applied to the power-on timing control circuit as described in any one of claims 1 to 4, comprises: An initialization module is used for enabling and initializing the first controller. A power control module is used by the first controller to control the enabling of M power modules according to a preset enabling sequence, where M is a positive integer; The signal transmitting module is used to send an enable signal through the i-th pin of the first controller, and the enable signal is used to sequentially start each power chip group in the power module; A power enable module is used so that after the enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset. The power monitoring module is used to monitor the signal terminal of the power chip in the last power chipset of the i-th power module by the i-th pin of the second controller to determine whether the i-th power module is powered on normally, where i is 1, 2, 3, ..., M in sequence.

10. A data acquisition board, characterized in that, Includes the power-on timing control circuit as described in any one of claims 1 to 4.

Images