A low voltage low power bandgap reference source circuit without triode

Abstract

The application claims a low-voltage low-power bandgap reference source circuit without triode, comprising a starting and biasing circuit, a bandgap reference core circuit and a temperature compensation circuit. The application adopts the techniques of the difference between the gate-source voltage of PMOS tube M6 and PMOS tube M7 working in the sub-threshold region to generate the positive temperature coefficient voltage and the gate-source voltage of NMOS tube M8 working in the sub-threshold region to realize the first-order temperature compensation of the bandgap reference voltage, and the technique of the absolute value of the threshold voltage of MOS tube working in the saturation region having the negative temperature coefficient to realize the high-order nonlinear current I NL , and then compensate the high-order nonlinearity of the temperature of the first-order temperature compensation bandgap reference voltage provided by the bandgap reference core circuit, and then obtain the high-order temperature compensation bandgap reference voltage, so as to realize the low-voltage low-power bandgap reference source circuit without triode.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a triode-free low-voltage and low-power bandgap reference source circuit. Background Art

[0002] Bandgap reference circuits are one of the key functional modules of integrated circuit chip systems, providing high-performance reference signals. With the advancement of integrated circuit technology, more and more functional modules are integrated onto the same chip, placing higher demands on the performance of bandgap reference circuits.

[0003] Figure 1 This is a traditional bandgap reference source circuit, in which PMOS transistors M1, M2, amplifier AMP, resistor R1, PNP transistors Q1, and PNP transistors Q2 generate a positive temperature coefficient current. This current flows through resistor R2 to generate a positive temperature coefficient voltage, which is weighted with the emitter-base voltage of PNP transistor Q3 with a negative temperature coefficient to generate a bandgap reference voltage. PMOS transistors M1, M2, and M3 have the same channel width-to-length ratio, the emitter area of ​​PNP transistor Q2 is m times that of PNP transistor Q1, and resistors R1 and R2 are made of the same material. The output voltage V REF for Among them, V EB1 is the emitter-base voltage of the PNP transistor Q1, R1 is the impedance of the resistor R1, R2 is the impedance of the resistor R2, q is the electron charge, k is the Boltzmann constant, and T is the absolute temperature. By optimizing the relevant parameters of the resistor, a reference voltage V with zero temperature characteristics can be obtained within a certain temperature range. REF . Figure 1 Three transistors are used, which occupy a large physical area and consume a large amount of power, thereby restricting its application in high-performance and low-power integrated circuit chip systems. Summary of the Invention

[0004] The present invention aims to solve the above problems of the prior art and proposes a low-voltage, low-power bandgap reference source circuit without a transistor. The technical solution of the present invention is as follows:

[0005] A transistor-free, low-voltage, low-power bandgap reference circuit comprises a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The startup and bias circuit has a signal output connected to the bandgap reference core circuit and the temperature compensation circuit, respectively. The bandgap reference core circuit has a signal output connected to the startup and bias circuit, while the temperature compensation circuit has a signal output connected to the bandgap reference core circuit. The startup and bias circuit provides bias and startup signals to the bandgap reference core circuit and the temperature compensation circuit, and the temperature compensation circuit provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit.

[0006] Furthermore, the startup and bias circuit includes: a PMOS transistor MS1, a PMOS transistor MS2, a PMOS transistor MS3, an NMOS transistor MS4, an NMOS transistor MS5, an NMOS transistor MS6, a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a resistor R1, and a resistor R2, wherein the source of the PMOS transistor MS1 is respectively connected to the source of the PMOS transistor M1 and the external power supply VDD, the gate of the PMOS transistor MS1 is respectively connected to the drain of the PMOS transistor MS1 and the source of the PMOS transistor MS2, the gate of the PMOS transistor MS2 is respectively connected to the drain of the PMOS transistor MS2 and the source of the PMOS transistor MS3, the gate of the PMOS transistor MS3 is respectively connected to the drain of the PMOS transistor MS3, the drain of the NMOS transistor MS4, the gate of the NMOS transistor MS5, and the NMOS transistor MS6. The gate of the OS transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4, and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

[0007] Furthermore, the bandgap reference core circuit includes: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, a resistor R3, and a resistor R4, wherein the source of the PMOS transistor M5 is connected to the external power supply VDD, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M6 and the source of the PMOS transistor M7, the gate of the PMOS transistor M6 is connected to the drain of the PMOS transistor M6 and one end of the resistor R3, and the other end of the resistor R3 is connected to the gate of the NMOS transistor M8. The drain of the NMOS transistor M8 is connected to the gate of the NMOS transistor M8 and the gate of the NMOS transistor M9. The source of the NMOS transistor M8 is respectively connected to the source of the NMOS transistor M9 and the external ground GND. The gate of the PMOS transistor M7 is respectively connected to the drain of the PMOS transistor M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS transistor M4, the gate of the NMOS transistor MS4 and the circuit output terminal VREF. The other end of the resistor R4 is connected to the drain of the NMOS transistor M9.

[0008] Furthermore, the temperature compensation circuit includes: a PMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a resistor R5, a resistor R6, a resistor R7 and a resistor R8, wherein the source of the PMOS tube M10 is connected to the source of the PMOS tube M13 and the external power supply VDD respectively, the drain of the PMOS tube M10 is connected to the other end of the resistor R5 and the gate of the NMOS tube M11 respectively, the other end of the resistor R6 is connected to the gate of the NMOS tube M11 respectively, The drain of the NMOS transistor M11 is connected to the gate of the NMOS transistor M12, the source of the NMOS transistor M11 is connected to the drain of the NMOS transistor M12, the source of the NMOS transistor M12 is respectively connected to the source of the NMOS transistor M15 and the external ground GND, the drain of the PMOS transistor M13 is connected to the source of the PMOS transistor M14, the gate of the PMOS transistor M14 is respectively connected to the drain of the PMOS transistor M14 and the other end of the resistor R7, and the other end of the resistor R8 is respectively connected to the gate of the NMOS transistor M15 and the drain of the NMOS transistor M15.

[0009] Furthermore, in the bandgap reference core circuit, the PMOS transistor M6, the PMOS transistor M7, the NMOS transistor M8 and the NMOS transistor M9 all operate in the subthreshold region, and the drain current I D and the gate-source voltage V GS They are and Where W / L is the channel width-to-length ratio of the MOS tube, I0 is a parameter related to the process, η is a non-ideal factor greater than 1, and V TH is the threshold voltage of the MOS tube, VGS is the gate-source voltage of the MOS tube, V T is the thermovoltage with a temperature coefficient. And the threshold voltage of MOS tube |V TH |Has negative temperature characteristics, so the gate-source voltage V of the MOS tube working in the subthreshold region GS The bandgap reference core circuit provides a voltage V at the output end of the circuit. REF1 for Among them, V GS8 is the gate-source voltage of NMOS tube M8, R3 is the impedance of resistor R3, I D8-0 is the drain current of the NMOS transistor M8 when the bandgap reference core circuit is working, (W / L)6 is the channel width-to-length ratio of the PMOS transistor M6, (W / L)7 is the channel width-to-length ratio of the PMOS transistor M7, (W / L)8 is the channel width-to-length ratio of the NMOS transistor M8, and (W / L)9 is the channel width-to-length ratio of the NMOS transistor M9. Factor V GS8 +I D8-0 R3 has a negative temperature coefficient, factor Has a positive temperature coefficient, so the voltage V REF1 It is a bandgap reference voltage with first-order temperature compensation.

[0010] Furthermore, in the temperature compensation circuit, the NMOS transistor M12 operates in the linear region, and the PMOS transistor M10, NMOS transistor M11, PMOS transistor M13, PMOS transistor M14 and NMOS transistor M15 all operate in the saturation region. The current I provided by the temperature compensation circuit to the bandgap reference core circuit is NL For I NL =I D10 +I D13 -I D11 -I D15 , where I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, I D11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15. At the same time, the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL It has high-order temperature nonlinearity.

[0011] Furthermore, the output terminal VREF voltage V REF for Among them, the factor It has high-order temperature nonlinearity, and can compensate V by optimizing the relevant circuit parameters. REF1 The high-order temperature nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF The advantages and beneficial effects of the present invention are as follows:

[0012] The present invention provides a triode-free low-voltage and low-power bandgap reference source circuit. The first-order bandgap reference voltage is realized by adopting the technology that the difference between the gate-source voltages of two MOS tubes working in the subthreshold region generates a positive temperature characteristic and the gate-source voltage of the MOS tube working in the subthreshold region has a negative temperature characteristic. The high-order temperature nonlinear current is generated by adopting the negative temperature characteristic of the absolute value of the threshold voltage of the MOS tube working in the saturation region and the high-order temperature nonlinearity of the first-order bandgap reference voltage is compensated, thereby obtaining a high-order temperature-compensated bandgap reference voltage, thereby realizing a triode-free low-voltage and low-power bandgap reference source circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the schematic diagram of the traditional bandgap reference source circuit;

[0014] Figure 2 A schematic diagram of a low-voltage, low-power bandgap reference source circuit without a triode is provided for a preferred embodiment of the present invention;

[0015] Figure 3 The present invention provides a simulation diagram of output voltage and temperature of a low-voltage and low-power bandgap reference source circuit without a transistor according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0017] The technical solution of the present invention to solve the above technical problems is:

[0018] In the embodiments of the present application, a first-order bandgap reference voltage is realized by using the difference in gate-source voltage of two MOS transistors operating in the subthreshold region to generate a positive temperature characteristic, and a negative temperature characteristic of the gate-source voltage of the MOS transistor operating in the subthreshold region. A high-order temperature nonlinear current is generated by using the negative temperature characteristic of the absolute value of the threshold voltage of the MOS transistor operating in the saturation region to compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap reference voltage, thereby realizing a low-voltage, low-power bandgap reference source circuit without a transistor.

[0019] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] Example

[0021] A low-voltage and low-power bandgap reference source circuit without a transistor, such as Figure 2 As shown, it includes a startup and bias circuit 1, a bandgap reference core circuit 2 and a temperature compensation circuit 3; wherein, the signal output end of the startup and bias circuit 1 is respectively connected to the signal input end of the bandgap reference core circuit 2 and the signal input end of the temperature compensation circuit 3, the signal output end of the bandgap reference core circuit 2 is connected to the signal input end of the startup and bias circuit 1, and the signal output end of the temperature compensation circuit 3 is connected to the signal input end of the bandgap reference core circuit 2. The startup and bias circuit 1 provides bias and startup signals for the bandgap reference core circuit 2 and the temperature compensation circuit 3, and the temperature compensation circuit 3 provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit 2.

[0022] As a preferred technical solution, Figure 2 As shown, the startup and bias circuit 1 includes: a PMOS transistor MS1, a PMOS transistor MS2, a PMOS transistor MS3, an NMOS transistor MS4, an NMOS transistor MS5, an NMOS transistor MS6, a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a resistor R1, and a resistor R2, wherein the source of the PMOS transistor MS1 is respectively connected to the source of the PMOS transistor M1 and the external power supply VDD, the gate of the PMOS transistor MS1 is respectively connected to the drain of the PMOS transistor MS1 and the source of the PMOS transistor MS2, the gate of the PMOS transistor MS2 is respectively connected to the drain of the PMOS transistor MS2 and the source of the PMOS transistor MS3, the gate of the PMOS transistor MS3 is respectively connected to the drain of the PMOS transistor MS3, the drain of the NMOS transistor MS4, the gate of the NMOS transistor MS5, and the NMOS transistor VDD. The gate of the S transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4, and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

[0023] The bandgap reference core circuit 2 includes: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, a resistor R3, and a resistor R4, wherein the source of the PMOS transistor M5 is connected to the external power supply VDD, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M6 and the source of the PMOS transistor M7, the gate of the PMOS transistor M6 is connected to the drain of the PMOS transistor M6 and one end of the resistor R3, and the other end of the resistor R3 is connected to the drain of the NMOS transistor M8 and the drain of the NMOS transistor M9. The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M9. The source of the NMOS transistor M8 is connected to the source of the NMOS transistor M9 and the external ground GND respectively. The gate of the PMOS transistor M7 is connected to the drain of the PMOS transistor M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS transistor M4, the gate of the NMOS transistor MS4 and the circuit output terminal VREF respectively. The other end of the resistor R4 is connected to the drain of the NMOS transistor M9.

[0024] The temperature compensation circuit 3 includes: a PMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a resistor R5, a resistor R6, a resistor R7 and a resistor R8, wherein the source of the PMOS transistor M10 is connected to the source of the PMOS transistor M13 and the external power supply VDD respectively, the drain of the PMOS transistor M10 is connected to the other end of the resistor R5 and the gate of the NMOS transistor M11 respectively, the other end of the resistor R6 is connected to the gate of the NMOS transistor M11 respectively, and the The drain of the NMOS transistor M11 is connected to the gate of the NMOS transistor M12, the source of the NMOS transistor M11 is connected to the drain of the NMOS transistor M12, the source of the NMOS transistor M12 is respectively connected to the source of the NMOS transistor M15 and the external ground GND, the drain of the PMOS transistor M13 is connected to the source of the PMOS transistor M14, the gate of the PMOS transistor M14 is respectively connected to the drain of the PMOS transistor M14 and the other end of the resistor R7, and the other end of the resistor R8 is respectively connected to the gate of the NMOS transistor M15 and the drain of the NMOS transistor M15.

[0025] In the bandgap reference core circuit 2, the PMOS transistor M6, the PMOS transistor M7, the NMOS transistor M8 and the NMOS transistor M9 all work in the subthreshold region. The drain current I D for

[0026]

[0027] Where W / L is the channel width-to-length ratio of the MOS tube, I0 is a parameter related to the process, η is a non-ideal factor greater than 1, and V TH is the threshold voltage of the MOS tube, VGS is the gate-source voltage of the MOS tube, V T is the thermal voltage with temperature coefficient. Then, the gate-source voltage V GS for

[0028]

[0029] In the formula, the factor And the threshold voltage of MOS tube |V TH |Has negative temperature characteristics, so the gate-source voltage V of the MOS tube working in the subthreshold region GS The voltage V provided by the bandgap reference core circuit 2 at the output end of the circuit is REF1 for

[0030]

[0031] Where V GS8 is the gate-source voltage of NMOS tube M8, R3 is the impedance of resistor R3, I D8-0 is the drain current of the NMOS transistor M8 when the bandgap reference core circuit 2 is working, (W / L)6 is the channel width-to-length ratio of the PMOS transistor M6, (W / L)7 is the channel width-to-length ratio of the PMOS transistor M7, (W / L)8 is the channel width-to-length ratio of the NMOS transistor M8, and (W / L)9 is the channel width-to-length ratio of the NMOS transistor M9. Factor V GS8 +I D8-0 R3 has a negative temperature coefficient, factor has a positive temperature coefficient, so the voltage V provided by the bandgap reference core circuit 2 at the circuit output REF1 It is a bandgap reference voltage with first-order temperature compensation.

[0032] In the temperature compensation circuit 3, the NMOS transistor M12 operates in the linear region, and the PMOS transistor M10, NMOS transistor M11, PMOS transistor M13, PMOS transistor M14 and NMOS transistor M15 all operate in the saturation region. Then, the current I provided by the temperature compensation circuit 3 to the bandgap reference core circuit 2 is NL for

[0033] I NL =I D10 +I D13 -I D11 -I D15 (4)

[0034] Where, I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, ID11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15. At the same time, the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL It has high-order nonlinearity at temperature. Therefore, the output terminal VREF voltage V of the low-voltage and low-power bandgap reference source circuit without a transistor is REF for

[0035]

[0036] In the formula, the factor It has high-order temperature nonlinearity, and can compensate V by optimizing the relevant circuit parameters. REF1 The high-order temperature nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF .

[0037] Figure 3 The output voltage V of the triode-free low-voltage and low-power bandgap reference source circuit of the present invention is REF The temperature characteristic simulation curve of the circuit is shown in Figure 1, where the horizontal axis is temperature and the vertical axis is output voltage. The simulation results show that within the temperature range of -40℃ to 125℃, the output voltage V REF The temperature coefficient is 2.26ppm / ℃.

[0038] In the above-mentioned embodiment of the present application, a transistor-free low-voltage, low-power bandgap reference source circuit includes a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The embodiment of the present application uses the difference between the gate-source voltages of two MOS transistors operating in the subthreshold region to generate a positive temperature characteristic, and the gate-source voltage of the MOS transistor operating in the subthreshold region has a negative temperature characteristic to achieve a first-order bandgap reference voltage. The absolute value of the threshold voltage of the MOS transistor operating in the saturation region has a negative temperature characteristic to generate a high-order temperature nonlinear current and compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap reference voltage, thereby achieving a transistor-free low-voltage, low-power bandgap reference source circuit.

[0039] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0040] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A triode-free low-voltage, low-power bandgap reference source circuit, characterized in that: include: A start-up and bias circuit (1), a bandgap reference core circuit (2) and a temperature compensation circuit (3), wherein the signal output end of the start-up and bias circuit (1) is respectively connected to the signal input end of the bandgap reference core circuit (2) and the signal input end of the temperature compensation circuit (3), the signal output end of the bandgap reference core circuit (2) is connected to the signal input end of the start-up and bias circuit (1), and the signal output end of the temperature compensation circuit (3) is connected to the signal input end of the bandgap reference core circuit (2); the start-up and bias circuit (1) provides bias and start-up signals for the bandgap reference core circuit (2) and the temperature compensation circuit (3), and the temperature compensation circuit (3) provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit (2); the temperature compensation circuit (3) includes: a PMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, and a PMOS tube M15. MOS transistor M14, NMOS transistor M15, resistor R5, resistor R6, resistor R7 and resistor R8, wherein the source of the PMOS transistor M10 is respectively connected to the source of the PMOS transistor M13 and the external power supply VDD, the drain of the PMOS transistor M10 is respectively connected to the other end of the resistor R5 and the gate of the NMOS transistor M11, the other end of the resistor R6 is respectively connected to the drain of the NMOS transistor M11 and the gate of the NMOS transistor M12, the source of the NMOS transistor M11 is connected to the drain of the NMOS transistor M12, the source of the NMOS transistor M12 is respectively connected to the source of the NMOS transistor M15 and the external ground GND, the drain of the PMOS transistor M13 is connected to the source of the PMOS transistor M14, the gate of the PMOS transistor M14 is respectively connected to the drain of the PMOS transistor M14 and the other end of the resistor R7, and the other end of the resistor R8 is respectively connected to the gate of the NMOS transistor M15 and the drain of the NMOS transistor M15.

2. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, characterized in that: The startup and bias circuit (1) comprises: a PMOS tube MS1, a PMOS tube MS2, a PMOS tube MS3, an NMOS tube MS4, an NMOS tube MS5, an NMOS tube MS6, a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R1 and a resistor R2, wherein the source of the PMOS tube MS1 is respectively connected to the source of the PMOS tube M1 and an external power supply VDD, the gate of the PMOS tube MS1 is respectively connected to the drain of the PMOS tube MS1 and the source of the PMOS tube MS2, the gate of the PMOS tube MS2 is respectively connected to the drain of the PMOS tube MS2 and the source of the PMOS tube MS3, the gate of the PMOS tube MS3 is respectively connected to the drain of the PMOS tube MS3, the drain of the NMOS tube MS4, the gate of the NMOS tube MS5 and the NMOS The gate of the S transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4, and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

3. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, characterized in that: The bandgap reference core circuit (2) comprises: a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, a resistor R3 and a resistor R4, wherein the source of the PMOS tube M5 is connected to an external power supply VDD, the drain of the PMOS tube M5 is respectively connected to the source of the PMOS tube M6 and the source of the PMOS tube M7, the gate of the PMOS tube M6 is respectively connected to the drain of the PMOS tube M6 and one end of the resistor R3, and the other end of the resistor R3 is respectively connected to the drain of the NMOS tube M8. The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M9. The source of the NMOS transistor M8 is connected to the source of the NMOS transistor M9 and the external ground GND respectively. The gate of the PMOS transistor M7 is connected to the drain of the PMOS transistor M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS transistor M4, the gate of the NMOS transistor MS4 and the circuit output terminal VREF respectively. The other end of the resistor R4 is connected to the drain of the NMOS transistor M9.

4. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 3, characterized in that: In the bandgap reference core circuit (2), the PMOS tube M6, the PMOS tube M7, the NMOS tube M8 and the NMOS tube M9 all operate in the subthreshold region, and the drain current I D and the gate-source voltage V GS They are and Where W / L is the channel width-to-length ratio of the MOS tube, I0 is a parameter related to the process, η is a non-ideal factor greater than 1, and V TH is the threshold voltage of the MOS tube, V GS is the gate-source voltage of the MOS tube, V T is the thermovoltage with temperature coefficient, and the factor And the threshold voltage of MOS tube |V TH |Has negative temperature characteristics, so the gate-source voltage V of the MOS tube working in the subthreshold region GS The drain current of the MOS tube working in the subthreshold region has a negative temperature characteristic. The voltage V provided by the bandgap reference core circuit at the circuit output terminal VREF REF1 for Among them, V GS8 is the gate-source voltage of the NMOS tube M8 in the working subthreshold region, R3 is the impedance of the resistor R3, and I D8-0 is the drain current of the NMOS transistor M8 when the bandgap reference core circuit is working, (W / L)6 is the channel width-to-length ratio of the PMOS transistor M6, (W / L)7 is the channel width-to-length ratio of the PMOS transistor M7, (W / L)8 is the channel width-to-length ratio of the NMOS transistor M8, (W / L)9 is the channel width-to-length ratio of the NMOS transistor M9, and the factor V GS8 +I D8-0 R3 has a negative temperature coefficient, factor It has a positive temperature coefficient, so by optimizing the corresponding parameters, the voltage V REF1 It is a bandgap reference voltage with first-order temperature compensation.

5. A triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, wherein in the temperature compensation circuit (3), the NMOS transistor M12 operates in the linear region, and the PMOS transistor M10, the NMOS transistor M11, the PMOS transistor M13, the PMOS transistor M14 and the NMOS transistor M15 all operate in the saturation region, and the current I provided by the temperature compensation circuit (3) to the bandgap reference core circuit (2) is NL For I NL =I D10 +I D13 -I D11 -I D15 , where I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, I D11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15, and the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL It has high-order temperature nonlinearity.

6. A triode-free low-voltage and low-power bandgap reference source circuit according to any one of claims 4-5, wherein the output terminal VREF voltage V REF for Where V REF1 is the first-order bandgap reference voltage provided by the bandgap reference core circuit (2), (W / L)8 is the channel width-to-length ratio of the NMOS tube M8, (W / L)9 is the channel width-to-length ratio of the NMOS tube M9, I NL is the temperature high-order nonlinear current provided by the temperature compensation circuit (3), R3 is the impedance of the resistor R3, and the factor It has high-order nonlinearity over temperature, and can compensate for V by optimizing the relevant circuit parameters. REF1 The high-order temperature nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF .

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