Storage device and method of operating the same

Abstract

A memory device including a non-volatile memory device and a memory controller configured to control the non-volatile memory device, the method including: dividing the non-volatile memory device into a plurality of domains; determining a scrambling function based on seed values of seed bits corresponding to a first portion of a plurality of address bits of a logical address among the plurality of logical addresses provided from the host device; generating a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to a second portion of a plurality of address bits of a logical address among the plurality of logical addresses; and assigning a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among a plurality of domains.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0134752 filed on October 11, 2023 in the Korean Intellectual Property Office (KIPO), and the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Example embodiments relate generally to semiconductor integrated circuits, and more particularly to memory devices and methods of operating the same. Background Art

[0004] In recent years, storage devices using non-volatile memory devices, such as solid-state drives (SSDs), have become very popular. The advantage of such storage devices is that there is no mechanical drive, so the storage device can be more reliable and durable, and information can be accessed very quickly (e.g., faster than a storage device using a mechanical drive), and consumes less power. Recently, since electronic circuits are applied not only to electronic systems such as laptops, but also to various systems such as automobiles, airplanes, drones, etc., storage devices using non-volatile memory devices are used in various systems. If access is concentrated in a specific area of ​​the storage device, the durability and performance of the storage device may be reduced. Summary of the invention

[0005] Some example embodiments may provide a storage device and a method of operating the storage device capable of efficiently distributing access to the storage device.

[0006] According to an example embodiment, a method of operating a storage device including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device, the method including: dividing the nonvolatile memory device into a plurality of domains; determining a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device; generating a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to a second portion of a plurality of address bits of the logical address among the plurality of logical addresses; and allocating a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among the plurality of domains.

[0007] According to an example embodiment, a storage device includes: a nonvolatile memory device including a plurality of domains; and a storage controller configured to control the nonvolatile memory device, the storage controller including: a scrambling circuit configured to determine a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device, and configured to generate a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; and a processor configured to assign a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among the plurality of domains.

[0008] According to an example embodiment, a method of operating a storage device, the storage device including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device, the method including: dividing the nonvolatile memory device into a plurality of domains; determining a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device; generating a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to a second portion of a plurality of address bits of the logical address among the plurality of logical addresses; allocating a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among the plurality of domains; and in response to receiving a request from the host device to perform the same operation on an address range including a plurality of sequential logical addresses among the plurality of logical addresses, classifying the address range into a main range and an edge range, wherein generating the scrambled domain value includes: omitting generating the scrambled domain value for the main range.

[0009] According to the storage device and the method of operating the storage device according to the example embodiment, the durability and performance of the storage device can be improved by preventing input and output from being squeezed into a specific domain through two-level address scrambling, and the two-level address scrambling determines a scrambling function based on a seed value of a logical address, and scrambles the domain value of the logical address based on the scrambling function.

[0010] Furthermore, according to the storage device and the method of operating the storage device according to example embodiments, in the case of a range operation in which the same operation is performed on an address range, the range operation can be efficiently supported by selectively performing address scrambling and classifying the address range into a main range and an edge range. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram illustrating a storage system according to example embodiments.

[0013] Figure 2 is a flowchart illustrating a method of operating a storage device according to example embodiments.

[0014] Figure 3 is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to example embodiments.

[0015] Figure 4 and Figure 5 is a diagram illustrating an example embodiment of address scrambling in a method of operating a memory device according to example embodiments.

[0016] Figure 6 is a diagram illustrating a scrambling function in a method of operating a storage device according to example embodiments.

[0017] Figure 7 , Figure 8 , Fig. 9 and Figure 1 0 is a diagram illustrating an embodiment of dividing and setting domains in a method of operating a storage device according to example embodiments.

[0018] Fig.11 is a block diagram illustrating a storage device according to example embodiments.

[0019] Figure 1 2 is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to an example embodiment.

[0020] Fig.13 It shows that according to Fig.12 FIG. 1 is a diagram of an example embodiment of a scrambling function for setting address bits.

[0021] Fig.14 It shows the use of Fig.12 The address bits are set and Fig.13 FIG. 1 is a diagram of an example embodiment of address scrambling of a scrambling function.

[0022] Fig.15 It shows that according to Fig.14 A diagram of an example embodiment of domain allocation for address scrambling.

[0023] Fig.16 It shows the use of Fig.12 The address bits are set and Fig.13 FIG. 1 is a diagram of an example embodiment of address scrambling of a scrambling function.

[0024] Fig.17 is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to example embodiments.

[0025] Fig.18It shows that according to Fig.17 FIG. 1 is a diagram of an example embodiment of a scrambling function for setting address bits.

[0026] Fig.19 is a flowchart illustrating a method of operating a storage device according to example embodiments.

[0027] Fig. 20 is a diagram illustrating an example embodiment of a range operation controller included in a storage device according to an example embodiment.

[0028] Fig.21 Is used to describe Fig. 20 A diagram of the scope of the operation controller.

[0029] Fig. 22 is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to example embodiments.

[0030] Fig.23 It shows the use of Fig. 22 The address bits are set and Fig.13 FIG. 1 is a diagram of an example embodiment of address scrambling of a scrambling function.

[0031] Fig.24 is a diagram illustrating an example embodiment of adjusting the number of granularity bits in a method of operating a storage device according to example embodiments.

[0032] Fig.25 is a flowchart illustrating a method of operating a storage device according to example embodiments.

[0033] Fig.26 is a diagram illustrating an example embodiment of address scrambling in a method of operating a memory device according to example embodiments.

[0034] Fig. 27 is a flowchart illustrating an example embodiment of address bit setting in a method of operating a memory device according to example embodiments.

[0035] Fig.28 and Fig.29 is a diagram illustrating an example embodiment of setting a buffer memory in a method of operating a memory device according to example embodiments.

[0036] Fig.30 is a block diagram illustrating an example embodiment of a memory controller included in a memory device according to an example embodiment.

[0037] Fig.31 is a block diagram illustrating a nonvolatile memory device included in a memory device according to example embodiments.

[0038] Fig.32is a block diagram illustrating a storage device according to example embodiments.

[0039] Fig.33 is a circuit diagram illustrating an equivalent circuit of a memory block of a nonvolatile memory device included in a memory device according to example embodiments.

[0040] Fig.34 is a block diagram illustrating an example embodiment of an interconnect architecture of a storage system according to an example embodiment.

[0041] Fig.35 is a block diagram illustrating a computing system according to an example embodiment. DETAILED DESCRIPTION

[0042] Various example embodiments will be described more fully below with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, similar reference numerals may always refer to similar elements unless otherwise explicitly stated. Repeated descriptions may be omitted.

[0043] Figure 1 is a block diagram illustrating a storage system according to an example embodiment, and Figure 2 is a flowchart illustrating a method of operating a storage device according to example embodiments.

[0044] Reference Figure 1 , the storage system 100 may include a host device 200, a storage device 300, and a link 50 that connects (e.g., electrically connects) the host device 200 to the storage device 300. The storage device 300 may include a storage controller 310 and a non-volatile memory device 320. For example, the storage device 300 may be a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash memory (UFS) device, etc., but is not limited thereto. In one embodiment, the link 50 may be a peripheral component interconnect express (PCIe) link, but is not limited thereto. It is understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly located on the other element or layer, directly connected to or coupled to the other element or layer, or one or more intermediate elements or layers may exist. In contrast, when an element is referred to as being "directly coupled to", "directly connected to", or "directly responsive to" another element, or "directly" "on" another element, there is no intermediate element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection.

[0045] The host device 200 may be a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor, but is not limited thereto. The storage device 300 may be embedded in an electronic device having the host device 200, or the storage device 300 may be detachably electrically connected to (e.g., physically detachably and electrically connected to) an electronic device including the host device 200.

[0046] The host device 200 may control the overall operation of the memory system 100. The host device 200 may include a host processor HPRC and a host memory HMEM.

[0047] The host processor HPRC can execute software (e.g., applications, operating systems (OS) and / or device drivers). The host processor HPRC can run, for example, an operating system (OS) loaded into the host memory HMEM. The file system can be implemented as software executed by the host processor HPRC as part of the operating system (OS). The host processor HPRC can also execute various application programs running on the operating system (OS). The host processor HPRC can be provided as a homogeneous multi-core processor or a heterogeneous multi-core processor. A multi-core processor is a computing component having at least two processor cores (hereinafter referred to as cores) that can run independently. Each core can read and execute program instructions independently. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0048] The host memory HMEM may store instructions and data executed and processed by the host processor HPRC. For example, an operating system (OS) and / or an application program may be loaded into the host memory HMEM during a boot sequence. For example, when the storage system 100 is booted, an operating system (OS) stored on the storage device 300 may be loaded into the host memory HMEM, and the application may then be loaded into the host memory HMEM by the operating system (OS).

[0049] The host device 200 may send a data operation request (i.e., a request REQ and a logical address LA) to the memory controller 310, and may send and receive data DTA to and from the memory controller 310. The memory controller 310 may send a response RSND in response to the request REQ to the host device 200. The request REQ may include a data read request, a data write request, and / or a data erase request.

[0050] The storage controller 310 may control the nonvolatile memory device 320 in response to a request REQ from the host device 200. The storage controller 310 may perform a read operation and / or a write operation on the nonvolatile memory device 320 by providing a physical address PA mapped to (i.e., mapped by) a logical address LA, a command CMD, and a control signal CTRL to the nonvolatile memory device 320. The write operation may be referred to as a programming operation. The storage controller 310 may perform a flash translation layer (FTL) operation to convert the logical address LA sent from the host device 200 into a physical address PA.

[0051] For example, the memory controller 310 may control the nonvolatile memory device 320 to read out data stored in the nonvolatile memory device 320 in response to a data read request (e.g., a data read request of request REQ) received from the host device 200, or write data in the nonvolatile memory device 320 in response to a data write request (e.g., a data write request of request REQ) received from the host device 200. In addition, the nonvolatile memory device 320 may be controlled to erase data stored in the nonvolatile memory device 320 in response to an erase request (e.g., an erase request of request REQ) received from the host device 200. The nonvolatile memory device 320 may transmit a response RSND corresponding to the command CMD to the memory controller 310.

[0052] The nonvolatile memory device 320 may be implemented as one or more nonvolatile memories, such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and resistive RAM (ReRAM), but the type of the nonvolatile memory device 320 is not limited thereto. The nonvolatile memory device 320 may be connected to (e.g., electrically connected to) the storage controller 310 via a plurality of channels. For the convenience of description, the nonvolatile memory device 320 may be described as a NAND flash memory device below. Figure 30 to Figure 33 An embodiment of the configuration and operation of a storage device 300 including a NAND flash memory device will be described.

[0053] According to example embodiments, the memory controller 310 may include a memory processor SPRC for controlling overall operations of the memory controller 310 and a scrambling circuit SCR for supporting a method of operating the memory device 300 .

[0054] Reference Figure 1 and Figure 2, the storage controller 310 may divide the nonvolatile memory device 320 into a plurality of domains (S100). The storage controller 310 may divide the storage area of ​​the nonvolatile memory device 320 into a plurality of domains in any appropriate manner according to the configuration, storage capacity, operation speed, etc. of the nonvolatile memory device 320. Figures 7 to 19 An embodiment of dividing domains and setting domains will be described.

[0055] The scrambling circuit SCR may determine a scrambling function based on a seed value of a seed bit corresponding to a portion of a plurality of address bits of a logical address LA provided from the host device 200 (S200). The scrambling function may be in the form of a mathematical function (e.g., an equation), but is not limited thereto. The scrambling circuit SCR may generate a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to another portion of the plurality of address bits (S300). Various embodiments of address scrambling performed by the scrambling circuit SCR will be described below.

[0056] Based on the scrambled domain value, the storage processor SPRC can allocate the write operation corresponding to the logical address LA to the domain corresponding to the scrambled domain value among the multiple domains (S400). Fig.11 and Fig.15 An embodiment of domain allocation is described below.

[0057] When the storage device 300 has a parallel input / output (I / O) processing structure, the address (e.g., logical address LA) of the host device (e.g., host device 200) can be divided into address areas managed by each parallel processor. The traditional static address distribution method can allocate the address of the host device to each domain in the storage device (e.g., storage device 300) in a fixed order, such as a round-robin method, which is widely used due to its simple structure and operation. Since the (allocated or distributed) logical addresses within the domain are linear and / or static, it has the advantage that sequential operations can be performed when address ranges need to be processed, thereby obtaining performance improvements. For example, a specific range of addresses within a domain can be calculated sequentially to improve performance.

[0058] In a multi-domain environment, static address distribution can easily lead to I / O being squeezed into a particular domain, which can be referred to as I / O skew. Fig.16 As described above, if logical addresses (e.g., logical addresses LA) corresponding to multiples of 4 (e.g., 0, 4, 8, etc.) are sequentially received from a host device (e.g., host device 200), I / O and workload may be squeezed into a specific domain. I / O skew may cause reduced endurance and performance degradation of a storage device (e.g., storage device 300), and an additional function (global wear leveling) may be required to address such issues.

[0059] According to the storage device 300 of the example embodiment and the method of operating the storage device 300, the durability and performance of the storage device 300 can be improved by preventing input and output (I / O) from being squeezed into a specific domain through two-level address scrambling, and the two-level address scrambling determines a scrambling function based on a seed value of a logical address LA, and then scrambles the domain value of the logical address LA based on the scrambling function.

[0060] Figure 3 is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to example embodiments.

[0061] Reference Figure 3 , the logical address LA provided by the host device (e.g., the host device 200) may include a plurality of address bits from the least significant bit LSB to the most significant bit MSB. The storage controller (e.g., the storage controller 310) may set a portion of the plurality of address bits to the seed bit SDB, and another portion of the plurality of address bits to the domain bit DMB. According to an example embodiment, the storage controller 310 may set another portion of the plurality of address bits to the granularity bit GRB.

[0062] In one embodiment, as in the first case CS1, the storage controller may set adjacent address bits including the least significant bit LSB as domain bits DMB, and set bits higher than the domain bit DMB (higher significant bits or bits closer to the most significant bit MSB) as seed bits SDB.

[0063] In one embodiment, as in the second case CS2, the storage controller may set the adjacent address bits including the least significant bit LSB as domain bits DMB, and set a portion of bits higher than the domain bits DMB as seed bits SDB. In this case, the seed bits SDB and the domain bits DMB may be set adjacent to each other.

[0064] In one embodiment, as in the third case CS3, the storage controller may set adjacent address bits including the least significant bit LSB as granularity bits GRB, set a portion of bits above the granularity bit GRB as domain bits DMB, and set all bits above the domain bit DMB as seed bits SDB.

[0065] In one embodiment, as in the fourth case CS4, the storage controller may set adjacent address bits including the most significant bit MSB to domain bits DMB, and set all bits below the domain bit DMB (lower significant bits or bits closer to the least significant bit LSB) to seed bits SDB.

[0066] The determined address bit settings may be stored in a non-volatile storage device (eg, non-volatile storage device 320 ) as part of metadata used to control the operation of the storage device (eg, storage device 300 ). Figure 3 Four example embodiments of address bit settings are shown in FIG. 1 , but the embodiments are not limited thereto.

[0067] Figure 4 and Figure 5 is a diagram illustrating an example embodiment of address scrambling in a method of operating a memory device according to example embodiments.

[0068] Reference Figure 1 and Figure 4 , the scrambling circuit SCR may determine the scrambling function "fi" based on the seed value VS of the seed bit SDB corresponding to a portion of the plurality of address bits of the logical address LA provided from the host device 200. The scrambling function fi may be determined in a variety of ways. In one embodiment, the seed value VS may be input into a specified function "g" to generate an index value "i" representing the scrambling function fi. For example, the index value i may represent one of a plurality of preset functions (preset scrambling function fi).

[0069] According to an example embodiment, the method of determining the scrambling function fi may be statically fixed or may be changed (dynamically). In other words, the function g that determines the scrambling function fi may be a fixed function or a variable function. By (dynamically) changing the scrambling function fi, it is possible to prevent access (e.g., I / O) from being concentrated in a specific domain during repetition of the same access pattern from a host device (e.g., host device 200).

[0070] The scrambling circuit SCR can generate a scrambled domain value SVD based on the scrambling function fi and the domain value VD of the domain bit DMB corresponding to another part of the plurality of address bits of the logical address LA. In other words, the scrambled domain value SVD can be generated by inputting the domain value VD into the determined scrambling function fi.

[0071] like Figure 4 As shown, the seed value VS of the seed bits SDB of the scrambled logical address SLA may be the same as the seed value VS of the seed bits SDB of the logical address LA provided from the host device 200. At the same time, the domain value VD of the domain bits DMB of the logical address LA may be replaced by the scrambled domain value SVD of the domain bits DMB of the scrambled logical address SLA.

[0072] Figure 5 Address descrambling in a method of operating a storage device according to example embodiments is illustrated.

[0073] Reference Figure 1 and Figure 5The scrambling circuit SCR can determine the scrambling function fi based on the seed value VS of the seed bit SDB of the scrambled logical address SLA. The scrambling function fi can be used in the same manner as Figure 4 In one embodiment, the seed value VS may be input into a specific function "g" to generate an index value "i" representing the scrambling function fi.

[0074] The scrambling circuit SCR can be based on the scrambled domain value SVD of the domain bit DMB of the scrambled logical address SLA and the inverse function fi of the scrambling function fi. -1 , recover the domain value VD of the domain bit of the logical address LA. In other words, the scrambled domain value SVD can be input into the inverse function fi of the scrambling function fi -1 To restore the domain value VD.

[0075] Therefore, by performing such address descrambling on the scrambled logical address SLA, the logical address LA before address scrambling can be restored.

[0076] Figure 6 is a diagram illustrating a scrambling function in a method of operating a storage device according to example embodiments.

[0077] Figure 6 An example scrambling function fi is shown in FIG. Figure 4 As described above, the scrambling function fi may vary according to the seed value VS.

[0078] Reference Figure 6 , all possible values ​​(a, b, c) of the domain value VD and all possible values ​​(a, b, c) of the scrambled domain value SVD can be equal and correspond one to one, so there can be an inverse function fi of the scrambling function fi -1 For example, Figure 6 As shown, the functional relationship fi(a)=c, fi(b)=a, fi(c)=b, fi -1 (a) = b, fi -1 (b) = c, fi -1 (c) = a. In this way, the scrambling function (fi) can be set so that the inverse function (fi -1 ) exists to ensure consistency between address scrambling and address descrambling.

[0079] Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a diagram illustrating an embodiment of dividing and setting domains in a method of operating a storage device according to example embodiments.

[0080] Reference Figures 7 to 10, the nonvolatile memory device (e.g., the nonvolatile memory device 320) may include a plurality of nonvolatile memories NVM11 to NVMjk (j, k are each a natural number greater than or equal to 2), each of which is connected (e.g., electrically connected) to a plurality of channels CH1 to CHi (i is a natural number greater than or equal to 2). For example, the natural number i may be equal to the natural number j. The number of the plurality of channels and the number of the plurality of nonvolatile memories may vary and are not limited to Figures 7 to 10 Embodiment shown. It should be understood that although the terms "i", "n", "j", "k", etc. can be used herein to indicate various natural numbers, it should not be limited by these terms. These terms are used to distinguish one natural number from another natural number. Therefore, the natural number "i" can be different natural numbers depending on the element indicated by the natural number "i".

[0081] Each non-volatile memory (e.g., NVM1 1 to NVMjk) may be a NAND flash memory. However, the scope of the present disclosure is not limited thereto, and each of the plurality of non-volatile memories may include at least one of a plurality of non-volatile memories, such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

[0082] In one embodiment, Figure 7 As shown, the nonvolatile memory device (e.g., the nonvolatile memory device 320) can be connected (e.g., electrically connected) to the memory controller (e.g., the memory controller 310) via channels CH1 to CH4. At this time, the nonvolatile memories NVM11, NVM12, NVM13, NVM14 connected (e.g., electrically connected) to the first channel CH1 can be set as the first domain DM1, the nonvolatile memories NVM21, NVM22, NVM23, NVM24 connected (e.g., electrically connected) to the second channel CH2 can be set as the second domain DM2, the nonvolatile memories NVM31, NVM32, NVM33, NVM34 connected (e.g., electrically connected) to the third channel CH3 can be set as the third domain DM3, and the nonvolatile memories NVM41, NVM42, NVM43, NVM44 connected (e.g., electrically connected) to the fourth channel CH4 can be set as the fourth domain DM4.

[0083] In one embodiment, Figure 8As shown, the nonvolatile memory device (e.g., the nonvolatile memory device 320) can be connected (e.g., electrically connected) to the memory controller (e.g., the memory controller 310) via channels CH1 to CH8. In this case, the nonvolatile memories NVM11, NVM12, NVM13, and NVM14 connected (e.g., electrically connected) to the first channel CH1 can be set as the first domain DM1, the nonvolatile memories NVM21, NVM22, NVM23, and NVM24 connected (e.g., electrically connected) to the second channel CH2 can be set as the second domain DM2, the nonvolatile memories NVM31, NVM32, NVM33, and NVM34 connected (e.g., electrically connected) to the third channel CH3 can be set as the third domain DM3, the nonvolatile memories NVM41, NVM42, NVM43, and NVM44 connected (e.g., electrically connected) to the fourth channel CH4 can be set as the fourth domain DM4, and the nonvolatile memories NVM51, NVM52, NVM53, and NVM54 connected (e.g., electrically connected) to the fifth channel CH5 can be set as the fourth domain DM5. The volatile memories NVM51, NVM52, NVM53, and NVM54 are set to the fifth domain DM5, the non-volatile memories NVM61, NVM62, NVM63, and NVM64 connected (for example, electrically connected) to the sixth channel CH6 can be set to the sixth domain DM6, the non-volatile memories NVM71, NVM72, NVM73, and NVM74 connected (for example, electrically connected) to the seventh channel CH7 can be set to the seventh domain DM7, and the non-volatile memories NVM81, NVM82, NVM83, and NVM84 connected (for example, electrically connected) to the eighth channel CH8 can be set to the eighth domain DM8.

[0084] In this way, the storage controller can set the number of domains based on the number of multiple channels connecting (e.g., electrically connecting) the non-volatile memory device to the storage controller. According to the number of domains, the number of bits of the above-mentioned domain bit DMB can be set, and the domain value VD of the domain bit DMB can represent the corresponding domain.

[0085] When the number of domains is 4, such as Figure 7 As shown in the example embodiment of the present invention, the number of bits of the domain bit DMB can be set to 2. For example, a domain value VD of 00(b)=0(d) (where "b" represents a binary number and "d" represents a decimal number) can indicate a first domain DM1, a domain value VD of 01(b)=1(d) can indicate a second domain DM2, a domain value VD of 10(b)=2(d) can indicate a third domain DM3, and a domain value VD of 11(b)=3(d) can indicate a fourth domain DM4.

[0086] When the number of domains is 8, such as Figure 8In an example embodiment of the present invention, the number of bits of the domain bit DMB may be set to 3. For example, a domain value VD of 000(b)=0(d) may indicate a first domain DM1, a domain value VD of 001(b)=1(d) may indicate a second domain DM2, a domain value VD of 010(b)=2(d) may indicate a third domain DM3, a domain value VD of 011(b)=3(d) may indicate a fourth domain DM4, a domain value VD of 100(b)=4(d) may indicate a fifth domain DM5, a domain value VD of 101(b)=5(d) may indicate a sixth domain DM6, a domain value VD of 110(b)=6(d) may indicate a seventh domain DM7, and a domain value VD of 111(b)=7(d) may indicate an eighth domain DM8.

[0087] Although Figure 7 and Figure 8 An example in which one domain is set for each channel is shown, but the example embodiments are not limited thereto. Fig. 9 and Fig.10 As shown, a domain may be established for every two channels. According to an exemplary embodiment, a domain may be established for every three or more channels, or two or more domains may be established for each channel.

[0088] Fig.11 is a block diagram showing a storage device according to an example embodiment. Figure 1 Duplicate description.

[0089] Reference Fig.11 , the storage device 300 may include a storage controller 310, a non-volatile memory device 320, and a buffer memory 330. The storage controller 310 may be configured to process a request from a host device (eg, Figure 1 For example, the storage controller 310 may store data in the nonvolatile memory device 320 and / or read stored data from the nonvolatile memory device 320 in response to a request (eg, a request REQ) from the host device.

[0090] The storage controller 310 can be used through multiple channels (for example, refer to Figure 7 , Figure 8 , Fig. 9 and Fig.10 The channel CH) of the nonvolatile memory device 320 communicates (is connected or electrically connected) with the nonvolatile memory device 320. As described above, the nonvolatile memory device 320 may be divided into a plurality of domains DM1 to DMn.

[0091] The buffer memory 330 may store data and / or output the stored data under the control of the memory controller 310. For example, the buffer memory 330 may be a dynamic random access memory (DRAM), but example embodiments are not limited thereto. The buffer memory 330 may temporarily store data before the data is stored in the nonvolatile memory device 320. For example, from a host device (e.g., referring to Figure 1 The data acquired by the host device 200 may be first stored in the buffer memory 330. Subsequently, the data stored in the buffer memory 330 may be allocated to a physical address of the nonvolatile memory device 320 (eg, referring to Figure 1 physical address PA) and is stored in the space pointed to by the physical address.

[0092] The buffer memory 330 may include or be divided into first to nth buffers BRG1 to BRGn. Each buffer BRGi (where i is a natural number greater than 1 and less than or equal to n) may be managed by an i-th flash translation layer FTLi, respectively.

[0093] The storage controller 310 may include a scrambling circuit SCR and a plurality of flash translation layers FTL (FTL1 to FTLn). Each of the plurality of flash translation layers FTL1 to FTLn may control a plurality of domains DM1 to DMn of the nonvolatile memory device 320 via a corresponding channel (e.g., channel CH). For example, the first flash translation layer FTL1 may control the corresponding first domain DM1. In an example embodiment, the first flash translation layer FTL1 may perform various maintenance operations on the first domain DM1, such as mapping table management, bad block management, wear leveling, etc. The second flash translation layer FTL2 may control the corresponding second domain DM2 (e.g., may perform various maintenance operations), and in the same manner, the nth flash translation layer FTLn may control the corresponding nth domain DMn.

[0094] The scrambling circuit SCR can transfer the data from the host device (for example, Figure 1A write request including a logical address LA of a host device 200 of the host device is distributed to a plurality of flash translation layers FTL1 to FTL4. For example, the logical address LA may refer to a logical block address LBA or a logical page address LPA managed by the host device, and the host device may identify and / or manage a storage area in the storage device 300 based on the logical block address LBA. In an example embodiment, a file system (e.g., a part of an operating system (OS)) of the host device may use the logical block address LBA to write data to and read data from a storage area of ​​the storage device 300 in the form of a data block. In an example embodiment, the scrambling circuit SCR may distribute a write request (i.e., a write operation corresponding to the write request) to a plurality of flash translation layers FTL1 to FTLn based on the logical address LA.

[0095] In example embodiments, the performance of the storage device 300 may not remain constant under various operating conditions or operating environments. The performance of the storage device 300 may refer to the performance of the storage device 300 in relation to the host device (e.g., Figure 1 The amount of data transmitted per unit time between the non-volatile memory device 320 and the host device 200, the data transmission rate (speed), etc. For example, depending on the physical characteristics of the non-volatile memory device 320 or various environmental variables (e.g., the size of the buffer memory 330, the amount of available memory in the non-volatile memory device 320, etc.), the time to complete the operation of the same write request may be different. Specifically, when a specific pattern of data is received, the data may be skewed toward a specific channel among multiple channels (e.g., among the channels CH). This may cause performance fluctuations in the storage device 300, that is, despite the need to maximize input / output (I / O) parallelism, the storage device 300 may experience performance degradation due to uneven distribution of write requests to multiple resources.

[0096] In order to provide uniform performance or maximum performance of the storage device 300, the scrambling circuit SCR may perform address scrambling on the logical address LA. As described above, the address scrambling may be performed on the slave host device (e.g., reference Figure 1 The host device 200 of the present invention scrambles the logical address LA received by the host device 200 to generate a scrambled logical address SLA, and distributes the corresponding request to each of the multiple flash translation layers FTL1 to FTLn based on the scrambled logical address SLA. In an example embodiment, the address scrambling can change the order in which the request is distributed to the multiple flash translation layers FTL1 to FTLn based on the logical address LA segment. In this case, the request can be relatively evenly distributed to the multiple flash translation layers FTL1 to FTLn, and the sequentiality of the data can be maintained. Therefore, the performance of the storage device 300 can be improved.

[0097] Fig.12is a diagram illustrating an example embodiment of address bit settings in a method of operating a memory device according to example embodiments.

[0098] Reference Fig.12 , by a host device (e.g., referring to Figure 1 The logical address LA provided by the host device 200 may include a plurality of address bits B0 to Bk. Among them, "k" may be a natural number greater than 1. In one embodiment, the nonvolatile memory device (e.g., the nonvolatile memory device 320) may be divided into four domains (e.g., four domains DM). At this time, the two lower bits B0 and B1 may be set as domain bits DMB, and all bits B2 to Bk higher than the domain bit DMB may be set as seed bits SDB, such as Fig.12 shown.

[0099] Fig.13 It shows that according to Fig.12 FIG. 1 is a diagram of an example embodiment of a scrambling function for setting address bits.

[0100] Reference Fig.13 Each of the plurality of scrambling functions f0 to f4 may be a reference Figure 6 The functions that describe the inverse function correspond one-to-one. Fig.13 Five scrambling functions f0 to f4 are shown as examples, but the number of scrambling functions may vary. Generally speaking, when the number of bits of the domain bit DMB is "s", there may be at most (2 s )! scrambling functions. Where "s" can be a natural number less than or equal to "k". For example, if the number of bits in the domain bit DMB is 2, there can be at most (2 2 )! =4! =4x3x2x1=24 scrambling functions.

[0101] As reference Figure 4 As described above, the scrambling circuit SCR may determine the scrambling function fi based on the seed value VS of the seed bits SDB corresponding to a portion of the plurality of address bits of the logical address LA provided from the host device 200 .

[0102] Fig.14 It shows the use of Fig.12 The address bits are set and Fig.13 A diagram of an example embodiment of address scrambling of a scrambling function, and Fig.15 It shows that according to Fig.14 A diagram of an example embodiment of domain allocation for address scrambling.

[0103] Reference Fig.14 , for sequential logical addresses LA, for example, LA=0 to LA=15, for a request for a write operation (for example, referring to Figure 1A request REQ) may be received from a host device (eg, referring to Figure 1 host device 200) is sent sequentially to a storage device (e.g., storage device 300). Figure 1 The scrambling circuit SCR can determine one of the scrambling functions f0 to f4 based on the seed value VS of each logical address LA as described above, and generate a scrambled domain value SVD corresponding to each domain value VD based on or using the determined scrambling function. Fig.14 The correspondence between the logical addresses LA=0 to LA=15 according to this address scrambling and the scrambled logical addresses SLA=0 to SLA=15 is shown.

[0104] exist Fig.14 In the example, the unit range UR represents 2 with the same seed value (e.g., the same seed value VS). N A set of logical addresses (e.g., logical addresses LA), where N is the number of bits of the seed bit SDB. When N=2, each unit range UR includes 4 logical addresses, such as Fig.14 The address scrambling according to the example embodiment may be referred to as short-distance scrambling because it is performed by a scrambling function (eg, scrambling function fi) determined for each unit range UR.

[0105] Figure 1 The storage processor SPRC may respectively allocate write operations corresponding to the logical addresses LA=0 to LA=15 to the domains DM1 to DM4 based on the scrambled domain value SVD.

[0106] As a result, write operations can be assigned to the corresponding domains, such as Fig.15 As shown. The write operation for the logical address LA=2, 7, 9 and 12 corresponding to SVD=0 may be allocated to the first flash translation layer FTL1 to store the (corresponding) write data to the first domain DM1. The write operation for the logical address LA=0, 5, 10 and 14 corresponding to SVD=1 may be allocated to the second flash translation layer FTL2 to store the (corresponding) write data to the second domain DM2. The write operation for the logical address LA=1, 4, 11 and 13 corresponding to SVD=2 may be allocated to the third flash translation layer FTL3 to store the (corresponding) write data to the third domain DM3. The write operation for the logical address LA=3, 6, 8 and 15 corresponding to SVD=3 may be allocated to the fourth flash translation layer FTL4 to store the (corresponding) write data to the fourth domain DM4.

[0107] Fig.16 It shows the use of Fig.12 The address bits are set and Fig.13FIG. 1 is a diagram of an example embodiment of address scrambling of a scrambling function.

[0108] Reference Fig.16 For a specific pattern of logical addresses LA (e.g., logical addresses LA corresponding to multiples of 4 (e.g., LA=0, LA=4, LA=8, LA=12)), a request for a write operation may be received from a host device (e.g., referring to Figure 1 host device 200) is sent sequentially to a storage device (e.g., storage device 300).

[0109] For this specific address mode, conventionally, a write operation may be squeezed into one of the first to fourth flash translation layers FTL1 to FTL4 , thereby reducing endurance and performance of a nonvolatile memory device (eg, nonvolatile memory device 320 ).

[0110] In contrast, according to example embodiments, a write operation with a specific address mode may be performed via a reference Figures 12 to 15 The described address scrambling is distributed between the first to fourth flash translation layers FTL1 to FTL4, and the write data can be distributed and stored in the first to fourth domains DM1 to DM4. By distributing the write operation, parallel processing of data input and output (I / O) can be efficiently supported.

[0111] Therefore, a storage device (e.g., storage device 300) and a method of operating a storage device according to an example embodiment can prevent input and output (I / O) from being squeezed into a specific domain through two-level address scrambling, which determines a scrambling function (e.g., scrambling function fi) based on a seed value (e.g., seed value VS) of a logical address (e.g., logical address LA), and scrambles the domain value (e.g., domain value VD) of the logical address based on the scrambling function.

[0112] Fig.17 is a diagram showing an example embodiment of address bit settings in a method of operating a memory device according to an example embodiment, and Fig.18 It shows that according to Fig.17 FIG. 1 is a diagram of an example embodiment of a scrambling function for setting address bits.

[0113] Reference Fig.17 , by a host device (e.g., referring to Figure 1 The logical address LA provided by the host device 200 may include a plurality of address bits B0 to Bk. In one embodiment, the nonvolatile memory device (e.g., the nonvolatile memory device 320) may be divided into eight domains. At this time, the three lower bits B0, B1, and B2 may be set as domain bits DMB, and all bits B3 to Bk higher than the domain bits DMB may be set as seed bits SDB, such as Fig.17shown.

[0114] Reference Fig.18 , each scrambling function fi can be a one-to-one corresponding function, and the one-to-one corresponding function exists as shown in the reference Figure 6 The inverse function of . Fig.18 An example scrambling function fi corresponding to a one-to-one correspondence is shown. When the number of bits of the domain bit DMB is 3, there may be up to (2 3 =8! =8x7x6x5x4x3x2x1=40320 scrambling functions.

[0115] Fig.19 is a flowchart illustrating a method of operating a storage device according to an example embodiment, and Fig. 20 is a diagram illustrating an example embodiment of a range operation controller included in a storage device according to an example embodiment.

[0116] Reference Figure 1 , Fig.19 and Fig. 20 , the storage controller 310 may receive a request REQ from the host device 200 to perform the same operation for an address range ADRG including a plurality of sequential logical addresses LA (S21). Fig. 20 and Fig.21 As shown, the address range ADRG can be represented by a starting logical address LAs and an ending logical address LAe. In some embodiments, the address range ADRG can be provided by the host device 200 in the form of a starting address LAs and a size or length of the address range ADRG.

[0117] The range operation controller ROC included in the storage controller 310 can classify the address range ADRG into a main range BDRG and an edge range EGRG excluding the main range BDRG (S22). For example, the main range BDRG can be represented by a start logical address LAs′ and an end logical address LAe′, and the edge range EGRG can be represented by corresponding logical addresses LAa, LAb, and LAc.

[0118] Here, the main range BDRG may include (eg, may be composed of) unit ranges UR, each of which contains 2 unit ranges UR having the same seed value VS. N logical addresses, where N is the number of bits of the seed bit SDB. For example, when N=2, each unit range UR contains 4 logical addresses with the same seed value VS.

[0119] The storage controller 310 may omit generating the scrambled domain value SVD for the logical address (eg, logical address LA) corresponding to the body range BDRG and perform the same operation for the logical address corresponding to the body range BDRG based on the domain value VD ( S23 ).

[0120] On the other hand, the storage controller 310 may generate a scrambled domain value SVD for a logical address (e.g., a logical address LA) corresponding to the edge range EGRG, and perform the same operation (S24) for the logical address corresponding to the edge range EGRG based on the scrambled domain value SVD. In some embodiments, the range operation controller ROC may provide a processor (e.g., a scrambling circuit SCR) with a logical address corresponding to the main range BDRG, and may provide the processor with a scrambled logical address corresponding to the edge range EGRG by replacing the domain value VD with the scrambled domain value SVD.

[0121] Fig.21 Is used to describe Fig. 20 A diagram of the scope of the operation controller.

[0122] Fig.21 The seed value VS of the seed bits SDB, the domain value VD of the domain bits DMB, and the scrambled domain value SVD of the domain bits DMB of the example address range ADRG are shown.

[0123] The address range ADRG may include the logical addresses LA between the start logical address LAs and the end logical address LAe. Fig.21 In the example of , the start logical address LAs of the address range ADRG corresponds to (N-1)+2, and the end logical address LAe of the address range ADRG corresponds to (N+3).

[0124] The main range BDRG may include all unit ranges UR within the address range ADRG. The main range BDRG may include the logical addresses LA between the start logical address LAs and the end logical address LAe. Fig.21 In the example of FIG. 5 , the start logical address LAs′ of the body range BDRG corresponds to N, and the end logical address LAe′ of the body range BDRG corresponds to (N+2)+3.

[0125] The edge range EGRG may correspond to the remaining portion of the address range ADRG except for the main range BDRG. Fig.21 In the example of , the edge range EGRG contains three logical addresses LAa, LAb and LAc. LAa corresponds to (N-1)+2, LAb corresponds to (N-1)+3, and LAc corresponds to (N+3).

[0126] exist Fig.21 In the example, DNC indicates "don't care", i.e., address scrambling is not required. The same operation can be performed for all address ranges ADRG. The same operation can be performed sequentially for the four logical addresses LA in each unit range UR, and address scrambling is not required.

[0127] On the other hand, for the logical addresses LAa, Lab and LAc corresponding to the edge region EGRG, address scrambling can be performed to generate the corresponding scrambled domain value SVD, and the same operation can be performed on the scrambled logical address (for example, the scrambled logical address SLA) to replace the domain value VD of the logical addresses LAa, Lab and LAc respectively with the generated scrambled domain value SVD.

[0128] For the main range BDRG that can be processed sequentially, a sequential access operation with fast operation speed and which can be processed in blocks (such as memset) can be performed, and for the edge range EGRG other than the main range BDRG, a random access operation can be performed by scrambling the address (for example, logical address LA) using a scrambling circuit SCR.

[0129] Therefore, a storage device (e.g., storage device 300) and an operating method of the storage device according to an example embodiment can selectively perform address scrambling in the case of a range operation in which the same operation is performed on an address range ADRG by classifying the address range ADRG into a main range BDRG and an edge range EGRG, thereby efficiently supporting (e.g., implementing) the above-mentioned range operation.

[0130] Fig. 22 is a diagram showing an example embodiment of address bit settings in a method of operating a memory device according to an example embodiment, and Fig.23 It shows the use of Fig. 22 The address bits are set and Fig.13 FIG. 1 is a diagram of an example embodiment of address scrambling of a scrambling function.

[0131] Reference Fig. 22 , by a host device (e.g., referring to Figure 1 The logical address LA provided by the host device 200 may include a plurality of address bits B0 to Bk. In one embodiment, the nonvolatile memory device (e.g., the nonvolatile memory device 320) may be divided into eight domains. In this case, the least significant bit B0 (e.g., the least significant bit LSB) may be set as the granularity bit GRB, the two bits B1 and B2 adjacent to the granularity bit GRB may be set as the domain bit DMB, and all bits B3 to Bk higher than the domain bit DMB may be set as the seed bit SDB, as shown in FIG. Fig. 22 shown.

[0132] Reference Fig.23 , for sequential logical addresses LA (ie, LA=0 to LA=15), a request for a write operation (eg, request REQ) may be received from a host device (eg, referring to Figure 1 host device 200) is sent sequentially to a storage device (e.g., storage device 300). Figure 1 The scrambling circuit SCR can determine one of the scrambling functions f0 and f1 based on the seed value VS of each logical address LA as described above, and generate a scrambled domain value SVD corresponding to each domain value VD in the determined scrambling function (for example, corresponding to the calculation of each domain value VD by the determined scrambling function). Fig.23 The correspondence between the logical addresses LA=0 to LA=15 according to this address scrambling and the scrambled logical addresses SLA=0 to SLA=15 is shown.

[0133] The domain value VD of the domain bit DMB may be independent of the granularity bit GRB corresponding to the least significant bit. Fig.23 As shown, two sequential (adjacent) logical addresses LA can be paired to have the same scrambled domain value SVD. Therefore, the corresponding write operations of the two sequential logical addresses can be assigned to the same domain.

[0134] exist Fig.23 The unit range UR represents 2 with the same seed value VS. N+M A set of logical addresses LA, where N is the number of bits of the seed bits SDB and M is the number of bits of the granularity bits GRB. For N=2 and M=1, each unit range UR contains 8 logical addresses LA, such as Fig.23 As shown. For 2 M Corresponding write operations of two sequential logical addresses LA may be assigned to the same domain.

[0135] Fig.24 is a diagram illustrating an example embodiment of adjusting the number of granularity bits in a method of operating a storage device according to example embodiments.

[0136] The first case CS11 shows a case where the granularity bit GRB is not set, the second case CS12 shows a case where the granularity bit GRB of one bit B0 is set, and the third case CS13 shows a case where the granularity bit GRB of two bits B0 and B1 is set.

[0137] In the first case CS11, as referenced Figures 12 to 15 As described above, address scrambling may be performed based on one logical address LA in each unit range UR, so that the logical address LA in each unit range UR may be allocated to different domains.

[0138] In the second case CS12, as referenced Fig. 22 and Fig.23 As described above, address scrambling may be performed in units of two logical addresses LA in each unit range UR, so that two sequential (adjacent) logical addresses LA in each unit range UR may be respectively allocated to the same domain.

[0139] In a third case CS1 to 3 (not shown in the reference drawing), address scrambling may be performed in units of four logical addresses LA in each unit range UR so that four sequential (adjacent) logical addresses LA in each unit range UR may be allocated to the same domain.

[0140] Therefore, finer scrambling can be performed by reducing the number of bits of the granularity bits GRB, and coarser scrambling can be performed by increasing the number of bits of the granularity bits GRB.

[0141] Fig.25 is a flowchart illustrating a method of operating a storage device according to an example embodiment, and Fig.26 is a diagram illustrating an example embodiment of address scrambling in a method of operating a memory device according to example embodiments.

[0142] Reference Figure 1 , Fig.25 and Fig.26 The scrambling circuit SCR may determine a sub-scrambling function fi′ based on a sub-seed value VS′ of a sub-seed bit SDB′ corresponding to a portion of the seed bit SDB ( S500 ).

[0143] The scrambling circuit SCR may generate a scrambled subfield value SVD′ based on the sub-scrambling function fi′ and the subfield value VD′ of the subfield bits DMB′ corresponding to another part of the seed bits SDB ( S600 ).

[0144] Figure 2 The processes S200 and S300 may be referred to as the first scrambling, and Fig.25 The processes S500 and S600 may be referred to as the second scrambling. The scrambling circuit SCR may be completed with Figure 2 After the first scrambling corresponding to the processes S200 and S300, the Fig.25 The processes S500 and S600 correspond to the second scrambling, such as Fig.26 shown.

[0145] Based on the scrambled sub-domain value VD′, the storage processor SPCR may allocate a write operation corresponding to the logical address LA to a sub-domain corresponding to the scrambled sub-domain value VD′ among the plurality of sub-domains ( S700 ).

[0146] Reference Fig.26 , the address bits of the logical address LA can be set to the granularity bit GRB, the domain bit DMB and the seed bit SDB. Figure 4 The scrambling circuit SCR may determine the scrambling function fi according to the seed value VS of the seed bit SDB, and perform the first scrambling based on the domain value VD of the domain bit DMB and the scrambling function fi to generate a scrambled domain value SVD.

[0147] In addition, the seed bit SDB can be set to the sub-granularity bit GRB', the sub-domain bit DMB' and the sub-seed bit SDB'. In a similar manner to the first scrambling, the scrambling circuit SCR can perform the second scrambling to determine the sub-scrambling function fi' based on the sub-seed value VS' of the sub-seed bit SDB', and generate the scrambled sub-domain value SVD' based on the sub-domain value VD' of the sub-domain bit DMB' and the sub-scrambling function fi'.

[0148] For example, in the following reference Fig.32 In the case of the structure of the non-volatile memory device described in the embodiment, the domain can be divided into channels one by one, and the sub-domain can be divided into paths one by one for each channel. In this way, when the storage area of ​​the non-volatile memory device is hierarchically divided, the reference Fig.25 and Fig.26 Multiple address scrambling is described to further enhance address distribution.

[0149] Fig. 27 is a flowchart illustrating an example embodiment of address bit setting in a method of operating a memory device according to example embodiments.

[0150] Reference Fig. 27 , the number of bits of the domain bit (e.g., domain bit DMB) may be set based on the number of multiple channels connecting (e.g., electrically connecting) the storage controller (e.g., storage controller 310) and the nonvolatile memory device (e.g., nonvolatile memory device 320) (S41). In one embodiment, as shown in FIG. Figure 7 and Figure 8 As described above, each channel can be set to a domain. In another embodiment, as shown in FIG. Fig. 9 and Fig.10 As described above, one domain may be set for every two or more channels.

[0151] The number of bits of the sub-domain bit (e.g., sub-domain bit DMB') may be set based on the number of paths connected (e.g., electrically connected) to each of the plurality of channels (S42). According to an embodiment, one sub-domain may be set for each path, or one sub-domain may be set for every two or more paths.

[0152] Fig.28 and Fig.29is a diagram illustrating an example embodiment of setting a buffer memory in a method of operating a memory device according to example embodiments.

[0153] Reference Fig.28 and Fig.29 , a buffer memory (eg, buffer memory 330) may include a plurality of buffers, each buffer BRGi (where "i" is a natural number greater than 1 and less than or equal to "n") may be managed by an i-th flash translation layer FTLi, respectively. Fig.28 An example is shown in which a nonvolatile memory device (eg, nonvolatile memory device 320) includes four buffers BRG1 to BRG4 corresponding to four domains (eg, first to fourth domains DM1 to DM4), and Fig.29 An example is shown in which the nonvolatile memory device includes eight buffers BRG1 to BRG8 corresponding to eight domains (eg, first to eighth domains DM1 to DM8 ).

[0154] In one embodiment, the number of bits of the granularity bit GRB can be set based on the capacity of the buffer memory and the number of multiple domains included in the non-volatile memory device. Fig.28 and Fig.29 When the buffer memory has the same capacity, the amount of data that can be buffered by each buffer BRGi can be reduced as the number of multiple domains increases. Therefore, as the number of multiple domains increases, the number of bits of the granularity bit GRB can be reduced, that is, Fig.29 The number of bits of the corresponding granularity bit GRB is set to be less than Fig.28 The corresponding number of bits of the granularity bit GRB. On the other hand, the number of bits of the granularity bit GRB can increase as the capacity of the buffer memory increases. In this way, by setting the number of bits of the granularity bit GRB suitable for hardware resources (such as the number of channels of the non-volatile memory device, the capacity of the buffer memory, etc.), data input / output parallel processing can be efficiently supported.

[0155] Fig.30 is a block diagram illustrating an example embodiment of a memory controller included in a memory device according to an example embodiment.

[0156] Reference Fig.30 , the storage controller 400 may include a processor 410, a memory 420, a scrambling circuit 430, a host interface (I / F) 440, an error correction code (ECC) engine 450, a memory interface (I / F) 460, and a RAID controller 470. In some embodiments, the storage controller 400, the processor 410, and the scrambling circuit 430 may correspond to Figure 1 The storage controller 310, storage processor SPRC and scrambling circuit SCR in.

[0157] Processor 410 may respond to a request from a host device (eg, Figure 1 4. For example, the processor 410 may control the storage device (e.g., Figure 1 The processor 410 may include a flash translation layer FTL that can be operated in units of domains as described above.

[0158] The memory 420 may store instructions and data executed and processed by the processor 410. For example, the memory 420 may include (may be implemented as) a volatile memory such as a DRAM, an SRAM, a cache memory, and the like.

[0159] The scrambling circuit 430 may perform address scrambling as described above. According to example embodiments, the scrambling circuit 430 may include (may be implemented as) hardware, software, and / or firmware.

[0160] The ECC engine 450 for error correction may perform coded modulation using, for example, Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0161] The host interface 440 may provide a physical connection (and / or electrical connection) between the host device and the storage device. The host interface 440 may provide an interface corresponding to the bus format of the host device for communication between the host device and the storage device. In some example embodiments, the bus format of the host device may be a small computer system interface (SCSI) or a serial attached SCSI (SAS) interface. In other example embodiments, the bus format of the host device may be a USB, a peripheral component interconnect (PCI) express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a SATA, a non-volatile memory (NVM) express (NVMe), and the like.

[0162] The memory interface 460 can communicate with a non-volatile memory device (eg, Figure 1The memory interface 460 may be connected to the nonvolatile memory device 320 for data communication. The memory interface 460 may send data to the nonvolatile memory device or may receive data read from the nonvolatile memory device. In some example embodiments, the memory interface 460 may be connected (e.g., electrically connected) to the nonvolatile memory device via one channel. In other example embodiments, the memory interface 460 may be connected (e.g., electrically connected) to the nonvolatile memory device via two or more channels. For example, the memory interface 460 may be configured to comply with a standard protocol, such as Toggle or an open NAND flash interface (ONFI).

[0163] RAID controller 470 may be implemented to perform conventional RAID recovery functions. According to an example embodiment, RAID controller 470 may also be used to perform indirect read operations.

[0164] The memory controller 400 may include an Advanced Encryption Standard (AES) engine. The AES engine may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 400 using a symmetric key algorithm.

[0165] Fig.31 is a block diagram illustrating a nonvolatile memory device included in a memory device according to example embodiments.

[0166] Reference Fig.31 , the nonvolatile memory 500 may include a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data I / O circuit 540, a voltage generator 550, and a control circuit 560. In some embodiments, the nonvolatile memory 500 may correspond to a reference Figure 1 A non-volatile memory device 320 is provided.

[0167] The memory cell array 510 may be connected (e.g., electrically connected) to the address decoder 520 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The memory cell array 510 may also be connected (e.g., electrically connected) to the page buffer circuit 530 via a plurality of bit lines BL. The memory cell array 510 may include a plurality of memory cells (e.g., a plurality of nonvolatile memory cells) connected (e.g., electrically connected) to a plurality of word lines WL and a plurality of bit lines BL. The memory cell array 510 may be divided into a plurality of memory blocks BLK1, BLK2, ..., BLKi, each memory block including memory cells. In addition, each of the plurality of memory blocks BLK1, BLK2, ..., BLKi may be divided into a plurality of pages.

[0168] In some example embodiments, a plurality of memory cells included in the memory cell array 510 may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. Fig.33 To describe a memory cell array of a 3D vertical array structure.

[0169] The control circuit 560 can be controlled from the outside (e.g., Figure 1 The storage controller 310 in the non-volatile memory 500 receives the command CMD and the address ADDR, and controls the erase operation, programming operation and read operation of the non-volatile memory 500 based on the command CMD and the address ADDR. The erase operation may include performing a series of erase cycles, and the programming operation may include performing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0170] For example, the control circuit 560 may generate a control signal CON for controlling the voltage generator 550, may generate a control signal PBC for controlling the page buffer circuit 530 based on the command CMD, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 560 may provide the row address R_ADDR to the address decoder 520 and may provide the column address C_ADDR to the data I / O circuit 540.

[0171] The address decoder 520 may be connected (eg, electrically connected) to the memory cell array 510 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL.

[0172] For example, in data erase / write / read operations, the address decoder 520 may determine at least one of the plurality of word lines WL as a selected word line based on the row address R_ADDR, and may determine the remaining word lines except the selected word line as unselected word lines.

[0173] Furthermore, in data erase / write / read operations, the address decoder 520 may determine at least one of the plurality of string selection lines SSL as a selected string selection line based on the row address R_ADDR, and determine the remaining string selection lines except the selected string selection line as unselected string selection lines.

[0174] Further, in data erase / write / read operations, the address decoder 520 may determine at least one of the plurality of ground selection lines GSL as a selected ground selection line based on the row address R_ADDR, and determine the remaining ground selection lines except the selected ground selection line as unselected ground selection lines.

[0175] The voltage generator 550 may generate a voltage V required for the operation of the nonvolatile memory 500 based on the power PWR and the control signal CON. The voltage V may be applied to a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL through the address decoder 520. In addition, the voltage generator 550 may generate an erase voltage (erase voltage VERS) required for a data erase operation based on the power PWR and the control signal CON. The erase voltage may be applied directly to the memory cell array 510 or to the memory cell array 510 via the bit line BL.

[0176] For example, during an erase operation, the voltage generator 550 may apply an erase voltage to a common source line and / or a bit line BL of a memory block (e.g., a selected memory block), and may apply an erase enable voltage (e.g., a ground voltage) to all or part of the word lines of the memory block via the address decoder 520. In addition, during an erase verification operation, the voltage generator 550 may simultaneously apply an erase verification voltage to all word lines of the memory block or sequentially apply an erase verification voltage to the word lines one by one.

[0177] For example, during a program operation, the voltage generator 550 may apply a program voltage to a selected word line, and may apply a program pass voltage to unselected word lines via the address decoder 520. In addition, during a program verification operation, the voltage generator 550 may apply a program verification voltage to a selected word line, and may apply a verification pass voltage to unselected word lines via the address decoder 520.

[0178] In addition, during a normal read operation, the voltage generator 550 may apply a read voltage to a selected word line, and may apply a read pass voltage to unselected word lines via the address decoder 520. During a data recovery read operation, the voltage generator 550 may apply a read voltage to word lines adjacent to the selected word line, and may apply a recovery read voltage to the selected word line via the address decoder 520.

[0179] The page buffer circuit 530 may be connected (e.g., electrically connected) to the memory cell array 510 via a plurality of bit lines BL. The page buffer circuit 530 may include a plurality of page buffers. In some example embodiments, each page buffer may be connected (e.g., electrically connected) to one bit line. In other example embodiments, each page buffer may be connected (e.g., electrically connected) to two or more bit lines.

[0180] The page buffer circuit 530 may store data DAT to be programmed in the memory cell array 510, or may read data DAT sensed (e.g., read) from the memory cell array 510. In other words, the page buffer circuit 530 may operate as a write driver or a sense amplifier according to an operation mode of the nonvolatile memory 500.

[0181] The data I / O circuit 540 may be connected (e.g., electrically connected) to the page buffer circuit 530 via a data line DL. The data I / O circuit 540 may provide data DAT from the outside of the nonvolatile memory 500 to the memory cell array 510 through the page buffer circuit 530 based on the column address C_ADDR, or provide data DAT from the memory cell array 510 to the outside of the nonvolatile memory 500. As used hereinafter, the terms "external / external configuration", "external / external device", "external / external power supply", "external / external signal", or "external" are intended to broadly refer to devices, circuits, blocks, modules, power supplies, and / or signals that reside externally (e.g., outside the functional or physical boundaries) relative to a given circuit, block, module, system, or device.

[0182] Although the nonvolatile memory is described based on NAND flash memory, example embodiments are not limited thereto, and the nonvolatile memory may be any nonvolatile memory, for example, phase random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.

[0183] Fig.32 is a block diagram illustrating a storage device according to example embodiments.

[0184] Reference Fig.32 , the storage device 600 may include a storage device 610 and a storage controller 620. The storage device 600, the storage device 610, and the storage controller 620 may correspond to Figure 1 The storage device 300, the nonvolatile memory device 320, and the storage controller 310 are provided. The storage device 600 may support a plurality of channels CH1, CH2, ..., CHm, and the storage device 610 may be connected (e.g., electrically connected) to the storage controller 620 through the plurality of channels CH1 to CHm. For example, the storage device 600 may be implemented as a storage device (e.g., a universal flash memory (UFS), a solid state drive (SSD), etc.).

[0185] The memory device 610 may include a plurality of nonvolatile memories NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn. Each of the nonvolatile memories NVM11 to NVMmn may be connected (e.g., electrically connected) to one of the plurality of channels CH1 to CHm through a path (path W11 to Wmn) corresponding thereto. For example, the nonvolatile memories NVM11 to NVM1n may be connected (e.g., electrically connected) to the first channel CH1 through the paths W11, W12, ..., W1n, the nonvolatile memories NVM21 to NVM2n may be connected (e.g., electrically connected) to the second channel CH2 through the paths W21, W22, ..., W2n, and the nonvolatile memories NVMm1 to NVMmn may be connected (e.g., electrically connected) to the mth channel CHm through the paths Wm1, Wm2, ..., Wmn. In some example embodiments, each of the nonvolatile memories NVM11 to NVMmn may be implemented as a memory unit that may be operated according to a separate command from the memory controller 620. For example, each of the nonvolatile memories NVM11 to NVMmn may be implemented as a chip or a die, but example embodiments are not limited thereto.

[0186] The memory controller 620 may transmit and receive signals to and from the memory device 610 through a plurality of channels CH1 to CHm. For example, the memory controller 620 may transmit commands CMDa, CMDb, ..., CMDm, addresses ADDRa, ADDRb, ..., ADDRm, and data DATAa, DATAb, ..., DATAm to the memory device 610 through the channels CH1 to CHm, or may receive data DATAa to DATAm from the memory device 610 through the channels CH1 to CHm.

[0187] The storage controller 620 may select one of the nonvolatile memories NVM11 to NVMmn connected to (e.g., electrically connected to) one of the channels CH1 to CHm using a corresponding one of the paths W11 to Wmn, and may send and receive signals to and from the selected nonvolatile memory. For example, the storage controller 620 may select (by using the path W11) a nonvolatile memory NVM11 connected to (e.g., electrically connected to) the first channel CH1 among the nonvolatile memories NVM11 to NVM1n. The storage controller 620 may send a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory NVM11 through the first channel CH1, or may receive data DATAa from the selected nonvolatile memory NVM11 through the first channel CH1.

[0188] The memory controller 620 may send and receive signals to and from the memory device 610 in parallel through different channels. For example, the memory controller 620 may send a command CMDb to the memory device 610 through the second channel CH2 while sending a command CMDa to the memory device 610 through the first channel CH1. For example, the memory controller 620 may receive data DATAb from the memory device 610 through the second channel CH2 while receiving data DATAa from the memory device 610 through the first channel CH1.

[0189] The memory controller 620 may control the overall operation of the memory device 610. The memory controller 620 may send signals to the channels CH1 to CHm, and may control each of the nonvolatile memories NVM11 to NVMmn connected (e.g., electrically connected) to the channels CH1 to CHm. For example, the memory controller 620 may send a command CMDa and an address ADDRa to the first channel CH1, and may control one nonvolatile memory selected from the nonvolatile memories NVM11 to NVM1 n.

[0190] Each of the nonvolatile memories NVM11 to NVMmn may operate under the control of the memory controller 620. For example, the nonvolatile memory NVM11 may program data DATAa based on a command CMDa, an address ADDRa, and data DATAa provided from the memory controller 620 through the first channel CH1. For example, the nonvolatile memory NVM21 may read data DATAb based on a command CMDb and an address ADDRb provided from the memory controller 620 through the second channel CH2, and may transmit the read data DATAb to the memory controller 620 through the second channel CH2.

[0191] although Fig.32 An example is shown in which the memory device 610 communicates with the memory controller 620 through m channels and includes n nonvolatile memories corresponding to each channel, but example embodiments are not limited thereto, and various changes may be made to the number of channels and the number of nonvolatile memories connected (e.g., electrically connected) to one channel.

[0192] Fig.33 is a circuit diagram illustrating an equivalent circuit of a memory block of a nonvolatile memory device included in a memory device according to example embodiments.

[0193] Reference Fig.33 , including Fig.31 Each memory block BLKi in the memory cell array 510 may be formed on a substrate in a three-dimensional structure (or a vertical structure). For example, a NAND string or a cell string included in the memory block BLKi may be formed along a vertical direction D3 perpendicular to the upper surface of the substrate. The first direction D1 and the second direction D2 are parallel to the upper surface of the substrate. The first direction D1 and the second direction D2 may intersect each other (e.g., may be perpendicular).

[0194] The memory block BLKi may include, for example, NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string selection transistor SST, memory cells MC1 to MC8, and a ground selection transistor GST. Fig.33 , each of the NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, embodiments are not limited thereto, and each of the NAND strings NS11 to NS33 may include a different number of memory cells.

[0195] Each string selection transistor SST may be connected (e.g., electrically connected) to a corresponding string selection line (one of SSL1 to SSL3). Memory cells MC1 to MC8 may be connected (e.g., electrically connected) to corresponding gate lines GTL1 to GTL8, respectively. Gate lines GTL1 to GTL8 may be word lines, and some of gate lines GTL1 to GTL8 may be dummy word lines. Each ground selection transistor GST may be connected (e.g., electrically connected) to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST may be connected (e.g., electrically connected) to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST may be connected to a common source line CSL.

[0196] Word lines (eg, gate line GTL1) having the same height may be connected in common, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Fig.33 , the memory block BLKi is shown to be coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto, and each memory block BLKi in the memory cell array 510 may be coupled to a different number of word lines and a different number of bit lines.

[0197] Fig.34 is a block diagram illustrating an example embodiment of an interconnect architecture of a storage system according to an example embodiment.

[0198] Reference Fig.34 , shows an example embodiment of a design consisting of point-to-point links interconnecting a set of components. System 102 may include a host processor (HPRC) 210, a host memory device (or system memory) (HMEM) 220, and a memory management unit (MMU) 230 connected (e.g., electrically connected) to a controller hub 315. Host processor 210 may include any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Host processor 210 may be connected (e.g., electrically connected) to controller hub 315 via a front-end bus (FSB) 306. In one example embodiment, FSB 306 may be a serial point-to-point interconnect. In another example embodiment, FSB 306 may include a serial differential interconnect architecture that complies with different interconnect standards.

[0199] The system memory 220 may include any memory device, such as random access memory (RAM), non-volatile (NV) memory, solid-state memory, or other memory accessible to devices in the system 102. The system memory 220 may be connected (e.g., electrically connected) to the controller hub 315 via a memory interface 316. Examples of the memory interface 316 may include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0200] In an example embodiment, the controller hub 315 can be a root hub, root complex, or root controller in a peripheral component interconnect express (PCIe or PCIE) interconnection hierarchy. Examples of the controller hub 315 can include a chipset, a memory controller hub (MCH), a north bridge, an interconnect controller hub (ICH), a south bridge, and a root controller / hub. Typically, the term "chipset" refers to two physically independent controller hubs, namely a memory controller hub (MCH) connected (e.g., electrically connected) to an interconnect controller hub (ICH). Please note that current systems typically include an MCH integrated with the host processor 210, and the controller hub 315 is used to communicate with I / O devices in a manner similar to that described below. In some example embodiments, peer-to-peer routing is optionally supported through a root complex or controller hub 315.

[0201] Here, the controller hub 315 may be connected (e.g., electrically connected) to the switch 319 via a serial link. The input / output modules 317 and 321 (also referred to as interfaces / ports 317 and 321) may include / implement a layered protocol stack to provide communication between the controller hub 315 and the switch 319. In an example embodiment, a plurality of devices may be able to connect (e.g., electrically connected) to the switch 319. The switch 319 may be referred to as a bridge.

[0202] The switch 319 can route packets / messages from the storage devices 301, 302, and 303 upstream (e.g., up the hierarchy to the root complex) to the controller hub 315, and downstream (e.g., down the hierarchy away from the root controller) from the host processor 210 or the system memory 220 to the storage devices 301, 302, and 303. In an example embodiment, the switch 319 can be referred to as a logical component of multiple virtual PCI to PCI bridge devices. The storage devices 301, 302, and 303 can include any internal or external devices or components to be connected (e.g., electrically connected) to the electronic system, such as I / O devices, network interface controllers (NICs), add-on cards, audio processors, network processors, hard drives, storage devices, CD / DVDROMs, monitors, printers, mice, keyboards, routers, portable storage devices, Firewire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. In PCIe terminology, such devices are generally referred to as endpoints. Storage devices 301, 302, and 303 may also include PCIe to PCI / PCI-X bridges to support legacy or other versions of PCI devices.Endpoint devices in PCIe can generally be categorized as legacy endpoints, PCIe endpoints, or root complex integrated endpoints.

[0203] The memory management unit 230 may also be connected (eg, electrically connected) to the controller hub 315 via a serial link 332. The I / O modules 331 and 318 may be used to implement a layered protocol stack to enable communication between the memory management unit 230 and the controller hub 315.

[0204] The memory management unit 230 may include a translation lookaside buffer (TLB) configured to store recently and / or frequently referenced address mapping information.

[0205] As described above, (each of) the storage devices 301 , 302 , and 303 may include a scrambling circuit SCR configured to perform address scrambling so that accesses to the storage devices 301 , 302 , and 303 may be distributed.

[0206] Fig.35 is a block diagram illustrating a computing system according to an example embodiment.

[0207] Reference Fig.35 , the multi-core system 1000 may include a system on chip (SoC), a working memory 1130, a display device (eg, LCD) 1152, a touch panel 1154, a storage device 1170, a power management integrated circuit (PMIC) 1200, etc. The storage device 1170 may correspond to Figure 1 The SoC may include a central processing unit (CPU) 1110, a task monitoring circuit TMON 1115, a DRAM controller 1120, a performance controller 1140, a user interface controller (UI controller) 1150, a storage interface 1160, an accelerator 1180, a power management unit (PMU) 1144, a clock management unit (CMU) 1146, etc. It should be understood that the components of the multi-core system 1000 are not limited to Fig.35 For example, the multi-core system 1000 may also include a hardware codec for processing image data, a security block, etc.

[0208] The CPU 1110 can execute the software (e.g., application programs, operating systems (OS) and / or device drivers) of the multi-core system 1000. The CPU 1110 can execute the operating system (OS) loaded into the working memory 1130. The CPU 1110 can execute various application programs driven on the operating system (OS). The CPU 1110 can be provided as a homogeneous multi-core processor or a heterogeneous multi-core processor. A multi-core processor is a computing component including at least two processors (hereinafter referred to as "cores" or "processor cores") that can be driven independently. Each core can read and execute program instructions independently.

[0209] The processor cores of the CPU 1100 may be grouped into a plurality of clusters, each cluster operating with an independent drive clock and an independent drive voltage. The processor cores within the same cluster may be included in a clock domain operating based on the same clock signal and / or in a power domain operating based on the same drive voltage. The drive voltage and / or clock signal provided to each processor core may be cut off or connected in units of a single core.

[0210] The kernel of the operating system (OS) may monitor the number of tasks in the task queue and the driving voltage and driving clock of the CPU 1110 at specific time intervals to control the CPU 1110. In addition, the kernel of the operating system (OS) may control the hot plugging of the CPU 1110 based on the monitored information. Therefore, as discussed in more detail below, the DVFS module and the frequency control module may be provided as part of the kernel.

[0211] The DRAM controller 1120 may provide an interface between the working memory 1130 and a system on chip (SoC). The DRAM controller 1120 may access the working memory 1130 according to a request of the CPU 1110 or another intellectual property (IP) block.

[0212] An operating system (OS) or a basic application program may be loaded into the working memory 1130 during a boot operation. For example, an OS image stored in the storage device 1170 may be loaded into the working memory 1130 based on a boot sequence when the multi-core system 1000 is booted. The overall input / output operation of the multi-core system 1000 may be supported by the operating system (OS). The working memory 1130 may be a volatile memory (e.g., a static random access memory (SRAM) and a dynamic random access memory (DRAM)), or a non-volatile memory device (e.g., a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory).

[0213] The performance controller 1140 may adjust the operating parameters of the system on chip (SoC) according to a control request provided from the kernel of the operating system (OS). For example, the performance controller 1140 may adjust the level of DVFS to enhance the performance of the system on chip (SoC). Alternatively, the performance controller 1140 may generate a frequency selection signal to control the frequency of the processor core according to the request of the kernel. In this case, the performance controller 1140 may include a performance table PFM T1142 to set the frequency of the drive voltage and the drive clock therein. The performance controller 1140 may control the PMU 1144 and the CMU 1146, which together form a power management circuit, connected (e.g., electrically connected) to the PMIC 1200 to provide a determined drive voltage and a determined drive clock to each power domain.

[0214] The user interface controller 1150 may control user input and output from the user interface device. For example, the user interface controller 1150 may display a keyboard screen for inputting data to the LCD 1152 according to the control of the CPU 1110. The user interface controller 1150 may control the LCD 1152 to display data requested by the user. The user interface controller 1150 may decode data provided from a user input device (e.g., a touch panel 1154) into user input data.

[0215] The storage interface 1160 may access the storage device 1170 according to a request of the CPU 1110. For example, the storage interface 1160 may provide an interface between a system on chip (SoC) and the storage device 1170. For example, data processed by the CPU 1110 may be stored in the storage device 1170 through the storage interface 1160. The data stored in the storage device 1170 may be provided to the CPU 1110 through the storage interface 1160.

[0216] The storage device 1170 may be provided as a storage medium of the multi-core system 1000. The storage device 1170 may store applications, OS images, and various types of data. The storage device 170 may be provided as a memory card (e.g., MMC, eMMC, SD, MicroSD, etc.). The storage device 170 may include a NAND-type flash memory with a large storage capacity. The storage device 1170 may include a next-generation non-volatile memory such as PRAM, MRAM, ReRAM, and FRAM or NOR-type flash memory.

[0217] The accelerator 1180 can be provided as a separate intellectual property (IP) component to increase the processing speed of multimedia or multimedia data. For example, the accelerator 1180 can be provided as an intellectual property (IP) component to enhance the processing performance of text, audio, still images, animation, video, two-dimensional data, or three-dimensional data.

[0218] The system interconnector 1190 may be a system bus for providing an on-chip network in a system on chip (SoC). The system interconnector 1190 may include, for example, a data bus, an address bus, and a control bus. The data bus may be a data transmission path. A memory access path to the working memory 1130 or the storage device 1170 may also be provided. The address bus may provide an address exchange path between intellectual property rights (IPs). The control bus may provide a path for sending control signals between intellectual property rights (IPs). However, the configuration of the system interconnector 1190 is not limited to the above description, and the system interconnector 1190 may also include an arbitration device to achieve efficient management.

[0219] As described above, the storage device 1170 may include a scrambling circuit SCR configured to perform address scrambling so that access to the storage device 1170 may be distributed.

[0220] The example embodiments disclosed herein may be embodied as a system, method, or computer program product embodied in one or more computer-readable media, on which a computer-readable program code is embodied. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be any tangible medium that may contain or store a program used by or associated with an instruction execution system, device, or apparatus.

[0221] The exemplary embodiments of the present disclosure can be applied to any electronic device and system. For example, the exemplary embodiments of the present disclosure can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, notebook computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, and automotive driving systems.

[0222] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the example embodiments without materially departing from the scope of the present disclosure.

Claims

1. A method for operating a storage device, the storage device comprising a non-volatile memory device and a storage controller configured to control the non-volatile memory device, the method comprising: dividing the nonvolatile memory device into a plurality of domains; determining a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device; generating a scrambled domain value based on the scrambling function and a domain value of domain bits corresponding to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; as well as A write operation corresponding to the logical address is allocated to a domain corresponding to the scrambled domain value among the plurality of domains.

2. The method according to claim 1, further comprising: The number of bits of the domain bit is set based on the number of a plurality of channels electrically connecting the memory controller and the nonvolatile memory device.

3. The method according to claim 1, wherein: The first portion corresponds to bits higher than the second portion among the plurality of address bits of the logical address among the plurality of logical addresses.

4. The method according to claim 3, further comprising: A third portion of the plurality of address bits of the logical address among the plurality of logical addresses is set as a granularity bit, the granularity bit being a bit lower than the second portion of the plurality of address bits of the logical address among the plurality of logical addresses.

5. The method according to claim 4, wherein: In response to determining that the number of bits of the granularity bit is a natural number M, 2 of the plurality of logical addresses are M The write operations corresponding to the sequential logical addresses are allocated to the same domain among the multiple domains.

6. The method according to claim 4, further comprising: The number of bits of the granularity bit is set based on a memory capacity of the memory controller and a number of the plurality of domains.

7. The method according to claim 1, further comprising: Each of the plurality of domains is divided into a plurality of subdomains.

8. The method according to claim 7, further comprising: determining a sub-scrambling function based on a sub-seed value of the sub-seed bits corresponding to the first portion of the seed bits; generating a scrambled subfield value based on the sub-scrambling function and the subfield value of the subfield bits corresponding to the second part of the seed bits; as well as The write operation corresponding to the logical address among the plurality of logical addresses is allocated to a subfield corresponding to the scrambled subfield value among the plurality of subfields.

9. The method according to claim 8, further comprising: setting the number of bits of the domain bit based on the number of a plurality of channels electrically connecting the memory controller to the nonvolatile memory device; as well as The number of bits of the sub-field bits is set based on the number of paths electrically connected to each of the plurality of channels.

10. The method according to claim 1, further comprising: receiving, from the host device, a request to perform the same operation for an address range including a plurality of sequential logical addresses among the plurality of logical addresses; as well as In response to receiving the request, the address range is classified into a principal range and an edge range.

11. The method according to claim 10, wherein: The subject range includes the unit range, and In response to determining that the number of the seed bits is N, where N is a natural number, each of the unit ranges includes 2 of the plurality of sequential logical addresses corresponding to the same seed value. N Sequential logical addresses.

12. The method according to claim 10, wherein: Generating the scrambled domain value includes: omitting generating the scrambled domain value for a first logical address corresponding to the subject range among the plurality of sequential logical addresses among the plurality of logical addresses, and The generating of the scrambled domain value comprises: generating the scrambled domain value for a second logical address corresponding to the edge range among the plurality of sequential logical addresses among the plurality of logical addresses.

13. The method according to claim 12, further comprising: Based on the domain value, performing the same operation on the first logical address corresponding to the subject range; as well as Based on the scrambled domain value, the same operation is performed on the second logical address corresponding to the edge range.

14. A storage device comprising: a non-volatile memory device comprising a plurality of domains; as well as a memory controller configured to control the nonvolatile memory device, The storage controller comprises: a scrambling circuit configured to determine a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device, and configured to generate a scrambled domain value based on the scrambling function and a domain value of a domain bit corresponding to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; as well as The processor is configured to allocate a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among the multiple domains.

15. The storage device according to claim 14, wherein: The number of granularity bits corresponding to the third part of the plurality of address bits of the logical address among the plurality of logical addresses is a natural number M, and The processor is configured to: connect 2 of the plurality of logical addresses to M The write operations corresponding to the sequential logical addresses are allocated to the same domain among the multiple domains.

16. The storage device according to claim 14, wherein: The scrambling circuit is configured to: divide each of the plurality of domains into a plurality of sub-domains; determine a sub-scrambling function based on a sub-seed value of a sub-seed bit corresponding to a first portion of the seed bits; and generate a scrambled sub-domain value based on the sub-scrambling function and a sub-domain value of a sub-domain bit corresponding to a second portion of the seed bits, and The processor is configured to: allocate the write operation corresponding to the logical address among the multiple logical addresses to a sub-domain corresponding to the scrambled sub-domain value among the multiple sub-domains.

17. The storage device according to claim 14, wherein: The storage controller further includes: A range operation controller is configured to, in response to receiving a request from the host device to perform the same operation on an address range including a plurality of sequential logical addresses among the plurality of logical addresses, classify the address range into a main range and an edge range excluding the main range.

18. The storage device according to claim 17, wherein: The range operation controller is configured to provide the processor with a logical address corresponding to the main range, and provide the processor with a scrambled logical address by replacing a domain value of a logical address corresponding to the edge range with the scrambled domain value.

19. A method of operating a storage device, the storage device comprising a non-volatile memory device and a storage controller configured to control the non-volatile memory device, the method comprising: dividing the nonvolatile memory device into a plurality of domains; determining a scrambling function based on a seed value of a seed bit corresponding to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses provided from a host device; generating a scrambled domain value based on the scrambling function and a domain value of domain bits corresponding to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; Allocating a write operation corresponding to the logical address to a domain corresponding to the scrambled domain value among the plurality of domains; as well as In response to receiving a request from the host device to perform the same operation on an address range including a plurality of sequential logical addresses among the plurality of logical addresses, classifying the address range into a main range and an edge range, Wherein, generating the scrambled domain value includes: The generation of the scrambled domain value for the subject range is omitted.

20. The method according to claim 19, wherein: The same operation is performed for the body range based on the domain value, and the same operation is performed for the edge range based on the scrambled domain value.

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