Addition module and its operation method, multiplier and its operation method, processor and device

Abstract

Embodiments of this disclosure provide an addition module and its operation method, a multiplier and its operation method, a processor, and a device. The addition module includes an adder, a register, and a control unit. The adder is configured to perform addition operations with a first computational precision to obtain a first operation result. The register is coupled to the adder and configured to receive the first operation result obtained by the adder. The control unit is coupled to both the register and the adder and configured to control the register and the adder to perform a reconfiguration operation to obtain a first multiplication module supporting a second computational precision. By reconfiguring the addition module, the ratio of the number of addition modules to the number of multiplication modules in the multiplier can be dynamically adjusted, and the computational precision of the multiply-adder can be adjusted.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an addition module and its operation method, a multiplier and its operation method, a processor, and a device. Background Technology

[0002] With the development of artificial intelligence, in order to meet its ever-increasing computing power demands, more and more computational structures tailored to the characteristics of machine learning computation have been proposed. In the computational process of machine learning, vector multiplication and matrix multiplication account for the majority of the computational load; therefore, how to improve the computational power and efficiency of these two types of operations is a key research focus. The basic operators for both vector multiplication and matrix multiplication are multiplication and addition; therefore, an efficient multiply-accumulator can significantly improve the efficiency of these two types of operations. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an addition module, comprising: an adder configured to perform an addition operation with a first computational precision to obtain a first operation result; a register coupled to the adder and configured to receive the first operation result obtained by the adder; and a control unit coupled to the register and the adder respectively and configured to control the register and the adder to perform a reconstruction operation to obtain a first multiplication module supporting a second computational precision; wherein the adder includes a plurality of full adders, each full adder including a first input terminal, a second input terminal, a carry input terminal, a sum bit output terminal, and a carry output terminal, the plurality of full adders being configured in a manner that... The multiple full adders are coupled in a cascaded manner, with the carry output of the previous full adder coupled to the carry input of the next full adder. The first input of each full adder is configured to receive a first addend, the second input of each full adder is configured to receive a second addend, the sum output of each full adder is configured to output the sum data, the carry output of the previous full adder is configured to output the carry data as the input data of the carry input of the next full adder, and the carry output of the last full adder is configured to output the final carry data. The first operation result includes the sum data and the final carry data.

[0004] At least one embodiment of this disclosure also provides an operation method for the addition module according to the above embodiments, including: performing splitting or merging operations on the adder and the register of the addition module to obtain at least one first adder and at least one first register, wherein the first adder supports the second calculation precision; reconstructing the connection mode of the at least one first adder and the at least one first register to obtain the first multiplication module.

[0005] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the step of splitting or merging the adders and registers of the addition module to obtain at least one first adder and at least one first register includes: in response to the first calculation precision being higher than the second calculation precision, splitting a plurality of full adders in the adders of the addition module into at least two groups, coupling each group of full adders in a first cascading manner to obtain the first adder, and splitting the registers of the addition module into at least two first registers; in response to the first calculation precision being lower than the second calculation precision, merging the adders of at least two addition modules into the first adder, and merging the registers of the at least two addition modules into the first register; in response to the first calculation precision being equal to the second calculation precision, using the adders and registers of the addition module as the first adder and the first register, respectively.

[0006] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the at least two addition modules include a first addition module and a second addition module. The step of merging the adders of the at least two addition modules into the first adder includes: coupling the carry output terminal of the last stage full adder in the adder of the first addition module with the carry input terminal of the first stage full adder in the adder of the second addition module to obtain the first adder.

[0007] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the second calculation precision is N-bit integer, the first multiplication module includes N first adders and N first registers, each first adder includes N full adders coupled in the first cascade manner, N=2n, n is a positive integer, the reconfiguration of the connection of the at least one first adder and the at least one first register to obtain the first multiplication module includes: coupling the N first adders to the N first registers respectively, so that the first registers receive the second operation result obtained by the corresponding coupled first adders performing the addition operation with the second calculation precision; coupling the N first adders in the second cascade manner, wherein the sum output terminal of the 2nd to Nth full adders in the previous stage first adder is coupled to the first input terminal of the 1st to (N-1)th full adders in the next stage first adder respectively, and the carry output terminal of the Nth full adder in the previous stage first adder is coupled to the first input terminal of the Nth full adder in the next stage first adder.

[0008] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the first multiplication module performs a multiplication operation with the second calculation precision on the first multiplier and the second multiplier, wherein the first multiplier and the second multiplier each include N bits of data, and the operation method further includes: taking the shifted first multiplier or the shifted preset addend as the first addend of the first stage first adder according to the first bit of the second multiplier; taking the first multiplier or the preset addend as the second addend of the (i-1)th stage first addend according to the i-th bit of the second multiplier, wherein i=2, 3, ..., N.

[0009] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the step of using the shifted first multiplier or the shifted preset addend as the first addend of the first-stage first adder according to the first bit data of the second multiplier includes: using the shifted first multiplier as the first addend of the first-stage first adder in response to the first bit data of the second multiplier being 1, and using the shifted preset addend as the first addend of the first-stage first adder in response to the first bit data of the second multiplier being 0.

[0010] For example, in the operation method of the addition module provided in at least one embodiment of this disclosure, the step of using the first multiplier or a preset addend as the second addend of the (i-1)th stage first adder according to the i-th bit data of the second multiplier includes: in response to the i-th bit data of the second multiplier being 1, using the first multiplier as the second addend of the (i-1)th stage first adder; and in response to the i-th bit data of the second multiplier being 0, using the preset addend as the second addend of the (i-1)th stage first adder.

[0011] At least one embodiment of this disclosure also provides a multiply-adder, comprising: a plurality of second multiplication modules, a plurality of first addition modules, and a plurality of second addition modules, wherein the second addition modules are addition modules according to claim 1, the first addition modules include a plurality of full adders coupled in the first cascade manner, the second multiplication modules are configured to perform multiplication operations with a third computational precision, and the first addition modules and the second addition modules are configured to receive the multiplication operation results output by the correspondingly coupled second multiplication modules and perform addition operations with the first computational precision.

[0012] At least one embodiment of this disclosure also provides a method for operating a multiply-accumulator according to the above embodiments, comprising: reconstructing at least a portion of the second addition modules into the second multiplication modules and / or the first addition modules to adjust the ratio of the number of the second multiplication modules, the first addition modules, and the second addition modules in the multiply-accumulator; or, in response to the multiply-accumulator switching from the third calculation precision to the second calculation precision, reconstructing the plurality of second multiplication modules into at least one first multiplication module, reconstructing the plurality of first addition modules into at least one third addition module, and reconstructing the at least a portion of the second addition modules into the at least one first multiplication module, wherein the third addition module supports a fourth calculation precision.

[0013] For example, in the operation method of the multiply-adder provided in at least one embodiment of this disclosure, the third calculation precision is int4, the first calculation precision and the second calculation precision are int8, and the fourth calculation precision is int16; the second multiplication module includes four second adders supporting the third calculation precision and four second registers, the second registers having a bit width of 8 bits, and the second adders including four full adders coupled in the first cascade manner; the first addition module includes eight full adders coupled in the first cascade manner; the second addition module includes a third adder and a third register, the third adder including the eight full adders coupled in the first cascade manner, the third register having a bit width of 16 bits, and the third register being coupled to the third adder to receive the operation result obtained by the corresponding third adder performing the addition operation with the first calculation precision.

[0014] For example, in the operation method of the multiply-adder provided in at least one embodiment of this disclosure, the step of reconstructing the plurality of second multiplication modules into at least one first multiplication module includes: merging the second adders and second registers in every four second multiplication modules into eight first adders and eight first registers, respectively, for reconstructing the first multiplication module, wherein the first adders support the second calculation precision, and the bit width of the first registers is 16 bits; coupling the eight first adders to the eight first registers respectively, so that each first register receives the operation result obtained by the corresponding coupled first adder performing the addition operation with the second calculation precision; and coupling the eight first adders in a second cascade manner, wherein the sum output of the second to eighth full adders in the previous stage first adder is coupled to the first input of the first to seventh full adders in the next stage first adder, and the carry output of the eighth full adder in the previous stage first adder is coupled to the first input of the eighth full adder in the next stage first adder.

[0015] For example, in the operation method of the multiply-adder provided in at least one embodiment of this disclosure, the step of reconstructing the plurality of first adder modules into at least one third adder module includes: merging every two first adder modules into the third adder module, wherein the third adder module includes the eight full adders coupled in the first cascade manner.

[0016] For example, in the operation method of the multiply-adder provided in at least one embodiment of this disclosure, the step of reconstructing the at least part of the second adder modules into the at least one first multiplyer module includes: coupling the third adders of every 8 second adder modules in the plurality of second adder modules in the second cascade manner, wherein the sum output terminals of the 2nd to 8th full adders in the previous stage third adder are respectively coupled to the first input terminals of the 1st to 7th full adders in the next stage first adder, and the carry output terminal of the 8th full adder in the previous stage first adder is coupled to the first input terminal of the 8th full adder in the next stage first adder.

[0017] At least one embodiment of this disclosure also provides a processor that includes the multiply-accumulator described in any of the above embodiments.

[0018] At least one embodiment of this disclosure also provides an electronic device that includes the processor described in any of the above embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0020] Figure 1 A schematic diagram of a multiply-accumulator is shown.

[0021] Figure 2 A schematic diagram of a convolution operation is shown;

[0022] Figure 3A A schematic diagram of the structure of an addition module provided in at least one embodiment of this disclosure is shown;

[0023] Figure 3B It shows Figure 3A A schematic diagram showing the connection between the adder and the register;

[0024] Figure 4 A schematic diagram illustrating an operation method of an addition module provided in at least one embodiment of this disclosure is shown;

[0025] Figure 5A A schematic diagram of the structure of a first multiplication module provided in at least one embodiment of the present disclosure is shown;

[0026] Figure 5B A schematic diagram is shown showing a first adder provided in at least one embodiment of the present disclosure coupled in a second cascade manner;

[0027] Figure 6 A schematic diagram illustrating the multiplication operation of two binary data in at least one embodiment of this disclosure is shown;

[0028] Figure 7 A schematic diagram showing the parameters used for multiplication operations in the first multiplication module is shown;

[0029] Figure 8 A schematic diagram of the structure of a multiply-accumulator provided in at least one embodiment of the present disclosure is shown;

[0030] Figure 9 A schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] With the rapid development of machine learning technology, efficient data processing and computing capabilities have become key factors in improving model performance. In hardware design, multipliers and adders are the core components for performing machine learning operations. Considering the characteristics of machine learning operations and the limitations of hardware design, multipliers and adders are generally combined in a fixed ratio to form a multiply-accumulate unit.

[0034] For example, Figure 1 A schematic diagram of a multiply-accumulator is shown. The multipliers and adders in this multiply-accumulator are combined in a 1:1 ratio, and the multiply-accumulator includes 16 multipliers and 16 adders. The computational precision of the multipliers can be FP16, INT16, INT8, and INT4, etc., and the computational precision of the adders can be FP16, INT16, INT8, and INT4, etc.

[0035] However, different machine learning algorithms and varying computational precisions result in different resource requirements for multipliers and adders. For example, some algorithms may require more multiplication operations, while others may rely more on addition, and still others may demand higher computational precision. Therefore, designing a multiply-accumulator with a fixed ratio has limitations. Because the ratio of multipliers to adders in a multiply-accumulator is designed as a fixed value, the utilization rate of hardware resources in the multiply-accumulator is low in certain scenarios, thus failing to maximize the computing power of the hardware design.

[0036] For example, taking the Convolutional Neural Network (CNN) algorithm as an example, the CNN algorithm involves convolution operations, pooling operations, activation function operations, etc. Among them, the computing power required for convolution operations accounts for the majority of the computing power required for the CNN algorithm. Therefore, when designing CNN hardware acceleration design, the focus is on accelerating convolution operations.

[0037] For example, Figure 2 A schematic diagram of a convolution operation is shown. For example... Figure 2As shown, convolution is achieved by multiplying the convolution kernel with the original feature map. The kernel has a size of 2×2 (4 elements). The kernel performs dot product operations with each of the 2×2 feature data in the original feature map, generating one data point per dot product. After the kernel has performed dot product operations with all 2×2 datasets in the original feature map, the resulting datasets form a new feature map. For example, in a single dot product operation, A0×k0+A1×k2+A8×k1+A9×k3=P9, each dot product operation requires 4 two-input multiplications and 3 two-input additions. When a multiplier-adder can handle exactly 4 multiplications and 3 additions simultaneously (i.e., the ratio of multipliers to adders is 4:3), the multiplier-adder achieves the highest computational efficiency when performing this convolution operation. However, as the algorithm changes (for example, the size of the convolution kernel changes), the number of multipliers and adders required to execute the algorithm also changes. At this time, the original multiply-adder cannot achieve the highest computational efficiency, and some multipliers or adders will be idle.

[0038] This disclosure provides one or more embodiments of an addition module and its operation method, and a multiply-adder and its operation method.

[0039] The addition module includes an adder, a register, and a control unit. The adder is configured to perform addition operations with a first computational precision to obtain a first operation result. The register is coupled to the adder and configured to receive the first operation result obtained by the adder. The control unit is coupled to both the register and the adder and configured to control the register and the adder to perform a reconfiguration operation to obtain a first multiplication module supporting a second computational precision. The addition module provided in this disclosure can be used to reconfigure multiplication modules with different computational precisions, thereby dynamically adjusting the ratio of multiplication modules to addition modules in the multiplier to adapt to the computational precision and hardware resource requirements of different machine learning algorithms, and improving the hardware resource utilization, computational efficiency, and flexibility of the multiply-adder.

[0040] The present disclosure will now be described with reference to several specific embodiments and the accompanying drawings. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0041] Figure 3A A schematic diagram of the structure of an addition module provided in at least one embodiment of the present disclosure is shown.

[0042] like Figure 3AAs shown, the addition module 300 includes an adder 310, a register 320, and a control unit 330. The adder 310 is configured to perform addition operations with a first computational precision to obtain a first operation result. The register 320 is coupled to the adder 310 and configured to receive the first operation result obtained by the adder 310. The control unit 330 is coupled to both the adder 310 and the register 320 and configured to control the adder 310 and the register 320 to perform a reconstruction operation to obtain a first multiplication module supporting a second computational precision.

[0043] For example, the adder includes multiple full adders, each including a first input, a second input, a carry input, a sum output, and a carry output. The multiple full adders are coupled in a first cascade configuration; specifically, the carry output of the preceding full adder is coupled to the carry input of the next full adder. The first input of each full adder is configured to receive a first addend, the second input is configured to receive a second addend, the sum output is configured to output the sum data, the carry output of the preceding full adder is configured to output carry data as input data to the carry input of the next full adder, and the carry output of the last full adder is configured to output the final carry data. The first operation result includes multiple sum data and the final carry data.

[0044] It should be noted that the calculation precision of the adder is related to the number of full adders coupled in the first cascade manner. For example, if the calculation precision of the adder is int4, the adder includes four full adders coupled in the first cascade manner. In addition, the full adder in the embodiments of this disclosure is a 1-bit full adder by default, but other types of full adders, such as 2-bit full adders, can also be used, and this disclosure does not limit this.

[0045] For example, Figure 3B It shows Figure 3A A schematic diagram showing the connection between the adder and the register.

[0046] like Figure 3B As shown, the calculation precision (i.e., the first calculation precision) of adder 310 is int8. Adder 310 includes eight full adders 3100~3107 coupled in a first cascade manner. For example, the carry output terminal Cout0 of the first-stage full adder 3100 is coupled to the carry input terminal Cin1 of the second-stage full adder 3101, and the carry output terminal Cout1 of the second-stage full adder 3101 is coupled to the carry input terminal Cin2 of the third-stage full adder 3102.

[0047] For example, consider full adders 3100-3107 configured to perform addition operations with a first computational precision on a first addend A and a second addend B. The first addend A and the second addend B each comprise 8 bits of data, for example, A = [a7, a6, a5, a4, a3, a2, a1, a0], B = [b7, b6, b5, b4, b3, b2, b1, b0]. For instance, the carry data received at the carry input Cin0 of the first-stage full adder 3100 can be set to 0.

[0048] like Figure 3B As shown, the first input terminals A0 to A7 of full adders 3100 to 3107 are configured to receive the first addend A. For example, the first input terminal A0 of full adder 3100 is configured to receive the first bit data a0 of the first addend A, the first input terminal A1 of full adder 3101 is configured to receive the second bit data a1 of the first addend A, and so on.

[0049] like Figure 3B As shown, the second input terminals B0 to B7 of full adders 3100 to 3107 are configured to receive the second addend B. For example, the second input terminal B0 of full adder 3100 is configured to receive the first bit data b0 of the first addend B, the second input terminal B1 of full adder 3101 is configured to receive the second bit data b1 of the first addend B, and so on.

[0050] like Figure 3B As shown, the sum output terminals S0-S7 of full adders 3100-3107 are configured to output sum data (e.g., Sum0-Sum7). The carry output terminal of the previous stage full adder is configured to output carry data as input data for the carry input terminal of the next stage full adder. For example, the carry output terminal Cout0 of the first stage full adder 3100 outputs carry data (e.g., C0) as input data for the carry input terminal Cin1 of the second stage full adder 3101. The carry output terminal Cout7 of the last stage full adder 3107 is configured to output the final carry data (e.g., C7).

[0051] After all eight full adders 3100-3107 have performed addition operations with the first computational precision, the eight sum data (e.g., Sum0-Sum7) and the final carry data (e.g., C7) are stored as the first operation result in register 320, and then the first operation result is output through register 320. Alternatively, after all eight full adders 3100-3107 have performed addition operations with the first computational precision, the first operation result can be output directly.

[0052] At least one embodiment of this disclosure also provides a method for operating an addition module, wherein the addition module is the addition module provided in any of the above embodiments. Figure 4As shown, the operation method includes steps S401 and S402.

[0053] Step S401: Perform splitting or merging operations on the adder and register of the addition module to obtain at least one first adder and at least one first register, wherein the first adder supports the second calculation precision.

[0054] Step S402: Reconstruct the connection of at least one first adder and at least one first register to obtain the first multiplication module.

[0055] For example, after adjusting the calculation precision of the adder and the bit width of the register in the addition module (i.e., after obtaining the first adder and the first register), it is necessary to reconstruct (i.e., adjust or modify) the connection method of the first adder and the first register to obtain the first multiplication module.

[0056] For example, step S401 above may include: in response to the first calculation precision being higher than the second calculation precision, splitting the multiple full adders in the adder of the adder module into at least two groups, coupling each group of full adders in a first cascade manner to obtain a first adder, and splitting the register of the adder module into at least two first registers.

[0057] For example, when the first calculation precision is int8 and the second calculation precision is int4, the bit width of the register in the addition module is 16 bits, and the adder of the addition module includes 8 adders in a first cascaded manner (see, for example, [link to example]). Figure 3B The fully added units (referred to here as "FullAdder_0~FullAdder_7") are coupled together. Through a splitting operation, two first adders and two first registers can be obtained. The first adders consist of four fully added units coupled in a first cascade manner, and the first registers have a bit width of 8 bits.

[0058] For example, the eight full adders FullAdder_0 to FullAdder_7 in the adder can be divided into two groups: the first group includes full adders FullAdder_0 to FullAdder_3, and the second group includes full adders FullAdder_4 to FullAdder_7. Then, the connection between the carry-out terminal of the fourth-stage full adder FullAdder_3 and the carry-in terminal of the fifth-stage full adder FullAdder_4 can be disconnected, resulting in two first adders. For example, the register in this example can be composed of 16 cascaded D flip-flops. When splitting this register into two first registers, the first eight D flip-flops in the register can be cascaded to obtain one first register, and the last eight D flip-flops in the register can be cascaded to obtain the other first register. Each first register is coupled to a first adder to receive and store the result of an addition operation with a second computational precision performed by the corresponding coupled first adder.

[0059] For example, when the first calculation precision is int16 and the second calculation precision is int4, the register width of the addition module is 32 bits, and the adder of the addition module includes 16 adders in a first cascaded manner (see, for example, [link to example]). Figure 3B In the case of a coupled full adder, the adder can be split into four first adders, and the registers of the adder module can be split into four first registers. The specific splitting method can be referred to the example above, and will not be repeated here.

[0060] For example, step S401 above may further include: in response to the first calculation precision being lower than the second calculation precision, merging the adders of at least two addition modules into a first adder, and merging the registers of at least two addition modules into a first register.

[0061] For example, at least two addition modules include a first addition module and a second addition module. The step of merging the adders of at least two addition modules into a first adder includes: coupling the carry output terminal of the last full adder in the adder of the first addition module with the carry input terminal of the first full adder in the adder of the second addition module to obtain the first adder.

[0062] For example, when the first calculation precision is int4 and the second calculation precision is int8, the register of the addition module has a bit width of 8 bits. The adder of the addition module includes four full adders coupled in the first cascade manner (here denoted as "FullAdder_0~FullAdder_3"). The first adder obtained through the merging operation needs to include eight full adders coupled in the first cascade manner. The bit width of the first register is 16 bits. Therefore, it is necessary to perform merging operations on the adders and registers in the two addition modules respectively. For example, the carry output of the last full adder FullAdder_3 in the adder of the first addition module is coupled to the carry input of the first full adder FullAdder_0 in the adder of the second addition module. For example, the registers in these two addition modules can each include eight D flip-flops. By cascading 16 D flip-flops, a first register with a bit width of 16 bits can be obtained.

[0063] For example, step S401 above may further include: in response to the first calculation precision being equal to the second calculation precision, using the adder and register of the addition module as the first adder and the first register, respectively. Since the first calculation precision is equal to the second calculation precision, there is no need to perform splitting or merging operations to adjust the calculation precision of the adder and the bit width of the register. The adder and register of the addition module can be directly used to reconstruct the first multiplication module that supports the second calculation precision.

[0064] For example, Figure 5A A schematic diagram of the structure of a first multiplication module provided in at least one embodiment of the present disclosure is shown.

[0065] like Figure 5A As shown, when the second calculation precision is N-bit integer (intN), where N=2n and n is a positive integer, the first multiplication module 500 includes N first adders 510~5N0 and N first registers Reg1~RegN. Each first adder includes N full adders coupled in a first cascade manner.

[0066] For example, the first multiplication module may also include a control unit configured to control the first adders 510~5N0 and the first registers Reg1~RegN to jointly implement the second calculation precision multiplication operation performed by the first multiplication module.

[0067] For example, when performing step S402 above, N first adders 510~5N0 are coupled to N first registers Reg1~RegN respectively, so that the first registers receive the second operation result obtained by the corresponding coupled first adders performing addition operations with a second calculation precision; the N first adders 510~5N0 are coupled in a second cascade manner, wherein the sum output of the 2nd to Nth full adders in the previous stage is coupled to the first input of the 1st to (N-1)th full adders in the next stage, and the carry output of the Nth full adder in the previous stage is coupled to the first input of the Nth full adder in the next stage. It should be noted that, in addition to the above second cascade manner, the first adders 510~5N0 can also be coupled in other cascade manners, and this disclosure does not limit this.

[0068] Figure 5B It shows Figure 5A A schematic diagram showing the first adder coupled in a second cascade configuration.

[0069] For example, when N=4, Figure 5A The first multiplication module 500 shown supports a calculation precision of int4. The first multiplication module 500 includes four first adders 510~540 and four first registers Reg1~Reg4. Figure 5B (not shown in the image), each first adder includes four full adders coupled in a first cascade manner.

[0070] For example, such as Figure 5B As shown, the first adder 510 includes full adders 5100-5103. The carry input and carry output terminals of the full adders 5100-5103 are coupled in a first cascade configuration. For details, please refer to the above description. Figure 3BThe description will not be repeated here. The four first adders 510~540 are respectively coupled to the four first registers Reg1~Reg4, so that each first register receives the second operation result obtained by the corresponding coupled first adder performing an addition operation with a second calculation precision. For example, the first register Reg1 is coupled to the first adder 510 to receive the sum data (e.g., Sum1_0~Sum1_3) output by the sum bit output terminals S0~S3 of the full adders 5100~5103 in the first adder 510, and the carry data (e.g., C1_3) output by the carry output terminal Cout3 of the full adder 5103. That is, the second operation result obtained by the first adder 510 is [C1_3, Sum1_3, Sum1_2, Sum1_1, Sum1_0]. Similarly, the first register Reg2 is coupled to the first adder 520 to receive the sum data (e.g., Sum2_0~Sum2_3) output from the sum output terminals S0~S3 of the full adders 5200~5203 in the first adder 520, and the carry data (e.g., C2_3) output from the carry output terminal Cout3 of the full adder 5203. The second operation result obtained by the first adder 520 is [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0].

[0071] To reconstruct the first multiplication module 500 with a computational precision of int4, the four first adders 510~540 also need to be coupled in a second cascade manner. For example... Figure 5BAs shown, the sum output terminals S1~S3 of the second to fourth full adders 5101~5103 in the first stage first adder 510 are respectively coupled to the first input terminals A0~A2 of the first to third full adders 5200~5202 in the second stage first adder 520. The carry output terminal Cout3 of the fourth full adder 5103 in the first stage first adder 510 is coupled to the first input terminal A3 of the fourth full adder 5203 in the second stage first adder 520. The sum output terminals S1~S3 of the second to fourth full adders 5201~5203 in the second-stage first adder 520 are respectively coupled to the first input terminals A0~A2 of the first to third full adders 5300~5302 in the third-stage first adder 530. The carry output terminal Cout3 of the fourth full adder 5203 in the second-stage first adder 520 is coupled to the first input terminal A3 of the fourth full adder 5303 in the third-stage first adder 530. The sum output terminals S1~S3 of the second to fourth full adders 5301~5303 in the third-stage first adder 530 are respectively coupled to the first input terminals A0~A2 of the first to third full adders 5400~5402 in the fourth-stage first adder 540. The carry output terminal Cout3 of the fourth full adder 5303 in the third-stage first adder 530 is coupled to the first input terminal A3 of the fourth full adder 5403 in the fourth-stage first adder 540.

[0072] The principle of the first multiplication module in performing multiplication on two binary data is as follows: the multiplicand (hereinafter referred to as the "first multiplier") is shifted successively, and then the value of each bit of the multiplier (hereinafter referred to as the "second multiplier") is used to determine whether to accumulate the shifted multiplicand, thereby obtaining the product of the two binary data.

[0073] For example, Figure 6 A schematic diagram of performing a multiplication operation on two binary data in at least one embodiment of the present disclosure is shown.

[0074] like Figure 6As shown, the first multiplier is 1011, the second multiplier is 1101, and the calculation precision is int4. This multiplication operation can be converted into three addition operations. Specifically, starting from the least significant bit of the second multiplier 1101, each bit of the second multiplier 1101 is multiplied by the first multiplier 1011, resulting in four multiplication results: [a3, a2, a1, a0] = [1, 0, 1, 1], [b3, b2, b1, b0] = [0, 0, 0, 0], [c3, c2, c1, c0] = [1, 0, 1, 1], and [d3, d2, d1, d0] = [1, 0, 1, 1]. Then, the result of each multiplication is shifted left by one bit, and finally, all the multiplication results are added together to obtain the multiplication result [1, 0, 0, 0, 1, 1, 1, 1]. Since the multiplication operation is performed on two binary data, the second multiplier consists of 0 and 1. The result of multiplying each bit of the second multiplier with the first multiplier is either the first multiplier or 0. That is, the four addends participating in the addition operation can be determined based on the value of each bit of the second multiplier.

[0075] It is important to note that in the example above, a multiplication operation with a precision of int4 is converted into three addition operations with a precision of int4, i.e., as shown... Figure 5A The first multiplication module 500 shown actually uses three first adders (e.g., adders 510-530) and three first registers Reg1-Reg3 when performing multiplication operations on the first multiplier 1011 and the second multiplier 1101. The remaining first adder 540 and first register Reg4 are temporarily idle.

[0076] For example, Figure 7 This diagram illustrates the setting of parameters for multiplication operations in the first multiplication module.

[0077] For example, when the first multiplication module performs a multiplication operation with a second computational precision (i.e., int4) on the first multiplier (e.g., 1011) and the second multiplier (e.g., 1101), the operation method of the addition module provided in at least one embodiment of this disclosure further includes: using the shifted first multiplier or the shifted preset addend as the first addend of the first-stage first adder according to the first bit data of the second multiplier; using the first multiplier or the preset addend as the second addend of the (i-1)th-stage first adder according to the i-th bit data of the second multiplier, where i = 2, 3, 4. Here, the preset addend is 4-bit binary data, which can be set to 0000.

[0078] For example, when the first multiplication module performs a multiplication operation with a second computational precision (i.e., int4) on the first multiplier (e.g., 1011) and the second multiplier (e.g., 1101), the carry data received by the carry input terminal Cin0 of the first full adder 5100-5300 in the first adder 510-530 can be set to 0, or it can be set to other values ​​according to the needs of the machine learning algorithm. This disclosure does not limit this.

[0079] like Figure 7 As shown, in response to the first bit of the second multiplier being 1, the shifted first multiplier is used as the first addend [a3, a2, a1, a0] of the first-stage first adder 510. Here, "shift operation" means arithmetically shifting the first multiplier 1011 one bit to the right, resulting in the shifted first multiplier 0101. At this time, the first addend [a3, a2, a1, a0] of the first-stage first adder 510 is [0, 1, 0, 1]. In response to the second bit of the second multiplier being 0, the preset addend 0000 is used as the second addend [b3, b2, b1, b0] of the first-stage first adder 510, that is, [b3, b2, b1, b0] = [0, 0, 0, 0]. Then, the first adder 510 of the first stage performs an addition operation on the first addend [a3, a2, a1, a0] and the second addend [b3, b2, b1, b0]. The first register Reg1, which is coupled to the first adder 510 of the first stage, receives and stores the result of the addition operation and the least significant bit data before the first multiplier shift (i.e., the rightmost "1" in "1011"). That is, the data stored in the first register Reg1 is [C1_3, Sum1_3, Sum1_2, Sum1_1, Sum1_0, 1].

[0080] like Figure 7As shown, in response to the third bit of the second multiplier being 1, the first multiplier 1011 is used as the second addend [c3, c2, c1, c0] of the second-stage first adder 520, i.e., [c3, c2, c1, c0] = [1, 0, 1, 1]. The second-stage first adder 520 performs an addition operation on the second addend [c3, c2, c1, c0] and the data received from the first-stage first adder 510 (i.e., [C1_3, Sum1_3, Sum1_2, Sum1_1]), and stores the result [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0] in the first register Reg2 coupled to the second-stage first adder 520. Furthermore, the first register Reg2 can also store the least significant bit data before the first multiplier shift (i.e., the rightmost "1" in "1011") and the sum data Sum1_0 output by the sum output terminal S1 of the full adder 5100. At this time, the data stored in the first register Reg2 is [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0, Sum1_0, 1].

[0081] like Figure 7As shown, in response to the 4th bit of the second multiplier being 1, the first multiplier 1011 is used as the second addend [d3, d2, d1, d0] of the third-stage first adder 530, i.e., [d3, d2, d1, d0] = [1, 0, 1, 1]. The third-stage first adder 530 performs addition on the second addend [d3, d2, d1, d0] and the data received from the second-stage first adder 520 (i.e., [C2_3, Sum2_3, Sum2_2, Sum2_1]), and stores the result [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0] in the first register Reg3 coupled to the third-stage first adder 530. Furthermore, the first register Reg3 can also store the least significant bit data before the first multiplier shift (i.e., the rightmost "1" in "1011"), the sum data Sum1_0 output by the sum output terminal S1 of the full adder 5100, and the sum data Sum2_0 output by the sum output terminal S1 of the full adder 5200. At this time, the data stored in the first register Reg3 is [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0, Sum2_0, Sum1_0, 1]. Therefore, the first multiplication module performs a multiplication operation with a second calculation precision (i.e., int4) on the first multiplier 1011 and the second multiplier 1101, and the resulting multiplication operation [M7, M6, M5, M4, M3, M2, M1, M0] is [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0, Sum2_0, Sum1_0, 1]=[1, 0, 0, 0, 1, 1,1, 1].

[0082] At least one embodiment of this disclosure also provides a multiply-adder, which includes the addition module (hereinafter referred to as "second addition module") provided in any of the above embodiments.

[0083] For example, Figure 8 A schematic diagram of the structure of a multiply-accumulator provided in at least one embodiment of the present disclosure is shown.

[0084] like Figure 8 As shown, the multiply-adder 800 includes multiple multiplication modules 810 (i.e., "second multiplication modules"), multiple addition modules 820 (i.e., "first addition modules"), and multiple addition modules 830 (i.e., "second addition modules," see, for example, [reference needed]). Figure 3A Each adder module 820 includes multiple adders arranged in a first-cascade manner (see, for example, see...). Figure 3B A full adder coupled in a first cascade manner. Each adder module 830 includes an adder, a register, and a control unit, and the adder includes multiple adders in a first cascade manner (see, for example, see...). Figure 3BA full adder coupled together. Each multiplication module 810 is configured to perform multiplication operations with a third computational precision, and each adder module 820 and each adder module 830 are configured to receive the multiplication results output by the corresponding coupled multiplication module 810 and perform addition operations with a first computational precision.

[0085] For example, the ratio of the number of multiplication modules 810, addition modules 820 and addition modules 830 in multiplier-adder 800 can be 2:1:1, and this disclosure does not limit this.

[0086] It is important to note that Figure 8 The connection method between the multiple multiplication modules 810, multiple addition modules 820 and multiple addition modules 830 shown is exemplary. This connection method can be modified according to actual needs, and this disclosure does not limit it.

[0087] At least one embodiment of this disclosure also provides a method for operating a multiply-accumulator, the multiply-accumulator being as follows: Figure 8 The multiply-accumulator 800 shown includes the following operation method: refactoring at least a portion of the second adder modules into second multiplyer modules and / or first adder modules to adjust the ratio of the number of second multiplyer modules, first adder modules, and second adder modules in the multiply-accumulator; and in response to the multiply-accumulator switching from a third computational precision to a second computational precision, refactoring a plurality of second multiplyer modules into at least one first multiplyer module, refactoring a plurality of first adder modules into at least one third adder module, and refactoring at least a portion of the second adder modules into at least one first multiplyer module, wherein the third adder module supports a fourth computational precision.

[0088] The above-mentioned operation method of the multiply-accumulator can switch and adjust the calculation precision of the multiply-accumulator and dynamically adjust the ratio of the number of multiplication modules and addition modules in the multiply-accumulator by reconstructing the first multiplication module, the first addition module and the second addition module. This is to adapt to the requirements of different machine learning algorithms for calculation precision and hardware resources (i.e., multiplication modules and addition modules) and improve the hardware resource utilization, calculation efficiency and flexibility of the multiply-accumulator.

[0089] The following example uses int4 as the third calculation precision, int8 as the first and second calculation precisions, and int16 as the fourth calculation precision, and combines them with... Figure 8 The multiply-accumulator 800 shown further illustrates the operation method of the aforementioned multiply-accumulator.

[0090] In this example, the second multiplication module (i.e., "multiplication module 810") has a computational precision of int4, and each second multiplication module includes four second adders supporting a third computational precision (i.e., int4) and four second registers. Each second register has a bit width of 8 bits (i.e., it can store 8 bits of data), and each second adder includes four full adders coupled in a first cascade manner. The first addition module (i.e., "addition module 820") has a computational precision of int8 and includes eight full adders coupled in a first cascade manner. The second addition module (i.e., "addition module 830") has a computational precision of int8 and includes a third adder and a third register. The third adder includes eight full adders coupled in a first cascade manner, and the third register has a bit width of 16 bits (i.e., it can store 16 bits of data). The third register is coupled to the third adder to receive the result of the first computational precision (i.e., int8) addition operation performed by the corresponding third adder. For example, the structure of the second multiplication module (i.e., "multiplication module 810") here can be referred to Figure 5A The structure of the first addition module (i.e., "addition module 820") can be referred to Figure 3B The adder 310 shown, and the second adder module (i.e., "adder module 830") can be referred to. Figure 3A .

[0091] For example, when refactoring multiple second multiplication modules (i.e., "multiplication modules 810", with a computational precision of int4) in multiply-adder 800 into at least one first multiplication module (with a computational precision of int8), every four second multiplication modules (e.g., the four multiplication modules 810 in dashed box G1) can be refactored into one first multiplication module. Specifically, the four multiplication modules 810 include a total of 16 second adders with a computational precision of int4 and 16 second registers with a bit width of 8 bits. The 16 second adders are combined into eight first adders with a computational precision of int8, and the 16 second registers are combined into eight first registers with a bit width of 16 bits. Then, the resulting eight first adders are coupled to the eight first registers respectively, so that each first register receives the result of the addition operation with the second computational precision performed by the corresponding coupled first adder. Finally, the eight first adders are coupled in a second cascade configuration. The sum outputs of the second to eighth full adders in the previous stage are coupled to the first inputs of the first to seventh full adders in the next stage, respectively. The carry output of the eighth full adder in the previous stage is coupled to the first input of the eighth full adder in the next stage. Specifically, the connection method between the eight first adders and the eight first registers can be referred to the above. Figure 5B The description will not be repeated here.

[0092] For example, when refactoring multiple first adder modules (i.e., "adder module 820", with a computational precision of int8) in multiply-adder 800 into at least one third adder module (with a computational precision of int16), every two first adder modules (e.g., the two adder modules 820 in dashed box G2) can be combined into one third adder module. This third adder module includes eight full adders coupled in a first cascade manner, as can be seen in [reference needed]. Figure 3B Adder 310 in the middle.

[0093] For example, when refactoring at least a portion of the second adder modules (i.e., "adder module 830", with a computational precision of int8) into at least one first multiplication module (with a computational precision of int8), every eight second adder modules (e.g., the eight adder modules 830 in dashed box G3_1) can be merged into one first multiplication module. Specifically, the eight adder modules 830 in dashed box G3_1 include eight third adders with a computational precision of int8 and eight third registers with a bit width of 16 bits, wherein the eight third registers are coupled to the eight third adders respectively. Therefore, the eight third adders also need to be coupled in a second cascade configuration. Specifically, the sum outputs of the second to eighth full adders in the previous stage are coupled to the first inputs of the first to seventh full adders in the next stage, and the carry output of the eighth full adder in the previous stage is coupled to the first input of the eighth full adder in the next stage. The connection method between the eight third adders and the eight third registers can be referenced as described above. Figure 5B The description will not be repeated here.

[0094] In addition, every two second addition modules (e.g., the two addition modules 830 in dashed box G4) can be merged into one third addition module. The merging method can refer to the above method of merging the two addition modules 820 in dashed box G2 into one third addition module, which will not be repeated here.

[0095] For example, such as Figure 8As shown, the multiply-accumulator 800 includes 48 multiplication modules 810, 24 first addition modules 820, and 24 second addition modules 830, with a multiplication module to addition module ratio of 2:1. In response to the multiply-accumulator 800 switching its computational precision from int4 to int8, following the aforementioned operation method, the 48 multiplication modules 810 with int4 precision can be reconstructed into 12 first multiplication modules with int8 precision, the 24 first addition modules 820 with int8 precision can be reconstructed into 12 third addition modules with int16 precision, and the 24 second addition modules 830 with int8 precision can be reconstructed into 3 first multiplication modules with int8 precision (corresponding to dashed boxes G3_1~G3_3). At this point, the multiply-accumulator obtained based on the reconstruction operation includes 15 first multiplication modules and 12 third addition modules, with a multiplication module to addition module ratio of 5:4.

[0096] In another example, the 24 second adder modules 830 with a calculation precision of int8 can be reconstructed into 2 first multiplication modules with a calculation precision of int8 and 2 third adder modules with a calculation precision of int16. In this case, the multiply-adder obtained based on the reconstruction operation includes 14 first multiplication modules and 14 third adder modules, with a ratio of 1:1 between the number of multiplication modules and the number of adder modules.

[0097] Furthermore, when configuring the multiply-accumulator provided in at least one embodiment of this disclosure, the first addition module (e.g.) can be used. Figure 8 Replace all instances of "Adder Module 820" with the second adder module (e.g., ...). Figure 8 The "second addition module" is dynamically adjusted within the ratio of the number of multiplication modules to the number of addition modules in the multiply-adder, but this disclosure does not limit this range.

[0098] In at least one embodiment of this disclosure, if the machine learning algorithm has a large demand for addition modules, for example, the second multiplication module (i.e., "multiplication module 810") with a calculation precision of int4 in one multiply-accumulator 800 can be split into four addition modules with a calculation precision of int4, and then these four addition modules with a calculation precision of int4 can be reconstructed into two second addition modules with a calculation precision of int8 (i.e., "addition module 830").

[0099] It should be noted that the specific calculation precision mentioned in the embodiments of this disclosure, such as the first and second calculation precisions being int8, the third calculation precision being int4, and the fourth calculation precision being int16, are only illustrative. These calculation precisions can also be int4, int8, int16, int32, etc., and users can set them according to their actual needs. This disclosure does not impose any restrictions on this.

[0100] Based on the addition module provided in this embodiment, by reorganizing multiple addition modules into a multiplication module and / or an addition module, the ratio of the number of multiplication modules and addition modules in the multiply-accumulator and their respective calculation precision can be flexibly changed, thereby better adapting to the needs of various machine learning algorithms and calculation precision requirements, and maximizing the utilization of the multiply-accumulator hardware resources.

[0101] At least one embodiment of this disclosure also provides a processor, which includes the multiply-accumulator provided in any of the above embodiments. The processor may be, for example, a central processing unit (CPU) or a coprocessor, and the coprocessor may be, for example, a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), an AI accelerator (e.g., a tensor processor), etc., and the embodiments of this disclosure do not limit this; furthermore, the embodiments of this disclosure do not limit the specific architecture of the processor, the applicable instruction set, etc.

[0102] One or more embodiments of this disclosure also provide an electronic device that includes the processor provided in any of the above embodiments.

[0103] For example, Figure 9 A schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0104] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers, and may also be used to implement various types of servers.

[0105] For example, such as Figure 9 As shown, in some examples, electronic device 900 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which may include a multiply-accumulator provided in at least one embodiment of this disclosure. The processing device 901 can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 902 or a program loaded from storage device 908 into random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the computer system. The processing device 901, ROM 902, and RAM 903 are connected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0106] For example, the following components can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909, such as network interface cards like LAN cards and modems, etc. Communication device 909 allows electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 910 is also connected to I / O interface 905 as needed. Removable media 911, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 910 as needed so that computer programs read from them can be installed into storage device 908 as needed. Although Figure 9 An electronic device 900 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0107] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 909 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0108] In addition to the illustrative examples described above, the following points also need to be noted:

[0109] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0110] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0111] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An addition module, comprising: An adder is configured to perform addition operations with a first computational precision to obtain a first result. A register, coupled to the adder, is configured to receive the first operation result obtained by the adder; A control unit, coupled to the register and the adder respectively, is configured to control the register and the adder to perform a reconfiguration operation to obtain a first multiplication module that supports a second computational precision; The adder includes multiple full adders, each of which includes a first input terminal, a second input terminal, a carry input terminal, a sum output terminal, and a carry output terminal. The plurality of full adders are coupled in a first cascade configuration, with the carry output of the previous full adder coupled to the carry input of the next full adder. The first input of the plurality of full adders is configured to receive a first addend, the second input of the plurality of full adders is configured to receive a second addend, the sum output of the plurality of full adders is configured to output the sum data, the carry output of the previous full adder is configured to output the carry data as the input data of the carry input of the next full adder, and the carry output of the last full adder in the plurality of full adders is configured to output the final carry data. The first operation result includes the plurality of sum data and the final carry data.

2. A method for operating the addition module according to claim 1, comprising: The adder and the register of the addition module are split or merged to obtain at least one first adder and at least one first register, wherein the first adder supports the second calculation precision; The connection configuration of the at least one first adder and the at least one first register is reconfigured to obtain the first multiplication module.

3. The operating method according to claim 2, wherein, The step of splitting or merging the adder and register of the addition module to obtain at least one first adder and at least one first register includes: In response to the first calculation precision being higher than the second calculation precision, the multiple full adders in the adder of the addition module are split into at least two groups, each group of full adders is coupled in the first cascade manner to obtain the first adder, and the register of the addition module is split into at least two first registers; In response to the first calculation precision being lower than the second calculation precision, the adders of at least two addition modules are merged into the first adder, and the registers of the at least two addition modules are merged into the first register; In response to the first calculation precision being equal to the second calculation precision, the adder and the register of the addition module are respectively used as the first adder and the first register.

4. The operating method according to claim 3, wherein, The at least two addition modules include a first addition module and a second addition module, and the step of merging the adders of the at least two addition modules into the first adder includes: The carry-out terminal of the last full adder in the first adder module is coupled to the carry-in terminal of the first full adder in the second adder module to obtain the first adder.

5. The operating method according to claim 3, wherein, The second calculation precision is N-bit integer. The first multiplication module includes N first adders and N first registers. Each first adder includes N full adders coupled in the first cascaded manner, where N=2. n n is a positive integer. The reconfiguration of the connection between the at least one first adder and the at least one first register to obtain the first multiplication module includes: N first adders are coupled to N first registers respectively, so that the first registers receive the second operation result obtained by the corresponding coupled first adders performing addition operations with the second calculation precision; N first adders are coupled in a second cascade manner, wherein the sum output of the 2nd to Nth full adders in the previous stage is coupled to the first input of the 1st to (N-1)th full adders in the next stage, and the carry output of the Nth full adder in the previous stage is coupled to the first input of the Nth full adder in the next stage.

6. The operating method according to claim 5, wherein, The first multiplication module performs a multiplication operation with the second calculation precision on the first multiplier and the second multiplier, wherein the first multiplier and the second multiplier each include N bits of data, and the operation method further includes: Based on the first bit data of the second multiplier, the shifted first multiplier or the shifted preset addend is used as the first addend of the first stage first adder; Based on the i-th bit data of the second multiplier, the first multiplier or the preset addend is used as the second addend of the (i-1)-th stage first adder, where i = 2, 3, ..., N.

7. The operating method according to claim 6, wherein, The step of using the shifted first multiplier or the shifted preset addend as the first addend of the first-stage first adder based on the first bit data of the second multiplier includes: In response to the first bit of the second multiplier being 1, the shifted first multiplier is used as the first addend of the first stage first adder, and In response to the first bit of the second multiplier being 0, the shifted preset addend is used as the first addend of the first stage first adder.

8. The operating method according to claim 6, wherein, The step of using the first multiplier or a preset addend as the second addend of the (i-1)th stage first adder based on the i-th bit data of the second multiplier includes: In response to the i-th bit of the second multiplier being 1, the first multiplier is used as the second addend of the (i-1)-th stage first adder. In response to the i-th bit of the second multiplier being 0, the preset addend is used as the second addend of the (i-1)-th stage first adder.

9. A multiply-accumulate unit, comprising: Multiple second multiplication modules, multiple first addition modules, and multiple second addition modules, wherein, The second addition module is the addition module according to claim 1. The first addition module includes multiple full adders coupled in the first cascaded manner. The second multiplication module is configured to perform multiplication operations with a third computational precision. The first addition module and the second addition module are configured to receive the multiplication result output by the correspondingly coupled second multiplication module and perform an addition operation with the first calculation precision.

10. A method of operating the multiply-accumulator according to claim 9, comprising: At least a portion of the second adder modules are reconstructed into the second multiplication module and / or the first adder module to adjust the ratio of the number of the second multiplication module, the first adder module, and the second adder module in the multiply-adder; or In response to the multiply-accumulator switching from the third calculation precision to the second calculation precision, the plurality of second multiplication modules are reconstructed into at least one first multiplication module, the plurality of first addition modules are reconstructed into at least one third addition module, and at least some of the second addition modules are reconstructed into the at least one first multiplication module, wherein the third addition module supports a fourth calculation precision.

11. The operating method according to claim 10, wherein, The third calculation precision is int4, the first and second calculation precisions are int8, and the fourth calculation precision is int16; The second multiplication module includes four second adders supporting the third calculation precision and four second registers. The second registers have a bit width of 8 bits. The second adders include four full adders coupled in the first cascaded manner. The first addition module includes eight full adders coupled in the first cascaded manner. The second addition module includes a third adder and a third register. The third adder includes the eight full adders coupled in the first cascaded manner. The third register has a bit width of 16 bits. The third register is coupled to the third adder to receive the operation result obtained by the corresponding third adder performing the addition operation with the first calculation precision.

12. The operating method according to claim 11, wherein, The step of reconstructing the plurality of second multiplication modules into at least one first multiplication module includes: The second adder and the second register in every four second multiplication modules are merged into eight first adders and eight first registers, respectively, to reconstruct the first multiplication module. The first adder supports the second calculation precision, and the first register has a bit width of 16 bits. The eight first adders are respectively coupled to the eight first registers, so that each first register receives the calculation result obtained by the corresponding coupled first adder performing the addition operation with the second calculation precision; The eight first adders are coupled in a second cascade configuration, wherein the sum output of the second to eighth full adders in the previous stage is coupled to the first input of the first to seventh full adders in the next stage, and the carry output of the eighth full adder in the previous stage is coupled to the first input of the eighth full adder in the next stage.

13. The operating method according to claim 11, wherein, The step of reconstructing the plurality of first addition modules into at least one third addition module includes: Every two of the first addition modules are combined into the third addition module, wherein the third addition module includes the eight full adders coupled in the first cascade manner.

14. The operating method according to claim 11, wherein, The step of reconstructing at least a portion of the second addition module into at least one first multiplication module includes: The third adders of every eight second adder modules in the plurality of second adder modules are coupled in a second cascade manner. In this circuit, the sum output terminals of the 2nd to 8th full adders in the previous stage third adder are respectively coupled to the first input terminals of the 1st to 7th full adders in the next stage third adder, and the carry output terminal of the 8th full adder in the previous stage third adder is coupled to the first input terminal of the 8th full adder in the next stage third adder.

15. A processor, comprising: The multiply-accumulator as described in claim 9.

16. An electronic device comprising the processor as claimed in claim 15.

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