Optimization method for basic arithmetic operation of large number

Abstract

The invention provides an optimization method for basic arithmetic of large numbers, and belongs to the technical field of computers. The method comprises the following steps: identifying the digit length of two pieces of data to be operated, and combining operation types to obtain the data reference length under each operation type; in response to the fact that the data reference length is smaller than 64 bits, the data address attribute is processed to meet the natural pair-bound attribute of the scalar memory access instruction, and operation is carried out through a scalar operation instruction; in response to the fact that the data reference length is larger than or equal to 64 bits, data address attributes are processed to meet natural pair-bound attributes of a vector memory access instruction, and operation is carried out through a vector operation instruction and an operation optimization strategy; wherein the operation optimization strategy comprises an addition and subtraction optimization strategy, a multiplication optimization strategy and a division optimization strategy. According to the method, under the condition that the data length exceeds the scalar instruction processing range, the data size of single operation is increased through the vector instruction, the total number of instructions is reduced, the number of loop iterations is reduced, and therefore the overhead of instruction scheduling and execution is reduced.

Description

Technical Field

[0001] The invention relates to an optimization method for large number basic four arithmetic operations, belonging to the technical field of computers. Background Art

[0002] Big number operations play a vital role in modern computing technology, and their application areas include cryptography, big data, scientific research, and engineering. In these fields, the accuracy and efficiency of big number operations directly affect the performance and security of the system.

[0003] At present, there are many ways to implement large number operations. One of the methods is to use arrays to perform large number operations, decompose the large number into array units, perform bit-by-bit operations on each part (the length of each part does not exceed the range of standard data type representation), and then merge them to get the operation result. During this period, detailed issues such as carry need to be handled. Another method is to simulate large number operations through scalar operation combinations within the range of standard data type representation, use scalar operation instructions, combine vertical calculation simulation, carry management, divide and conquer method and other operation strategies, to achieve the simulation of large number operations and obtain the operation result.

[0004] However, the above methods mainly consider common operation strategies and scalar instructions within the range of standard data types, and fail to make full use of a wide range of data lengths for optimization. Therefore, the existing large number operation methods cannot accurately and efficiently operate on data of different lengths when the length range of the data to be operated is wide. This limitation is reflected in the following aspects:

[0005] 1. The implementation of large number operations simulates vertical operations, which is a bit-by-bit operation method. This method causes the operation time to increase linearly with the number of bits of the data. When the data to be operated is large, bit-by-bit processing will take a lot of time and it is difficult to meet the requirements of efficient calculation;

[0006] 2. When the data to be calculated is large, the overhead of looping and judgment is large and the calculation efficiency is low;

[0007] 3. The current large number calculation methods use the same calculation strategy for data of different lengths, which cannot achieve the optimization of calculation efficiency and accuracy.

[0008] In summary, the current computing strategy for large number operations has a large overhead, the optimization methods are relatively simple, and they fail to optimize for different data lengths, resulting in poor performance benefits. Summary of the invention

[0009] The purpose of the present invention is to overcome the deficiencies in the prior art and provide an optimization method for the basic four arithmetic operations of large numbers, which adopts vector instructions combined with operation optimization strategies under various operation types to reduce the total number of instructions and improve the operation efficiency of large number operations.

[0010] To achieve the above object, the present invention is implemented by adopting the following technical solutions:

[0011] The present invention provides an optimization method for basic four arithmetic operations of large numbers, comprising:

[0012] Identify the digit lengths of two data to be operated, and obtain the data reference length under each operation type in combination with the operation type;

[0013] In response to the data reference length being smaller than the processing word length of the scalar instruction, processing the data address attribute to satisfy the natural boundary attribute of the scalar memory access instruction, and performing the operation through the scalar operation instruction;

[0014] In response to the data reference length being greater than or equal to the processing word length of the scalar instruction, processing the data address attribute to satisfy the natural boundary attribute of the vector memory access instruction, and performing the operation through the vector operation instruction and the operation optimization strategy;

[0015] Wherein, the operation types include: addition, subtraction, multiplication and division operations;

[0016] The operation optimization strategy includes: addition and subtraction optimization strategy, multiplication optimization strategy and division optimization strategy.

[0017] Further, the combining operation types to obtain the data reference length under each operation type includes:

[0018] In response to the two data to be operated being equal, one of the data to be operated is used as the first operand, and the other data to be operated is used as the second operand,

[0019] In response to the two data to be operated being unequal, the smaller data to be operated is used as a first operand, and the larger data to be operated is used as a second operand;

[0020] In response to an addition or subtraction operation, the digit length of the first operand is used as a data reference length,

[0021] In response to a multiplication or division operation, the digit length of the second operand is used as a data reference length.

[0022] Furthermore, the addition and subtraction optimization strategy includes:

[0023] Set the first threshold according to the processing word length of the vector instruction ;

[0024] In response to the data reference length being less than a first threshold , use vector memory access instructions to read the first operand and the low-order bits of the second operand bits, and completes the operation through vector operation instructions;

[0025] In response to the data reference length being greater than or equal to a first threshold , execute S11 to S15;

[0026] S11: The first operand is divided into blocks starting from the lowest bit, and the blocks; among them, , where is the data reference length; It is the rounding operation;

[0027] S12: Divide the second operand into blocks starting from the lowest bit and take out the low bits. The blocks are calculated with the first operand;

[0028] S13: According to the principle of least significant bit alignment, the aligned blocks in the two operands are set as a group of operation blocks to obtain Group operation block;

[0029] S14: cyclically calculating each group of operation blocks through vector operation instructions in order from low to high bits; wherein each cyclic calculation includes: cyclically reading a group of operation block data using vector memory access instructions, and calculating the operation block through vector operation instructions, completing carry / borrow within the block, and obtaining a corresponding calculation result;

[0030] S15: After the cycle calculation is completed, The calculation results within the block of the group operation block and the remaining blocks in the second operand are concatenated in sequence, and carry / borrow are processed uniformly to obtain the final calculation result.

[0031] Furthermore, the addition and subtraction optimization strategy also includes: determining the number of loop unrolling times according to the processor cache line size and the processing length of the vector instruction ; In response to , then between S13 and S14, there is also: in order from low to high, each The group operation block is a loop body, and S14 is executed in each loop body to complete n loop unrollings.

[0032] Furthermore, the first threshold is 256, the number of loop unrolling is 4.

[0033] Furthermore, the multiplication optimization strategy includes:

[0034] Set the second threshold according to the processing word length of the vector instruction ;

[0035] In response to the data reference length being less than or equal to a second threshold , use vector memory access instructions to read two operands, and complete the operation through vector operation instructions;

[0036] In response to the data reference length being greater than a second threshold , execute S21 to S24;

[0037] S21: The first operand is obtained by dividing the two operands into units starting from the lowest bit. Units , the second operand is obtained Units ;

[0038] S22: Combine each unit in the first operand with each unit in the second operand to form operation pairs; S23: looping and calculating each operation pair through the vector operation instruction, wherein each loop calculation includes:

[0039] Use the vector memory access instruction loop to read the data of an operation pair, and record the data of the two units in the operation pair as and ;

[0040] Completed through vector operation instructions and The compound calculation is performed to obtain the calculation result of the operation pair; wherein the compound calculation includes:

[0041] Respectively and Divided into low and high parts, expressed as:

[0042] ;

[0043] ;

[0044] in, is the cardinality, yes Medium to high bit data, yes Low to medium bit data, yes Medium to high bit data, yes Low to medium Bit data;

[0045] calculate As the calculation result of the operation pair;

[0046] S24: After the cycle calculation is completed, The calculation results of the operation pairs are concatenated to obtain the final product.

[0047] Furthermore, the number of loop unrolling is set to 4; the multiplication optimization strategy also includes: in response to , S22 and S23 also include: the first operand And the second operation Constitute a loop body, each loop body contains , , and 4 operation pairs; among them, is the data reference length, ; This is a round-down operation; S23 is executed in each loop body to complete 4 loop unrollings.

[0048] Furthermore, the second threshold is 128.

[0049] Further, the division optimization strategy includes: optimizing the division operation whose divisor digit length is not greater than the vector instruction processing word length through a simulation algorithm;

[0050] The simulation algorithm includes:

[0051] Let the dividend be , whose digit length is recorded as , the divisor is written as , whose digit length is recorded as ;

[0052] In response to , then the quotient of the division operation is 0 and the remainder is ;

[0053] In response to , execute S31 to S35;

[0054] S31: Use vector memory access instructions to read from the highest bit of the current dividend bit data, denoted as ,

[0055] In response to , read from the highest bit of the current dividend bit data,

[0056] In response to a successful read, update , jump to S32;

[0057] In response to a read failure, the quotient of the current cycle is 0 and the remainder is , jump to S35;

[0058] S32: Remove the current dividend from the The remaining part of , whose digit length is recorded as , jump to S33;

[0059] S33: Complete the current operation through vector operation instructions and Simulate the operation to obtain the quotient and remainder of the current loop, and jump to S34;

[0060] S34: The remainder of the current loop and the remaining part Combine into a new dividend, update and ;

[0061] In response to , jump to S35 to end the loop calculation;

[0062] In response to , then jump to S31 to perform the next cycle calculation;

[0063] S35: concatenate the quotient values ​​calculated in each cycle to obtain the quotient of the division operation, and the current remainder is the remainder of the division operation.

[0064] Furthermore, the simulation operation includes: solving of value; As the quotient value of the current cycle, as the remainder of the current loop.

[0065] Compared with the prior art, the present invention has the following beneficial effects: (1) The optimization method for the basic four arithmetic operations of large numbers provided by the present invention realizes a combined operation mode by combining vector instructions on the basis of using scalar instructions. When the data length exceeds the processing range of scalar instructions, the amount of data for a single operation is increased through vector instructions, the total number of instructions is reduced, and the number of loop iterations is reduced, thereby reducing the overhead of instruction scheduling and execution; (2) The optimization method for the basic four arithmetic operations of large numbers provided by the present invention optimizes the process of the basic four arithmetic operations of large numbers through the operation optimization strategy, uses the block carry / borrow strategy to independently process the addition and subtraction operations of each block, reduces the length of the carry / borrow chain, and improves the operation efficiency of large number addition and subtraction; uses the composite algorithm strategy to reduce the time complexity of large number multiplication operations; uses the simulation operation strategy to reduce the complexity of large number division operations and reduce error accumulation; (3) The optimization method for the basic four arithmetic operations of large numbers provided by the present invention adopts loop unrolling technology to reduce the number of loop iterations in large number addition, subtraction and multiplication operations, thereby improving the parallelism and operation efficiency of large number operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a schematic flow chart of the optimization method for the basic four arithmetic operations of large numbers in Embodiment 1 of the present invention; Figure 2 This is an optimized flow chart of large number addition operation in Embodiment 2 of the present invention; Figure 3 It is an optimized flow chart of large number subtraction operation in embodiment 2 of the present invention; Figure 4 This is an optimized flow chart of large number multiplication operation in embodiment 4 of the present invention. DETAILED DESCRIPTION

[0067] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0068] Example 1

[0069] This embodiment provides an optimization method for the four basic arithmetic operations of large numbers, such as Figure 1 As shown, including:

[0070] Identify the digit lengths of two data to be operated, and obtain the data reference length under each operation type in combination with the operation type.

[0071] The operation types mentioned here refer to the four basic arithmetic operations of addition, subtraction, multiplication and division.

[0072] Specifically, if two data to be calculated are equal, the two data to be calculated are randomly recorded as the first operand and the second operand; if the two data to be calculated are not equal, the smaller data to be calculated is recorded as the first operand, and the larger data to be calculated is recorded as the second operand.

[0073] For addition or subtraction operations, the smaller data length, that is, the digit length of the first operand, is used as the data reference length. For multiplication or division operations, the larger data length, that is, the digit length of the second operand, is used as the data reference length.

[0074] As is known, a scalar instruction can process 8 bytes (64 bits) of data at a time, and a vector instruction can process 32 bytes (256 bits) of data at a time.

[0075] A comparison is made between the specific value of the data reference length and the processing word length (64 bits) of the scalar instruction. If the data reference length is smaller than the processing word length (64 bits) of the scalar instruction, it means that the operation data is small and scalar instructions can be used for memory access and operation. Specifically, the data address attributes are processed to satisfy the natural bound attributes of the scalar memory access instruction, and the operation is performed through the scalar operation instruction.

[0076] However, if the data reference length is greater than or equal to the processing word length of the scalar instruction (64 bits), vector instructions that can process more data are used for memory access and operation, including: processing the data address attributes to meet the natural boundary attributes of the vector memory access instruction, and performing operations through vector operation instructions and operation optimization strategies. Among them, the operation optimization strategies include: addition and subtraction optimization strategy, multiplication optimization strategy and division optimization strategy.

[0077] This method flexibly matches scalar instructions or vector instructions for memory access and operation according to the data length of the operands to maximize the operation efficiency, especially for large number operations. Through vector operation instructions and operation optimization strategies under each operation type, the total number of instructions and the number of loop iterations are reduced, thereby reducing the overhead of loop control.

[0078] Example 2

[0079] Based on Example 1, this embodiment provides specific content of the addition and subtraction optimization strategy for the case where the data reference length is greater than or equal to 64 bits.

[0080] First, set the first threshold according to the vector instruction processing word length .

[0081] In a specific embodiment, the first threshold The same as the vector instruction processing word length, which is 256.

[0082] like Figure 2 and Figure 3 As shown, if the data reference length is less than 256 bits, that is, the first operand is less than 256 bits, a vector memory access instruction is used to read the first operand and the low bits of the second operand. bits, and completes the operation through a vector operation instruction and ends.

[0083] If the data reference length is greater than or equal to 256 bits, the addition and subtraction operations are optimized through vector operations and delayed carry / borrow combined with loop unrolling, specifically including S11 to S15:

[0084] S11: Divide the first operand into blocks starting from the lowest bit with 256 bits as one block, and obtain blocks; among them, , where is the data reference length; It is the rounding operation;

[0085] S12: Divide the second operand into blocks starting from the lowest bit and take out the low bits. The blocks are calculated with the first operand;

[0086] S13: According to the principle of least significant bit alignment, the aligned blocks in the two operands are set as a group of operation blocks to obtain Group operation block;

[0087] S14: Calculate each group of operation blocks in a loop through vector operation instructions in order from low to high; wherein each loop calculation includes: using vector memory access instructions to cyclically read a group of operation block data, and calculating the operation blocks through vector operation instructions, completing carry / borrow within the block, and obtaining the corresponding calculation result.

[0088] S15: After the cycle calculation is completed, The calculation results within the block of the group operation block and the remaining blocks in the second operand are concatenated in sequence, and carry / borrow are processed uniformly to obtain the final calculation result.

[0089] If the number of operation blocks Greater than the preset number of loop unrolls , then in order from low to high, each The group operation block is a loop body, and S14 is executed in each loop body to complete n loop unrollings.

[0090] In a specific embodiment, the number of loop unrolling times It is 4, which is determined by the processor cache line size and the processing length of the vector instruction.

[0091] Example 3

[0092] Based on Example 2, this example provides a detailed process for optimizing the operation of adding a 2176-bit large number to a 1152-bit large number through vector operation instructions and addition and subtraction optimization strategies.

[0093] In this addition operation, the 1152-bit large number is the first operand, the 2176-bit large number is the second operand, and the data reference length is 1152 bits. The data reference length is much larger than the first threshold of 256 bits. Therefore, the 1152-bit first operand is divided into blocks starting from the lowest bit, with 256 bits as a block, to obtain 5 blocks. ,in Both are 256 bits, is 128 bits.

[0094] Then, with 256 bits as a block, the 2176-bit second operand is divided into blocks starting from the lowest bit to obtain 9 blocks. ,in Both are 256 bits, is 128 bits.

[0095] Take the low-order 5 blocks from the second operand , according to the principle of least significant bit alignment, respectively with the first operand Consists of 5 groups of operation blocks.

[0096] Then, use the vector memory access instruction to read each group of operation block data in turn, and perform loop calculations through the vector operation instructions. When calculating, each group of operation blocks first completes the carry / borrow within the block to obtain the corresponding 5 block calculation results.

[0097] After the five groups of operation blocks have completed the calculation within the block, the calculation results within the five blocks and the remaining four blocks in the second operand are The data are concatenated in order from low to high, and carry / borrow are processed uniformly to obtain the final calculation result.

[0098] Example 4

[0099] Based on Example 1, this example provides specific content of the multiplication optimization strategy for the case where the data reference length is greater than or equal to 64 bits.

[0100] First, set the second threshold according to the vector instruction processing word length .

[0101] In a specific embodiment, the second threshold It is 1 / 2 of the word length of vector instructions, which is 128.

[0102] like Figure 4 As shown, if the data reference length is less than or equal to 128 bits, that is, both multipliers are less than or equal to 128 bits, a vector memory access instruction is used to read the two operands, and the operation is completed and ended through a vector operation instruction.

[0103] If the data reference length is greater than 128 bits, that is, at least one multiplier exceeds 128 bits, vector operations and compound calculations are used in combination with loop unrolling to optimize the addition and subtraction operations, including S21 to S24:

[0104] S21: Taking 256 bits as a unit, divide the two operands into units starting from the lowest bit, and obtain the first operand Units , the second operand is obtained Units ;

[0105] S22: Combine each unit in the first operand with each unit in the second operand to form operation pairs; S23: looping and calculating each operation pair through the vector operation instruction, wherein each loop calculation includes:

[0106] Use the vector memory access instruction loop to read the data of an operation pair, and record the data of the two units in the operation pair as and ;

[0107] Completed through vector operation instructions and The compound calculation is performed to obtain the calculation result of the operation pair; wherein the compound calculation includes:

[0108] Respectively and Divided into low and high parts, expressed as:

[0109] ;

[0110] ;

[0111] in, is the cardinality, yes Medium to high bit data, yes Low to medium bit data, yes Medium to high bit data, yes Low to medium Bit data;

[0112] calculate As the calculation result of the operation pair;

[0113] S24: After the cycle calculation is completed, The calculation results of the operation pairs are concatenated to obtain the final product.

[0114] In a specific embodiment, when the data reference length , that is, 512 bits, and between S22 and S23 also includes:

[0115] The first operand And the second operation Constitute a loop body, each loop body contains , , and 4 operation pairs; among them, for ; This is a floor operation.

[0116] That is, every two cells in the first operand form a cell group, and every two cells in the second operand also form a cell group, and then each cell group in the first operand and each cell group in the second operand in turn form a corresponding loop body.

[0117] S23 is executed in each loop body, completing four loop unrollings.

[0118] Example 5

[0119] Based on Example 4, this example provides a detailed process for optimizing the multiplication of a 1728-bit large number by a 1216-bit large number through vector operation instructions and multiplication optimization strategies.

[0120] In this multiplication operation, the 1216-bit large number is the first operand, the 1728-bit large number is the second operand, and the data reference length is 1728 bits, which is much larger than the second threshold value of 128 bits.

[0121] The two operands are divided into units starting from the lowest bit, with 256 bits as a block. The first operand of 1216 bits obtains 5 units. , Both are 256 bits, 192 bits; the 1728-bit second operand gets 7 units , Both are 256 bits, It is 192 bits.

[0122] Each unit in the first operand is combined with each unit in the second operand into 35 operation pairs, which are: , , , , , , , , , .

[0123] The vector operation instruction loop calculates each operation pair and obtains the calculation results of 35 operation pairs. Take the following as an example to explain the calculation process of each cycle.

[0124] Use vector memory access instructions to read in a loop Operate the data on the pair and Recorded as , Recorded as ;

[0125] Completed through vector operation instructions and The composite calculation includes: It is expressed as:

[0126] ;

[0127] ;

[0128] in, is the cardinality, yes The 128-bit data in the middle and high order, yes The low-order 128-bit data, yes The 128-bit data in the middle and high order, yes The low-mid 128-bit data;

[0129] calculate As The result of the operation pair.

[0130] It should be noted that It is determined by the base of the two operands. If the two operands are binary numbers, then is 2. If both operands are decimal numbers, then It's 10.

[0131] refer to , completing the compound calculation of 35 operation pairs. Among them, it should be noted that for the 192-bit and , represented by the low-order 128-bit data and the high-order 64-bit data.

[0132] Example 6

[0133] Based on Example 1, this example provides specific content of the division optimization strategy for the case where the data reference length is greater than or equal to 64 bits.

[0134] It should be noted that the division optimization strategy includes: optimizing the division operation with the divisor digit length not greater than the vector instruction processing word length (256 bits) through a simulation algorithm. In other words, the division optimization strategy is only applicable to the division operation with the divisor digit length not greater than 256 bits.

[0135] The simulation algorithm includes: writing the dividend as , whose digit length is recorded as , the divisor is written as , whose digit length is recorded as ;

[0136] If the dividend is less than the divisor, , then the quotient of the division operation is 0 and the remainder is ;

[0137] If the dividend is not less than the divisor, that is , optimizing the division operation through vector operation and simulation algorithm, specifically including: S31 to S35;

[0138] S31: Use vector memory access instructions to read from the highest bit of the current dividend bit data, denoted as ,

[0139] In response to , read from the highest bit of the current dividend bit data,

[0140] In response to a successful read, update , jump to S32;

[0141] In response to a read failure, the quotient of the current cycle is 0 and the remainder is , jump to S35;

[0142] S32: Remove the current dividend from the The remaining part of , whose digit length is recorded as , jump to S33;

[0143] S33: Complete the current operation through vector operation instructions and Simulate the operation to obtain the quotient and remainder of the current loop, and jump to S34;

[0144] S34: The remainder of the current loop and the remaining part Combine into a new dividend, update and ;

[0145] In response to , jump to S35 to end the loop calculation;

[0146] In response to , then jump to S31 to perform the next cycle calculation;

[0147] S35: concatenate the quotient values ​​calculated in each cycle to obtain the quotient of the division operation, and the current remainder is the remainder of the division operation.

[0148] In a specific embodiment, the simulation operation includes: solving a problem satisfying of value; As the quotient value of the current cycle, as the remainder of the current loop.

[0149] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An optimization method for basic arithmetic operations of large numbers, characterized in that: include: Identify the digit lengths of two data to be operated, and obtain the data reference length under each operation type in combination with the operation type; In response to the data reference length being smaller than the processing word length of the scalar instruction, processing the data address attribute to satisfy the natural boundary attribute of the scalar memory access instruction, and performing the operation through the scalar operation instruction; In response to the data reference length being greater than or equal to the processing word length of the scalar instruction, processing the data address attribute to satisfy the natural boundary attribute of the vector memory access instruction, and performing the operation through the vector operation instruction and the operation optimization strategy; Wherein, the operation types include: addition, subtraction, multiplication and division operations; The operation optimization strategy includes: addition and subtraction optimization strategy, multiplication optimization strategy and division optimization strategy.

2. The optimization method for the four basic arithmetic operations of large numbers as claimed in claim 1, characterized in that: The combining operation types to obtain the data reference length under each operation type includes: In response to the two data to be operated being equal, one of the data to be operated is used as the first operand, and the other data to be operated is used as the second operand, In response to the two data to be operated being unequal, the smaller data to be operated is used as a first operand, and the larger data to be operated is used as a second operand; In response to an addition or subtraction operation, the digit length of the first operand is used as a data reference length, In response to a multiplication or division operation, the digit length of the second operand is used as a data reference length.

3. The optimization method for large number basic arithmetic operations as claimed in claim 2, characterized in that: The addition and subtraction optimization strategy includes: Set the first threshold according to the processing word length of the vector instruction ; In response to the data reference length being less than a first threshold , use vector memory access instructions to read the first operand and the low-order bits of the second operand bits, and completes the operation through vector operation instructions; In response to the data reference length being greater than or equal to a first threshold , execute S11 to S15; S11: The first operand is divided into blocks starting from the lowest bit, and the blocks; among them, , where is the data reference length; It is the rounding operation; S12: Divide the second operand into blocks starting from the lowest bit and take out the low bits. The blocks are calculated with the first operand; S13: According to the principle of least significant bit alignment, the aligned blocks in the two operands are set as a group of operation blocks to obtain Group operation block; S14: cyclically calculating each group of operation blocks through vector operation instructions in order from low to high bits; wherein each cyclic calculation includes: cyclically reading a group of operation block data using vector memory access instructions, and calculating the operation block through vector operation instructions, completing carry / borrow within the block, and obtaining the corresponding calculation result within the block; S15: After the cycle calculation is completed, The calculation results within the block of the group operation block and the remaining blocks in the second operand are concatenated in sequence, and carry / borrow are processed uniformly to obtain the final calculation result.

4. The optimization method for large number basic four arithmetic operations as claimed in claim 3, characterized in that: Addition and subtraction optimization strategies also include: Determine the number of loop unrolls based on the processor cache line size and the processing length of the vector instruction ; In response to , then between S13 and S14, there is also: in order from low to high, each The group operation block is a loop body, and S14 is executed in each loop body to complete n loop unrollings.

5. The optimization method for large number basic arithmetic operations as claimed in claim 4, characterized in that: The first threshold is 256, the number of loop unrolling is 4.

6. The optimization method for large number basic arithmetic operations as claimed in claim 2, characterized in that: The multiplication optimization strategy includes: Set the second threshold according to the processing word length of the vector instruction ; In response to the data reference length being less than or equal to a second threshold , use vector memory access instructions to read two operands, and complete the operation through vector operation instructions; In response to the data reference length being greater than a second threshold , execute S21 to S24; S21: The first operand is obtained by dividing the two operands into units starting from the lowest bit. Units , the second operand is obtained Units ; S22: Combine each unit in the first operand with each unit in the second operand to form operation pairs; S23: looping and calculating each operation pair through the vector operation instruction, wherein each loop calculation includes: Use the vector memory access instruction loop to read the data of an operation pair, and record the data of the two units in the operation pair as and ; Completed through vector operation instructions and The compound calculation is performed to obtain the calculation result of the operation pair; wherein the compound calculation includes: Respectively and Divided into low and high parts, expressed as: ； ； in, is the cardinality, yes Medium to high bit data, yes Low to medium bit data, yes Medium to high bit data, yes Low to medium Bit data; calculate As the calculation result of the operation pair; S24: After the cycle calculation is completed, The calculation results of the operation pairs are concatenated to obtain the final product.

7. The optimization method for large number basic arithmetic operations as claimed in claim 6, characterized in that: The number of loop unrolling is set to 4; The multiplication optimization strategy also includes: In response to , then between S22 and S23, there is also: And the second operation Constitute a loop body, each loop body contains , , and 4 operation pairs; in, is the data reference length, ; It is a floor rounding operation; S23 is executed in each loop body, completing four loop unrollings.

8. The optimization method for large number basic arithmetic operations as claimed in claim 7, characterized in that: The second threshold is 128.

9. The optimization method for large number basic arithmetic operations as claimed in claim 2, characterized in that: The division optimization strategy includes: optimizing the division operation whose divisor digit length is not greater than the vector instruction processing word length through a simulation algorithm; The simulation algorithm includes: Let the dividend be , whose digit length is recorded as , the divisor is written as , whose digit length is recorded as ; In response to , then the quotient of the division operation is 0 and the remainder is ; In response to , execute S31 to S35; S31: Use vector memory access instructions to read from the highest bit of the current dividend bit data, denoted as , In response to , read from the highest bit of the current dividend bit data, In response to a successful read, update , jump to S32; In response to a read failure, the quotient of the current cycle is 0 and the remainder is , jump to S35; S32: Remove the current dividend from the The remaining part of , whose digit length is recorded as , jump to S33; S33: Complete the current operation through vector operation instructions and Simulate the operation to obtain the quotient and remainder of the current loop, and jump to S34; S34: The remainder of the current loop and the remaining part Combine into a new dividend, update and ; In response to , jump to S35 to end the loop calculation; In response to , then jump to S31 to perform the next cycle calculation; S35: concatenate the quotient values ​​calculated in each cycle to obtain the quotient of the division operation, and the current remainder is the remainder of the division operation.

10. The optimization method for the four basic arithmetic operations of large numbers as claimed in claim 9, characterized in that: The simulation operation includes: Solving Satisfaction of value; Will As the quotient value of the current cycle, as the remainder of the current loop.

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