Multiplication operation device

Abstract

A multiplication device includes: a sign calculator adapted to determine a sign bit of a target product based on a sign bit of a first value and a sign bit of a second value; the first value and the second value are both floating-point numbers; a compensator adapted to determine an exponent flag bit and a first compensation value based on a mantissa bit of the first value and a mantissa bit of the second value; an exponent calculator adapted to determine a first exponent bit based on an exponent bit of the first value and an exponent bit of the second value, and determine an exponent bit of the target product based on the first exponent bit and the exponent flag bit; a mantissa calculator adapted to determine a first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value, and determine a mantissa bit of the target product based on the first mantissa bit and the first compensation value, to obtain the target product finally. The above scheme can convert floating-point multiplication into floating-point addition, has good approximation accuracy, and can reduce the area and power consumption of a calculation unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a multiplication operation device. BACKGROUND

[0002] In the field of artificial intelligence (AI) accelerator, due to the computing-intensive characteristics of neural networks, it is often necessary to design an operation unit with huge area and power consumption to process data. Since there are a large number of convolution calculation operations in neural networks, and the results of convolution calculation are basically generated by an operation unit composed of multipliers and adders, a large number of area and power consumption resources in the AI accelerator are allocated to the operation unit composed of multipliers and adders.

[0003] In the current field of AI accelerator, the resource consumed by the multiplier is large. Therefore, an approximate multiplier with less resource consumption is usually used to replace the multiplier, which can greatly reduce the power consumption while not causing great impact on the accuracy of the neural network. SUMMARY

[0004] The purpose of the present application is to provide a multiplication operation device that converts floating point multiplication into floating point addition and has good approximate accuracy, which can greatly reduce the area and power consumption of the calculation unit.

[0005] To solve the above technical problems, the present application provides a multiplication operation device, comprising: a sign calculator, an exponent calculator, a mantissa calculator, and a compensator, wherein: the sign calculator is adapted to determine the sign bit of a target product based on the sign bit of a first value and the sign bit of a second value; the first value and the second value are both floating point numbers; the compensator is adapted to determine an exponent flag bit and a first compensation value based on the mantissa bit of the first value and the mantissa bit of the second value; the exponent calculator is adapted to determine a first exponent bit based on the exponent bit of the first value and the exponent bit of the second value, and determine the exponent bit of the target product based on the first exponent bit and the exponent flag bit; the mantissa calculator is adapted to determine a first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value, and determine the mantissa bit of the target product based on the first mantissa bit and the first compensation value; and the target product is obtained by splicing the sign bit of the target product, the exponent bit of the target product, and the mantissa bit of the target product.

[0006] Optionally, the sign calculator comprises an exclusive-OR operation unit, the first input end of the exclusive-OR operation unit inputs the sign bit of the first value, the second input end inputs the sign bit of the second value, and the output end outputs the exclusive-OR operation result of the sign bit of the first value and the sign bit of the second value, and the exclusive-OR operation result is the sign bit of the target product.

[0007] Optionally, the exponent calculator comprises a first adder, a first subtractor and a selector, wherein: the first input end of the first adder inputs the exponent bit of the first value, the second input end inputs the exponent bit of the second value, and the output end is coupled with the first input end of the first subtractor to output the first exponent bit; the selector inputs the exponent flag bit at the input end and outputs the exponent correction value corresponding to the exponent flag bit at the output end; and the second input end of the first subtractor is coupled with the output end of the selector to output the exponent bit of the target product.

[0008] Optionally, the mantissa calculator comprises a second adder, a third adder and a shift splicer, wherein: the first input end of the second adder inputs the mantissa bit of the first value, the second input end inputs the mantissa bit of the second value, and the output end is coupled with the first input end of the shift splicer and the first input end of the third adder to output the first mantissa bit; the second input end of the third adder inputs the first compensation value, and the output end is coupled with the second input end of the shift splicer to output the second sum of the first mantissa bit and the first compensation value; and the first output end of the shift splicer outputs the exponent flag bit, and the second output end outputs the mantissa bit of the target product.

[0009] Optionally, when the high 2 bits of the second sum are 00, the shift splicer determines that the exponent flag bit is a first value; when the high 2 bits of the second sum are 01 or 10, the shift splicer determines that the exponent flag bit is a second value; and the first value is not equal to the second value.

[0010] Optionally, when the exponent flag bit is the first value, the mantissa bit of the target product is the splicing result of the low 2N bits of the second sum and the low X bits of the first mantissa bit; the length of the first mantissa bit is X+2N-1 bits; when the exponent flag bit is the second value and the high 2 bits of the second sum are 01, the mantissa bit of the target product is: the highest bit is 0, the 2nd-2N+1 bits are the low 2N bits of the second sum, and the 2N+2th- Xth bits are the X-1th-2nd bit from the top of the first mantissa bit; and when the exponent flag bit is the second value and the high 2 bits of the second sum are 10, the mantissa bit of the target product is: the highest bit is 1, the 2nd-2N+1 bits are the low 2N bits of the second sum, and the 2N+2th-Xth bits are the X-1th-2nd bit from the top of the first mantissa bit.

[0011] Optionally, the compensator is adapted to determine a first product based on the high N bits of the mantissa bits of the first value and the high N bits of the mantissa bits of the second value, determine a compensation amount based on the N+1 to N+M bits of the mantissa bits of the first value and the N+1 to N+M bits of the mantissa bits of the second value, and determine the first compensation value based on the first product and the compensation amount.

[0012] Optionally, the compensator comprises a multiplier, a compensation amount determining module and a fourth adder, wherein the first input end of the multiplier inputs the high N bits of the mantissa bits of the first value, the second input end of the multiplier inputs the high N bits of the mantissa bits of the second value, and the output end of the multiplier is coupled with the first input end of the fourth adder; the first input end of the compensation amount determining module inputs the N+1 to N+M bits of the mantissa bits of the first value, the second input end of the compensation amount determining module inputs the N+1 to N+M bits of the mantissa bits of the second value, and the output end of the compensation amount determining module is coupled with the second input end of the fourth adder and outputs the compensation amount; and the output end of the fourth adder outputs the first compensation value.

[0013] Optionally, the multiplication operation device further comprises a data splitting module, wherein the first input end of the data splitting module inputs the first value, the first output end of the data splitting module outputs the sign bit of the first value, the exponent bit of the first value and the mantissa bit of the first value, the second input end of the data splitting module inputs the second value, and the second output end of the data splitting module outputs the sign bit of the second value, the exponent bit of the second value and the mantissa bit of the second value.

[0014] Optionally, the multiplication operation device further comprises a data splicing module adapted to splice the sign bit of the target product, the exponent bit of the target product and the mantissa bit of the target product.

[0015] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0016] The multiplication operation of the first value and the second value of the floating-point number is converted into an addition operation through the sign calculator, the exponent calculator and the mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation process are adjusted through the compensator, so that the error distribution is uniformized, the area and power consumption of the calculation unit are reduced, and the calculation precision is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a structure schematic diagram of a multiplication operation device in an embodiment of the present application;

[0018] Figure 2 is a structure schematic diagram of an exponent calculator in an embodiment of the present application;

[0019] Figure 3is a structure diagram of a mantissa calculator in an embodiment of the present application;

[0020] Figure 4 is a structure diagram of a compensator in an embodiment of the present application;

[0021] Figure 5 is a flow chart of a multiplication calculation in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In the prior art, there are some design schemes of an operation unit of an AI accelerator using an approximate multiplier. One scheme is to modify the encoder part in the booth multiplier, and simplify the Karnaugh map of the encoder to save the area and power consumption of the calculation unit. Another scheme is to simplify the compression process of part of the product in the multiplier. However, the above two schemes will cause a large loss of the precision of the neural network.

[0023] In the present application, the multiplication operation of the first value and the second value of the floating-point number is converted into an addition operation through the sign calculator, the exponent calculator and the mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation process are adjusted through the compensator, which can uniformly distribute the error, reduce the area and power consumption of the calculation unit, and improve the calculation precision.

[0024] In order to make the above-mentioned purposes, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0025] The multiplication operation device provided in the following embodiments of the present application is based on the Mitchell algorithm. The principle of the Mitchell algorithm will be briefly described below.

[0026] In the prior art, it is known that for a decimal number A, its corresponding floating-point representation method can be represented by the following formula (1):

[0027] A=(-1) S *2 (e-bias )*(1+0.m) (1)

[0028] Wherein, S is a sign bit, e constitutes an exponent bit, 0.m represents a real number greater than 0 and less than 1; bias is a bias quantity calculated based on the exponent bit, if the exponent bit is specified as n, then bias=2 (n-1) -1.

[0029] The multiplication operation device provided in the following embodiments of the present application can approximate the multiplication of two numbers through two binary additions based on the Mitchell algorithm, and the maximum error is not more than 1 / 9. The principle of the Mitchell algorithm is as follows:

[0030] If two positive real numbers A, B are multiplied, P=A*B, then log2P=log2A+log2B.

[0031] A is represented in floating point format, A=2 (e1-bias) *(1+0.m1), then log2A=(e1-bias)+log2(1+0.m1). B is represented in floating point format, B=2 (e2-bias )*(1+0.m2).

[0032] Thus, log2P=(e1-bias+e2-bias)+log2(1+0.m1)+log2(1+0.m2).

[0033] Since 0.m is between 0 and 1, log2(1+0.m)≈0.m, thus, the following simplified formula can be obtained:

[0034] P≈2 (e1+e2-2bias )*(1+0.m1+0.m2), 0.m1+0.m2<1.

[0035] P≈2 (e1+e2-2bias) *(0.m1+0.m2-1), 0.m1+0.m2≥1.

[0036] Thus, the approximate multiplication result is obtained by Mitchell algorithm, the hardware of the above Mitchell algorithm can be used to construct a multiplier with two adders and partial logic structure, thereby eliminating the multiplication operation in the multiplier.

[0037] The embodiment of the present application provides a multiplication device for performing approximate multiplication, referring to Figure 1 , the multiplication device is described in detail below.

[0038] In the embodiment of the present application, the multiplication device can include a sign calculator 11, an exponent calculator 12, a mantissa calculator 13 and a compensator 14.

[0039] In the specific implementation, the multiplication device can be used to calculate the product between the first value and the second value. It should be noted that the target product calculated by the multiplication device provided by the embodiment of the present application is actually the approximate product between the first value and the second value, because the multiplication device described below converts the multiplication operation between the first value and the second value into the addition operation based on the Mitchell algorithm.

[0040] In the embodiments of the present application, the first value and the second value can be floating-point numbers in IEEE-754 floating-point format or floating-point numbers in a variant format corresponding to the IEEE-754 floating-point format. The first value and the second value in floating-point format each consist of a sign bit, an exponent bit and a mantissa bit.

[0041] In a specific application, for a single-precision floating-point number, the length is 32 bits, wherein the first bit is a sign bit, the length of the sign bit is 1 bit; the second bit to the ninth bit is an exponent bit, the length of the exponent bit is 8 bits, and the tenth bit to the thirty-second bit is a mantissa bit, the length of the mantissa bit is 23 bits.

[0042] For a double-precision floating-point number, the length is 64 bits, wherein the first bit is a sign bit, the length of the sign bit is 1 bit; the second bit to the eleventh bit is an exponent bit, the length of the exponent bit is 11 bits, and the twelfth bit to the sixty-fourth bit is a mantissa bit, the length of the mantissa bit is 52 bits.

[0043] In the embodiments of the present application, the multiplication device can split the first value and the second value, and the split first value includes a sign bit, an exponent bit and a mantissa bit, and the split second value also includes a sign bit, an exponent bit and a mantissa bit.

[0044] In some embodiments, the multiplication device can further include a data splitting module 10 configured to split the first value and the second value to obtain a sign bit of the first value, an exponent bit of the first value and a mantissa bit of the first value, and a sign bit of the second value, an exponent bit of the second value and a mantissa bit of the second value.

[0045] In a specific implementation, the sign bit of the target product can be determined based on the sign bit of the first value and the sign bit of the second value.

[0046] Specifically, the sign bit of the first value and the sign bit of the second value can be input into the sign calculator 11, and the sign calculator 11 calculates and outputs the sign bit of the target product.

[0047] In some embodiments, the first bit of the first value can be obtained, which is the sign bit of the first value; the first bit of the second value can be obtained, which is the sign bit of the second value. The sign calculator 11 can be an exclusive OR operator, which performs exclusive OR operation on the sign bit of the first value and the sign bit of the second value, and takes the result of the exclusive OR operation as the sign bit of the target product.

[0048] For example, the value of the sign bit of the first value is 1, and the value of the sign bit of the second value is 0. The sign calculator 11 performs exclusive OR operation on the sign bit of the first value and the sign bit of the second value, and the result of the exclusive OR operation is 1. It is determined that the value of the sign bit of the target product is 1.

[0049] In specific implementation, the exponent bits of the first value and the exponent bits of the second value can be input to the exponent calculator 12 respectively, and the exponent calculator 12 can perform operation on the exponent bits of the first value and the exponent bits of the second value to obtain the first exponent bits.

[0050] Specifically, the exponent calculator 12 can perform addition operation on the exponent bits of the first value and the exponent bits of the second value to obtain the first exponent bits.

[0051] In specific implementation, the mantissa bits of the first value and the mantissa bits of the second value can be input to the mantissa calculator 13 respectively, and the mantissa calculator 13 can perform operation on the mantissa bits of the first value and the mantissa bits of the second value to obtain the first mantissa bits.

[0052] Specifically, the mantissa calculator 13 can perform addition operation on the mantissa bits of the first value and the mantissa bits of the second value to obtain the first mantissa bits.

[0053] In specific implementation, the compensator 14 can obtain the high N bits of the mantissa bits of the first value and the high N bits of the mantissa bits of the second value, and perform multiplication operation on the high N bits of the mantissa bits of the first value and the high N bits of the mantissa bits of the second value to obtain a first product with a length of 2N.

[0054] The compensator 14 can also obtain the (N+1)th to (N+M)th bits of the mantissa bits of the first value and the (N+1)th to (N+M)th bits of the mantissa bits of the second value, and determine a compensation amount based on the (N+1)th to (N+M)th bits of the mantissa bits of the first value and the (N+1)th to (N+M)th bits of the mantissa bits of the second value.

[0055] The values of N and M are related to the precision requirement of the multiplication operation device. Specifically, when M is the same, the greater the value of N is, the higher the precision of the multiplication operation device is. Correspondingly, when N is the same, the greater the value of M is, the higher the precision of the multiplication operation device is.

[0056] For different values of the (N+1)th to (N+M)th bits of the mantissa bits of the first value and the (N+1)th to (N+M)th bits of the mantissa bits of the second value, the corresponding compensation amounts can be different.

[0057] Specifically, for different values of the (N+1)th to (N+M)th bits of the mantissa bits of the first value and the (N+1)th to (N+M)th bits of the mantissa bits of the second value, a compensation amount corresponding to each value can be set.

[0058] For example, when N=3 and M=1, if the 4th bit of the mantissa of the first value and the 4th bit of the mantissa of the second value are both 1, the preset compensation value is 000010; if the 4th bit of the mantissa of the first value and the 4th bit of the mantissa of the second value are both 0, the preset compensation value is 000000; if either of the 4th bit of the mantissa of the first value and the 4th bit of the mantissa of the second value is 1, the preset compensation value is 000001.

[0059] The compensator 14 performs addition operation on the first product and the compensation value, and takes the obtained first sum as the first compensation value. The compensation value has the same number of bits as the first product.

[0060] In some embodiments, N=3 and M=1 can be taken. Thus, the compensator 14 can take the high 3 bits of the mantissa of the first value and the high 3 bits of the mantissa of the second value, perform multiplication operation thereon, and obtain a first product with a length of 6 bits. The compensator 14 determines the compensation value based on the 4th bit of the mantissa of the first value and the 4th bit of the mantissa of the second value.

[0061] In other embodiments, N=4 and M=2 can be taken. Thus, the compensator 14 can take the high 4 bits of the mantissa of the first value and the high 4 bits of the mantissa of the second value, perform multiplication operation thereon, and obtain a first product with a length of 8 bits. The compensator 14 determines the compensation value based on the 5th-6th bits of the mantissa of the first value and the 5th-6th bits of the mantissa of the second value.

[0062] In a specific implementation, the mantissa calculator 13 can determine the exponent flag and the mantissa of the target product according to the first compensation value and the first mantissa.

[0063] Specifically, the mantissa calculator 13 can take the high 2N+1 bits of the first mantissa and perform addition operation thereon with the high 2N+1 bits of the first compensation value to obtain a second sum. The mantissa calculator 13 can take the high 2 bits of the second sum.

[0064] If the high 2 bits of the second sum are 00, the exponent flag is determined to be 0, and the mantissa of the target product is determined to be the splicing result of the low X bits of the first mantissa and the low 2N bits of the second sum, wherein the length of the first mantissa is X+2N+1 bits.

[0065] For example, the first value is a single-precision floating-point number, and the length of the sum of the mantissa of the first value and the mantissa of the second value is 24 bits. If N=3, the low 6 bits of the second sum are taken and spliced with the low 17 bits of the first mantissa (i.e., X=17) to obtain the mantissa of the target product.

[0066] The "splicing" in the embodiments of the present application can refer to directly splicing different binary numbers. Specifically, as in the above example, the low 6 bits of the second sum value are taken as the high 6 bits of the mantissa bits of the target product, and the low 17 bits of the first mantissa bits are taken as the low 17 bits of the mantissa of the target product. In this way, the mantissa of the target product with a length of 23 bits is obtained.

[0067] If the high 2 bits of the second sum value are 01, it is determined that the exponent flag bit is 1, and the mantissa bits of the target product are determined as follows: the highest bit is 0, the 2nd to 2N+1 bits are the low 2N bits of the second sum value, and the 2N+2 bit to the X bit are the X-1 bit to the 2nd bit from the end of the first mantissa bits.

[0068] For example, if the first value is a single-precision floating-point number, the length of the first mantissa bits is 23 bits. If N=3 is taken, the highest bit is taken as 0, the low 6 bits of the second sum value are spliced with the 16th bit to the 2nd bit from the end of the first mantissa bits, and the spliced result is the mantissa bits of the target product.

[0069] If the high 2 bits of the second sum value are 10, it is determined that the exponent flag bit is 1, and the mantissa bits of the target product are determined as follows: the highest bit is 1, the 2nd to 2N+1 bits are the low 2N bits of the second sum value, and the 2N+2 bit to the X bit are the X-1 bit to the 2nd bit from the end of the first mantissa bits.

[0070] For example, if the first value is a single-precision floating-point number, the length of the first mantissa bits is 23 bits. If N=3 is taken, the highest bit is taken as 1, the low 6 bits of the second sum value are spliced with the 16th bit to the 2nd bit from the end of the first mantissa bits, and the spliced result is the mantissa bits of the target product.

[0071] In a specific implementation, the exponent calculator 12 can determine the exponent bits of the target product based on the first exponent bit and the exponent flag bit.

[0072] In some embodiments, the exponent calculator 12 can determine a corresponding exponent correction value based on the value of the exponent flag bit. Then, the exponent calculator 12 calculates the difference between the first exponent bit and the exponent correction value as the exponent bits of the target product.

[0073] Specifically, if the value of the exponent flag bit is a first value, a corresponding first exponent correction value can be determined, and the first exponent bit is subtracted from the first exponent correction value, and the difference obtained is taken as the exponent bits of the target product.

[0074] If the value of the exponent flag bit is a second value, a corresponding second exponent correction value can be determined, and the first exponent bit is subtracted from the second exponent correction value, and the difference obtained is taken as the exponent bits of the target product.

[0075] The first exponent correction value is different from the second exponent correction value. That is, the value of the exponent flag is different, and the corresponding exponent correction value is different.

[0076] In some embodiments, if the first value and the second value are both single-precision floating-point numbers, and the value of the exponent flag is 1, the value of the first exponent correction value can be 011111111; if the value of the exponent flag is 0, the value of the first exponent correction value can be 01111110.

[0077] The specific structures of the symbol calculator 11, the exponent calculator 12, the mantissa calculator 13, and the compensator 14 described above will be described in detail below.

[0078] Referring to Figure 2 , a structure diagram of an exponent calculator in an embodiment of the present application is given.

[0079] Figure 2 In the exponent calculator, the exponent calculator includes a first adder 21, a first subtractor 22, and a selector 23, and the selector 23 stores an exponent correction value.

[0080] The first input end of the first adder 21 can input the exponent bit of the first value, and the second input end of the first adder 21 can input the exponent bit of the second value. The first adder 21 sums the exponent bit of the first value and the exponent bit of the second value, and the output end of the first adder 21 outputs the first exponent bit.

[0081] The selector 23 can receive the exponent flag, determine the exponent correction value as the first exponent correction value or the second exponent correction value based on the value of the exponent flag, and output the determined exponent correction value to the first subtractor 22. It can be understood that the above-mentioned selector 23 is only an example, and in essence, any device or circuit that can realize the following functions can be understood as the above-mentioned selector 23: receiving the exponent flag, determining the exponent correction value and outputting to the first subtractor 22.

[0082] The first input end of the first subtractor 22 can input the first exponent bit, and the second input end of the first subtractor 22 can input the exponent correction value. The first subtractor 22 performs subtraction operation on the first exponent bit and the exponent correction value, and the output end of the first subtractor 22 outputs the difference value as the exponent bit of the target product.

[0083] Referring to Figure 3 , a structure diagram of a mantissa calculator in an embodiment of the present application is given.

[0084] Figure 3 In the mantissa calculator, the mantissa calculator can include a second adder 31, a third adder 32, and a shift splicer 33, wherein:

[0085] The first input end of the second adder 31 inputs the tail number bits of the first value, and the second input end of the second adder 31 inputs the tail number bits of the second value. The second adder 31 performs an addition operation on the tail number bits of the first value and the tail number bits of the second value, and the output end of the second adder 31 outputs the first tail number bit.

[0086] The first input end of the third adder 32 is coupled with the output end of the second adder 31, that is, the first input end of the third adder 32 inputs the first tail number bit. The second input end of the third adder 32 is coupled with the output end of the compensator and inputs the first compensation value.

[0087] The output end of the third adder 32 is also coupled with the first input end of the shift splicer 33, and the output end of the second adder 31 is coupled with the second input end of the shift splicer 33. The shift splicer 33 can output the exponent flag bit and the tail number bits of the target product.

[0088] Specifically, the output end of the third adder 32 outputs the sum (second sum) of the first tail number bit and the first compensation value. The shift splicer 33 receives the second sum, selects the high 2 bits of the second sum, and determines the value of the exponent flag bit based on the high 2 bits of the second sum.

[0089] Specifically, if the high 2 bits of the second sum are 00, the shift splicer 33 can determine that the exponent flag bit is 0; and the shift splicer 33 splices the low 2N bits of the second sum with the low X bits of the first tail number bit to obtain the tail number bits of the target product.

[0090] If the high 2 bits of the second sum are 01, it is determined that the exponent flag bit is 1; and the tail number bits of the target product are determined as follows: the highest bit is 0, the 2nd-2N+1 bits are the low 2N bits of the second sum, and the 2N+2th- Xth bits are the X-1th bit of the first tail number bit to the 2nd bit from the end of the first tail number bit.

[0091] If the value of the high 2 bits of the second sum is 10, it is determined that the exponent flag bit is 1; and the tail number bits of the target product are determined as follows: the highest bit is 1, the 2nd-2N+1 bits are the low 2N bits of the second sum, and the 2N+2th-Xth bits are the X-1th bit of the first tail number bit to the 2nd bit from the end of the first tail number bit.

[0092] Referring to Figure 4 , a structure diagram of a compensator in an embodiment of the present application is given.

[0093] Figure 4 In the embodiment, the compensator can include a multiplier 41, a compensation amount determination module 42, and a fourth adder 43.

[0094] The first input of multiplier 41 can accept the high N bits of the mantissa of a first value, and the second input can accept the high N bits of the mantissa of a second value. Multiplier 41 performs a multiplication operation between the high N bits of the mantissa of the first value and the high N bits of the mantissa of the second value to obtain a first product of length 2N. The output of multiplier 41 can output the first product.

[0095] The compensation amount determination module 42 can input the (N+1)th to (N+M)th bits of the mantissa of the first value and the (N+1)th to (N+M)th bits of the mantissa of the second value. The compensation amount determination module 42 can determine the compensation amount based on the (N+1)th to (N+M)th bits of the mantissa of the first value and the (N+1)th to (N+M)th bits of the mantissa of the second value.

[0096] The first input terminal of the fourth adder 43 is coupled to the output terminal of the multiplier 41, and the second input terminal of the fourth adder 43 is coupled to the output terminal of the compensation amount determination module 42. The first product and the compensation amount are added to obtain the first compensation value.

[0097] In this embodiment of the invention, the multiplication device may further include a data splicing module 15, which is adapted to splice the sign bit, the exponent bit and the exponent bit of the target product to obtain the target product.

[0098] The specific operation process of the multiplication apparatus provided in the above embodiments of the present invention will be described below through specific examples. (Refer to...) Figure 5 A flowchart of a multiplication calculation in an embodiment of the present invention is provided.

[0099] Let the first value be A and the second value be B, both of which are single-precision floating-point numbers. The sign bit of the first value is represented as A_S, and the sign bit of the second value is represented as B_S; the exponent bit of the first value is represented as A_E, and the exponent bit of the second value is represented as B_E; the mantissa bit of the first value is represented as A_M, and the mantissa bit of the second value is represented as B_M.

[0100] Step 501: Obtain the sign bit of the target product.

[0101] In practice, A_S and B_S are input into the sign calculator, which performs an XOR operation on A_S and B_S to obtain the sign bit P_S of the target product.

[0102] Step 502: Obtain the first exponent.

[0103] In practice, A_E and B_E are input into the exponent calculator, which then performs an addition operation on A_E and B_E to obtain the first exponent E_1.

[0104] Step 503: Obtain the first last digit.

[0105] In a specific implementation, A_M and B_M are input into the mantissa calculator respectively, and the mantissa calculator performs addition operation on A_M and B_M to obtain a first mantissa bit M_1, and the length of M_1 is 24 bits.

[0106] In step 504, a first compensation value is obtained.

[0107] In a specific implementation, the high 3 bits of A_M and the high 3 bits of B_M are obtained, and the high 3 bits of A_M and the high 3 bits of B_M are multiplied to obtain a first product M_2, and the length of M_2 is 6 bits.

[0108] The 4th bit of A_M and the 4th bit of B_M are obtained. Based on the values of the 4th bit of A_M and the 4th bit of B_M, the compensation amount is determined.

[0109] Specifically, if the 4th bit of A_M and the 4th bit of B_M are both 1, the first compensation value is M_3=M_2+000010; if only one of the 4th bit of A_M and the 4th bit of B_M is 1, the first compensation value M_3=M_2+000001; and if the 4th bit of A_M and the 4th bit of B_M are both 0, the first compensation value M_3=M_2.

[0110] In a specific implementation, the lengths of the above-mentioned compensation amounts (000010, 000001) are equal to the length of M_2.

[0111] It should be noted that in the above step 504, the high 4 bits of A_M and the high 4 bits of B_M can also be obtained to perform multiplication operation, and the length of the obtained product M_2 is 8 bits. Correspondingly, the 5th bit of A_M and the 5th bit of B_M can be obtained. In this scenario, if the 5th bit of A_M and the 5th bit of B_M are both 1, the first compensation value is M_3=M_2+00000010; if only one of the 4th bit of A_M and the 4th bit of B_M is 1, the first compensation value M_3=M_2+000001; and if the 4th bit of A_M and the 4th bit of B_M are both 0, the first compensation value M_3=M_2.

[0112] In step 505, the mantissa bit of the target product is obtained.

[0113] In a specific implementation, the high 7 bits of M_3 and the high 7 bits of M_1 can be added to obtain an 8-bit second sum M_4.

[0114] The high 2 bits of M_4 are obtained, and if the value of the high 2 bits of M_4 is 00, it is determined that the exponent flag bit is 0, and the mantissa bit of the target product output by the mantissa calculator is: P_M=M_4[5:0]~M_1[16:0];

[0115] M_4[5:0] is the low 6 bits of M_4. M_1[16:0] is the low 17 bits of M_1. M_4[5:0]~M_1[16:0] can mean that M_4[5:0] is spliced with M_1[16:0]. Specifically, in P_M, the high 6 bits are M_4[5:0] and the low 17 bits are M_1[16:0].

[0116] For example, M_4 is 00111001, M_4[5:0] is 111001. M_1 is 011010101010101010101011, M_1[16:0] is 01010101010101011, and the spliced P_M is 11100101010101010101011.

[0117] If the high 2 bits of M_4 are 01, it is determined that the exponent flag is 1, and the mantissa of the target product output by the mantissa calculator is P_M=0~M_4[5:0]~M_1[16:1].

[0118] M_4[5:0] is the low 6 bits of M_4. M_1[16:1] is the 2nd to 17th bits of M_1.

[0119] For example, M_4 is 00111001, M_4[5:0] is 111001. M_1 is 011010101010101010101011, M_1[16:1] is 0101010101010101, and the spliced P_M is 01110010101010101010101.

[0120] If the high 2 bits of M_4 are 10, it is determined that the exponent flag is 1, and the mantissa of the target product output by the mantissa calculator is P_M=1~M_4[5:0]~M_1[16:1].

[0121] For example, M_4 is 00111001, M_4[5:0] is 111001. M_1 is 011010101010101010101011, M_1[16:1] is 0101010101010101, and the spliced P_M is 11110010101010101010101.

[0122] Step 506, obtaining the exponent bit of the target product.

[0123] In specific implementation, according to the exponent flag obtained in the above step 505 and the first exponent bit obtained in the above step 503, the exponent bit of the target product is determined.

[0124] Specifically, if the value of the exponent flag bit is 0, the E_1 is subtracted by 011111111 to obtain the exponent bit P_E of the target product = E_1-011111111.

[0125] If the value of the exponent flag bit is 1, the E_1 is subtracted by 011111111 to obtain the exponent bit P_E of the target product = E_1-011111110.

[0126] Step 507, obtaining the target product.

[0127] In the specific implementation, the sign bit of the target product, the exponent bit of the target product and the mantissa bit of the target product can be spliced by the data splicing module, so that the target product can be obtained.

[0128] That is, the target product can be P=P_S~P_E~P_M.

[0129] For example, the sign bit of the target product is 1, the exponent bit of the target product is 01101100, and the mantissa bit of the target product is 01101010101010101010101. Thus, the target product obtained by splicing is 10110110001101010101010101010101.

[0130] As can be seen from the above, in the embodiment of the present application, the multiplication operation of the first value and the second value of the floating-point number is converted into an addition operation by the sign calculator, the exponent calculator and the mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation are adjusted by the compensator, so that the error can be evenly distributed, the area and power consumption of the calculation unit can be reduced, and the calculation precision can be improved.

[0131] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium, which can include ROM, RAM, magnetic disk or optical disk, etc.

[0132] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A multiplication arithmetic device, characterized in that, include: Sign calculator, exponent calculator, last digit calculator, compensator, among which: The sign calculator is adapted to determine the sign bit of the target product based on the sign bit of the first value and the sign bit of the second value; both the first value and the second value are floating-point numbers; The compensator is adapted to determine an exponent flag and a first compensation value based on the mantissa of the first value and the mantissa of the second value. The exponent calculator is adapted to determine a first exponent based on the exponent of the first value and the exponent of the second value; and to determine the exponent of the target product based on the first exponent and the exponent flag. The last digit calculator is adapted to determine a first last digit based on the last digits of the first value and the last digits of the second value; and to determine the last digits of the target product based on the first last digit and the first compensation value. The target product is obtained by concatenating the sign bit, the exponent bit, and the mantissa bit of the target product.

2. The multiplication apparatus as described in claim 1, characterized in that, The symbol calculator includes an XOR operation unit; The XOR operation unit has a first input terminal that receives the sign bit of the first value, a second input terminal that receives the sign bit of the second value, and an output terminal that outputs the XOR operation result of the sign bit of the first value and the sign bit of the second value. The XOR operation result is the sign bit of the target product.

3. The multiplication apparatus as described in claim 1, characterized in that, The exponent calculator includes a first adder, a first subtractor, and a selector, wherein: The first adder has a first input terminal that receives the exponent of the first value, a second input terminal that receives the exponent of the second value, and an output terminal that is coupled to the first input terminal of the first subtractor and outputs the first exponent. The selector takes the exponent flag bit as input and outputs the exponent correction value corresponding to the exponent flag bit. The first subtractor has its second input coupled to the output of the selector, and outputs the exponent of the target product.

4. The multiplication apparatus as described in claim 1, characterized in that, The last digit calculator includes: a second adder, a third adder, and a shifter / concatenater, wherein: The second adder has its first input terminal receiving the mantissa of the first value, its second input terminal receiving the mantissa of the second value, and its output terminal being coupled to the first input terminal of the shift splicer and the first input terminal of the third adder, and outputting the first mantissa. The third adder takes the first compensation value as input at its second input terminal and its output terminal is coupled to the second input terminal of the shift splicer to output the second sum of the first mantissa and the first compensation value. The shift splicer outputs the exponent flag bit at its first output terminal and the mantissa bit of the target product at its second output terminal.

5. The multiplication apparatus as described in claim 4, characterized in that, The shift splicer determines the exponent flag as a first value when the high 2 bits of the second sum are 00; and determines the exponent flag as a second value when the high 2 bits of the second sum are 01 or 10; the first value is not equal to the second value.

6. The multiplication apparatus as described in claim 5, characterized in that, When the exponent flag is the first value, the mantissa of the target product is: the concatenation result of the lower 2N bits of the second sum and the lower X bits of the first mantissa; the length of the first mantissa is X+2N-1 bits. When the exponent flag is the second value and the high 2 bits of the second sum are 0 or 1, the mantissa of the target product is: the highest bit is 0, the 2nd to 2N+1th bits are the low 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa to the second-to-last bit of the first mantissa; When the exponent flag is the second value and the high 2 bits of the second sum are 10, the mantissa of the target product is: the highest bit is 1, the 2nd to 2N+1th bits are the low 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa to the second-to-last bit of the first mantissa.

7. The multiplication apparatus as described in claim 1, characterized in that, The compensator is adapted to determine a first product based on the high N bits of the mantissa of the first value and the high N bits of the mantissa of the second value; to determine a compensation amount based on the (N+1)th to (N+M)th bits of the mantissa of the first value and the (N+1)th to (N+M)th bits of the mantissa of the second value; and to determine a first compensation value based on the first product and the compensation amount.

8. The multiplication apparatus as described in claim 7, characterized in that, The compensator includes: a multiplier, a compensation amount determination module, and a fourth adder, wherein: The multiplier has a first input terminal that receives the high N bits of the mantissa of the first value, a second input terminal that receives the high N bits of the mantissa of the second value, and an output terminal that is coupled to the first input terminal of the fourth adder. The compensation amount determination module has its first input terminal inputting the N+1 to N+M digits of the mantissa of the first value, its second input terminal inputting the N+1 to N+M digits of the mantissa of the second value, and its output terminal coupled to the second input terminal of the fourth adder to output the compensation amount. The fourth adder outputs the first compensation value at its output terminal.

9. The multiplication apparatus as described in claim 1, characterized in that, Also includes: The data splitting module takes the first value as input at its first input terminal and outputs the sign bit, exponent bit, and mantissa bit of the first value at its first output terminal. Its second input terminal takes in the second value, and its second output terminal outputs the sign bit, the exponent bit, and the mantissa bit of the second value.

10. The multiplication apparatus as described in claim 1, characterized in that, Also includes: The data splicing module is adapted to splice the sign bit, the exponent bit, and the mantissa bit of the target product.

Images