Fusion operator implementation method and device, equipment and medium

Abstract

The invention discloses a fusion operator implementation method and device, equipment and a medium. Comprising the following steps: performing semantic conversion on a high-level intermediate expression fusion operator on a multi-level storage chip to obtain an own semantic fusion operator; performing algebraic optimization on the own semantic fusion operator to obtain an optimized fusion operator; obtaining a cache size, a data stream cyclic polyhedral structure and a calculation stream corresponding to the optimized fusion operator; and combining the cache size, the data stream cyclic polyhedral structure and the computational stream to obtain a bottom-layer code, and running the bottom-layer code to realize an optimized fusion operator. And combining the obtained cache size, the data stream cyclic polyhedral structure and the calculation stream through the information in the optimized fusion operator so as to automatically determine a bottom layer code corresponding to the fusion operator, and realizing the fusion operator by running the bottom layer code without manual writing of a user. Therefore, the efficiency and the accuracy of realizing the fusion operator are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to computer technology, and in particular to a method, apparatus, device and medium for implementing a fusion operator. Background Art

[0002] A deep learning network usually contains a large number of operators. Artificial intelligence compilers usually use operator fusion to improve the efficiency of operator execution. Operator fusion refers to the process of merging multiple related operators into a larger operator for execution.

[0003] There are two ways to implement operator fusion currently used: the first way is to perform operator fusion in the process of automatically generating operator implementation. This type of operator fusion generally analyzes the cyclic polyhedron structure of operators with memory dependencies and performs fusion at the cyclic polyhedron level. When the cyclic polyhedron structure of the operator is relatively complex, it is difficult to perform fusion at the cyclic polyhedron level, and thus it is impossible to achieve the ideal operator fusion result; the second way is to separate operator fusion from operator implementation. The operator fusion process occurs at the high-level intermediate expression layer, that is, the high-level intermediate expression layer decides which operators to fuse together to generate a fusion operator based on certain rules. Since the fusion operator generated by the high-level intermediate expression layer only contains the semantic expression of the operator, but does not contain the specific implementation of the operator, the underlying operator implementation needs to support the upper-level fusion operator semantics to realize the fusion operator.

[0004] Although the second method mentioned above is more flexible in implementing fusion operators, it is also more dependent on the number of fusion operator implementations contained in the bottom layer. Only when the number of bottom-layer fusion operator implementations is rich enough can the upper layer have richer and more powerful fusion capabilities, and then the network can have higher execution efficiency. In a deep learning network, the operators are diverse and numerous. Correspondingly, the high-level intermediate expression layer HLIR can generate a wide variety of fusion operators. If the implementation of the bottom-layer fusion operator depends on handwriting, it requires huge manpower investment. Therefore, the handwritten fusion operator implementation can usually only meet the needs of certain specific networks and lacks generalization. Especially in the current situation where deep learning networks are becoming more and more complex and evolving faster and faster, handwritten operators can no longer meet current needs. Summary of the invention

[0005] An embodiment of the present invention provides a method for implementing a fusion operator to automatically implement the fusion operator.

[0006] In a first aspect, an embodiment of the present invention provides a method for implementing a fusion operator, comprising: performing semantic conversion on a high-level intermediate expression fusion operator on a multi-level storage chip to obtain a self-semantic fusion operator;

[0007] Performing algebraic optimization on the self-owned semantic fusion operator to obtain an optimized fusion operator;

[0008] Obtaining the cache size, data flow loop polyhedron structure and calculation flow corresponding to the optimized fusion operator;

[0009] The cache size, the data flow loop polyhedron structure and the calculation flow are combined to obtain the underlying code, and the optimized fusion operator is implemented by running the underlying code.

[0010] In a second aspect, an embodiment of the present invention provides a device for implementing a fusion operator, including: a semantic conversion module, used to perform semantic conversion on a high-level intermediate expression fusion operator on a multi-level storage chip to obtain an own semantic fusion operator;

[0011] an algebraic optimization module, used for performing algebraic optimization on the self-owned semantic fusion operator to obtain an optimized fusion operator;

[0012] A data flow cycle polyhedron structure and a calculation flow acquisition module, used to acquire the cache size, data flow cycle polyhedron structure and calculation flow corresponding to the optimized fusion operator;

[0013] The fusion operator implementation module is used to combine the cache size, the data flow loop polyhedron structure and the calculation flow to obtain the underlying code, and implement the optimized fusion operator by running the underlying code.

[0014] In a third aspect, an embodiment of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the method described above when executing the program.

[0015] In a fourth aspect, an embodiment of the present invention provides a storage medium of computer executable instructions, on which a computer program is stored, characterized in that the program implements the method described above when executed by a processor.

[0016] The present invention converts the semantics of high-level intermediate expression fusion operators into their own semantic fusion operators, performs algebraic optimization to obtain optimized fusion operators, and combines the obtained cache size, data flow loop polyhedron structure and calculation flow based on the information in the optimized fusion operator to automatically determine the underlying code corresponding to the fusion operator, and implements the fusion operator by running the underlying code without the need for manual writing by the user, thereby improving the efficiency and accuracy of the fusion operator implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flow chart of a method for implementing a fusion operator provided in Embodiment 1 of the present invention;

[0018] Figure 2This is a flow chart of a method for implementing a fusion operator provided in Embodiment 1 of the present invention;

[0019] Figure 3 This is a flow chart of a method for implementing a fusion operator provided in Embodiment 2 of the present invention;

[0020] Figure 4 It is a schematic diagram of the structure of a device for implementing a fusion operator provided in Embodiment 3 of the present invention;

[0021] Figure 5 It is a structural diagram of a computer device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0023] Embodiment 1

[0024] Figure 1 This is a flow chart of a method for implementing a fusion operator provided in the first embodiment of the present invention. This embodiment is applicable to the case of implementing a fusion operator. The method can be executed by a fusion operator implementation device, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0025] Step S101 , performing semantic conversion on high-level intermediate expression fusion operators on the multi-level storage chip to obtain own semantic fusion operators.

[0026] Optionally, semantic transformation is performed on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain its own semantic fusion operator, including: extracting the input and output information, sub-operator information and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip, wherein the sub-operator information includes the sub-operator type and the computational dependency between sub-operators; and obtaining the own semantic fusion operator based on the input and output information, sub-operator information and memory access mapping relationship.

[0027] Optionally, extracting input and output information, sub-operator information and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip, including: directly extracting input and output information and sub-operator information from the high-level intermediate expression fusion operator; determining whether the high-level intermediate expression fusion operator contains non-one-to-one sub-operators, if so, taking the non-one-to-one sub-operator as a typical operator, otherwise, taking any one-to-one sub-operator in the fusion operator as a typical operator; taking the memory access mapping relationship of the typical operator as the memory access mapping relationship of the high-level intermediate expression fusion operator.

[0028] Specifically, in this embodiment, the already fused high-level intermediate expression fusion operator can be obtained from the framework layer of the multi-level storage chip, such as the high-level intermediate expression layer. In this embodiment, each sub-operator in the high-level intermediate expression fusion operator is converted into a self-owned semantic operator and then wrapped in the func operator to form a self-owned semantic fusion operator. Among them, when performing semantic conversion, the specific operation is to extract the input and output information in the high-level intermediate expression fusion operator, the sub-operator information including the sub-operator type and the computational dependency between the sub-operators, and the memory access mapping relationship, and determine the self-owned semantic fusion operator based on the above three contents.

[0029] It should be noted that the input and output information and sub-operator information can be directly extracted from the high-level intermediate expression fusion operator, but the memory access mapping relationship needs to be processed by the high-level intermediate expression fusion operator before it can be obtained. Because unlike other types of operators that have fixed memory access mapping relationships, the high-level intermediate expression fusion operator has many types of sub-operators and an uncertain number. In this implementation, the memory access mapping relationship of the fusion operator is determined by traversing the sub-operators and finding typical operators among the sub-operators. Among them, typical operators are divided into two categories: the first type of operators are one-to-one operators, for example, simple Elementwise operators; the second type of operators are non-one-to-one operators, for example, complex operators such as softmax, layernorm and dot. In this implementation, the fusion of the first type of operators with the first type of operators, the fusion of the first type of operators with the second type of operators, and the fusion of the second type of operators with the first type of operators are supported, but the fusion of the second type of operators with the second type of operators is not supported. Therefore, in the high-level intermediate expression fusion operator, there is a situation where only one-to-one type sub-operators are included, or one-to-one type sub-operators and non-one-to-one type sub-operators are included at the same time, and the number of non-one-to-one type sub-operators is only one. Among them, when the high-level intermediate expression fusion operator only contains one-to-one type sub-operators, any one-to-one type sub-operator is selected as a typical operator; when the high-level intermediate expression fusion operator contains non-one-to-one type sub-operators, the non-one-to-one type sub-operator is selected as a typical operator. After the typical operators are determined, the memory access mapping relationships of the typical operators are extracted and used as the memory access mapping relationships of the advanced intermediate expression fusion operators, so that the semantic fusion operators are subsequently constructed based on the memory access mapping relationships of the advanced intermediate expression fusion operators. Therefore, although the types of sub-operators in the advanced intermediate expression fusion operators are diverse, the memory access mapping relationships of the fusion operators can be generated as long as the memory access mapping relationships of the typical operators are defined.

[0030] Step S102, performing algebraic optimization on the own semantic fusion operator to obtain an optimized fusion operator.

[0031] Optionally, algebraic optimization is performed on the own semantic fusion operator to obtain an optimized fusion operator, including: obtaining typical operators in the own semantic fusion operator, and determining a dimension adjustment method of input and output information based on the typical operator, wherein the dimension adjustment method includes dimension quantity adjustment and dimension size adjustment; and dimension adjustment is performed on the input and output information of the own semantic fusion operator according to the dimension adjustment method.

[0032] Specifically, in this embodiment, after obtaining the own semantic fusion operator through semantic conversion, the own semantic fusion operator can be algebraically optimized to obtain the optimized fusion operator, wherein the algebraic optimization mainly adjusts the dimension of the input and output information of the own semantic fusion operator, and the dimension adjustment method for the input and output information is mainly determined according to the type of typical operator. For example, when the typical operator in the own semantic fusion operator is a one-to-one type sub-operator, the input and output information are merged into one dimension during algebraic optimization. For example, when the input information is [d0, d1,…, dn], it is merged into one dimension, that is, [d0*d1*…*dn]. Of course, the dimension adjustment method of the output information is similar to this, which will not be repeated in this embodiment. After the dimension adjustment, the subsequently generated data flow loop polyhedron structure can be made simpler, and it is easier to optimize the data flow transportation. When the typical operator is a non-one-to-one type sub-operator, since the number of dimensions and the adjustment of dimension sizes corresponding to different non-one-to-one type sub-operators are different, when the typical operator is a non-one-to-one type operator, it can include multiple forms of dimension adjustment methods, which are specifically determined according to the specific form of the non-one-to-one type operator.

[0033] Step S103, obtaining the cache size, data flow loop polyhedron structure and calculation flow corresponding to the optimized fusion operator.

[0034] Optionally, the cache size, data flow loop polyhedron structure and computing flow corresponding to the optimized fusion operator are obtained, including: extracting the split size and transposition information from the tuning parameter set passed in from the outside, and obtaining the cache size according to the input and output information, split size and transposition information in the optimized fusion operator; obtaining the data flow loop polyhedron structure according to the cache size, the input and output information in the optimized fusion operator and the memory access mapping relationship; obtaining the computing flow according to the sub-operator information in the optimized fusion operator.

[0035] Among them, Figure 2 The flowchart of the method for implementing the fusion operator is shown, and step S103 is specifically described. Step S103 mainly includes steps S1031-S1033. The following is a specific description of each step S1031-S1033:

[0036] Step S1031 , extracting the segmentation size and transposition information from the externally transmitted tuning parameter set, and obtaining the cache size according to the input and output information, segmentation size and transposition information in the optimized fusion operator.

[0037] Among them, in this embodiment, due to the multi-level storage structure of the chip, the implementation of the operator usually needs to move data between different caches, so it is necessary to obtain the cache size allocated for moving data. In this embodiment, an externally transmitted tuning parameter set will be received, and when obtaining the cache size, it is necessary to extract the pre-set segmentation size and transposition information from the tuning parameter set. In addition, the input and output information will be extracted from the optimized fusion operator. When the segmentation size, input and output information, and transposition information are known, the cache size can be obtained by calculating according to the specified algorithm based on the above three parameters. The specific type of the specified algorithm is not limited in this embodiment. As long as the cache size can be determined based on the above known information, it is within the scope of protection of this application.

[0038] It should be noted that, when the cache size is determined, subsequent data transfer can be performed based on the determined cache size, and the calculated cache size also affects the determination of the subsequent data flow cycle polyhedron structure.

[0039] Step S1032, obtaining a data flow loop polyhedron structure according to the cache size, the input and output information in the optimized fusion operator, and the memory access mapping relationship.

[0040] Optionally, a data flow loop polyhedron structure is obtained according to the cache size, input and output information in the optimized fusion operator, and the memory access mapping relationship, including: determining the number of loop axes according to the number of dimensions of the input and output information, determining the boundaries of each loop axis according to the dimensional size of the input and output information, and determining the step size of each loop axis according to the segmentation size; constructing a loop body according to the number of loop axes, the boundaries of the loop axes, and the step size of the loop axes; determining the cache handling method according to the memory access mapping relationship, the cache size, and the variables of the loop body; and determining the data flow loop polyhedron structure based on the loop body and the cache handling method.

[0041] Specifically, in the multi-level storage structure of the chip, the cache close to the computing core is called a high-level cache, and the cache far away from the computing core is called a low-level cache. Similar to other common single operators, a data flow loop polyhedron structure can be generated based on the memory access mapping relationship and input and output information in the fusion operator, as well as the cache size determined above, so that the input of the fusion operator can be moved into the high-level cache or the output can be moved out of the high-level cache multiple times. The data flow loop polyhedron structure mainly includes a loop body and a cache handling method. An example of a data flow loop polyhedron structure is shown below:

[0042]

[0043] Among them, in the implementation method, the number of loop axes is determined according to the number of dimensions of the input and output information, such as the number of for; the boundaries of each loop axis are determined according to the dimensions of the input and output information, such as dim0; the step length of each loop is determined according to the segmentation size extracted from the tuning parameter set, such as length1, and the loop body can be constructed according to the confirmed number of loop axes, loop axis boundaries and loop axis steps. In addition, after the loop body is constructed, the variables of the loop body can be extracted, and the cache handling method can be determined according to the memory access mapping relationship in the optimized fusion operator, the cache size determined above, and the variables of the extracted loop body, so as to determine the data flow loop polyhedron structure based on the constructed loop body and the cache handling method.

[0044] It should be noted that the segmentation size for determining the loop axis step in this embodiment can be obtained from an external input tuning parameter set, or can be determined by calculation based on the chip's cache size and input and output information. In actual applications, the specific method for obtaining the segmentation size can be selected according to user needs, and this embodiment does not limit it.

[0045] Optionally, after obtaining the data flow loop polyhedron structure according to the cache size, the input and output information in the optimized fusion operator and the memory access mapping relationship, it also includes: identifying loop invariants for each data transfer operation in the cache transfer method, and externalizing the identified loop invariants that are not related to the loop; applying for an additional memory on the local cache for each data transfer operation to meet the requirement of synchronous calculation of historically transferred data when data is transferred to the memory; obtaining the number of running threads on the chip, and processing the input and output information in parallel based on the number of running threads.

[0046] Specifically, in this embodiment, after constructing the data flow loop polyhedron structure, a variety of general optimizations of data flows can be performed based on the data flow loop polyhedron structure of the fusion operator to significantly improve the operator performance. When performing general data flow optimization, loop invariant extraction, double cache optimization and parallel optimization can be performed. Among them, loop invariant extraction refers to the identification of loop invariants for each data handling operation in the cache handling method, and the extraction of loop invariants that are not related to the loop. In this embodiment, the number of operations that are not related to the loop invariant can be reduced by extracting the operations in the loop body. Double cache optimization refers to applying for another memory on the local cache of the multi-level storage chip for each data handling operation, so as to meet the need for synchronous calculation of the historically transported data when the data is subsequently transported to the memory of the multi-level storage chip. Therefore, the double cache optimization technology can be used to cache data handling and data calculation separately without affecting each other; parallel optimization refers to obtaining the number of running threads on the chip, that is, the number of processing units on the chip, and processing the input and output information in parallel based on the number of running threads. The efficiency of the fusion operator can be significantly improved through parallel optimization. Of course, in this embodiment, only loop invariant extraction, double buffer optimization and parallel optimization are used as examples for illustration, and in actual application, the specific optimization method of the general data flow optimization of the data flow loop polyhedron structure is not limited.

[0047] Step S1033, obtaining the calculation flow according to the sub-operator information in the optimized fusion operator.

[0048] Optionally, a calculation flow is obtained according to the sub-operator information in the optimized fusion operator, including: obtaining a pre-defined calculation flow template and a packaged vector instruction set that matches the multi-level storage chip, and obtaining the calculation flow according to the calculation flow template, the vector instruction set and the sub-operator information, or obtaining a code module database that matches the multi-level storage chip, and obtaining the calculation flow according to the code module database and the sub-operator information, wherein the code module database includes handwritten calculation flow code modules corresponding to each operator.

[0049] Optionally, a computation flow is obtained according to a computation flow template, a vector instruction set and sub-operator information, including: obtaining information of broadcast sub-operators in an optimized fusion operator, and filtering out a target computation flow template from the computation flow template according to the information of the broadcast sub-operators, wherein the information of the broadcast sub-operators includes existence and type of the broadcast sub-operators; filtering out target vector instructions matching each sub-operator from the vector instruction set according to the sub-operator type in the sub-operator information; obtaining a sequence relationship of each target vector instruction according to dependencies between sub-operators in the sub-operator information; and splicing each target vector instruction in the target computation flow template according to the sequence relationship to generate a computation flow.

[0050] Optionally, a calculation flow is obtained according to a code module database and sub-operator information, including: obtaining a target handwriting calculation flow code module corresponding to each sub-operator from the code module database according to the sub-operator type in the sub-operator information; obtaining a calling order of each target handwriting calculation flow code module according to the dependency relationship between sub-operators in the sub-operator information; and calling each target handwriting calculation flow code module according to the calling order to generate a calculation flow.

[0051] Specifically, in this embodiment, the calculation flow corresponding to the optimized fusion operator can also be obtained, and the calculation flow is determined specifically according to the sub-operator information in the optimized fusion operator, that is, the sub-operator type and the calculation dependency between the sub-operators. In this embodiment, there are two ways to obtain the calculation flow: the first way is to automatically generate the code related to the calculation flow in the code generation stage according to the pre-defined calculation flow template and the packaged vector instruction set; the second way is to directly call the handwritten calculation flow code module in the code module database to automatically generate the code related to the calculation flow.

[0052] In a specific implementation, the first method mentioned above is applicable to simple fusion operators of the computational flow, such as operators of the elementwise class. This generation method supports the use of vector instructions for data broadcasting in the generation of the computational flow, so the operators generated by this method achieve register-level fusion. Among them, in this implementation, the information of the broadcast sub-operator in the optimized fusion operator is obtained, and the information of the broadcast sub-operator includes the existence and type of the broadcast sub-operator, and the target computational flow template is screened from the computational flow template according to the information of the broadcast sub-operator. In this implementation, three types of computational flow templates are provided. The first type of computational flow template can handle fusion operators that do not perform data broadcasting or only perform scalar data broadcasting; the second type of computational flow template can handle fusion operators that need to perform [N, 1]->[N, M] type broadcasting on data; the third type of computational flow template can handle fusion operators that need to perform [1, M]->[N, M] type broadcasting on data. This classification is to generate broadcast codes at different levels of the cyclic polyhedron of the computational flow according to the type of broadcasting, so as to improve the performance of the computational flow code. Therefore, when it is determined that there is no broadcast sub-operator in the fusion operator, the first type of computing flow template is directly used as the target computing flow template; when it is determined that there is a broadcast sub-operator in the fusion operator and the type of the broadcast sub-operator is [N, 1]->[N, M], the second type of computing flow template is used as the target computing flow template; when it is determined that there is a broadcast sub-operator in the fusion operator and the type of the broadcast sub-operator is [1, M]->[N, M], the third type of computing flow template is used as the target computing flow template. In addition, in the present embodiment, different vector instruction sets are respectively packaged for different chips. Therefore, in the present embodiment, after determining the multi-level storage chip where the fusion operator is located, a packaged vector instruction set matching the multi-level storage chip can be obtained, wherein the vector instruction set includes vector instructions corresponding to each sub-operator. Therefore, in the present embodiment, the target vector instructions matching each sub-operator are screened out from the vector instruction set according to the sub-operator type. For example, the fusion operator includes sub-operator a, sub-operator b and sub-operator c, and the target vector instruction 1 matching sub-operator a, the target vector instruction 2 matching sub-operator b, and the target vector instruction 3 matching sub-operator c are screened out from the vector instruction set according to the type of each sub-operator. In addition, in this embodiment, the dependency relationship between sub-operators will also be obtained. For example, the output of sub-operator a is passed to sub-operator b, and the output of sub-operator b is passed to sub-operator c, then it is determined that sub-operator b depends on sub-operator a, and sub-operator c depends on sub-operator b. The corresponding order of obtaining the above three target instructions is: target vector instruction 1, target vector instruction 2, and target vector instruction 3.Therefore, when the target calculation flow template, target vector instructions and sequence relationship are determined, the target vector instruction 1, target vector instruction 2 and target vector instruction 3 can be spliced ​​in the target calculation flow template in sequence to generate a calculation flow. Of course, this embodiment only takes the example of three sub-operators in the fusion operator for illustration, and this embodiment does not limit the specific number of sub-operators in the fusion operator.

[0053] In another specific implementation, the second method mentioned above is suitable for scenarios where the computational flow is complex and the automatically generated operators may not meet the requirements. When the data flow completes the transfer of the data blocks currently involved in the computation to the local cache, the handwritten sub-operator interface is called in the order of the sub-operators in the fusion operator. At this time, the computational results of each sub-operator are stored in the local cache. Therefore, the fusion operator generated in this way is a fusion operator at the local cache level. Obviously, in terms of the efficiency of using intermediate results, since the register-level fusion operator can read the intermediate computational results from the register, faster access efficiency can be achieved. However, for complex sub-operators, the performance improvement of efficient handwritten implementation can cover the performance degradation caused by the access to the intermediate results. In this embodiment, different code module databases are created for different chips. Therefore, in this embodiment, after determining the multi-level storage chip where the fusion operator is located, the code module database matching the multi-level storage chip can be obtained, wherein the code module database includes the handwriting calculation flow code modules corresponding to each operator. In this embodiment, the target handwriting calculation flow code modules corresponding to each sub-operator are screened out from the code module database according to the sub-operator type. For example, the fusion operator includes sub-operator a, sub-operator b and sub-operator c, and the target handwriting calculation flow code module 1 matching sub-operator a, the target handwriting calculation flow code module 2 matching sub-operator b, and the target handwriting calculation flow code module 3 matching sub-operator c are screened out from the code module database according to the type of each sub-operator. In addition, in this embodiment, the dependency relationship between sub-operators is also obtained. For example, the output of sub-operator a is passed to sub-operator b, and the output of sub-operator b is passed to sub-operator c, then it is determined that sub-operator b depends on sub-operator a, and sub-operator c depends on sub-operator b. Therefore, the calling order of the above three target handwriting calculation flow code modules can be obtained as follows: target handwriting calculation flow code module 1, target handwriting calculation flow code module 2, and target handwriting calculation flow code module 3. Thus, the above three target handwriting calculation flow code modules are called according to the calling order to generate the calculation flow. Of course, in this embodiment, only the example of three sub-operators included in the fusion operator is used for illustration, and the specific number of sub-operators in the fusion operator is not limited in this embodiment.

[0054] Step S104, combining the cache size, the data flow loop polyhedron structure and the calculation flow to obtain the underlying code, and implementing the optimized fusion operator by running the underlying code.

[0055] Specifically, in this embodiment, after obtaining the cache size, data flow loop polyhedron structure and calculation flow, since the above three parts are mainly displayed in the nature of the code, the above three parts can be combined in a specified order to obtain the code. For example, by splicing in the order of cache size, data flow loop polyhedron structure, and calculation flow, the underlying code can be obtained, and the underlying code obtained in this embodiment matches the optimized fusion operator, so the optimized fusion operator can be realized by running the underlying code.

[0056] It should be noted that, in this embodiment, before running the underlying code, it is necessary to detect the underlying code, specifically to detect whether there are obvious errors in the underlying code, such as the case where the parameter value exceeds the hardware support capability, etc. Of course, this embodiment is only an example, and does not limit the specific scenario of error detection. In addition, a prompt message can be generated in the case of an error detection, so that the user can adjust the underlying code in time, thereby ensuring the accuracy of the underlying code.

[0057] This implementation converts the semantics of the high-level intermediate expression fusion operator into a high-level intermediate expression fusion operator, performs algebraic optimization to obtain the optimized fusion operator, and combines the obtained cache size, data flow loop polyhedron structure and calculation flow based on the information in the optimized fusion operator to automatically determine the underlying code corresponding to the fusion operator, and implements the fusion operator by running the underlying code without the need for manual writing by the user, thereby improving the efficiency and accuracy of the fusion operator implementation.

[0058] Embodiment 2

[0059] Figure 3 A flowchart of a fusion operator implementation method provided in the second embodiment of the present invention. This embodiment is based on the above embodiment. After obtaining the data flow loop polyhedron structure according to the cache size, the input and output information in the optimized fusion operator and the memory access mapping relationship, it also includes: when the optimized fusion operator includes a broadcast sub-operator and the tuning parameter set includes a user broadcast selection instruction, extract the cache transport method in the data flow loop polyhedron structure, and modify the cache transport method to broadcast the input and output data. Figure 3 As shown, the method includes:

[0060] Step S201 , performing semantic conversion on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain its own semantic fusion operator.

[0061] Optionally, semantic transformation is performed on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain its own semantic fusion operator, including: extracting the input and output information, sub-operator information and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip, wherein the sub-operator information includes the sub-operator type and the computational dependency between sub-operators; and obtaining the own semantic fusion operator based on the input and output information, sub-operator information and memory access mapping relationship.

[0062] Optionally, extracting input and output information, sub-operator information and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip, including: directly extracting input and output information and sub-operator information from the high-level intermediate expression fusion operator; determining whether the high-level intermediate expression fusion operator contains non-one-to-one sub-operators, if so, taking the non-one-to-one sub-operator as a typical operator, otherwise, taking any one-to-one sub-operator in the fusion operator as a typical operator; taking the memory access mapping relationship of the typical operator as the memory access mapping relationship of the high-level intermediate expression fusion operator.

[0063] Step S202, performing algebraic optimization on the own semantic fusion operator to obtain an optimized fusion operator.

[0064] Optionally, algebraic optimization is performed on the own semantic fusion operator to obtain an optimized fusion operator, including: obtaining typical operators in the own semantic fusion operator, and determining a dimension adjustment method of input and output information based on the typical operator, wherein the dimension adjustment method includes dimension quantity adjustment and dimension size adjustment; and dimension adjustment is performed on the input and output information of the own semantic fusion operator according to the dimension adjustment method.

[0065] Step S203 , extracting the segmentation size and transposition information from the externally transmitted tuning parameter set, and obtaining the cache size according to the input and output information, segmentation size and transposition information in the optimized fusion operator.

[0066] Step S204, obtaining a data flow loop polyhedron structure according to the cache size, the input and output information in the optimized fusion operator, and the memory access mapping relationship.

[0067] Optionally, a data flow loop polyhedron structure is obtained according to the cache size, input and output information in the optimized fusion operator, and the memory access mapping relationship, including: determining the number of loop axes according to the number of dimensions of the input and output information, determining the boundaries of each loop axis according to the dimensional size of the input and output information, and determining the step size of each loop axis according to the segmentation size; constructing a loop body according to the number of loop axes, the boundaries of the loop axes, and the step size of the loop axes; determining the cache handling method according to the memory access mapping relationship, the cache size, and the variables of the loop body; and determining the data flow loop polyhedron structure based on the loop body and the cache handling method.

[0068] Step S205 , when the optimized fusion operator includes the broadcast sub-operator and the tuning parameter set includes the user broadcast selection instruction, extract the cache transport mode in the data flow loop polyhedron structure, and modify the cache transport mode to broadcast the input data.

[0069] Optionally, the cache transfer method is modified to broadcast the input data, including: determining the data transfer operation in the cache transfer method, dividing the input data that needs to be broadcast in the data transfer operation to obtain local slices; obtaining the broadcast type of the broadcast sub-operator, broadcasting the local slices according to the broadcast type to obtain broadcast data, and extracting the data required for the current cycle from the broadcast data.

[0070] Specifically, in this embodiment, when the optimized fusion operator includes a broadcast operator and the tuning parameter set includes a user broadcast selection instruction, the input data will also be broadcasted through direct memory access (DMA). Among them, for the broadcast of scalar data, you can always consider using instructions in the calculation flow. For vector data broadcast, if it is completed in the calculation flow, you also need to consider data alignment. When the shape to be broadcasted is not an integer multiple of the shape to be aligned, there may be a situation where it cannot be processed or a large local memory needs to be occupied. On the other hand, completing data broadcasting in the calculation flow will result in more vector instructions in the core calculation code. When the fusion operator is a calculation-intensive operator, more vector instructions will further reduce the operator performance. This patent proposes a set of methods for broadcasting using DMA for two common types of data broadcasting: the first is broadcasting from the shape [N, 1] to [N. M], and the second is broadcasting from the shape [1, M] to [N, M]). The segmentation size of the fusion operator is denoted as tilingSize, and the loop variable of the cyclic polyhedron is denoted as loopIndex. Then the data parameters that need to be broadcast each time can be calculated using the above four parameters (N, M, tilingSize, loopIndex).

[0071] Each data broadcast requires three steps: the first step is to split the input data that needs to be broadcast in the data handling operation to obtain local slices. The calculation parameters required for the local slice slice include the slice offset and the slice size. The second step is to obtain the broadcast type of the broadcast sub-operator, broadcast the local slice according to the broadcast type to obtain the broadcast data, and the calculation parameters required to execute the local slice broadcast include the broadcast data shape local buffer shape. The third step is to extract the data required in the current loop from the broadcast data, and the calculation parameters required for the extraction include the extraction offset subview offset.

[0072] Step S206, obtaining a calculation flow according to the sub-operator information in the optimized fusion operator.

[0073] Optionally, a calculation flow is obtained according to the sub-operator information in the optimized fusion operator, including: obtaining a pre-defined calculation flow template and a packaged vector instruction set that matches the multi-level storage chip, and obtaining the calculation flow according to the calculation flow template, the vector instruction set and the sub-operator information, or obtaining a code module database that matches the multi-level storage chip, and obtaining the calculation flow according to the code module database and the sub-operator information, wherein the code module database includes handwritten calculation flow code modules corresponding to each operator.

[0074] Step S207 , combining the cache size, the data flow loop polyhedron structure and the calculation flow to obtain the underlying code, and implementing the optimized fusion operator by running the underlying code.

[0075] This implementation converts the semantics of the high-level intermediate expression fusion operator into its own semantic fusion operator, and performs algebraic optimization to obtain the optimized fusion operator. Based on the information in the optimized fusion operator, the obtained cache size, data flow loop polyhedron structure and calculation flow are combined to automatically determine the underlying code corresponding to the fusion operator, and the fusion operator is implemented by running the underlying code without the need for manual writing by the user, thereby improving the efficiency and accuracy of the fusion operator implementation.

[0076] Embodiment 3

[0077] Figure 4 This is a schematic diagram of the structure of a device for implementing a fusion operator provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a semantic conversion module 310, an algebraic optimization module 320, a data flow loop polyhedron structure and a calculation flow acquisition module 330 and a fusion operator implementation module 340.

[0078] Among them, the semantic conversion module 310 is used for performing semantic conversion on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain its own semantic fusion operator;

[0079] An algebraic optimization module 320 is used to perform algebraic optimization on the own semantic fusion operator to obtain an optimized fusion operator;

[0080] An information acquisition module 330 is used to acquire the cache size, data flow loop polyhedron structure and calculation flow corresponding to the optimized fusion operator;

[0081] The fusion operator implementation module 340 is used to combine the cache size, the data flow loop polyhedron structure and the calculation flow to obtain the underlying code, and implement the optimized fusion operator by running the underlying code.

[0082] Optionally, the semantic conversion module includes an information extraction unit for extracting input and output information, sub-operator information, and memory access mapping relationships of the high-level intermediate expression fusion operator on the multi-level storage chip, wherein the sub-operator information includes sub-operator types and computational dependencies between sub-operators;

[0083] The free semantic fusion operator acquisition unit is used to acquire the free semantic fusion operator based on input and output information, sub-operator information and memory access mapping relationship.

[0084] Optionally, the semantic conversion module includes an information extraction unit for directly extracting input and output information and sub-operator information from the high-level intermediate expression fusion operator;

[0085] Determine whether the high-level intermediate expression fusion operator contains a non-one-to-one type sub-operator. If so, take the non-one-to-one type sub-operator as a typical operator. Otherwise, take any one-to-one type sub-operator in the fusion operator as a typical operator.

[0086] The memory access mapping relationship of the typical operator is used as the memory access mapping relationship of the high-level intermediate expression fusion operator.

[0087] Optionally, the algebraic optimization module includes a dimension adjustment method acquisition unit, which is used to acquire a typical operator in the own semantic fusion operator, and determine the dimension adjustment method of the input and output information according to the typical operator, wherein the dimension adjustment method includes dimension quantity adjustment and dimension size adjustment;

[0088] The dimension adjustment unit is used to adjust the dimension of the input and output information of the own semantic fusion operator according to the dimension adjustment method.

[0089] Optionally, the information acquisition module includes a cache size acquisition unit, which is used to extract the segmentation size and transposition information from the externally input tuning parameter set, and acquire the cache size according to the input and output information, segmentation size and transposition information in the optimized fusion operator;

[0090] A data stream loop polyhedron structure acquisition unit, used for acquiring a data stream loop polyhedron structure according to a cache size, input and output information in an optimized fusion operator, and a memory access mapping relationship;

[0091] The computing flow acquisition unit is used to acquire the computing flow according to the sub-operator information in the optimized fusion operator.

[0092] Optionally, a data stream cyclic polyhedron structure acquisition unit is used to determine the number of cyclic axes according to the number of dimensions of the input and output information, determine the boundaries of each cyclic axis according to the size of the dimensions of the input and output information, and determine the step size of each cyclic axis according to the segmentation size;

[0093] Construct the loop body according to the number of loop axes, loop axis boundaries and loop axis steps;

[0094] Determine the cache transfer method based on the memory access mapping relationship, cache size, and loop body variables;

[0095] The data flow loop polyhedron structure is determined based on the loop body and cache handling method.

[0096] Optionally, the device further comprises a broadcast module, which is used to extract the cache handling mode in the data stream loop polyhedron structure when the optimized fusion operator includes a broadcast sub-operator and the tuning parameter set includes a user broadcast selection instruction;

[0097] Modify the cache handling method to broadcast input and output data.

[0098] Optionally, the broadcast module is further used to determine the data transfer operation in the cache transfer mode, and to divide the input data that needs to be broadcast in the data transfer operation to obtain local slices;

[0099] Get the broadcast type of the broadcast sub-operator, broadcast the local slice according to the broadcast type to obtain the broadcast data, and extract the data required in the current loop from the broadcast data.

[0100] Optionally, the device further comprises a general data flow optimization module, which is used to identify loop invariants for each data handling operation in the cache handling mode, and to extract the identified loop invariants that are not related to the loop;

[0101] For each data transfer operation, an additional memory is requested on the local cache to ensure that when data is transferred to the memory, the historical data that has been transferred can be calculated synchronously;

[0102] The number of running threads on the chip is obtained, and input and output information are processed in parallel based on the number of running threads.

[0103] The calculation flow acquisition unit is used to obtain a pre-defined calculation flow template and a packaged vector instruction set matching the multi-level storage chip, and obtain the calculation flow according to the calculation flow template, the vector instruction set and the sub-operator information.

[0104] Alternatively, a code module database matching the multi-level storage chip is obtained, and a calculation flow is obtained according to the code module database and sub-operator information, wherein the code module database includes a handwritten calculation flow code module corresponding to each operator.

[0105] Optionally, a computing flow acquisition unit is used to acquire information of a broadcast sub-operator in the optimized fusion operator, and filter out a target computing flow template from the computing flow template according to the information of the broadcast sub-operator, wherein the information of the broadcast sub-operator includes existence and type of the broadcast sub-operator;

[0106] Filtering target vector instructions matching each sub-operator from the vector instruction set according to the sub-operator type in the sub-operator information;

[0107] Obtaining the sequence relationship of each target vector instruction according to the dependency relationship between sub-operators in the sub-operator information;

[0108] In the target computing flow template, each target vector instruction is spliced ​​in a sequential order to generate a computing flow.

[0109] Optionally, a calculation flow acquisition unit is used to acquire a target handwritten calculation flow code module corresponding to each sub-operator from a code module database according to the sub-operator type in the sub-operator information;

[0110] Obtain the calling order of each target handwritten calculation flow code module according to the dependency relationship between sub-operators in the sub-operator information;

[0111] Each target handwritten calculation flow code module is called according to the calling order to generate the calculation flow.

[0112] The device for implementing the fusion operator provided in the embodiment of the present invention can execute the method for implementing the fusion operator provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0113] Embodiment 4

[0114] Figure 5 A schematic diagram of the structure of a computer device provided in Embodiment 4 of the present invention is shown in FIG. Figure 5 As shown, the computer device includes a processor 610, a memory 620, an input device 630, and an output device 640; the number of the processor 610 in the computer device can be one or more. Figure 5 A processor 610 is taken as an example; the processor 610, memory 620, input device 630 and output device 640 in the computer device can be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0115] The memory 620, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the method for implementing the fusion operator in the embodiment of the present invention. The processor 610 executes various functional applications and data processing of the computer device by running the software programs, instructions and modules stored in the memory 620, that is, implementing the above-mentioned method for implementing the fusion operator.

[0116] The memory 620 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 620 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 620 may further include a memory remotely arranged relative to the processor 610, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0117] The input device 630 may be used to receive input digital or character information and generate key signal input related to user settings and function control of the computer device. The output device 640 may include a display device such as a display screen.

[0118] Embodiment 5

[0119] Embodiment 5 of the present invention further provides a storage medium including computer executable instructions, which are used to execute a method for implementing a fusion operator when executed by a computer processor, including:

[0120] Perform semantic conversion on high-level intermediate expression fusion operators on multi-level storage chips to obtain self-owned semantic fusion operators;

[0121] Perform algebraic optimization on the own semantic fusion operator to obtain the optimized fusion operator;

[0122] Obtain the cache size, data flow loop polyhedron structure, and calculation flow corresponding to the optimized fusion operator;

[0123] The cache size, data flow loop polyhedron structure and calculation flow are combined to obtain the underlying code, and the optimized fusion operator is implemented by running the underlying code.

[0124] Of course, the storage medium containing computer executable instructions provided in an embodiment of the present invention, whose computer executable instructions are not limited to the above method operations, can also execute related operations in the method for implementing the fusion operator provided in any embodiment of the present invention.

[0125] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various embodiments of the present invention.

[0126] It is worth noting that in the above-mentioned embodiment of the compilation optimization device according to the computational graph, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0127] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for implementing a fusion operator, characterized in that: include: Perform semantic conversion on high-level intermediate expression fusion operators on multi-level storage chips to obtain self-owned semantic fusion operators; Performing algebraic optimization on the self-owned semantic fusion operator to obtain an optimized fusion operator; Obtaining the cache size, data flow loop polyhedron structure and calculation flow corresponding to the optimized fusion operator; The cache size, the data flow loop polyhedron structure and the calculation flow are combined to obtain the underlying code, and the optimized fusion operator is implemented by running the underlying code.

2. The method according to claim 1, characterized in that The step of performing semantic conversion on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain the own semantic fusion operator includes: Extracting input and output information, sub-operator information, and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip, wherein the sub-operator information includes sub-operator type and computational dependency relationship between sub-operators; The own semantic fusion operator is obtained based on the input and output information, the sub-operator information and the memory access mapping relationship.

3. The method according to claim 2, characterized in that The extracting the input and output information, sub-operator information and memory access mapping relationship of the high-level intermediate expression fusion operator on the multi-level storage chip includes: Directly extracting the input and output information and the sub-operator information from the high-level intermediate expression fusion operator; Determine whether the high-level intermediate expression fusion operator contains a non-one-to-one type sub-operator. If so, take the non-one-to-one type sub-operator as a typical operator. Otherwise, take any one-to-one type sub-operator in the fusion operator as a typical operator. The memory access mapping relationship of the typical operator is used as the memory access mapping relationship of the high-level intermediate expression fusion operator.

4. The method according to claim 2, characterized in that: The step of performing algebraic optimization on the own semantic fusion operator to obtain an optimized fusion operator includes: Acquire a typical operator in the self-owned semantic fusion operator, and determine a dimension adjustment method of the input and output information according to the typical operator, wherein the dimension adjustment method includes dimension quantity adjustment and dimension size adjustment; The input and output information of the own semantic fusion operator is dimensionally adjusted according to the dimension adjustment method.

5. The method according to claim 2, characterized in that: The obtaining and optimizing the cache size, data flow loop polyhedron structure and calculation flow corresponding to the fusion operator includes: Extracting the split size and transposition information from the externally input tuning parameter set, and obtaining the cache size according to the input and output information, the split size and the transposition information in the optimized fusion operator; Acquire the data flow loop polyhedron structure according to the cache size, the optimized input and output information in the fusion operator, and the memory access mapping relationship; The calculation flow is obtained according to the sub-operator information in the optimized fusion operator.

6. The method according to claim 5, characterized in that The obtaining the data flow cycle polyhedron structure according to the cache size, the optimized input and output information in the fusion operator, and the memory access mapping relationship includes: Determine the number of circulation axes according to the number of dimensions of the input and output information, determine the boundaries of each circulation axis according to the size of the dimensions of the input and output information, and determine the step size of each circulation axis according to the segmentation size; Construct a loop body according to the number of loop axes, the loop axis boundaries and the loop axis step length; Determine a cache transfer method according to the memory access mapping relationship, the cache size and the variables of the loop body; The data flow loop polyhedron structure is determined based on the loop body and the cache handling method.

7. The method according to claim 6, characterized in that After acquiring the data flow cycle polyhedron structure according to the cache size, the optimized input and output information in the fusion operator and the memory access mapping relationship, the method further includes: When the optimized fusion operator includes a broadcast sub-operator and the tuning parameter set includes a user broadcast selection instruction, extracting the cache transport mode in the data stream cycle polyhedron structure; The cache handling method is modified to broadcast the input data.

8. The method according to claim 7, characterized in that The modifying the cache handling method to broadcast the input data includes: Determine a data transfer operation in the cache transfer mode, and divide the input data that needs to be broadcast in the data transfer operation into local slices; The broadcast type of the broadcast sub-operator is obtained, the local slice is broadcasted according to the broadcast type to obtain broadcast data, and data required in the current cycle is extracted from the broadcast data.

9. The method according to claim 6, characterized in that After acquiring the data flow cycle polyhedron structure according to the cache size, the optimized input and output information in the fusion operator and the memory access mapping relationship, the method further includes: Identifying loop invariants for each data transfer operation in the cache transfer mode, and extracting the identified loop invariants that are not related to the loop; For each of the data transfer operations, a memory is additionally applied for in the local cache, so as to meet the requirement of synchronously calculating the historically transferred data when transferring data to the memory; The number of running threads on the chip is obtained, and the input and output information is processed in parallel based on the number of running threads.

10. The method according to claim 5, characterized in that The obtaining the calculation flow according to the sub-operator information in the optimized fusion operator includes: Acquire a predefined calculation flow template and a packaged vector instruction set matching the multi-level storage chip, and acquire the calculation flow according to the calculation flow template, the vector instruction set and the sub-operator information, Alternatively, a code module database matching the multi-level storage chip is obtained, and the calculation flow is obtained according to the code module database and the sub-operator information, wherein the code module database includes a handwritten calculation flow code module corresponding to each operator.

11. The method according to claim 10, characterized in that The obtaining the calculation flow according to the calculation flow template, the vector instruction set and the sub-operator information includes: Acquire information of the broadcast sub-operator in the optimized fusion operator, and filter out a target computing flow template from the computing flow template according to the information of the broadcast sub-operator, wherein the information of the broadcast sub-operator includes existence and type of the broadcast sub-operator; Filtering target vector instructions matching each sub-operator from the vector instruction set according to the sub-operator type in the sub-operator information; Acquire the sequence relationship of each of the target vector instructions according to the dependency relationship between the sub-operators in the sub-operator information; In the target computing flow template, each of the target vector instructions is spliced ​​according to the sequence relationship to generate the computing flow.

12. The method according to claim 10, characterized in that The obtaining the calculation flow according to the code module database and the sub-operator information includes: Acquire a target handwriting calculation flow code module corresponding to each sub-operator from the code module database according to the sub-operator type in the sub-operator information; Acquire the calling order of each of the target handwritten calculation flow code modules according to the inter-sub-operator dependency relationship in the sub-operator information; Each of the target handwritten calculation flow code modules is called according to the calling sequence to generate the calculation flow.

13. A device for implementing a fusion operator, characterized in that: include: The semantic conversion module is used to perform semantic conversion on the high-level intermediate expression fusion operator on the multi-level storage chip to obtain its own semantic fusion operator; an algebraic optimization module, used for performing algebraic optimization on the self-owned semantic fusion operator to obtain an optimized fusion operator; An information acquisition module, used to acquire the cache size, data flow cycle polyhedron structure and calculation flow corresponding to the optimized fusion operator; The fusion operator implementation module is used to combine the cache size, the data flow loop polyhedron structure and the calculation flow to obtain the underlying code, and implement the optimized fusion operator by running the underlying code.

14. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 12 is implemented.

15. A computer executable instruction storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

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