Adaptive quantization method for simulating memory computing system, adaptive quantization system and non-transitory machine readable medium

Abstract

One or more systems, methods, and / or machine-readable media are described herein for adaptively quantifying parameters intended to be deployed on a memory computing system based on a magnetic storage device. The method includes quantizing a parameter based on a conductance offset sensing process, a sensed conductance offset value, a conductance offset lookup table, and the parameter to be quantized. The parameter may be quantized by using values recorded in a lookup table, such as rounding to the closest value. The lookup table may be generated by a conductance offset sensing process that is capable of recording sensed conductance and associated device status of the magnetic storage device. A conductance offset sensing process may set a magnetic storage device (MMD) to different states, and a suitable device may be used to measure a conductance offset of the MMD caused by the state setting.

Description

Technical Field

[0001] The present disclosure relates to an adaptive quantization method for simulating an in-memory computing system, an adaptive quantization system, and a non-transitory machine-readable medium. Background Art

[0002] In-memory computing (IMC) architecture may provide a framework for system operations, such as running computations entirely within computer memory (eg, random access memory or RAM). Summary of the Invention

[0003] The following summary is presented to provide a basic understanding of one or more embodiments described herein. This summary is not intended to identify key or essential elements, or to describe any scope of a particular embodiment and / or any scope of the claims. The sole purpose of this summary is to present the concepts in a simplified form as a prelude to the more detailed description that will be presented later.

[0004] In one or more embodiments described herein, devices, systems, methods, and / or machine-readable media are described that can facilitate a framework for system operations, such as running computations entirely within computer memory (e.g., random access memory or RAM). For example, one or more embodiments described herein can employ a magnetic memory device (MMD) to adaptively quantize parameters of an analog IMC system.

[0005] According to an embodiment, an adaptive quantization method includes: quantizing parameters of a neural network at a magnetic memory device (MMD); performing a first calibration of the parameters, wherein the first calibration includes determining a first error resulting from a first forward computation pass using first data for the parameters, and backpropagating the first error to update the parameters, wherein the first calibration is performed using a noise level that is selectively increased added to the parameters prior to the first forward computation pass, and wherein performing the first calibration produces initial calibration parameters; determining a conductance error of the MMD based on a specific state of the MMD and based on a sensed conductance of the MMD, thereby producing a determined conductance offset of the MMD; and tuning the initial calibration parameters using the determined conductance offset of the MMD, thereby producing primary training parameters.

[0006] According to another embodiment, an adaptive quantization system includes: at least one memory storing computer-executable components; and at least one processor executing the computer-executable components stored in the at least one memory to perform operations, the operations including: determining a conductance error of a magnetic memory device (MMD) based on a specific state of the memory cell and based on sensed conductance of the memory cell of the MMD in the specific state, thereby generating a plurality of known conductance offsets of the MMD; and tuning a plurality of initial calibration parameters of a neural network, the tuning including mapping the plurality of initial calibration parameters to the memory cell using the plurality of known conductance offsets of the MMD, thereby generating a set of master training parameters.

[0007] According to yet another embodiment, a non-transitory machine-readable medium may include executable instructions that, when executed by a processor, facilitate performance of operations comprising: generating output data using a neural network based on input data obtained via the neural network, wherein parameters of the neural network have been calibrated, tuned, and quantized at memory cells of a magnetic memory device (MMD), and wherein in-memory computation is employed at the MMD to generate the output data; and, prior to quantizing the parameters at the MMD and prior to generating the output data, performing training of parameters by updating the parameters based on back propagation of an error determined using the parameters, and subsequently tuning the parameters based on a determined conductance shift of the memory cells of the MMD.

[0008] Compared to existing frameworks, the benefits of the above-described systems, non-transitory machine-readable media, and / or computer-implemented methods can include the ability to employ less hardware to support performance and throughput specifications, such as service level agreements (SLAs). That is, by employing the adaptive quantization methods described herein, greater data center consolidation, reduced capital costs, and / or reduced operational and / or infrastructure overhead can be achieved. Relatedly, by utilizing currently employed hardware and one or more embodiments described herein for adaptive quantization-based IMC, performance can be improved, thereby increasing the longevity of existing hardware and software.

[0009] Furthermore, one or more embodiments described herein may provide more accurate output and / or reduced (multiplication and accumulation) MAC errors in analog IMC systems compared to existing IMC approaches.

[0010] Another benefit of the above-described systems, non-transitory machine-readable media, and / or computer-implemented methods can be the ability to significantly reduce multiplications and accumulations (MACs) in analog in-memory computing systems. In one or more cases, deep neural network models optimized by the methods can maintain high accuracy despite significant memory device variations and circuit noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Many embodiments, objects and advantages of the present disclosure will become apparent from the following detailed description considered in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout.

[0012] Figure 1 An example diagram of an apparatus including an adaptive quantization system according to one or more implementations described herein is shown.

[0013] Figure 2 An example diagram of another apparatus including an adaptive quantization system according to one or more implementations described herein is shown.

[0014] Figure 3 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2 A schematic diagram of one or more processes performed by an adaptive quantization system.

[0015] Figure 4 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2 Schematic diagram of one or more pre-training processes performed by the adaptive quantization system.

[0016] Figure 5 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2 Schematic diagram of one or more conductance shift sensing processes performed by an adaptive quantization system.

[0017] Figure 6 A graphical illustration of conductance shifts in a memory device according to one or more embodiments described herein is provided.

[0018] Figure 7 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2 Schematic diagram of one or more adaptive quantization fine-tuning processes performed by an adaptive quantization system.

[0019] Figure 8 Provided are methods and methods according to one or more embodiments described herein. Figure 7 The corresponding non-ideal diagram.

[0020] Figure 9 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2 Graphical illustration of a 1-bit example of a parameter calibrated by a 3-bit conductance offset sensing process performed by the adaptive quantization system of FIG.

[0021] Figure 10 Provided are methods that can be implemented according to one or more embodiments described herein. Figure 2Graphical illustration of a 2-bit example of a parameter calibrated by a 3-bit conductance offset sensing process performed by the adaptive quantization system of FIG.

[0022] Figure 11 Also shown is a diagram according to one or more embodiments described herein. Figure 2 A processing flow of a method for using an adaptive quantization system.

[0023] Figure 12 shows a schematic diagram according to one or more embodiments described herein. Figure 2 Method of using the adaptive quantization system Figure 11 Continuation of the processing flow.

[0024] Figure 13 shows a schematic diagram according to one or more embodiments described herein. Figure 2 Another process flow of a method for using an adaptive quantization system.

[0025] Figure 14 shows a schematic diagram according to one or more embodiments described herein. Figure 2 Method of using the adaptive quantization system Figure 13 Continuation of the processing flow.

[0026] Figure 15 shows a schematic diagram according to one or more embodiments described herein. Figure 2 Another processing flow of a method for using an adaptive quantization system.

[0027] Figure 16 shows a schematic diagram according to one or more embodiments described herein. Figure 2 Method of using the adaptive quantization system Figure 15 Continuation of the processing flow.

[0028] Figure 17 A block diagram illustrating an exemplary, non-limiting operating environment in which one or more embodiments described herein may operate.

[0029] Figure 18 A block diagram illustrating an exemplary, non-limiting cloud computing environment according to one or more embodiments described herein is shown. Figure 2 The system may operate in or with the cloud computing environment. DETAILED DESCRIPTION

[0030] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. In addition, no one is expected to be bound by any expressed or implied information presented in the previous background or summary or this detailed description.

[0031] Overview

[0032] In-memory computing (also referred to herein as in-memory computing or IMC) refers to a framework for system operations such as running calculations entirely within computer memory (e.g., random access memory or RAM). RAM storage and parallel distributed processing are two fundamental pillars of IMC. That is, in-memory computing can be performed using an in-memory data grid (IMDG) to allow complex computations on large data sets to be performed across hardware clusters. That is, in one or more cases, IMC can be employed to perform complex computations across computer clusters, where the RAM of the computer clusters is pooled together. One or more memories in the computer cluster may include an in-memory grid (IMG) on which computations can be performed.

[0033] Therefore, the IMC can utilize the collective RAM space of the computer cluster to perform complex calculations.In one or more embodiments, the collective RAM space can be referred to as a shared storage space for shared memory data.

[0034] The use of an IMC can reduce and / or eliminate input / output (I / O) requirements and / or atomicity, consistency, isolation, and durability (ACID) transaction requirements of online transaction processing (OLTP) applications. The use of an IMC can exponentially speed up data access because data stored in RAM is instantly available, while data stored on disk may be limited by network and disk speeds. The IMC can cache large amounts of data, making response times very fast, and store session data, which can help achieve optimal performance. Therefore, the benefits of using an IMC can include reducing the latency common to such disk drives compared to accessing hard drives or solid-state drives (SSDs). That is, the use of an IMC can reduce and / or eliminate slow data access by relying at least in part on data stored in RAM.

[0035] The computations performed by the IMC can be managed by one or more of the computers with RAM for stored data space, and / or by one or more other computers. That is, the software on these one or more computers and / or one or more other computers can, where appropriate, separate (e.g., partition) a complex computation into two or more smaller tasks, which can be distributed to the other computers with RAM for stored data space. The two or more smaller tasks can be executed at least partially in parallel with each other.

[0036] IMC can be used in a variety of applications, including, but not necessarily limited to, financial assessment, weather tracking, geographic change monitoring, statistical surveys, counterparty risk assessment, etc. In fact, IMC can often be employed in situations where large amounts of data are analyzed, such as to determine one or more patterns that vary over a time horizon based on one or more parameters, which themselves may vary and / or evolve over a time horizon.

[0037] In other words, in-memory computing (IMC) architectures can aim to address both energy and speed bottlenecks, such as those found in conventional von Neumann architectures used in existing data-intensive artificial intelligence (AI) applications. One intensive operation in existing deep neural networks (DNNs) is large-scale generalized matrix multiplication (GEMM). While the development of modern AI applications is pushing hardware to its limits in both computation and data movement, IMC architectures are becoming increasingly important by addressing both computation and data access bottlenecks to further improve the performance of GEMMs on accelerated hardware.

[0038] Analog IMC can provide more efficient GEMM operations than digital accelerators. Based on Ohm's law and Kirchhoff's current law, analog multiplication and addition can be processed simultaneously by activating multiple columns in the memory crossbar of the RAM. In this way, the result can be directly obtained by sensing the output current or voltage of the memory crossbar. However, this computing scheme introduces a defect that requires the analog calculation to be robust to noise and variations in large crossbar arrays, where the large crossbar arrays can have various architectures due to hardware-induced variations. In addition to hardware-induced variations, compact, low-bit representation IMC networks are inherently less robust than large, full-precision IMC networks due to fewer redundant parameters. Therefore, scaling also provides a bottleneck factor in determining the noise tolerance of the hardware.

[0039] In-situ learning can be performed. This can include bringing software training to hardware, which can naturally include variations during training. This approach has been explored on static random access memory (SRAM)-based IMCs. However, for emerging non-volatile memories (eNVMs) such as phase change memory (PCM), resistive random access memory (RRAM), and / or magnetic random access memory (MRAM), the shorter endurance of such devices may render them incompatible with in-situ learning. Note that even though one can attempt to mitigate the variation problem by training DNNs ex-situ with some simulated variation based on statistical analysis to increase network robustness, existing frameworks still suffer from variation deficiencies.

[0040] In short, the decline of Moore's Law and the severe challenges of the memory bottleneck of the von Neumann architecture have limited the development of computing hardware in the fields of artificial intelligence and scientific computing. Therefore, considering the inherent changes of MRAM analog IMC, deeper hardware-software co-design may be needed and how co-design schemes can improve the performance and accuracy of existing IMC systems (e.g., IMC).

[0041] To address one or more of the above-mentioned deficiencies, one or more embodiments described herein provide a framework for sensing conductance shifts of memory cells of a memory device (eg, RAM) using a conductance shift sensing process.

[0042] One or more embodiments described herein may provide for the use of unique (e.g., typical and / or non-ideal) variations of magnetic storage devices for adaptive quantization of parameters in simulated IMC systems. In conjunction with this, a conductance offset sensing process may be performed to directly sense the conductance offset of each memory cell of a particular storage device. A device-specific conductance offset sensing lookup table may be generated based on the sensed device conductance offset.

[0043] The subsequent adaptive quantization process can adjust parameters in the analog IMC system based on the device-specific conductance offset sensing lookup table. This adaptive quantization process can minimize the IMC calculation errors (e.g., MAC errors) associated with the use of memory cells. The adaptive quantization methods discussed herein can be used with unique memory devices (e.g., non-ideal memory devices and / or memory devices with various hardware variations) that cannot be represented in existing quantization methods.

[0044] More specifically, using the adaptive quantization method discussed herein, quantization parameters stored in one or more memory cells of a memory device can be calibrated based on capturing the noise of the memory device to be used for IMC. The calibration process can be performed off-chip, without using on-chip write or read cycles. Compared to existing frameworks, this method can enable faster, more efficient, more accurate, and more hardware-friendly use of one or more of the frameworks described herein.

[0045] Therefore, a method for adaptively quantizing a set of parameters intended for deployment on an emulated in-memory computing system is provided. The method includes quantizing the parameters based on a pre-training process, a conductance offset sensing process, a sensed conductance offset value, generating a conductance offset lookup table, and iterating an adaptive quantization process.

[0046] In one or more embodiments, parameters can be quantized by rounding to the nearest value recorded in a lookup table. The lookup table can be obtained through a conductance offset sensing process that records the sensed conductance of each magnetic storage device and the associated device state. The conductance offset sensing process can set the storage device to different states and measure the conductance offset using the necessary equipment. This method can optimize parameters based on the sensed conductance offset value. Therefore, this method can significantly reduce the number of multiplications and accumulations (MACs) in an analog in-memory computing system. In one or more cases, a deep neural network model optimized using this method can maintain high accuracy despite storage device variations and high circuit noise.

[0047] Exemplary embodiments

[0048] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that, in various circumstances, one or more embodiments may be practiced without these specific details.

[0049] Furthermore, it will be understood that the embodiments depicted in one or more of the figures described herein are for illustration only, and similarly, the architecture of the embodiments is not limited to the systems, devices, and / or components depicted herein, nor to any particular order, connection, and / or coupling of the systems, devices, and / or components described herein. For example, in one or more embodiments, one or more of the devices, systems, and / or apparatuses may also include a reference operating environment (such as Figure 17 1700) is an operating environment depicted in FIG. 1700 and includes one or more computers and / or computing-based elements described herein. In one or more of the described embodiments, computers and / or computing-based elements may be used in conjunction with implementing one or more of the systems, apparatuses, devices, and / or computer-implemented operations depicted and / or described in conjunction with one or more of the figures.

[0050] As used herein, "data" may include metadata.

[0051] As used herein, "use" may include access.

[0052] As used herein, "cost" may refer to time, money, electricity, storage, memory, bandwidth, user entity labor, and the like.

[0053] As used herein, the terms "entity," "requesting entity," "user entity," and "managing entity" may refer to a machine, device, component, hardware, software, intelligent device, group, organization, individual, and / or person.

[0054] Turning now to the figures, one or more embodiments described herein may include one or more apparatuses, systems, devices, and / or system-implemented methods that may enable a process to provide for the use of adaptive quantization MMD support analysis performed by a NN. Generally, one or more embodiments may provide for faster, more efficient, more accurate, and more hardware-friendly use of one or more frameworks described herein compared to existing frameworks.

[0055] In general, an adaptive quantization system as described herein can employ conductance sensed from different states of an MMD to tune parameters quantized at the MMD. The MMD with the quantized and tuned parameters can then be employed to perform IMC using MMD input data (e.g., provided by a NN), thereby producing an MMD output used by the NN in providing an NN output.

[0056] See first Figure 1 , illustrates a non-limiting system 100 that may include one or more devices, systems, and / or apparatuses that can implement processes for providing use of MMD-enabled analysis of adaptive quantization performed by a NN. Generally, one or more embodiments can provide for faster, more efficient, more accurate, and more hardware-friendly use of one or more frameworks described herein compared to existing frameworks.

[0057] The non-limiting system 100 may include an adaptive quantization system 102 and a magnetic storage device (MMD) 180, either of which may include any one or more suitable types of components, machines, devices, facilities, equipment, and / or instruments that include a processor and / or are capable of effectively and / or operatively communicating with a wired and / or wireless network. Any one or more such suitable types of components may work in conjunction with another such suitable component of the same or different types, as described in detail below. All such embodiments are contemplated. For example, the adaptive quantization system 102 may include a server device, a computing device, a general-purpose computer, a special-purpose computer, a tablet computing device, a handheld device, a server-class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a cellular phone, a smartphone, a consumer appliance and / or instrument, an industrial and / or commercial device, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, and / or another type of device and / or computing device. Likewise, the adaptive quantization system 102 can be configured and / or executed on any suitable device, such as, but not limited to, a server device, a computing device, a general-purpose computer, a special-purpose computer, a tablet computing device, a handheld device, a server-class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a cellular telephone, a smartphone, a consumer appliance and / or instrument, an industrial and / or commercial device, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, and / or another type of device and / or computing device.

[0058] The adaptive quantization system 102 may be associated with a cloud computing environment, such as being accessible via the cloud computing environment. For example, the adaptive quantization system 102 may be associated with the following reference Figure 18 The example 1800 is associated with a cloud computing environment 1802 .

[0059] Note that the adaptive quantization system 102 is only relative to Figure 1 A brief description is given to provide an Figure 2 The following description of the more complex and / or extended adaptive quantization system 202 is provided. Figure 2 Non-limiting system 200 provides further details regarding processes that may be performed by one or more embodiments described herein.

[0060] Adaptive quantization system 102 may include at least memory 104, bus 105, processor 106, sensing component 112, and / or tuning component 116. Using these components and MMD 180, adaptive quantization system 102 may provide calibration and tuning of parameters to be quantized or requantized at the MMD, such as for subsequent use in an in-memory computing (IMC) process.

[0061] Sensing component 112 may generally determine conductance errors 194 of memory cells 186 of a magnetic memory device (MMD) 180 based on a particular state of the MMD 180 and based on sensed conductance 192 of the memory cells 186 in the particular state, thereby producing a plurality of known conductance offsets 196 of the MMD 180 .

[0062] The tuning component 116 can generally tune a plurality of initial calibration parameters 190 of the neural network model 150. The tuning can include mapping the plurality of initial calibration parameters 190 to the memory unit 186 using a plurality of known conductance offsets 196 of the MMD 180, thereby generating a set of primary training parameters 130.

[0063] As a result of the tuning, using MMD 180 for the IMC process may be more accurate and efficient than using raw parameters 187 alone (where raw parameters 187 are calibrated to obtain initial calibration parameters 190, which are then tuned to obtain primary training parameters 130).

[0064] See next Figure 2 , illustrates a non-limiting system 200 that may include one or more devices, systems, and / or apparatuses that can implement processes for providing use of MMD-enabled analysis of adaptive quantization performed by a NN. In general, one or more embodiments can provide for faster, more efficient, more accurate, and more hardware-friendly use of one or more frameworks described herein compared to existing frameworks.

[0065] The non-limiting system 200 may include an adaptive quantization system 202, a magnetic storage device (MMD) 280, and a neural network (NN) model 250, any of which may include any one or more suitable types of components, machines, devices, facilities, equipment, and / or instruments that include a processor and / or are capable of effectively and / or operatively communicating with a wired and / or wireless network. Any one or more such suitable types of components may work in conjunction with another such suitable component of the same or different types, as described in detail below. All such embodiments are foreseeable. For example, the adaptive quantization system 202 may include a server device, a computing device, a general-purpose computer, a special-purpose computer, a tablet computing device, a handheld device, a server-class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a cellular phone, a smart phone, a consumer appliance and / or instrument, an industrial and / or commercial device, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, and / or another type of device and / or computing device. Likewise, the adaptive quantization system 202 can be configured and / or executed on any suitable device, such as, but not limited to, a server device, a computing device, a general-purpose computer, a special-purpose computer, a tablet computing device, a handheld device, a server-class computing machine and / or database, a laptop computer, a notebook computer, a desktop computer, a cellular telephone, a smartphone, a consumer appliance and / or instrument, an industrial and / or commercial device, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, and / or another type of device and / or computing device.

[0066] The adaptive quantization system 202 may be associated with a cloud computing environment, such as being accessible via the cloud computing environment. For example, the adaptive quantization system 202 may be associated with the following reference Figure 18 The example 1800 is associated with a cloud computing environment 1802 .

[0067] One or more communications between one or more components of the non-limiting system 200 and / or the adaptive quantization system 202 may be provided by wired and / or wireless means, including but not limited to using a cellular network, a wide area network (WAN) (e.g., the Internet), and / or a local area network (LAN). Suitable wired or wireless technologies for providing communications may include, but are not limited to, Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), Third Generation Partnership Project (3GPP), Long Term Evolution (LTE), Third Generation Partnership Project 2 (3GPP2), Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or traditional telecommunication technologies, Session Initiation Protocol (SIP), RF4CE protocol, WirelessHART protocol, 6LoWPAN (Low Power Wireless LAN IPv6), Z-wave, ANT, Ultra-Wideband (UWB) standard protocol and / or other proprietary and / or non-proprietary communication protocols.

[0068] Adaptive quantization system 202 may include at least memory 204, bus 205, processor 206, calibration component 210, mapping component 211, sensing component 212, generation component 214, tuning component 216, update component 218, and / or execution component 220. Using these components and MMD 280, adaptive quantization system 202 may provide calibration and tuning of parameters to be quantized or requantized at the MMD, such as for subsequent use in an in-memory computing (IMC) process.

[0069] The discussion first turns to the processor 206 , memory 204 , and bus 205 of the adaptive quantization system 202 .

[0070] For example, in one or more embodiments, the adaptive quantization system 202 may include a processor 206 (e.g., a computer processing unit, a microprocessor, a classical processor, and / or the like). In one or more embodiments, components associated with the adaptive quantization system 202, as described herein with or without reference to one or more figures of one or more embodiments, may include one or more computer and / or machine readable, writable, and / or executable components and / or instructions that are executable by the processor 206 to provide performance of one or more processes defined by such components and / or instructions. In one or more embodiments, the processor 206 may include a calibration component 210, a mapping component 211, a sensing component 212, a generation component 214, a tuning component 216, an update component 218, and / or an execution component 220.

[0071] In one or more embodiments, the adaptive quantization system 202 may include a computer-readable memory 204 that may be operably connected to the processor 206. The memory 204 may store computer-executable instructions that, when executed by the processor 206, may cause the processor 206 and / or one or more other components of the adaptive quantization system 202 (e.g., calibration component 210, mapping component 211, sensing component 212, generation component 214, tuning component 216, update component 218, and / or execution component 220) to perform one or more actions. In one or more embodiments, the memory 204 may store computer-executable components (e.g., calibration component 210, mapping component 211, sensing component 212, generation component 214, tuning component 216, update component 218, and / or execution component 220).

[0072] As described herein, the adaptive quantization system 202 and / or its components may be communicatively, electrically, operatively, optically, and / or otherwise coupled to each other via a bus 205 to perform the functions of the non-limiting system 200, the adaptive quantization system 202, and / or one or more of its components and / or one or more components coupled thereto. The bus 205 may include one or more of a memory bus, a memory controller, a peripheral bus, an external bus, a local bus, and / or another type of bus that may employ one or more bus architectures. One or more of these examples of the bus 105 may be used to implement one or more embodiments described herein.

[0073] In one or more embodiments, the adaptive quantization system 202 can be coupled to one or more external systems (e.g., an electrical output production system (not shown), one or more output targets, an output target controller, etc.), sources, and / or devices (e.g., computing devices, communication devices, and / or the like), such as via a network (e.g., communicatively, electrically, operatively, optically, and / or the like). In one or more embodiments, one or more of the components of the adaptive quantization system 202 can reside in the cloud and / or can reside locally in a local computing environment (e.g., at a particular location).

[0074] In one or more embodiments, the adaptive quantization system 202 can be used as part of, include, or be included as part of a distributed system. That is, services, software, code, microservices, applications, etc. can be downloaded to one or more devices, each of which includes a display screen portion. One of the devices can serve as a centralized device (screen) or a parent device (screen). In one or more embodiments, a physical connection can be used to connect the systems.

[0075] In addition to the processor 206 and / or memory 204 described above, the adaptive quantization system 202 may also include one or more computer and / or machine readable, writable, and / or executable components and / or instructions that, when executed by the processor 206, may provide performance of one or more operations defined by such components and / or instructions.

[0076] The discussion next turns to additional components of the adaptive quantization system 202 (eg, calibration component 210 , mapping component 211 , sensing component 212 , generating component 214 , tuning component 216 , updating component 218 , and / or executing component 220 ).

[0077] First, it should be noted that in one or more embodiments, the calibration component 210, the mapping component 211, the sensing component 212, the generation component 214, the tuning component 216 and / or the update component 218 can be implemented independently without requiring one or more other components of the calibration component 210, the mapping component 211, the sensing component 212, the generation component 214, the tuning component 216 and / or the update component 218. Additionally and / or alternatively, the calibration component 210, the mapping component 211, the sensing component 212, the generating component 214, the tuning component 216 and / or the updating component 218 may be included by the high-level adaptive quantization component 203, one or more of the functions described below of the calibration component 210, the mapping component 211, the sensing component 212, the generating component 214, the tuning component 216 and / or the updating component 218 may be performed by the high-level adaptive quantization component 203, and / or the calibration component 210, the mapping component 211, the sensing component 212, the generating component 214, the tuning component 216 and / or the updating component 218 may be omitted, wherein the high-level adaptive quantization component 203 performs one or more of the functions described below of one or more omitted calibration components 210, mapping components 211, the sensing component 212, the generating component 214, the tuning component 216 and / or the updating component 218.

[0078] Therefore, we first turn briefly to Figure 3 , which shows a schematic diagram detailing a high-level view of a set of training and execution processes 300 that can be performed by the non-limiting system 200 for iterative training 310 of a set of parameters (e.g., including calibration and tuning of the set of parameters), and also for execution 350 of IMC using the output of the iterative training 310 at the MMD 280 (and / or any one or more other MMDs to be employed by one or more NN models 250).

[0079] That is, first, a noise-robust, MMD device-independent, general model (e.g., a set of parameters) can be trained using a variation-aware training (VAT) method. Second, calibration parameters can be fine-tuned using the device-specific conductance offset determined from the MMD 280. Thereafter, the parameters can be employed (e.g., quantized) at the MMD 280.

[0080] First go to Figure 3It is noted that, as is done in the existing framework, as an alternative, training the model / parameters specifically for each MMD device to be used would be both time-consuming and inefficient. To remedy these deficiencies, an iterative training process 310 can be used. These processes 310 can be performed for some or all of the memories 284 (e.g., 284A, 284B, 284C) of any one or more MMDs 180 employed by one or more neural network (NN) models 250. Applying this iterative training scheme, the fine-tuning training process for each device can be reduced to a few epochs or even one epoch, making fine-tuning very efficient. Furthermore, using this iterative training scheme, using calibrated and trained parameters in quantized form at the MMD 280 can allow for more accurate and efficient IMC compared to the existing framework.

[0081] Therefore, first turning to the calibration component 210, the component can generally initially calibrate the original parameters 287, which includes: gradually adding noise to the original parameters 287 to generate noisy original parameters; and then using back propagation to update the noisy original parameters, the initial calibration generating a plurality of initial calibration parameters 290. Note that the initial calibration parameters can be performed according to the same process regardless of the number of bits included by the original parameters 287. For example, briefly turning to Figure 3 , this same process may include: parameter quantization 311 at MMD 280; determining one or more errors 316 (e.g., training errors) corresponding to the parameters using a forward pass 312; and using a backward pass 318 (e.g., backpropagation). Note that each of these processes will be described in detail below. That is, the set of calibration processes may be the first part of the iterative training process 310, the second part of which may be a set of tuning processes, which will also be described in detail below. The set of calibration processes (also referred to herein as calibration processes) may be performed by calibration component 210 using neural network model 250.

[0082] That is, go to Figure 3 , the parameters of the NN model (e.g., NN model 250) can first be quantized (e.g., parameter quantization 311) to a low-bit representation to match the inference on the IMC hardware (including MMD 280). Then, the quantized parameters can be used to perform a forward pass (e.g., forward pass 312) using the quantized parameter data passed into the NN model 250, and the output 314 can be used to calculate the training error 316, such as the parameter-specific training error. In one or more cases, the backward pass 318 can be a conventional back-propagation-based gradient update process.

[0083] Note that calibration output using the MMD hardware (using the MMD device-specific conductance offset lookup table 298 ) may be used to determine parameter update values ​​322 for each parameter, as described in further detail below with respect to the sensing component 212 and the generating component 214 .

[0084] Note that in one or more implementations, the NN model 250 may be a deep NN.

[0085] The training process of the NN model parameters (e.g., the original parameters 287) can be iteratively performed several times until a termination condition is met. In one or more embodiments, the termination condition can be a specific number of iterations, a specific parameter increment threshold (e.g., the parameter change between iterations), and / or any other termination condition.

[0086] After the training process is completed, the parameters 287 for the DNN model can be converted into the state of the storage device 280 in the corresponding IMC system, thereby generating quantized parameters 288. In other words, the original parameters 287 can be stored as the state of the storage device 280 and represented by the conductance of the storage device 280.

[0087] Now go to Figure 4 , which shows a schematic flow chart 400 further detailing the calibration portion of the above-described pre-training process, which may be performed by the calibration component 210 using the neural network model 250. Figure 4 As shown in , first, the training data can be passed to the NN model 250 (e.g., step 410). The parameters can be clipped to the range [-1, 1] and quantized to low-bit representation values, such as to match inference on IMC hardware (e.g., step 412).

[0088] The parameters can then be modified with noise, such as Gaussian random noise (e.g., step 414), where the intensity increases in each of a set of target steps (e.g., step 416). For example, one can explore quantizing the network to gradually increase noise, such as simulated noise exhibited during on-chip inference, to increase the noise resistance of the parameters, and thus the noise resistance of the NN model 1250. In one or more embodiments of the calibration phase of the training process 310, ΔG T ~N(0,σ) can be used as training noise. Here, ΔG T represents the total conductance shift in the storage device, N is the normal distribution (Gaussian distribution), and σ is the standard deviation of the Gaussian distribution (also considered here as the strength of the training noise).

[0089] Since it is impossible to obtain a single optimal model that performs well for all types of MMD hardware variations, instead of training a noise-resistant quantization network with very good performance, this noise-based process can intentionally increase the noise to a very high level to obtain parameters for a general NN model 250 that can provide better accuracy after one tuning than the NN model 250 trained without noise.

[0090] A forward pass 312 (e.g., step 418) can be performed to calculate the input training data processed by the NN model 250. The target labels can then be used to calculate the errors 316, and the backpropagation / backward pass 318 can be used to update the parameters (e.g., step 420). This calibration portion of the training process can iterate for a specific set of target cycles until a termination condition is met. In one or more embodiments, the termination condition can be a specific number of iterations, a specific parameter increment threshold (e.g., the parameter change between iterations), and / or any other termination condition. Finally, the resulting initial calibration parameters 290 of the NN model 250 are recorded.

[0091] As a result of the calibration portion of the pre-training method, initial calibration parameters 290 are output as a prerequisite for the subsequent fine-tuning portion of the iterative training 310. Alternatively, further iterations may be performed via path 422, such as until a termination condition. In one or more embodiments, the calibration component 210 may make a determination (e.g., decision step 421) based on whether the termination condition is met or not met.

[0092] The pre-trained model can then be fine-tuned (e.g., a fine-tuning phase performed by the tuning component 216) to complete an iteration of iterative training 310.

[0093] However, in the discussion Figure 7 Before discussing the one or more fine-tuning processes in the present invention, the discussion first turns to the corresponding conductance offset sensing 500. Figure 5 and Figure 6 , which can result in the generation of a lookup table 298. In particular, generation of the lookup table 298 (e.g., by generation component 214) can be based on determining one or more device-specific conductance offsets 296 based on one or more sensed conductances 292 sensed at the MMD (e.g., in a direction from sensing component 212).

[0094] To set the stage for a discussion of determining one or more device-specific and / or memory cell-specific conductance shifts 296 , a description of a parameter mapping scheme that may be used by mapping component 211 for MMD 280 is first provided.

[0095] To describe the parameter mapping scheme, a ternary storage unit case is used as an example. Using the ternary storage unit case, an n-bit parameter (e.g., n is the number of bits of the parameter) can be stored in two storage units 286 (e.g., 286A, 286B, 286C). The real value of the corresponding weight W can be calculated using Equation 1.

[0096] Equation 1:

[0097] In Equation 1, G i is the conductance of each differential pair, and is normalized by the standard conductance value of each state to represent the signed integer value in Equation 1. Unlike other ternary bit weight mapping methods that use two's complement representation, this example uses an encoding method that is a variant of binary coded decimal (BCD) code as a digital representation scheme to implement an adaptive quantization algorithm on MMD hardware. That is, in a dual storage device architecture, each differential unit has three states with signed values. This encoding method only allows the conductance G of each bit of a single weight to have the same sign to avoid identical representations of the same value. For example, if W=1 and n=2, since both combinations can result in W=1 in Equation 1, the conductance states of the two differential pairs can be (G0, G + ) or (G + , G - ).

[0098] For simulated IMC, natural variations in the MMD hardware can change the equivalent conductance of each MMD. A The variable ΔG in Equation 2 can be rewritten as T The influence is of the form, where ΔG T and G are also normalized.

[0099] Equation 2:

[0100] The multi-bit input may be converted into a sequence of voltages applied to corresponding locations of the corresponding MMD 280, such as one bit per cycle to activate a computation in the corresponding memory cell 286. The partial outputs may then be summed with the corresponding bit offsets to obtain the final mapping result.

[0101] The most computationally intensive point multiplication and addition is to convert the same column W A The a-th bit of the m weights in [a] is multiplied by the b-th bit of the input IN [b], and the current on each storage unit 286 is automatically summed, such as by the mapping component 211. The result can then be converted to a digital value by the output circuit and stored in a temporary register. The output value of the input IN multiplied and summed with the m weights can be described by Equation 3.

[0102] Equation 3:

[0103] As a result of this parameter mapping method performed by mapping component 211 employing MMDs 280 , one or more conductance offsets 296 for each MMD 280 may be determined.

[0104] Note that in one or more embodiments, one or more processes of the mapping component 211 may be performed by the sensing component 212, or vice versa. For example, in one or more embodiments, the sensing component 212 or the mapping component 211 may be omitted, or the sensing component 212 and the mapping component 211 may be combined into a combined sensing / mapping component.

[0105] The description next turns to a general overview of a conductance offset sensing process 500 that may be performed by the sensing component 212. For example, the sensing component 212 may generally determine a conductance error 294 for a memory cell 286 of a magnetic storage device (MMD) 280 based on a particular state of the MMD 280 and based on a sensed conductance 292 of the memory cell 286 in the particular state. This may result in a plurality of known conductance offsets 296 for the MMD 280. Specifically, the sensed conductance values ​​292 for the memory cell 286 may include using the sensing component 212 with a suitable device having the MMD 280 in a plurality of selected states of the MMD 280, wherein each selected state of the MMD 280 may include at least one array of memory cells 286 of the MMD 280 set to the same conductance value of -1, 0, or 1. In one or more embodiments, the sensed conductance values ​​292 for the memory cell 286 in the selected state of the MMD 280 may include a combination of conductance values ​​292 of -1, 0, and 1.

[0106] Based on the conductance error 294 and the sensed conductance 292, as shown below, Figure 5 and Figure 6 As described in detail, the sensing component 212 can also output the sensed corresponding conductance offsets as a set of known conductance offsets 296. Using the set of known conductance offsets 296, the generating component 214 can generally generate a lookup table 298 that includes the set of known conductance offsets 296 in any suitable form (e.g., text, log, list, chart, matrix, data, metadata, etc.) corresponding to the array of memory cells 286 of the MMD 280. Ultimately, the lookup table 298 can be used to tune the initial calibration parameters 290 (e.g., Figure 7 A set of fine-tuning processes 700) are performed to produce a set of main training parameters 230.

[0107] Now go to Figure 5, which shows a flow chart further describing the conductance shift sensing process 500. First, the target storage device 280 can be set to a state (e.g., -1, 0, 1) according to the instruction of the sensing component 212 (e.g., step 510). The measurement circuit / device used by the sensing component 212 can sense the conductance value 292 of the state of the MMD 280 (e.g., step 512). The entire array can be set to G - , G0 and G + , to measure the conductance shift 296 for each state. This actively induced change in the memory device can cause a conductance shift with a standard conductance G STD A normal distribution centered at .

[0108] Note that the sensing accuracy may depend on the conductance offset sensing circuit hardware accuracy.

[0109] The sensed conductance 292 of the MMD 280 can be used to calculate a target conductance to calibrate the error 294 caused by the conductance offset in the state of the MMD 280 (e.g., step 514). A suitably biased conductance offset sensing circuit can sense this distribution, and the digital readout value represents the quantized distribution of the conductance offset. Subsequently, the offset conductance and state of each cell can be obtained. Finally, the equivalent weight represented by multiple cells (bits) can be calculated using Equation 2 and / or Equation 5.

[0110] First, in the existing quantization method framework, the arbitrary bit quantization of the proposed ternary coding weight can be given by the following formula:

[0111] Equation 5:

[0112] In Equation 5, x is a real weight, and Q is an n-bit quantized weight. Q will naturally be located at a position with 2 n+1 The round(x) function rounds x to the nearest integer near x. However, this quantization method only works well for ideal storage devices, which is a huge drawback of existing frameworks. That is, as described above, for analog calculations, due to device variations, even without any random cycles to circulate the simulated noise, the weights represented by the device conductance cannot be uniformly distributed within a given range. Therefore, the processes 500 and 700 described herein introduce adaptive quantization to fill the gap between existing quantization frameworks and the conductance of non-uniform devices (e.g., MMD 280).

[0113] First, the weight is calculated using Equation 6 to determine which region it is located in.

[0114] Equation 6:

[0115] Here, S is the number of states for quantizing weights, and the weight x is calculated by Equation 6 to determine which state section x falls into.

[0116] The real value of the quantized weight is then given in Equation 7 by checking the equivalent value of the conductance of the corresponding device in the sensed lookup table.

[0117] Equation 7: G = LUT(S)

[0118] A straight-through estimation method can be used in the backpropagation of the dynamic quantization process. When the NN model 250 is deployed for inference, the parameters only record the device state of the corresponding device. The device startup process can be naturally equated with a lookup table matching. Therefore, during training, the lookup table check process is the only step in dynamic quantization that requires additional data access costs.

[0119] Combined with the above, Figure 9 A 1-bit example of parameters calibrated by a 3-bit conductance offset sensing process is shown (e.g., graph 900). Instead of ideal values ​​(-1, 0, 1), these values ​​are calibrated by a conductance offset sensing process with 3-bit resolution. In this case, the equivalent weight value for each state is 7. The maximum error caused by device variation in the memory device is reduced by a factor of 7.

[0120] In addition, combined with the above, Figure 10 A 2-bit example of a parameter calibrated by a 3-bit conductance offset sensing process is shown (e.g., diagram 1000). Instead of the ideal value [-1, 1], these values ​​are calibrated using 7 values ​​by the conductance offset sensing process with 3-bit resolution. The conductance offset sensing process 500 (e.g., sensing component 212) identifies overlap between close values. As a result, the parameters 288 mapped to the storage device 280 can have significantly lower mapping errors.

[0121] Finally, the output of the conductance offset sensing circuit can be written as Equation 4.

[0122] Equation 4: ΔG = Quant(ΔG real )

[0123] Here, ΔG is the digital value of the conductance offset given by the conductance offset sensing circuit. Quantization errors caused by the conductance offset sensing circuit can lead to errors in the digital domain. In theory, a more accurate readout circuit can provide higher resolution and / or have fewer errors.

[0124] The calibrated conductance of the corresponding MMD 280 may be recorded in the device-specific conductance offset lookup table 298 (eg, step 516 ).

[0125] This sensing process may be iterated multiple times (e.g., step 518) until all states of one and / or all of the memory devices 280 in the IMC system are calibrated using the conductance offset sensing process 500. For example, at decision step 517, the sensing component 212 may determine whether there is another state to set the MMD 280 to (e.g., a state that the MMD 280 was not previously set to to complete steps 512 to 516 above). If so, the process 500 may be further iterated along step 518. If not, the process 500 may stop at step 519.

[0126] That is, after all array rows are sensed, a device-specific conductance shift lookup table (DSCS-LUT) as shown in Table 1 can be obtained for each IMC system.

[0127] Table 1

[0128]

[0129] Next, Figure 6 A graph 600 is provided of the conductance shift in a set of memory devices 280. For a particular state, the target conductance can be considered an ideal value and reference for the sensing circuit. Non-idealities in the memory devices can result in varying conductances between different devices. Therefore, the conductance shift sensing process 500 is designed to measure the non-idealities of each memory device. The conductance shift is shown as a percentage in graph 600, but could also be shown as an absolute conductance value and / or a conductance difference. Logistic regression in graph 600 demonstrates that the conductance shift follows a Gaussian distribution. The magnitude of the variation between devices can be related to manufacturing technology and device characteristics.

[0130] Next, go to Figure 3 , then go to Figure 7 and Figure 8 , the pre-trained NN model 250 / initial calibration parameters 290 can then be fine-tuned through adaptive quantization combined with the chip-specific conductance offset 296 and lookup table 298 output from the conductance offset sensing process 500.

[0131] The description first turns to a general overview of the fine tuning process 700. For example, the tuning component 216 ( Figure 2 ) can employ a lookup table 298 and can tune a plurality of initial calibration parameters 290 of the neural network model 250. The tuning performed by the tuning component 216 can include mapping the plurality of initial calibration parameters 290 to the memory unit 286 using a plurality of known conductance offsets 296 of the MMD 280 at the lookup table 298, thereby generating a set of primary training parameters 230.

[0132] Figure 3This fine-tuning process is represented as part of iterative training 310. Figure 3 , IMC output 249 may be a known conductance offset 296. Using known conductance offset 296, tuning component 216 may perform tuning 320.

[0133] That is to say, next, Figure 7 A flow chart of an adaptive quantization fine-tuning process 700 is provided. At this stage, the NN model 250 has converged to a local minimum that provides good noise immunity with reduced precision. Therefore, only a few epochs may be required to requantize and optimize the NN model 250 for a particular device. Although existing methods can be used to fill the accuracy gap between low-bit quantized networks and full-precision networks, the low-bit parameters are naturally in a lower dimensional space, which provides less ability to fit the training data. The adaptive quantization fine-tuning process 700 described herein performs non-uniform quantization of values, which increases the complexity of the quantization parameter space and can potentially increase the performance of the DNN model despite only recovering the accuracy lost due to the changes.

[0134] At step 710, pre-trained model parameters (e.g., initial calibration parameters 290) can be loaded for fine-tuning. That is, training data can first be received via path 728, and hardware non-idealities 715 can be added to the pre-trained NN model 250 (steps 712 and 714). Then, at step 716, the initial calibration parameters 290 can be adaptively quantized according to the device-specific conductance offset lookup table 717. At step 718, the calibrated parameters can be used for forward calculations. At step 720, the output of the NN model 250 can be used to calculate the training error, and the training error can be back-propagated to update the parameters (e.g., parameter update 322).

[0135] This fine-tuning portion of the iterative training process 310 may iterate for several cycles, such as until the error is reduced to a target value and / or until a maximum training cycle is achieved. For example, one or more of these factors may be evaluated by the tuning component 216 at decision step 721 .

[0136] Next, Figure 8 Provided is a diagram showing Figure 7 FIG800 is a graph showing the non-idealities of the corresponding MMDs mentioned in FIG80. The x-axis is the ideal MAC value obtained by randomly combining the inputs and parameters in the storage device. The y-axis is the measured MAC value that can be obtained by measuring the output of the IMC system. Due to non-idealities in the IMC system and variations in the MMD 280, the measured output may differ from the ideal value. In this case, the measured MAC value may be shown as follows: Figure 8The distribution 802 shown in . Overlap between nearby MAC values ​​may cause calculation errors because nearby MAC values ​​will mix and cause fault sensing in the output circuit.

[0137] Go to again Figure 2 In one or more embodiments, the updating component 218 can guide further iterative training of the set of primary training parameters based on a fine-tuning process using the output of the tuning component 216, including employing back-propagation using the determined errors to update the plurality of primary training parameters, thereby generating a plurality of intermediate calibration parameters 232. Additionally and / or alternatively, in one or more embodiments, the updating component 218 can use the plurality of known conductance offsets 296 to guide further iterative training of the plurality of intermediate calibration parameters 232, thereby generating a set of secondary training parameters 234. In one or more cases, these additional iterative processes can be performed using a decision step 358 performed by the updating component 218, such as based on a specific re-iteration frequency and / or based on an indication by a user entity using a computer device communicatively coupled to the non-limiting system 200.

[0138] Then go to Figure 2 And also go to Figure 3 , the execution component 220 can use the input data (e.g., Figure 3 The MMD input data 248 (also referred to as IMC input 248 in the example) is used to guide the operation of the MMD 280 (e.g., the execution 350 of the IMC) for on-chip inference at the MMD 280 to generate output data 249 (e.g., Figure 3 On-chip inference relies solely on trained data. Therefore, once the parameters are stored in storage device 280, no further on-chip write cycles are required. Output data 249 is typically based on a plurality of known conductance shifts 296 of memory cells 286 of MMD 280 and employs a plurality of secondary training parameters 234 or primary training parameters 230 quantized at MMD 280.

[0139] In one or more embodiments, the MMD output data 249 can be used as NN input data 251 and / or can be converted into NN input data 251 (e.g., into a form commensurate with the application of the NN model 250). The neural network output data 252 generated by employing the plurality of secondary training parameters 234 or primary training parameters 230 that have been quantized at the MMD 280 has a higher level of accuracy than other neural network output data generated by employing only the original parameters 287 / quantized parameters 288 at the neural network.

[0140] In fact, exemplary experimental results are shown in Table 2. With respect to Table 2, the accuracy of the output inference can be based on the converted input and stored parameters on the IMC system. The accuracy of the original model that has not been optimized by any method may be significantly affected by the noise intensity of the storage device in the IMC system. By applying the iterative training process 310 discussed in this article, the NN model 250 can be made more robust than the original NN model. The resulting fine-tuned NN model 250 can also significantly improve the inference accuracy. That is, in one or more embodiments, the accuracy loss can be reduced to an acceptable value by applying adaptive quantization.

[0141] Table 2

[0142]

[0143] Example usage

[0144] Now go to Figure 11 and Figure 12 , shows a flowchart of an exemplary, non-limiting method 1100 that can facilitate a process to adapt and perform in-memory computing. For the sake of brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0145] See first Figure 11 Operation 1102 of the non-limiting method 1100 may include initially calibrating raw parameters (e.g., raw parameters 287) by a system operably connected to a processor (calibration component 210), including: gradually adding noise to the raw parameters to generate noisy raw parameters, and then using backpropagation to update the noisy raw parameters, the initial calibration generating multiple initial calibration parameters (e.g., initial calibration parameters 290).

[0146] At operation 1104 , the non-limiting method 1100 may include performing, by the system (eg, calibration component 210 ), an initial calibration of the raw parameters according to the same process regardless of the number of bits contained in the raw parameters.

[0147] At operation 1106, non-limiting method 1100 may include determining, by a system (e.g., sensing component 212), a conductance error (e.g., conductance error 294) of a memory cell (e.g., memory cell 286) of the MMD based on a particular state of the MMD and based on a sensed conductance (e.g., sensed conductance 292) of the memory cell in the particular state, thereby generating a plurality of known conductance offsets (e.g., conductance offset 296) of the MMD.

[0148] At operation 1108, the determining (operation 1106) of the non-limiting method 1100 may include sensing, by a system (e.g., sensing component 212), conductance (sensed conductance) values ​​of the memory cells in a plurality of selected states of the MMD, wherein each selected state of the MMD includes setting memory cells of the array of the MMD to the same conductance value of -1, 0, or 1.

[0149] In one or more embodiments, the conductance value of the memory cell in the selected state of the MMD includes a combination of conductance values ​​of -1, 0, and 1 for the memory cell.

[0150] At operation 1110 , the determining (operation 1106 ) of the non-limiting method 1100 may include sensing, by a system (eg, sensing component 212 ), respective conductance shifts of memory cells of the MMD and outputting the sensed respective conductance shifts as a set of known conductance shifts.

[0151] At operation 1112 , non-limiting method 1100 may include generating, by the system (eg, generation component 214 ), a lookup table (eg, lookup table 298 ) of a set of known conductance offsets corresponding to the memory cell array of the MMD, wherein the lookup table is used to tune initial calibration parameters.

[0152] At operation 1114, non-limiting method 1100 may include tuning, by a system (e.g., tuning component 216), a plurality of initial calibration parameters of a neural network (e.g., neural network model 250), the tuning comprising mapping the plurality of initial calibration parameters to a memory cell using a plurality of known conductance offsets of the MMD, thereby generating a set of primary training parameters (e.g., primary training parameters 230).

[0153] At operation 1116, the non-limiting method 1100 may include determining, by the system (e.g., update component 218), whether to perform additional parameter training, the additional parameter training comprising further calibrating a set of primary training parameters and then tuning the results of the further calibration. If so, the non-limiting method 1100 may proceed to operation 1118. If not, the non-limiting method 1100 may proceed to operation 1122 using the primary training parameters.

[0154] At operation 1118, the non-limiting method 1100 may include further iteratively training, by the system (e.g., update component 218), a set of primary training parameters based on the tuning, the further iterative training including updating the plurality of primary training parameters using back propagation (e.g., back propagation 318) using the determined error (e.g., error 316) to generate a plurality of intermediate calibration parameters (e.g., plurality of intermediate calibration parameters 232).

[0155] At operation 1120 , the non-limiting method 1100 may include tuning, by the system, a plurality of intermediate calibration parameters using the plurality of known conductance offsets to generate a set of secondary trained parameters (eg, the secondary trained parameters 234 ).

[0156] At operation 1122, the non-limiting method 1100 may include using, by a system (e.g., execution component 220), at the MMD, input data for on-chip inference to guide operation of the MMD, thereby generating output data from the MMD, the output data being based on a plurality of known conductance offsets of memory cells of the MMD and employing a plurality of quadratic training parameters.

[0157] At operation 1124 , the non-limiting method 1100 may include using, by the system (eg, the execution component 220 ), the output from the MMD based on the plurality of primary training parameters to guide operation of the neural network.

[0158] In one or more embodiments, neural network output data (e.g., neural network output data 252) generated by employing multiple secondary trained parameters at the neural network has a higher level of accuracy than other neural network output data generated by employing original untrained parameters at the neural network.

[0159] Now go to Figure 13 and Figure 14 , shows a flowchart of another example (non-limiting method 1300) that can facilitate a process to adapt and perform in-memory computing. For the sake of brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0160] See first Figure 13 At operation 1302 of the non-limiting method 1300 , the non-limiting method 1300 may include quantizing, by a system operably coupled to a processor (e.g., the tuning component 216 ), neural network parameters (e.g., of the NN model 250 ) at a magnetic storage device (MMD) (e.g., the MMD 280 ).

[0161] At operation 1304, the non-limiting method 1300 may include performing, by a system operably coupled to a processor (calibration component 210), a first calibration of the parameters using the MMD, wherein the first calibration includes performing one or more series of determining a first error (e.g., error 316) and backpropagating (e.g., backpropagating 318) the first error to update the parameters, the first error resulting from a first forward computation pass (e.g., forward computation pass 312) using first data for the parameters, wherein the first calibration is performed using a selectively increasing noise level added to the parameters prior to the first forward computation pass, and wherein performing the first calibration results in initial calibration parameters (e.g., initial calibration parameters 290).

[0162] At operation 1306 , the non-limiting method 1300 may include performing, by the system (eg, calibration component 210 ), a first calibration of the parameter according to the same process regardless of the number of bits included in the parameter.

[0163] At operation 1308 , the non-limiting method 1300 may include performing a first calibration by the system, wherein the noise employed simulates the simulated noise of an inference process performed on the chip using the MMD.

[0164] At operation 1310, non-limiting method 1300 may include determining, by a system (e.g., sensing component 212), a conductance error of the MMD (e.g., conductance error 294) based on a particular state of the MMD and based on a sensed conductance of the MMD (e.g., sensed conductance 292), thereby producing a determined conductance offset (e.g., conductance offset 296) of the MMD.

[0165] At operation 1312 , the non-limiting method 1300 may include tuning, by the system (eg, the tuning component 216 ), initial calibration parameters using the determined conductance shift of the MMD to generate primary training parameters (eg, the primary training parameters 230 ).

[0166] At operation 1314, the non-limiting method 1300 may include performing, by the system (e.g., the update component 218 and / or the calibration component 210), a second calibration of the initial calibration parameters using the MMD, wherein the second calibration includes performing one or more second series of determining second errors and back-propagating the second errors to update the initial calibration parameters, the second errors being generated by a second forward computation pass of the first training data or the second training data using the initial calibration parameters, wherein performing the second calibration produces secondary training parameters, and wherein performing the second calibration improves the accuracy of the output data of the in-memory computation process relative to performing the first calibration.

[0167] At operation 1316 , the non-limiting method 1300 may include performing, by the system (e.g., calibration component 210 and tuning component 216 ), a second iteration of the first calibration relative to a second MMD instead of the first MMD, determining and tuning a second set of neural network parameters, thereby generating a second set of primary training parameters.

[0168] At operation 1318 , the non-limiting method 1300 may include employing, by the system (executing component 220 ), the second set of primary training parameters quantized at the second MMD and the primary training parameters quantized at the first MMD to evaluate the experimental data using the first MMD and the second MMD.

[0169] At operation 1320 , the non-limiting method 1300 may include analyzing, by a system (eg, the neural network model 250 ), the MMD output (eg, the MMD output data 249 ) based on the experimental data to generate a neural network output (eg, the NN output data 252 ).

[0170] Now go to Figure 15 and Figure 16 , shows a flowchart of another example (non-limiting method 1500) that can facilitate a process to adapt and perform in-memory computing. For the sake of brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0171] See first Figure 15 At operation 1502, non-limiting method 1500 may include performing, by a device including a processor (e.g., processor 206), training parameters (e.g., original parameters 287) of a neural network (e.g., neural network model 250) by updating the parameters based on backpropagation of errors determined using the parameters, and subsequently tuning the parameters based on a determined conductance offset (e.g., conductance offset 296) of a memory cell (e.g., memory cell 286) of a magnetic memory device (MMD) (e.g., MMD 280).

[0172] At operation 1504 , the non-limiting method 1500 may include iteratively training, by a processor, the tuned parameters (tuning parameters), the iterative training including: updating the tuning parameters, performing back propagation of additional errors determined using the tuning parameters; and subsequently retuning the tuning parameters based on the determined conductance shift.

[0173] At operation 1506 , the non-limiting method 1500 may include performing, by the processor, a calibration of the training, wherein the corresponding error is determined based on the noise level of the added parameter.

[0174] At operation 1508 , the non-limiting method 1500 may include generating, by the processor, a conductance shift of a memory cell of the MMD by setting a state of the MMD and sensing conductance of the memory cell of the MMD, thereby generating a determined conductance shift.

[0175] At operation 1510 , the non-limiting method 1500 may include setting, by a processor, a state of the MMD by setting an array of memory cells of the MMD to the same conductance of −1, 0, or 1 before sensing the conductance of the memory cells.

[0176] At operation 1512 , the non-limiting method 1500 may include employing in-memory computations by a processor at the MMD to generate output data (eg, the MMD output data 249 ).

[0177] At operation 1514 , the non-limiting method 1500 may include generating, by the processor, neural network output data (e.g., NN output data 252 ) based on input data obtained via the neural network (e.g., NN input data 251 ), using the neural network and based on the MMD output data.

[0178] In summary, one or more systems, methods, and / or machine-readable media are described herein for adaptively quantizing a parameter intended for deployment on an in-memory computing system based on a magnetic memory device. The method includes quantizing the parameter based on a conductance offset sensing process, a sensed conductance offset value, a conductance offset lookup table, and the parameter to be quantized. The parameter can be quantized using values ​​recorded in the lookup table, such as by rounding to the nearest value. The lookup table can be generated by a conductance offset sensing process that can record the sensed conductance of the magnetic memory device and the associated device state. The conductance offset sensing process can set the magnetic memory device (MMD) to different states, and suitable devices can be used to measure the conductance offset of the MMD caused by the state setting.

[0179] Compared to existing frameworks, the benefits of the above-described systems, non-transitory machine-readable media, and / or computer-implemented methods can include the ability to employ less hardware to support performance and throughput specifications, such as service level agreements (SLAs). That is, by employing the adaptive quantization methods described herein, greater data center consolidation, reduced capital costs, and / or reduced operational and / or infrastructure overhead can be achieved. Relatedly, by utilizing currently employed hardware and one or more embodiments described herein for adaptive quantization-based IMC, performance can be improved, thereby increasing the longevity of existing hardware and software.

[0180] Furthermore, one or more embodiments described herein may provide more accurate output and / or reduced (multiplication and accumulation) MAC errors in analog IMC systems compared to existing IMC approaches.

[0181] Another benefit of the above-described systems, non-transitory machine-readable media, and / or computer-implemented methods can be the ability to significantly reduce multiplications and accumulations (MACs) in analog in-memory computing systems. In one or more cases, deep neural network models optimized by the methods can maintain high accuracy despite significant memory device variations and circuit noise.

[0182] In practice, practical applications of the systems, computer-implemented methods, and / or computer program products described herein can use the framework described herein to measure conductance at a memory cell of a memory device and update parameter data stored at the memory cell based on the measured conductance. Thus, utilization of memory cells for in-memory computing operations can be optimized based at least on the conductance measurement. Overall, such computerized tools can constitute concrete and tangible technical improvements in various fields using IMC (e.g., neural network applications), but are not limited thereto.

[0183] One or more embodiments described herein may be inherently and / or inextricably linked to computer technology and cannot be implemented outside a computing environment. For example, one or more processes performed by one or more embodiments described herein may provide program and / or program instruction execution more efficiently or even more feasible than existing systems and / or technologies that lack such methods, such as operations relative to in-memory computing. Systems, computer-implemented methods, and / or computer program products that implement the performance of these processes have great utility in various fields using IMC (e.g., neural network use), but are not limited thereto, and cannot be practically implemented in a senseable manner outside a computing environment. In fact, IMC itself is and / or involves the use of data stored in storage cells of a storage device, and one or more adaptive quantization processes described herein involve the operation of MMD and the measurement of the conductance output by the MMD.

[0184] One or more embodiments described herein may employ hardware and / or software to solve problems that are highly technical, non-abstract, and not executable as a set of human mental activities. For example, a person, or even thousands of people, cannot effectively, accurately, and / or efficiently electronically manipulate and measure conductance at an MMD, or manipulate an MMD for IMC, as one or more embodiments described herein can provide. Furthermore, neither the human mind nor a person with a pen and paper can effectively electronically implement, provide, and / or execute such a process as performed by one or more embodiments described herein.

[0185] In one or more embodiments, one or more of the processes and / or frameworks described herein can be executed by one or more special-purpose computers (e.g., special-purpose processing units, special-purpose classical computers, and / or another type of special-purpose computer) to perform defined tasks related to one or more of the above-mentioned technologies. One or more embodiments described herein and / or components thereof can be used to solve new problems arising from advances in the above-mentioned technologies, cloud computing systems, computer architectures, and / or other technologies.

[0186] One or more embodiments described herein may be fully operational to perform one or more other functions (eg, fully powered on, fully executed, and / or another function) while also performing one or more of the one or more operations described herein.

[0187] To provide additional overview, a list of embodiments and their features is provided next.

[0188] A system includes: at least one memory storing computer-executable components; and at least one processor executing the computer-executable components stored in the at least one memory to perform operations, the operations including: determining a conductance error of a memory cell of a magnetic memory device (MMD) based on a particular state of the MMD and based on sensed conductance of the memory cells of the MMD in the particular state, thereby generating a plurality of known conductance offsets of the MMD; and tuning a plurality of initial calibration parameters of a neural network, the tuning including mapping the plurality of initial calibration parameters to the memory cells using the plurality of known conductance offsets of the MMD, thereby generating a set of master training parameters.

[0189] The system of claim 1 , wherein determining the known conductance offsets of the MMD comprises sensing corresponding conductance offsets of memory cells of the MMD and outputting the sensed corresponding conductance offsets as a set of known conductance offsets; and generating a lookup table of a set of known conductance offsets corresponding to the memory cell array of the MMD, wherein the lookup table is used to tune initial calibration parameters.

[0190] The system of any preceding paragraph, wherein determining the known conductance offset of the MMD comprises sensing conductance values ​​of memory cells in a plurality of selected states of the MMD as the sensed conductance, wherein each selected state of the MMD comprises memory cells of an array of the MMD set to the same conductance value of -1, 0, or 1.

[0191] The system of any preceding paragraph, wherein the conductance value of the memory cell in the selected state of the MMD comprises a combination of conductance values ​​of -1, 0, and 1 for the memory cell.

[0192] A system according to any of the preceding paragraphs, wherein the operation further comprises initially calibrating the original parameters, comprising: incrementally adding noise to the original parameters to generate noisy original parameters; and subsequently updating the noisy original parameters using back propagation, the initial calibration generating a plurality of initial calibration parameters.

[0193] The system of any preceding paragraph, wherein initially calibrating the raw parameters is performed according to the same process regardless of the number of bits included in the raw parameters.

[0194] The system of any preceding paragraph, wherein the operations further comprise: further iteratively training a set of primary training parameters based on the tuning, comprising employing back propagation using the determined errors to update the plurality of primary training parameters to generate a plurality of intermediate calibration parameters.

[0195] The system of any preceding paragraph, wherein the operations further comprise: further iteratively training the plurality of intermediate calibration parameters using the plurality of known conductance offsets to generate a set of secondary trained parameters.

[0196] The system of any preceding paragraph, wherein the operations further comprise: using input data for on-chip inference at the MMD to guide operation of the MMD to produce output data based on a plurality of known conductance shifts of memory cells of the MMD and employing a plurality of primary training parameters.

[0197] The system of any preceding paragraph, wherein neural network output data generated by employing the plurality of secondary training parameters at the neural network has a higher level of accuracy than other neural network output data generated by employing the primary training parameters at the neural network.

[0198] A method comprising: quantizing neural network parameters at a magnetic storage device (MMD); performing a first calibration of the parameters, wherein the first calibration includes determining a first error resulting from a first forward computation pass using first data for the parameters, and backpropagating the first error to update the parameters, wherein the first calibration is performed using a selectively increased noise level added to the parameters prior to the first forward computation pass, and wherein performing the first calibration produces initial calibration parameters; determining a conductance error of the MMD based on a particular state of the MMD and based on a sensed conductance of the MMD, thereby producing a determined conductance offset of the MMD; and tuning the initial calibration parameters using the determined conductance offset of the MMD, thereby producing primary training parameters.

[0199] The method described in the previous paragraph further includes: performing iterative training on the main training parameters, wherein the iterative training includes performing one or more series of calibration and tuning processes, the calibration and tuning processes including: determining a second error generated by a second forward calculation pass corresponding to the main training parameters, backpropagating the second error to update the main training parameters, wherein performing a second calibration generates intermediate calibration parameters; and using the determined conductance offset to tune the intermediate calibration parameters to generate secondary training parameters, wherein performing iterative training improves the accuracy of the output data of the memory calculation process using the secondary training parameters relative to performing the first calibration.

[0200] The method of any preceding paragraph, wherein the first calibration of the parameters using the MMD is performed according to the same procedure regardless of the number of bits the parameters comprise.

[0201] The method of any preceding paragraph, wherein the noise used mimics the simulated noise of an inference process performed on-chip using MMD.

[0202] The method of any preceding paragraph, wherein the MMD is a first MMD, and the method further comprises: performing a second iteration of the first calibration relative to a second MMD instead of the first MMD to determine and tune a second set of neural network parameters to produce a second set of principal training parameters; employing the second set of principal training parameters quantized at the second MMD, and employing the principal training parameters quantized at the first MMD to evaluate experimental data using the first MMD and the second MMD.

[0203] The method of any preceding paragraph, wherein the experimental data comprises analog data or digital data, wherein the experimental data is output from a neural network, and wherein the neural network analyzes an MMD output based on the experimental data to generate a neural network output.

[0204] A non-transitory machine-readable medium including executable instructions that, when executed by at least one processor, facilitate performance of operations, the operations comprising: generating neural network output data using a neural network based on input data obtained via the neural network, wherein parameters of the neural network have been calibrated, tuned, and quantized at memory cells of a magnetic memory device (MMD), and wherein in-memory computation at the MMD is employed to generate the output data; and prior to quantizing the parameters at the MMD and prior to generating the output data, performing training of parameters by updating the parameters based on back propagation of errors determined using the parameters and subsequently tuning the parameters based on conductance shifts determined at the memory cells of the MMD.

[0205] The non-transitory machine-readable medium of the preceding paragraph, wherein the operations further comprise: iteratively training the tuned parameters as tuning parameters, the iterative training comprising updating the tuning parameters, performing back propagation of additional errors determined using the tuning parameters; and subsequently retuning the tuning parameters based on the determined conductance shift.

[0206] The non-transitory machine-readable medium of any preceding paragraph, wherein the operations further comprise generating a conductance shift of a memory cell of the MMD by setting a state of the MMD and sensing conductance of the memory cell of the MMD, thereby generating the determined conductance shift.

[0207] The non-transitory machine-readable medium of any preceding paragraph, wherein setting the state of the MMD comprises setting an array of memory cells of the MMD to the same conductance of -1, 0, or 1 before sensing the conductance of the memory cells.

[0208] Exemplary Operating Environment

[0209] Next go to Figure 17 and Figure 18 , provides the Figures 1 to 16 A detailed description of additional context for one or more embodiments described in .

[0210] Figure 17 The following discussion is intended to provide a brief, general description of a suitable operating environment 1700 in which the present invention may be implemented. Figures 1 to 16 For example, one or more components and / or other aspects of the embodiments described herein may be implemented in or associated with operating environment 1700, such as being accessible via operating environment 1700. Furthermore, while one or more embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that one or more embodiments may also be implemented in conjunction with other program modules and / or as a combination of hardware and software.

[0211] Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. In addition, the above methods can be implemented with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronic devices, etc., each of which can be operably coupled to one or more associated devices.

[0212] Computing devices typically include various media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, as described below, and the two terms are used herein to distinguish one from another. A computer-readable storage medium or machine-readable storage medium can be any available storage medium that can be accessed by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium and / or machine-readable storage medium can be implemented in conjunction with any method or technology for storing information such as computer-readable and / or machine-readable instructions, program modules, structured data, and / or unstructured data.

[0213] Computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CDROM), digital versatile disks (DVD), Blu-ray disks (BD) and / or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and / or other magnetic storage devices, solid-state drives or other solid-state storage devices, and / or other tangible and / or non-transitory media that can be used to store specific information. In this regard, the terms "tangible" or "non-transitory" as applied to storage, memory, and / or computer-readable media herein should be understood as excluding only the propagation of transitory signals per se as a modifier, without disclaiming rights to all standard storage devices, memories, and / or computer-readable media that do not merely propagate transitory signals per se.

[0214] Computer-readable storage media can be accessed by one or more local or remote computing devices, eg, via access requests, queries, and / or other data retrieval protocols, for various operations regarding information stored by the media.

[0215] Communication media typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal (such as a modulated data signal, e.g., a carrier wave or other transport mechanism), and includes any information delivery or transmission media. The term "modulated data signal" or signal refers to a signal that has one or more of its characteristics set and / or changed in such a manner as to encode information in one or more signals. By way of example, and not limitation, communication media may include wired media (such as a wired network, a direct-wired connection) and / or wireless media (such as acoustic, RF, infrared, and / or other wireless media).

[0216] Also refer to Figure 17 , an exemplary operating environment 1700 for implementing one or more embodiments of aspects described herein may include a computer 1702 including a processing unit 1706, a system memory 1704, and / or a system bus 1705. One or more aspects of the processing unit 1706 may be applied to a processor, such as the processors 106, 206 of the non-limiting systems 100, 200. The processing unit 1706 may be implemented in combination with the processors 106, 206 and / or alternately with the processors 106, 206.

[0217] The memory 1704 may store one or more computer and / or machine readable, writable, and / or executable components and / or instructions that, when executed by the processing unit 1706 (e.g., a conventional processor and / or similar processor), may provide for the performance of operations defined by the executable components and / or instructions. For example, the memory 1704 may store computer and / or machine readable, writable, and / or executable components and / or instructions that, when executed by the processing unit 1706, may provide for the performance of one or more functions described herein in connection with the non-limiting systems 100, 200, as described herein with or without reference to one or more figures of one or more embodiments.

[0218] Memory 1704 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and / or non-volatile memory (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.), which may adopt one or more memory architectures.

[0219] The processing unit 1706 may include one or more types of processors and / or electronic circuits (e.g., classical processors and / or similar processors) that may implement one or more computer and / or machine readable, writable, and / or executable components and / or instructions that may be stored at the memory 1704. For example, the processing unit 1706 may perform one or more operations specified by the computer and / or machine readable, writable, and / or executable components and / or instructions, including but not limited to logic, control, input / output (I / O), arithmetic, etc. In one or more embodiments, the processing unit 1706 may be any of one or more commercially available processors. In one or more embodiments, the processing unit 1706 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, systems on a chip (SOCs), array processors, vector processors, and / or another type of processor. Examples of the processing unit 1706 may be used to implement one or more embodiments described herein.

[0220] The system bus 1705 can couple system components, including but not limited to the system memory 1704, to the processing unit 1706. The system bus 1705 can include one or more types of bus structures and can also interconnect to a local bus, a memory bus (with or without a memory controller), and / or a peripheral bus using one or more of a variety of commercially available bus architectures. The system memory 1704 can include ROM 1710 and / or RAM 1712. A basic input / output system (BIOS), containing the basic routines that help transfer information between elements within the computer 1702, such as during startup, can be stored in a nonvolatile memory such as ROM, an erasable programmable read-only memory (EPROM), and / or an EEPROM. RAM 1712 can include high-speed RAM, such as static RAM for caching data.

[0221] Computer 1702 may include an internal hard disk drive (HDD) 1714 (e.g., EIDE, SATA), one or more external storage devices 1716 (e.g., a magnetic floppy disk drive (FDD), a memory stick or flash drive reader, a memory card reader, etc.), and / or a drive 1720 (e.g., such as a solid-state drive or an optical drive) that can read from or write to a disk 1722 (such as a CD-ROM disk, a DVD, a BD, etc.). Additionally and / or alternatively, in the case of a solid-state drive, disk 1722 may not be included unless separately provided. Although internal HDD 1714 is shown as being located within computer 1702, internal HDD 1714 may also be configured for external use in an appropriate chassis (not shown). Additionally, although not shown in operating environment 1700, a solid-state drive (SSD) may be used in addition to HDD 1714 instead of HDD 1714. The HDD 1714, the external storage device 1716, and the drive 1720 can be connected to the system bus 1705 via an HDD interface 1724, an external memory interface 1726, and a drive interface 1728, respectively. The HDD interface 1724 for implementing the external drive can include at least one or both of a Universal Serial Bus (USB) and an Institute of Electrical and Electronics Engineers (IEEE) 1794 interface technology. Other external drive connection technologies are also contemplated by the embodiments described herein.

[0222] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. The drives and storage media accommodate the storage of any data in a suitable digital format for the computer 1702. Although the above description of computer-readable storage media refers to corresponding types of storage devices, other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the exemplary operating environment, and / or any such storage media may contain computer-executable instructions for performing the methods described herein.

[0223] A number of program modules may be stored in the drives and RAM 1712, including an operating system 1730, one or more applications 1732, other program modules 1734, and / or program data 1736. All or portions of the operating system, applications, modules, and / or data may also be cached in RAM 1712. The systems and / or methods described herein may be implemented using one or more commercially available operating systems and / or combinations of operating systems.

[0224] Computer 1702 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary program may emulate the hardware environment of operating system 1730, and the emulated hardware may optionally be used with the operating system 1730. Figure 17 . In a related embodiment, operating system 1730 may include one of multiple virtual machines (VMs) residing in computer 1702. In addition, operating system 1730 may provide an operating environment, such as a JAVA operating environment or a .NET framework, for application 1732. An operating environment is a consistent execution environment that allows application 1732 to run on any operating system that includes an operating environment. Similarly, operating system 1730 may support containers, and application 1732 may be in the form of containers, which are lightweight, independent, executable software packages that include, for example, code, runtime, system tools, system libraries, and / or settings for an application.

[0225] In addition, the computer 1702 can be enabled with a security module such as a Trusted Processing Module (TPM). For example, with a TPM, the boot component then hashes the guidance component in time and waits for the result to match the security value before loading the next boot component. This process can occur at any layer in the code execution stack of the computer 1702, for example, at the application execution level and / or the operating system (OS) kernel level, thereby achieving security at any level of code execution.

[0226] An entity may enter and / or send commands and / or information to the computer 1702 through one or more wired / wireless input devices, such as a keyboard 1738, a touch screen 1740, and / or a pointing device (such as a mouse 1742). Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, and / or other remote controls, a joystick, a virtual reality controller and / or a virtual reality headset, a game pad, a stylus, an image input device (such as a camera), a gesture sensor input device, a visual motion sensor input device, an emotion or facial detection device, a biometric input device (such as a fingerprint and / or iris scanner), etc. These and other input devices may be connected to the processing unit 1706 through an input device interface 1744, which may be coupled to the system bus 1705, but may also be connected through other interfaces (such as a parallel port, an IEEE 1794 serial port, a game port, a USB port, an IR interface, a fingerprint scanner ... interface, etc.) connection.

[0227] A monitor 1746 or other type of display device may alternatively and / or additionally be connected to the system bus 1705 via an interface, such as a video adapter 1748. In addition to the monitor 1746, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0228] The computer 1702 can operate in a network environment using logical connections to one or more remote computers, such as a remote computer 1750, via wired and / or wireless communications. The remote computer 1750 can be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment device, a peer device, and / or other public network node, and typically includes many or all of the elements described with respect to the computer 1702, although for simplicity, only a memory / storage device 1752 is shown. Additionally and / or alternatively, the computer 1702 can be coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources, and / or devices (e.g., computing devices, communication devices, and / or the like) via a data cable (e.g., a High-Definition Multimedia Interface (HDMI), Recommended Standard (RS) 232, an Ethernet cable, etc.).

[0229] In one or more embodiments, the network may include one or more wired and / or wireless networks, including but not limited to a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN). For example, one or more embodiments described herein may communicate with one or more external systems, sources, and / or devices, such as a computing device (or vice versa) using virtually any particular wired or wireless technology, including but not limited to Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE), 3rd Generation Partnership Project 2 (3GPP2), Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or traditional telecommunication technologies, Session Initiation Protocol (SIP), RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless LAN), Z-Wave, ANT, Ultra-Wideband (UWB) standard protocol and / or other proprietary and / or non-proprietary communication protocols. In a related example, one or more embodiments described herein may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, etc.), software (e.g., a set of threads, a set of processes, software in execution, etc.), and / or a combination of hardware and / or software that provides communication information between one or more embodiments described herein and external systems, sources, and / or devices (e.g., computing devices, communication devices, etc.).

[0230] The logical connections depicted include wired / wireless connections to a local area network (LAN) 1754 and / or a larger network, such as a wide area network (WAN) 1756. LAN and WAN networking environments may be commonplace in offices and businesses and may provide enterprise-wide computer networks, such as intranets, all of which may connect to a global communications network, such as the Internet.

[0231] When used in a LAN networking environment, the computer 1702 can be connected to the local network 1754 through a wired and / or wireless communication network interface or adapter 1758. The adapter 1758 can provide wired and / or wireless communication to the LAN 1754, which can also include a wireless access point (AP) provided thereon for communicating with the adapter 1758 in a wireless mode.

[0232] When used in a WAN networking environment, the computer 1702 can include a modem 1760 and / or can be connected to a communication server on the WAN 1756 via other means for establishing communications over the WAN 1756, such as through the Internet. The modem 1760 can be an internal and / or external device and can be a wired and / or wireless device, and the modem 1760 can be connected to the system bus 1705 via the input device interface 1744. In a networked environment, program modules depicted relative to the computer 1702, or portions thereof, can be stored in the remote memory / storage device 1752. The network connections shown are exemplary only, and one or more other means of establishing a communications link between the computers can be used.

[0233] When used in a LAN or WAN network environment, computer 1702 can access cloud storage systems or other network-based storage systems in addition to and / or in place of external storage devices 1716 as described above, such as, but not limited to, network virtual machines that provide one or more aspects of storage and / or processing of information. Typically, the connection between computer 1702 and the cloud storage system can be established over LAN 1754 or WAN 1756, for example, via adapter 1758 or modem 1760, respectively. When computer 1702 is connected to the associated cloud storage system, external storage interface 1726 can manage the storage provided by the cloud storage system (which would be other types of external storage), such as by means of adapter 1758 and / or modem 1760. For example, external storage interface 1726 can be configured to provide access to cloud storage sources as if they were physically connected to computer 1702.

[0234] The computer 1702 is operable to communicate with any wireless device and / or entity operable to be arranged in wireless communication, such as a printer, scanner, desktop and / or portable computer, portable data assistant, communication satellite, telephone and / or any device or location associated with a wirelessly detectable tag (e.g., a kiosk, news stand, store shelf, etc.). This may include Wireless Fidelity (Wi-Fi) and Wireless technology. Thus, the communication can be a predefined structure like a conventional network, or simply an ad hoc communication between at least two devices.

[0235] The illustrated embodiments described herein may be used with respect to a distributed computing environment (e.g., a cloud computing environment), such as the one described below with reference to Figure 18 As described, some tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and / or remote memory storage devices.

[0236] For example, one or more embodiments and / or one or more components thereof described herein may be described using the following references: Figure 18 One or more computing resources of the cloud computing environment 1802 described in example 1800. For example, one or more embodiments described herein and / or components thereof may employ such one or more resources to perform one or more of the following: mathematical functions, calculations and / or equations, computational and / or processing scripts, algorithms, models (e.g., artificial intelligence (AI) models, machine learning (ML) models, deep learning (DL) models, and / or the like), and / or other operations according to one or more embodiments described herein.

[0237] It should be understood that although one or more embodiments described herein include detailed descriptions regarding cloud computing, implementation of the teachings described herein is not limited to cloud computing environments. Rather, one or more embodiments described herein can be implemented in conjunction with any other type of computing environment now known or later developed. That is, for example, one or more embodiments described herein can be implemented solely in a local environment and / or a non-cloud integrated distributed environment.

[0238] A cloud computing environment may provide one or more of low connectivity, modularity, and / or semantic interoperability. At the core of cloud computing is the infrastructure of a network including interconnection aspects.

[0239] Furthermore, the non-limiting systems 100, 200 and / or Figure 17 The exemplary operating environment 1700 can be associated with and / or included in a cloud-based, and / or partially cloud-based system.

[0240] Now refer to Figure 18 , an illustrative cloud computing environment 1802 is described with details of one or more elements shown in FIG. Cloud computing environment 1802 may include one or more cloud computing nodes, virtual machines, etc., with cloud clients 1804 such as, for example, using local computing devices via one or more devices 1806, systems 1808, virtual machines 1810, networks 1812, and / or applications 1814.

[0241] One or more cloud computing nodes, virtual machines, etc. can be physically or virtually grouped in one or more networks (such as a local network, a distributed network, a private network, a public cloud network, and / or a combination thereof). The cloud computing environment 1802 can provide infrastructure, platforms, virtual machines, and / or software, and the client 1804 does not need to maintain all or at least a portion of the resources on a local device (such as a computing device). The various elements 1806 to 1812 are not intended to be limiting, but can be some of various examples of computerized elements that communicate with each other and / or with one or more cloud computing nodes via the cloud computing environment 1802 (such as through any suitable network connection and / or type).

[0242] in conclusion

[0243] The embodiments described herein may be directed to one or more of the systems, methods, devices, and / or computer program products at any possible level of integrated technical detail. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform various aspects of one or more embodiments described herein. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a superconducting storage device, and / or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card or raised structure with instructions recorded in grooves thereon), and / or any suitable combination of the foregoing. The computer-readable storage media used in this document should not themselves be interpreted as transient signals, such as radio waves and / or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides and / or other transmission media (e.g., light pulses passing through fiber optic cables), and / or electrical signals transmitted through wires.

[0244] The computer-readable program instructions described herein can be downloaded to corresponding computing / processing device and / or external computer or external storage device from a computer-readable storage medium via a network (for example, the Internet, local area network, wide area network and / or wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or the network interface in each computing / processing device receive computer-readable program instructions from the network, and forward computer-readable program instructions, so as to be stored in the computer-readable storage medium in the corresponding computing / processing device. The computer-readable program instructions for performing the operation of one or more embodiments described herein can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, and / or source code and / or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​(for example Smalltalk, C++ etc.) and / or procedural programming languages ​​(for example " C " programming language and / or similar programming languages)). The computer readable program instructions can be executed completely on a computer as an independent software package, in part on a computer, in part on a computer and / or in part on a remote computer, or in full on a remote computer and / or server. In the latter case, the remote computer can be connected to the computer and / or connected to an external computer (e.g., by using the Internet of an Internet Service Provider) through any type of network (including a local area network (LAN) and / or a wide area network (WAN)). In one or more embodiments, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array (FPGA) and / or a programmable logic array (PLA) can be executed by utilizing the state information personalization electronic circuit of the computer readable program instructions to perform the various aspects of one or more embodiments described herein.

[0245] With reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to one or more embodiments described herein, the aspects of one or more embodiments described herein are described.It will be understood that each frame of the flowchart and / or block diagram and the combination of frames in the flowchart and / or block diagram can be realized by computer-readable program instructions.These computer-readable program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device can create a device for realizing the function / action specified in one or more frames of the flowchart and / or block diagram.These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide a computer, a programmable data processing device and / or other devices to operate in an ad hoc manner, so that the computer-readable storage medium with instructions stored therein can include an article of manufacture, and the article of manufacture includes instructions for the aspect of the function / action specified in one or more frames of the flowchart and / or block diagram. Computer-readable program instructions can also be loaded onto a computer, other programmable data processing devices and / or other devices to cause a series of operational actions to be performed on the computer, other programmable devices and / or other devices, thereby generating a computer-implemented process, so that the instructions executed on the computer, other programmable devices and / or other devices implement specific functions / actions in one or more boxes of the flowchart and / or block diagram.

[0246] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and / or operations of possible implementations of the systems, computer-implemented methods and / or computer program products according to one or more embodiments described herein. In this regard, each box in the flowchart or block diagram can represent a portion of a module, segment and / or instruction, which includes one or more executable instructions for implementing a specific logical function. In one or more alternative embodiments, the functions annotated in the box may be inconsistent with the order annotated in the figure. For example, two boxes shown in succession can be performed substantially simultaneously, and / or these boxes can sometimes be performed in reverse order, depending on the functions involved. It will also be noted that each box in the block diagram and / or flowchart, and / or the combination of boxes in the block diagram and / or flowchart, can be implemented by a system based on dedicated hardware that can perform specific functions and / or actions, and / or perform one or more combinations of dedicated hardware and / or computer instructions.

[0247] Although the present subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one and / or multiple computers, it will be appreciated by those skilled in the art that one or more embodiments herein may also be implemented in combination with one or more other program modules. Typically, a program module includes routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. In addition, the above-mentioned computer-implemented methods may be implemented with other computer system configurations, including single-processor and / or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer and / or industrial electronic products, etc. The illustrated aspects may also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, one or more (if not all) aspects of one or more embodiments described herein may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0248] As used in this application, the terms "component", "system", "platform", "interface" and the like may refer to and / or may include computer-related entities or entities related to an operating machine having one or more specific functions. The entities described herein may be hardware, a combination of hardware and software, software, or software in operation. For example, a component may be, but is not limited to, a process, a processor, an object, an executable program, a thread of execution, a program, and / or a computer running on a processor. As an example, an application running on a server and a server may be a component. One or more components may reside within a process and / or a thread of execution, and a component may be located on a computer and / or distributed between two or more computers. In another example, the corresponding component may be executed from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes, such as according to signals with one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from another component interacting with other systems across a network (such as the Internet) via a signal). As another example, a component may be a device having a specific function provided by a mechanical component operated by an electrical or electronic circuit, which is operated by software and / or firmware application programs executed by a processor. In this case, the processor can be internal and / or external to the device and can execute at least a portion of a software and / or firmware application. As another example, the component can be a device that provides a specific functionality through electronic components rather than mechanical parts, where the electronic component can include a processor and / or other device that executes software and / or firmware that at least partially imparts the functionality of the electronic component. In one aspect, the component can emulate the electronic component via a virtual machine (e.g., within a cloud computing system).

[0249] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive permutation. That is, if X employs A, X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the above cases. In addition, unless otherwise specified or clear from the context to point to the singular form, the words "a" and "an" used in this specification and the drawings should generally be interpreted to mean "one or more". As used herein, the terms "example" and / or "exemplary" are used to mean used as an example, instance, or illustration. For the avoidance of doubt, the subject matter described herein is not limited to these examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or beneficial over other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0250] As used in this specification, the term "processor" may refer to substantially any computational processing unit and / or device, including but not limited to a single-core processor, a single processor with software multi-threaded execution capability, a multi-core processor, a multi-core processor with software multi-threaded execution capability, a multi-core processor with hardware multi-threading technology, a parallel platform and / or a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components and / or any combination thereof designed to perform the functions described herein. Furthermore, the processor may utilize nanoscale architectures, such as but not limited to molecular-based transistors, switches and / or gates, in order to optimize space usage and / or enhance the performance of associated devices. The processor may be implemented as a combination of computational processing units.

[0251] As used herein, terms such as "storage," "memory," "data storage," "data storage," "database," and substantially any other information storage component related to the operation and functionality of a component are used to refer to a "memory component," an entity contained in a "memory," or a component that includes a memory. The memories and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, and / or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM that may be used, for example, as external cache memory. By way of example and not limitation, RAM can exist in various forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and / or Rambus dynamic RAM (RDRAM). In addition, the memory components of the systems and / or computer-implemented methods described herein are intended to include, but are not limited to, these and / or any other suitable types of memory.

[0252] The above description includes only examples of systems and computer-implemented methods. Of course, for the purpose of describing one or more embodiments, it is not possible to describe every conceivable combination of components and / or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and / or permutations of one or more embodiments are possible. In addition, when the terms "including," "having," "having," and the like are used in the detailed description, claims, appendices, and / or drawings, these terms are intended to be inclusive in a manner similar to the term "comprising" and are to be interpreted as "including" when used as transition words in the claims.

[0253] The description of one or more embodiments is presented for the purpose of illustration and is not intended to be exhaustive or limited to the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, and / or technical improvements over technologies found in the marketplace, and / or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. An adaptive quantization system, comprising: at least one memory storing computer executable components; as well as at least one processor that executes the computer executable components stored in the at least one memory to perform operations, the operations comprising: determining a conductance error of a memory cell of a magnetic memory device MMD based on a specific state of the memory cell and based on a sensed conductance of the memory cell of the MMD in the specific state, thereby generating a plurality of known conductance offsets of the MMD; as well as A plurality of initial calibration parameters of a neural network are tuned, the tuning comprising mapping the plurality of initial calibration parameters to the memory cell using the plurality of known conductance shifts of the MMD to produce a set of master training parameters.

2. The system according to claim 1, wherein: Determining the known conductance shift of the MMD comprises: sensing respective conductance shifts of the memory cells of the MMD and outputting the sensed respective conductance shifts as the plurality of known conductance shifts; and A lookup table of the plurality of known conductance shifts corresponding to the array of memory cells of the MMD is generated, wherein the lookup table is used to tune the initial calibration parameters.

3. The system according to claim 1, wherein: Determining the known conductance shift of the MMD comprises: sensing the conductance value of the memory cell as the sensed conductance in a plurality of selected states of the MMD, Wherein each selected state of the MMD comprises the memory cells of the array of the MMD being set to the same conductance value of -1, 0 or 1.

4. The system according to claim 1, wherein: The conductance value of the memory cell in the selected state of the MMD includes a combination of conductance values ​​of -1, 0, and 1 of the memory cell.

5. The system according to claim 1, wherein: The operations also include: Initial calibration raw parameters, including: incrementally adding noise to the original parameters, thereby generating noisy original parameters; and Then, back propagation is adopted to update the noise original parameters, and the initial calibration generates the plurality of initial calibration parameters.

6. The system according to claim 5, wherein: Initially calibrating the raw parameters is performed according to the same procedure regardless of the number of bits included in the raw parameters.

7. The system according to claim 1, wherein: The operations also include: Based on the tuning, the set of main training parameters is further iteratively trained, including updating the set of main training parameters using back propagation using the determined errors, thereby generating a plurality of intermediate calibration parameters.

8. The system according to claim 7, wherein: The operations also include: The plurality of intermediate calibration parameters are further iteratively trained using the plurality of known conductance shifts, thereby generating a set of secondary trained parameters.

9. The system according to claim 8, wherein: The operations also include: Input data for on-chip inference is used at the MMD to guide operation of the MMD to generate output data based on the plurality of known conductance shifts of the memory cells of the MMD and employing the set of primary training parameters.

10. The system according to claim 9, wherein: Neural network output data generated at the neural network using the set of secondary training parameters has a higher level of accuracy than other neural network output data generated at the neural network using the primary training parameters.

11. An adaptive quantization method, comprising: quantizing the parameters of the neural network at a magnetic storage device MMD; performing a first calibration of the parameters, wherein the first calibration includes determining a first error resulting from a first forward computation pass using first data for the parameters, and back-propagating the first error to update the parameters, wherein the first calibration is performed using a selectively increased noise level added to the parameters prior to the first forward computation pass, and wherein performing the first calibration results in initial calibration parameters; determining a conductance error of the MMD based on a particular state of the MMD and based on a sensed conductance of the MMD, thereby producing a determined conductance offset of the MMD; and The determined conductance shift of the MMD is used to tune the initial calibration parameters, thereby generating primary training parameters.

12. The method according to claim 11, further comprising: Performing iterative training of the main training parameters, wherein the iterative training includes performing one or more series of calibration and tuning processes, including: determining a second error resulting from a second forward computation pass corresponding to the primary training parameters, back-propagating the second error to update the main training parameters, wherein performing a second calibration of the initial calibration parameters generates intermediate calibration parameters, and using the determined conductance shift to tune the intermediate calibration parameters, thereby generating secondary training parameters, Wherein, relative to performing the first calibration, performing the iterative training improves the accuracy of output data of the memory computing process using the secondary training parameters.

13. The method according to claim 11, wherein: The first calibration of the parameters using the MMD is performed according to the same procedure regardless of the number of bits the parameters comprise.

14. The method according to claim 11, wherein: The noise employed mimics the simulated noise of an inference process performed on-chip using the MMD.

15. The method according to claim 11, wherein: The MMD is a first MMD, and the method further comprises: performing a second iteration of performing the first calibration relative to a second MMD instead of the first MMD to determine and tune a second set of neural network parameters to produce a second set of principal training parameters; The experimental data using the first MMD and the second MMD are evaluated using the second set of main training parameters quantized at the second MMD and using the main training parameters quantized at the first MMD.

16. The method according to claim 15, wherein: The experimental data comprises analog data or digital data, wherein the experimental data is output from a neural network, and wherein an MMD output based on the experimental data is analyzed by the neural network to generate a neural network output.

17. A non-transitory machine-readable medium comprising executable instructions that, when executed by at least one processor, facilitate performance of operations comprising: generating neural network output data using the neural network based on input data obtained via the neural network, wherein parameters of the neural network have been calibrated, tuned and quantized at a memory cell of a magnetic memory device MMD, and wherein in-memory computing at the MMD is employed to generate the neural network output data; and Prior to quantizing the parameters at the MMD and prior to generating the neural network output data, training of the parameters is performed by updating the parameters based on back propagation of errors determined using the parameters and subsequently tuning the parameters based on determined conductance shifts of the memory cells of the MMD.

18. The non-transitory machine-readable medium of claim 17, wherein: The operations also include: Iteratively training the tuned parameters as tuning parameters, the iterative training comprising: updating the tuning parameters, performing back propagation of additional errors determined using the tuning parameters, and The tuning parameters are then retuned based on the determined conductance shift.

19. The non-transitory machine-readable medium of claim 17, wherein: The operations also include: The determined conductance shift is generated by setting a state of the MMD and sensing the conductance of the memory cells of the MMD to generate a conductance shift of the memory cells of the MMD.

20. The non-transitory machine-readable medium of claim 19, wherein: Setting the state of the MMD includes: Prior to sensing the conductance of the memory cells, the array of memory cells of the MMD are set to the same conductance of -1, 0, or 1.

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