216results about "Spin-exchange-coupled multilayers" patented technology

The present disclosure provides an orbitronic device having orbital Hall effect or inverse orbital Hall effect, and method for enhancing the efficiency thereof. The orbital torque device comprises: a ferromagnetic / non-magnetic heterojunction formed by compounding a ferromagnetic layer and a non-magnetic layer as an orbital current source, wherein the ferromagnetic layer contains a ferromagnetic material, the non-magnetic layer contains a non-magnetic material with weak spin-orbit coupling, the non-magnetic layer is used as an orbital Hall channel to generate orbital current, and the orbital current enters the ferromagnetic layer, so that an orbital torque is generated through an orbital-spin conversion effect of the ferromagnetic layer to realize switching of a magnetic moment. The present disclosure can provide orbitronic device with low cost and good performance.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

A magnetic memory device including a tunneling magnetoresistance layer and a memory device including the magnetic memory device are provided. The magnetic memory device includes the tunneling magnetoresistance layer, including a free layer, a tunneling barrier layer, and a pinned layer, and a spin orbit torque (SOT) layer configured to provide a spin current to change a magnetization direction of the free layer of the tunneling magnetoresistance layer, wherein the SOT layer includes an orbital Hall conductance (OHC) material layer configured to provide an orbital Hall current and a conversion layer configured to convert the orbital Hall current of the OHC material layer into the spin current, and the OHC material layer includes at least one material of iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), and rhenium (Re), or an alloy thereof.

A neuromorphic computing array includes horizontal lines and vertical lines that intersect the horizontal lines at cell locations. Magnetic tunnel junction cells are located at the cell locations. Each cell is electrically connected to a corresponding one of the horizontal lines and to a corresponding one of the vertical lines. Each cell includes a substrate, a seed layer overlying the substrate, and a nitride layer, overlying the seed layer, and optionally having a thickness greater than 5 Angstroms. Each cell further includes a templating layer, outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms. Each cell still further includes a magnetic layer overlying the templating layer, a tunnel barrier outward of the magnetic layer; and a magnetic layer outward of the tunnel barrier. The magnetic layer includes a Heusler compound and exhibits perpendicular magnetic anisotropy (PMA).

The present disclosure generally relates to spintronic devices comprising a YPtBi layer having a (111) orientation. The spintronic stack further comprises a ferromagnetic layer and a buffer layer. The buffer layer has a (002) or (111) orientation, which promotes the (111) orientation of the YPtBi layer. The buffer layer comprises an amorphous oxide or nitride layer, an amorphous metal layer disposed on the amorphous oxide or nitride layer, a textured pre-seed layer disposed on the amorphous metal layer, and one of: a (002) hexagon or (111) fcc layer, a B2 alloy layer, or first and second bcc or B2 alloy layers.

A memory device includes a bottom electrode, a selector, a memory layer, and a top electrode. The selector is over the bottom electrode. A sidewall of the bottom electrode and a sidewall of the selector are coterminous. The memory layer is formed over the selector and has a width greater than a width of the selector. A top electrode is formed over the memory layer.

Method for forming a magnetoresistive element by forming a sense layer having a free sense magnetization, a reference layer having a fixed reference magnetization, wherein the reference layer is formed by deposition in a Krypton atmosphere, a tunnel barrier layer between the reference layer and the sense layer, and a hard layer having a fixed reference magnetization layer opposite to that of the reference layer. The magnetoresistive element may be configured to measure an external magnetic field oriented substantially perpendicular to the plane of the reference layer. The reference magnetizations of the reference and hard layers may be oriented substantially perpendicularly to the plane of the reference and hard layers. The sense magnetization may have a vortex configuration in the absence of an external magnetic field.

The present disclosure generally relates to topological semi-metal (TSM) based spin-orbit torque (SOT) devices, and methods of forming a TSM layer. The TSM layer of the SOT device comprises YPtBi having a 1:1:1 stoichiometry. The YPtBi has a density between about 9.7 g / cc to about 11.2 g / cc. Kr, Ar, or Xe gas is used to sputter the YPtBi to form the YPtBi layer or film. Trace amounts of Kr, Ar, or Xe are detectable in the YPtBi layer, where the YPtBi layer comprises about 1% of Kr, Ar, or Xe. One or more targets comprising YPtBi; YPt and Bi; PtBi and Y; Y, Pt, and Bi; or YBi and Pt can be used when forming the YPtBi layer. In embodiments where two targets are used to form the YPtBi layer, different amounts of power may be applied to each target.

The present disclosure generally relates to spintronic material stacks and devices. A spintronic stack comprises an amorphous layer, a texturing layer comprising one or more materials selected from the group consisting of: TaxW1-x, where x is from zero to 1, MgO, Ru, Ti, TiN, YPt, B2 alloys X—Al, where X is one of Co, Ni, Ru, Rh, or Ir, CrMo, TaxW1-x N, HfN, and TaxHf1-xN, a barrier layer comprising one or more materials selected from the group consisting of: X—AlGe, X—AlGeN, where X is one of Co, Ni, Ru, or Ir, TaxW1-xN, HfN, and TaxHf1-xN, and TiN, a YPtBi layer having a (110), (111), or (100) orientation, an interlayer, and a ferromagnetic layer. The texturing barrier layers each individually comprises a material having a high resistivity to minimize shunting, and function as a crystal symmetry transfer layer to provide the a (110), (111), or (100) orientation to the YPtBi layer.

According to one aspect of the present disclosure, a magnetoresistance (MR) element includes a free layer. In some embodiments, the free layer also includes a vortex layer comprising a vortex and a skyrmion layer magnetically coupled to the vortex layer. In some embodiments, in the skyrmion layer is configured to form skyrmions that reduce annihilation of the vortex thereby increasing a linear response range of the MR element. In some embodiments, the MR element is a tunneling magnetoresistance element or a giant magnetoresistance element. In some embodiments, the MR element includes a barrier layer, wherein the vortex layer is closer to the barrier layer than the skyrmion layer.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

A device having a spin valve layer sequence, wherein the spin valve layer sequence includes a first magnetic layer having a variable direction of magnetization, a second magnetic layer having a fixed direction of magnetization, and a stabilization layer for stabilizing the fixed direction of magnetization of the second magnetic layer, wherein the stabilization layer includes a precious metal-free antiferromagnet.

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

A magnetic storage device includes first and second magnetic layers and a non-magnetic layer, where the non-magnetic layer includes a first oxide layer containing magnesium and oxygen, a second oxide layer containing magnesium and oxygen, a third oxide layer containing zinc and oxygen, a fourth oxide layer containing a first predetermined element and oxygen, and a fifth oxide layer containing a second predetermined element and oxygen, and a crystal structure of an oxide of the first predetermined element and a crystal structure of an oxide of the second predetermined element are each a rock salt structure. The first predetermined element and the second predetermined element each have an oxide formation free energy greater than an oxide formation free energy of zinc, and the oxide of the first predetermined element and the oxide of the second predetermined element each have a bandgap narrower than a bandgap of an oxide of magnesium.

The present disclosure generally relates to topological semi-metal (TSM) and topological insulator (Tl) based spin-orbit torque (SOT) devices and a method of forming thereof. Tl or TSM-based SOT device (such as that with BiSb in the SOT layer) has been proposed for applications in magnetic switching and sensor applications, where current flows in a CIP (current-in-plane) or CPP (current-perpendicular-to-the-plane) direction, respectively. For CPP SOT devices, the requirement for the Tl or TSM layer's bulk property is to be more insulating, to minimize shunting. However, for CIP SOT devices, the requirement for the Tl or TSM layer's bulk property is to be more conductive, for less power consumption. Disclosed herein are various embodiments covering types and amounts of dopants for the Tl or TSM layer, to decrease the bandgap of the Tl or TSM layer for CIP SOT devices, thereby increasing the bulk conductivity for lower power consumption.

An example memory includes a plurality of storage units and bit lines distributed in an array in a storage area of the memory, where each of the storage unit includes a transistor and a magnetic tunnel junction (MTJ) element connected to the transistor. The MTJ element is disposed on a current transmission path between a source or a drain of the transistor and the bit line. The MTJ element includes a pinning layer, a reference layer, a tunneling layer, and a free layer that are stacked in sequence, and a magnetization direction of the pinning layer is parallel to a stacking direction of layers in the MTJ. The example memory further includes a first magnetic structure disposed on the current transmission path and in contact with the MTJ element. An included angle between a magnetization direction of the first magnetic structure and the magnetization direction of the pinning layer is (90°, 180°].

This invention provides a nanoscale spin waveguide based on alternating magnet domain walls, belonging to the field of magnetic device technology. The device comprises, from bottom to top, a substrate, an alternating magnet thin film, and a microwave excitation source. The microwave excitation source excites an alternating magnetic field with a single frequency. The alternating magnetic field interacts with the magnetic moments of the alternating magnet thin film, causing the magnetic moments to precess. This precession is then propagated outward from the microwave excitation source in the form of a wave, forming a spin wave. By reducing the frequency of the alternating magnetic field, the spin wave propagates only within the domain walls of the alternating magnet thin film, realizing an alternating magnet domain wall spin waveguide. This invention reduces the difficulty of spin wave excitation, which is beneficial for reducing device energy consumption. Furthermore, this invention offers advantages in device miniaturization and high efficiency, and can promote the generation and development of spin wave devices based on anisotropic media, possessing broad application prospects.

A photonic spin register includes: a shift register unit including a magnetic material layer having a shape extending in one direction; and a write unit configured to write spin information into a magnetic domain in the magnetic material layer by transferring information included in an optical signal that is a pulse amplitude-modulated and serial input signal, to a spin state of the magnetic domain in the magnetic material layer by means of a photocurrent corresponding to the optical signal or by irradiation with the optical signal. When a shift current flows through the shift register unit in the one direction, a domain wall is configured to move in the magnetic material layer, thereby allowing the spin information to move and be buffered in the magnetic material layer.

A magnetoresistive random-access memory cell includes a templating layer, including a binary alloy having an alternating layer lattice structure, and a half metallic Heusler multilayer structure including a plurality of layers of two different Heusler compounds, at least one of which is half metallic. The half metallic Heusler multilayer structure is located outward of the templating layer and exhibits perpendicular magnetic anisotropy (PMA). A tunnel barrier is outward of the half metallic Heusler multilayer structure, and a magnetic layer is outward of the tunnel barrier.

Nitrogen doping an insulating layer can lower the bandgap of a magnetic storage device. It is challenging to nitrogen dope magnesium oxide (MgO). A cation can be added to allow the magnesium to hold onto the nitrogen dopant without highly oxidizing or nitriding the cation. The resulting nitrogen doped MgXO, where X is the cation, has a lower bandgap compared to a much similar barrier layer that has neither nitrogen nor a cation thus improving thermal and electrical reliabilities. The nitrogen doped MgXO is non-stoichiometric whereas comparably, an oxynitride is stoichiometric. Example cations that may be used include aluminum, titanium, vanadium, chromium, and scandium.

An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.

Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

A memory device includes a bottom electrode, a selector, a memory layer, and a top electrode. The selector is over the bottom electrode. A sidewall of the bottom electrode and a sidewall of the selector are coterminous. The memory layer is formed over the selector and has a width greater than a width of the selector. A top electrode is formed over the memory layer.

Disclosed are a spin logic device based on spin-charge conversion and a spin logic array using the same. A reconfigurable spin logic array according to an exemplary embodiment of the present invention may include: an input terminal receiving at least three current signals; a plurality of wires transmitting the current signal in connection with the input terminal and including a horizontal wire and a vertical wire which cross each other; a first gate array in which at least one first majority gate connected to the input terminal through the wires and implemented based on the spin logic device is arranged; and a second gate array in which at least one second majority gate connected to the first gate array through the wires and implemented based on the spin logic device is arranged.

The present disclosure generally relates to spintronic devices comprising a high oxidation resistive cap layer. The spintronic stack comprises a buffer layer, a topological material (TM) layer comprising YPtBi or BiSb, an interlayer, a ferromagnetic layer, and a cap layer. The cap layer comprises a high resistance material selected from the group consisting of: (1 ) lrxHfyAlz or lrxZryAlz, where x is between about 40 at. % to about 90 at. %, y is about 0.5 at. % to about 60 at. %, and z is about 0.5 at. % to about 60 at. %; (2) ZrQX or HfQX, where X and Q are each individually selected from the group consisting of: Ru, Co, Cu, Ir, Pt, Ti, Nb, Ni, RuAI, and CoFe; (3) SixAli-xN, TixAh-xN, CrxAli-xN, and ZrxAh-xN, where x is a numeral between 0.005 and 1; and (4) nitrides of Si, Al, Ti, Cr, and Zr.

A magnetic device capable of field-free spin-orbit torque includes a fixed ferromagnetic layer, a free ferromagnetic layer, and an insulating layer positioned between the fixed ferromagnetic layer and the free ferromagnetic layer, wherein the free ferromagnetic layer includes an in-plane magnetic anisotropy ferrimagnetic layer, a perpendicular magnetic anisotropy free ferromagnetic layer, and a non-magnetic layer positioned between the in-plane magnetic anisotropy ferrimagnetic layer and the perpendicular magnetic anisotropy free ferromagnetic layer.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.