System power supply synchronous control method
By using programmable logic devices to manage the power-on timing data of the motherboard and the system board in the server system on the motherboard, the problem of out-of-synchronization of the power-on timing of the motherboard and the system board power supply is solved, and the synchronization control of the system power supply is realized, avoiding the failure of the system function.
Patent Information
- Application Number
- CN202311316630.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-11
- Publication Date
- 2025-04-11
AI Technical Summary
In a server system, the power-on timing between the motherboard and the system board is not synchronized, resulting in system functions failure, such as the problem of hard disk loss.
By implementing programmable logic devices on the motherboard, managing the power-on timing data of the motherboard and the system board, determining whether there is a target power-on project on the system board, and performing a voltage start-up program based on this to ensure that the power-on timing of the motherboard and the system board is synchronized.
The power timing synchronization between the motherboard and the system board is achieved, which avoids the system function failure caused by the power timing out of synchronization and ensures the normal operation of the relevant devices.
Smart Images
Figure CN119806895A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a power-on timing synchronization method, and in particular to a system power synchronization control method for synchronizing the power-on timing of a mainboard and a system board. Background Art
[0002] The server system is composed of a mainboard and at least one system board to realize functions such as computing processing, network transmission and data storage. The chips or devices on each system board are controlled by their own power supply. These power control elements are distributed on the mainboard and at least one system board respectively. The single power provided by the power supply of the server system is converted into the required system power through a switching controller.
[0003] When the at least one system board uses a different power supply from the main board, the system power on time of the at least one system board will be out of sync with that of the main board. During the power restart process, some system functions may fail. For example,
[0004] When testing the DC cycle of a PCIe (peripheral component interconnect express) / SAS (Serial Attached Small Computer System Interface) SSD (Solid State Disk) combo backplane, you may find that during multiple system power cycle cycles, the hard disks that were hot-plugged into the backplane are lost because the system power is not synchronized. Summary of the invention
[0005] Therefore, the purpose of the present invention is to provide a system power synchronization control method that achieves power synchronization between a mainboard and a system board and satisfies power timing requirements of a chip or device, thereby avoiding the problem of power timing asynchrony.
[0006] Therefore, the system power synchronization control method of the present invention is implemented by a mainboard of a servo system, the mainboard signal is connected to the system board of the servo system, the mainboard includes a programmable logic device storing mainboard power-on timing data and system board power-on timing data, the mainboard power-on timing data includes multiple mainboard power-on items related to the mainboard power-on, the system board power-on timing data includes multiple system board power-on items related to the system board power-on, the method includes the following steps: (A) the programmable logic device of the mainboard obtains a to-be-powered item from multiple mainboard power-on items related to a power-on timing of the mainboard, and determines whether there is at least one target power-on item among the system board power-on items based on the to-be-powered item and the system board power-on timing data; (B) when the programmable logic device of the mainboard determines that there is at least one target power-on item (C) the programmable logic device of the mainboard transmits a result request related to the power-on result of the at least one target power-on project to the system board; (D) after the programmable logic device of the mainboard receives a power-on reply from the system board in response to the result request, the power-on reply includes at least one power-on status corresponding to the at least one target power-on project, and determines whether the at least one power-on status all indicates that the power-on is successful; and (E) when the programmable logic device of the mainboard determines that the at least one power-on status all indicates that the power-on is successful, return to step (A) until all power-on projects have executed the corresponding voltage startup procedures.
[0007] In particular, after step (A), the following steps are also included: (F) when the programmable logic device of the mainboard determines that the at least one target power-on item does not exist, a voltage startup procedure of the power-on voltage corresponding to the item to be powered on is performed, and the process returns to step (A) until all power-on items have completed the corresponding voltage startup procedure.
[0008] In particular, after step (D), the following steps are also included: (G) when the programmable logic device of the mainboard determines that the at least one power-on state does not all indicate successful power-on, the programmable logic device of the mainboard records the target power-on item corresponding to at least one power-on state that did not successfully power on.
[0009] In particular, after step (D), the mainboard further includes a plurality of indicator lights corresponding to the power-on items on the system boards, and further includes the following steps: (H) when the programmable logic device of the mainboard determines that the at least one power-on state does not all indicate a successful power-on, the programmable logic device of the mainboard transmits an indicator light control instruction group related to the target power-on item corresponding to at least one power-on state that did not power on successfully to the corresponding indicator light, so as to activate the indicator light corresponding to the target power-on item corresponding to at least one power-on state that did not power on successfully.
[0010] In particular, the servo system also includes a power supply electrically connected to the mainboard and the system board and used to provide power to the mainboard and the system board. Before the step (A), it also includes the following steps: (I) the power supply transmits a standby power to the mainboard and the system board; (J) after the mainboard obtains the standby power from the power supply, the programmable logic device of the mainboard sends a power-on timing data request to the system board; and (K) after the programmable logic device of the mainboard obtains the system board power-on timing data in response to the power-on timing data request from the system board, the programmable logic device of the mainboard stores the system board power-on timing data.
[0011] In particular, between the step (K) and the step (A), the following steps are also included: (L) the power supply transmits a working power to the mainboard and the system board, and performs step (A).
[0012] In particular, in step (A), the power-on voltage corresponding to each target power-on item is less than or equal to the power-on voltage corresponding to the item to be powered on and is greater than the power-on voltage corresponding to the next mainboard power-on item corresponding to the item to be powered on, or each target power-on item is less than or equal to the power-on voltage corresponding to the item to be powered on.
[0013] Compared with the prior art, the system power synchronization control method of the present invention uses the programmable logic device of the mainboard to determine that at least one power-on state indicates that the power-on is successful, and then the voltage startup program of the next mainboard power-on project of the project to be powered on is performed, so that the power-on timing of various voltages of the system board and the mainboard are synchronized, thereby avoiding the situation where the related devices cannot operate normally due to the problem of power timing asynchrony. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which:
[0015] Figure 1 is a block diagram illustrating a servo system for executing an embodiment of the system power synchronization control method of the present invention; and
[0016] Figure 2is a flow chart illustrating an embodiment of the system power synchronization control method of the present invention. DETAILED DESCRIPTION
[0017] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.
[0018] See also Figure 1 , an embodiment of the system power synchronization control method of the present invention is implemented by a servo system. The servo system includes a mainboard 1, a system board 2 connected to the mainboard 1 by at least one signal, and a power supply 3 electrically connected to the mainboard 1 and the system board 2 and used to provide power to the mainboard 1 and the system board 2. The mainboard 1 includes a programmable logic device 12 including a register 121, a plurality of indicator lights 13 connected to the programmable logic device 12 by signals, and a plurality of power controllers (Variable resistors, VR) 14 connected to the programmable logic device 12 by signals. The register 121 stores mainboard power-on timing data and system board power-on timing data. Each system board 2 includes a control device 21 including a register 211 and a plurality of power controllers (VR) 22 connected to the control device 21 by signals. The mainboard power-on timing data includes a plurality of mainboard power-on items related to the mainboard 1, and the system board power-on timing data includes a plurality of system board power-on items related to the system board 2. The control device 21 is, for example, a complex programming logic device 12 (CPLD), but is not limited thereto. It can also be a GPIO (General Purpose Input Output) expander supporting SMBus (System Management Bus), a field programmable gate array (FPGA), or a programmable controller such as a microcontroller unit (MCU). Each indicator light 13 corresponds to one of the power-on items on the system board, and is used to indicate whether the corresponding power-on item on the system board is successfully powered on. Since the operation of each system board 2 is similar, in the following specification, only a single system board 2 is used for description, wherein the power-on success means that the power controller 14 or the power controller 22 corresponding to the corresponding power-on item is successfully started and operates.
[0019] See also Figure 1 and Figure 2 The following will be used to illustrate the operation of each component of the servo system in conjunction with a system power synchronization control method. The system power synchronization control method includes the following steps.
[0020] In step 200, the power supply 3 transmits a standby power to the mainboard 1 and the system board 2 to provide the power required for the mainboard 1 and the system board 2 to standby. Specifically, the power supply 3 provides the standby power to the mainboard 1 and the system board 2 for at least some components to operate. It is worth mentioning that in the present embodiment, the power supply 3 directly transmits the standby power to the mainboard 1 and the system board 2; however, in other embodiments, the power supply 3 may also first transmit the standby power to the mainboard 1 and then transmit the standby power to the system board 2 through the mainboard 1.
[0021] In step 201, after the mainboard 1 obtains the standby power from the power supply 3, the programmable logic device 12 of the mainboard 1 sends a power-on timing data request to the system board 2 through a management bus (hereinafter taking the system management bus (SMBus) as an example, but not limited to this, it can also be a serial general purpose input and output bus (SGPIO Bus) or an internal integrated circuit bus (I2C Bus), etc., a communication interface supported by both the mainboard 1 and the system board 2) connecting the mainboard 1 and the corresponding system board 2. In detail, the programmable logic device 12 of the mainboard 1 receives the standby power and starts and operates, and then sends the power-on timing data request to the system board 2.
[0022] In step 202, after the control device 21 of the system board 2 receives the power-on timing data request, the control device 21 of the system board 2 transmits the system board power-on timing data in response to the power-on timing data request to the main board 1 via SMBus. In detail, the control device 21 of the system board 2 is started and operated by the standby power received by the system board 2, and after receiving the power-on timing data request, transmits the system board power-on timing data to the main board 1 via SMBus.
[0023] In step 203, after the programmable logic device 12 of the mainboard 1 receives the system board power-on timing data in response to the power-on timing data request from the system board 2, the programmable logic device 12 of the mainboard 1 obtains and updates the system board power-on timing data stored in the buffer 121 according to the received system board power-on timing data.
[0024] In step 204 , after the mainboard 1 receives a signal indicating a power-on, the mainboard 1 sends a power supply instruction to the power supply 3 .
[0025] In step 205, the power supply 3 transmits a working power (main power) to the mainboard 1 and the system board 2 to provide the power required for the mainboard and the system board 2 to work. It is worth mentioning that in this embodiment, the power supply 3 directly transmits the working power to the mainboard 1 and the system board 2; however, in other embodiments, the power supply 3 may first transmit the working power to the mainboard 1, and then transmit the working power to the system board 2 through the mainboard 1.
[0026] In step 206, the programmable logic device 12 of the mainboard 1 obtains a waiting power-on item from a plurality of mainboard power-on items related to a power-on timing of the mainboard 1, and determines whether there is at least one target power-on item among the system board power-on items according to the waiting power-on item and the system board power-on timing data, wherein the power-on voltage corresponding to each target power-on item is less than or equal to the power-on voltage corresponding to the waiting power-on item and greater than the power-on voltage corresponding to the next mainboard power-on item corresponding to the waiting power-on item, or each target power-on item is less than or equal to the power-on voltage corresponding to the waiting power-on item and the programmable logic device 12 of the mainboard 1 has not yet completed the corresponding voltage startup procedure. When the programmable logic device 12 of the mainboard 1 determines that there is at least one target power-on item, the process proceeds to step 207; when the programmable logic device 12 of the mainboard 1 determines that there is at least one target power-on item, the process proceeds to step 214.
[0027] It is worth mentioning that these mainboard power-on items are executed sequentially. When the programmable logic device 12 of the mainboard 1 performs step 206 for the first time, the power-on item obtained is the first mainboard power-on item among the mainboard power-on items. When the programmable logic device 12 of the mainboard 1 does not perform step 206 for the first time, the power-on item obtained is the next power-on item of the power-on item when step 206 was last executed.
[0028] In step 207, the programmable logic device 12 of the mainboard 1 performs a voltage startup procedure for the power-on voltage corresponding to the item to be powered on, and transmits a power-on notification related to the at least one target power-on item to the system board 2. The programmable logic device 12 of the mainboard 1 controls the corresponding power controller 14 to start and convert the working power to perform the voltage startup procedure for the power-on voltage corresponding to the item to be powered on. Specifically, the corresponding power controller 14 is controlled to start and operate, and then converts and generates the corresponding power-on voltage to provide the corresponding power-on voltage to the mainboard 1 for part of the power required for operation.
[0029] In step 208, after the control device 21 of the system board 2 receives the power-on notification, the control device 21 of the system board 2 performs a voltage startup procedure for at least one power-on voltage corresponding to at least one target power-on item of the power-on notification. The control device 21 of the system board 2 controls the corresponding power controller 22 to start and convert the working power to perform the voltage startup procedure for at least one power-on voltage corresponding to at least one target power-on item of the power-on notification. Specifically, the corresponding power controller 22 is controlled to start and operate, and then convert and generate the corresponding power-on voltage to provide the corresponding power-on voltage to the system board 2 for part of the power required for operation.
[0030] In step 209 , the programmable logic device 12 of the main board 1 transmits a result request related to the power-on result of the at least one target power-on item to the system board 2 .
[0031] In step 210, after the control device 21 of the system board 2 receives the result request, the control device 21 of the system board 2 generates and transmits a power-on response to the result request to the main board 1, and the power-on response includes at least one power-on state corresponding to the at least one target power-on item.
[0032] In step 211, after the programmable logic device 12 of the mainboard 1 receives the power-on reply, the programmable logic device 12 of the mainboard 1 determines whether the at least one power-on state indicates that the power-on is successful. When the programmable logic device 12 of the mainboard 1 determines that the at least one power-on state indicates that the power-on is successful, the process proceeds to step 212; when the programmable logic device 12 of the mainboard 1 determines that the at least one power-on state does not indicate that the power-on is successful, the process proceeds to step 213.
[0033] In step 212, the programmable logic device 12 of the mainboard 1 returns to step 206 until all power-on items have completed the corresponding voltage startup procedures.
[0034] In step 213, the programmable logic device 12 of the mainboard 1 records the target power-on item corresponding to at least one power-on state in which power-on is not successful, and transmits an indicator light control instruction group related to the target power-on item corresponding to at least one power-on state in which power-on is not successful to the corresponding indicator light 13, so as to activate the indicator light 13 corresponding to the target power-on item corresponding to at least one power-on state in which power-on is not successful, so as to allow the administrator to find the target power-on item with power startup abnormality at a glance.
[0035] In step 214, the programmable logic device 12 of the mainboard 1 performs a voltage startup procedure of the power-on voltage corresponding to the power-on item, and returns to step 206 until all power-on items have completed the corresponding voltage startup procedure.
[0036] In summary, the system power synchronization control method of the present invention, when the programmable logic device 12 of the mainboard 1 determines that at least one power-on state indicates that the power-on is successful, the voltage startup program of the next mainboard power-on project of the project to be powered on is performed, so that the power-on timing of various voltages of the system board 2 and the mainboard 1 are synchronized, that is, the same voltage coexisting in the system board 2 and the mainboard 1 will be powered on synchronously at the same stage, thereby avoiding the situation where the related devices cannot operate normally due to the problem of power timing asynchrony, so the purpose of the present invention can be achieved.
[0037] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A system power synchronization control method, implemented by a mainboard of a servo system, the mainboard signal is connected to the system board of the servo system, the mainboard includes a programmable logic device storing mainboard power-on timing data and system board power-on timing data, the mainboard power-on timing data includes a plurality of mainboard power-on items related to the mainboard power-on, the system board power-on timing data includes a plurality of system board power-on items related to the system board power-on, characterized in that: The method comprises the following steps: (A) the programmable logic device of the mainboard obtains a waiting-to-be-powered item from a plurality of mainboard power-on items related to a power-on timing of the mainboard, and determines whether there is at least one target power-on item among the system board power-on items according to the waiting-to-be-powered item and the system board power-on timing data; (B) when the programmable logic device of the mainboard determines that the at least one target power-on item exists, the programmable logic device of the mainboard performs a voltage startup procedure of a power-on voltage corresponding to the item to be powered on, and transmits a power-on notification related to the at least one target power-on item to the system board; (C) the programmable logic device of the main board transmits a result request related to the power-on result of the at least one target power-on item to the system board; (D) after receiving a power-on reply from the system board in response to the result request, the programmable logic device of the main board determines whether the at least one power-on status indicates that the power-on is successful; and (E) When the programmable logic device of the mainboard determines that at least one power-on state indicates that the power-on is successful, return to step (A) until all power-on items have executed the corresponding voltage startup program.
2. The system power synchronization control method according to claim 1, characterized in that: After step (A), the following steps are also included: (F) When the programmable logic device of the mainboard determines that the at least one target power-on item does not exist, a voltage startup procedure of the power-on voltage corresponding to the item to be powered on is performed, and the process returns to step (A) until all power-on items have completed the corresponding voltage startup procedure.
3. The system power synchronization control method according to claim 1, characterized in that: After step (D), the method further comprises the following steps: (G) When the programmable logic device of the mainboard determines that the at least one power-on state does not all indicate a successful power-on, the programmable logic device of the mainboard records a target power-on item corresponding to at least one power-on state that did not successfully power on.
4. The system power synchronization control method according to claim 1, characterized in that: After step (D), the mainboard further comprises a plurality of indicator lights corresponding to the power-on items of the system boards, and further comprises the following steps: (H) When the programmable logic device of the main board determines that the at least one power-on state does not all indicate a successful power-on, the programmable logic device of the main board transmits an indicator light control instruction group related to a target power-on item corresponding to at least one power-on state that did not power on successfully to the corresponding indicator light, so as to activate the indicator light corresponding to the target power-on item corresponding to at least one power-on state that did not power on successfully.
5. The system power synchronization control method according to claim 1, characterized in that: The servo system further comprises a power supply electrically connected to the mainboard and the system board and used for providing power to the mainboard and the system board. Prior to step (A), the servo system further comprises the following steps: (I) the power supply transmits a standby power to the main board and the system board; (J) after the mainboard obtains the standby power from the power supply, the programmable logic device of the mainboard sends a power-on timing data request to the system board; and (K) After the programmable logic device of the main board obtains the system board power-on timing data in response to the power-on timing data request from the system board, the programmable logic device of the main board stores the system board power-on timing data.
6. The system power synchronization control method according to claim 5, characterized in that: Between step (K) and step (A), the following steps are further included: (L) The power supply transmits a working power to the mainboard and the system board, and performs step (A).
7. The system power synchronization control method according to claim 1, characterized in that: In step (A), the power-on voltage corresponding to each target power-on item is less than or equal to the power-on voltage corresponding to the item to be powered on and is greater than the power-on voltage corresponding to the next mainboard power-on item corresponding to the item to be powered on, or each target power-on item is less than or equal to the power-on voltage corresponding to the item to be powered on.